ANALOG DEVICES AD526

Software Programmable a Gain Amplifier AD526 FEATURES PIN CONFIGURATION Digitally Programmable Binary Gains from 1 to 16 Two-Chip Cascade Mode Achieves Binary Gain from 1 to 256 DIG GND 1 16 A1 Gain Error: NULL 2 15 A0 0.01% Max, Gain = 1, 2, 4 (C Grade) V 3 14 CS IN 0.02% Max, Gain = 8, 16 (C Grade) NULL 4 AD526 13 CLK 0.5 ppm/8C Drift Over Temperature TOP VIEW ANALOG GND 2 5 12 A2 (Not to Scale) Fast Settling Time ANALOG GND 1 6 11 B 10 V Signal Change: –V +V 7 10 S S 0.01% in 4.5 ms (Gain = 16) V SENSE V FORCE 8 9 OUT OUT Gain Change: 0.01% in 5.6 ms (Gain = 16) Low Nonlinearity: 60.005% FSR Max (J Grade) Excellent DC Accuracy: Offset Voltage: 0.5 mV Max (C Grade) Offset Voltage Drift: 3 mV/8C (C Grade) TTL-Compatible Digital Inputs PRODUCT DESCRIPTION APPLICATION HIGHLIGHTS The AD526 is a single-ended, monolithic software program- 1. Dynamic Range Extension for ADC Systems: A single mable gain amplifier (SPGA) that provides gains of 1, 2, 4, 8 AD526 in conjunction with a 12-bit ADC can provide and 16. It is complete, including amplifier, resistor network 96 dB of dynamic range for ADC systems. and TTL-compatible latched inputs, and requires no external components. 2. Gain Ranging Preamps: The AD526 offers complete digital Low gain error and low nonlinearity make the AD526 ideal for gain control with precise gains in binary steps from 1 to 16. precision instrumentation applications requiring programmable Additional gains of 32, 64, 128 and 256 are possible by cas- gain. The small signal bandwidth is 350 kHz at a gain of 16. In cading two AD526s. addition, the AD526 provides excellent dc precision. The FET- input stage results in a low bias current of 50 pA. A guaranteed ORDERING GUIDE maximum input offset voltage of 0.5 mV max (C grade) and low gain error (0.01%, G = 1, 2, 4, C grade) are accomplished using Temperature Package Package Model Range Descriptions Options Analog Devices’ laser trimming technology. To provide flexibility to the system designer, the AD526 can be AD526JN Commercial 16-Lead Plastic DIP N-16 AD526AD Industrial 16-Lead Cerdip D-16 operated in either latched or transparent mode. The force/sense AD526BD Industrial 16-Lead Cerdip D-16 configuration preserves accuracy when the output is connected AD526CD Industrial 16-Lead Cerdip D-16 to remote or low impedance loads. AD526SD Military 16-Lead Cerdip D-16 The AD526 is offered in one commercial (0°C to +70°C) grade, AD526SD/883B Military 16-Lead Cerdip D-16 J, and three industrial grades, A, B and C, which are specified 5962-9089401MEA* Military 16-Lead Cerdip D-16 from –40°C to +85°C. The S grade is specified from –55°C to *Refer to official DESC drawing for tested specifications. +125°C. The military version is available processed to MIL- STD 883B, Rev C. The J grade is supplied in a 16-lead plastic DIP, and the other grades are offered in a 16-lead hermetic side-brazed ceramic DIP. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or Fax: 781/326-8703 © Analog Devices, Inc., 1999 otherwise under any patent or patent rights of Analog Devices. (@ V = 615 V, R = 2 kV and T = +258C unless otherwise noted) AD526–SPECIFICATIONS S L A AD526J AD526A AD526B/S AD526C Model Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units GAIN Gain Range (Digitally Programmable) 1, 2, 4, 8, 16 1, 2, 4, 8, 16 1, 2, 4, 8, 16 1, 2, 4, 8, 16 Gain Error Gain = 1 0.05 0.02 0.01 0.01 % Gain = 2 0.05 0.03 0.02 0.01 % Gain = 4 0.10 0.03 0.02 0.01 % Gain = 8 0.15 0.07 0.04 0.02 % Gain = 16 0.15 0.07 0.04 0.02 % Gain Error Drift Over Temperature G = 1 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ppm/°C G = 2 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ppm/°C G = 4 0.5 3.0 0.5 3.0 0.5 3.0 0.5 3.0 ppm/°C G = 8 0.5 5.0 0.5 5.0 0.5 5.0 0.5 5.0 ppm/°C G = 16 1.0 5.0 1.0 5.0 1.0 5.0 1.0 5.0 ppm/°C to T ) Gain Error (T MIN MAX Gain = 1 0.06 0.03 0.02 0.015 % Gain = 2 0.06 0.04 0.03 0.015 % Gain = 4 0.12 0.04 0.03 0.015 % Gain = 8 0.17 0.08 0.05 0.03 % Gain = 16 0.17 0.08 0.05 0.03 % Nonlinearity Gain = 1 0.005 0.005 0.005 0.0035 % FSR Gain = 2 0.001 0.001 0.001 0.001 % FSR Gain = 4 0.001 0.001 0.001 0.001 % FSR Gain = 8 0.001 0.001 0.001 0.001 % FSR Gain = 16 0.001 0.001 0.001 0.001 % FSR Nonlinearity (T to T ) MIN MAX Gain = 1 0.01 0.01 0.01 0.007 % FSR Gain = 2 0.001 0.001 0.001 0.001 % FSR Gain = 4 0.001 0.001 0.001 0.001 % FSR Gain = 8 0.001 0.001 0.001 0.001 % FSR Gain = 16 0.001 0.001 0.001 0.001 % FSR VOLTAGE OFFSET, ALL GAINS Input Offset Voltage 0.4 1.5 0.25 0.7 0.25 0.5 0.25 0.5 mV Input Offset Voltage Drift Over Temperature 5 20 3 10 3 10 3 10mV/°C Input Offset Voltage T to T 2.0 1.0 0.8 0.8 mV MIN MAX Input Offset Voltage vs. Supply (V – 10%) 80 80 84 90 dB S INPUT BIAS CURRENT Over Input Voltage Range – 10 V 50 150 50 150 50 150 50 150 pA ANALOG INPUT CHARACTERISTICS Voltage Range (Linear Operation) 610–12 610–12 610–12 610–12 V Capacitance 5555 pF RATED OUTPUT Voltage 610–12 610–12 610–12 610–12 V Current (V = –10 V)–10 65–10 65–10 65–10 mA OUT Short-Circuit Current 15 30 15 30 15 30 15 30 mA DC Output Resistance 0.002 0.002 0.002 0.002W Load Capacitance (For Stable Operation) 700 700 700 700 pF –2– REV. D AD526 AD526J AD526A AD526B/S AD526C Model Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units NOISE, ALL GAINS Voltage Noise, RTI 0.1 Hz to 10 Hz 3 3 3 3mV p-p Voltage Noise Density, RTI f = 10 Hz 70 70 70 70 nV√Hz f = 100 Hz 60 60 60 60 nV√Hz f = 1 kHz 30 30 30 30 nV√Hz f = 10 kHz 25 25 25 35 nV√Hz DYNAMIC RESPONSE –3 dB Bandwidth (Small Signal) G = 1 4.0 4.0 4.0 4.0 MHz G = 2 2.0 2.0 2.0 2.0 MHz G = 4 1.5 1.5 1.5 1.5 MHz G = 8 0.65 0.65 0.65 0.65 MHz G = 16 0.35 0.35 0.35 0.35 MHz Signal Settling Time to 0.01% (DV = –10 V) OUT G = 1 2.1 4 2.1 4 2.1 4 2.1 4ms G = 2 2.5 5 2.5 5 2.5 5 2.5 5ms G = 4 2.7 5 2.7 5 2.7 5 2.7 5ms G = 8 3.6 7 3.6 7 3.6 7 3.6 7ms G = 16 4.1 7 4.1 7 4.1 7 4.1 7ms Full Power Bandwidth G = 1, 2, 4 0.10 0.10 0.10 0.10 MHz G = 8, 16 0.35 0.35 0.35 0.35 MHz Slew Rate G = 1, 2, 4 4 6 4 6 4 6 46V/ms G = 8, 16 18 24 18 24 18 24 18 24 V/ms DIGITAL INPUTS (T to T ) MIN MAX Input Current (V = 5 V) 60 100 140 60 100 140 60 100 140 60 100 140mA H Logic “1” 2 6 2 6 2 6 2 6 V Logic “0” 0 0.8 0 0.8 0 0.8 0 0.8 V 1 TIMING (V = 0.2 V, V = 3.7 V) L H A0, A1, A2 T 50 50 50 50 ns C 30 30 30 30 ns T S T 30 30 30 30 ns H B T 50 50 50 50 ns C T 40 40 40 40 ns S T 10 10 10 30 ns H TEMPERATURE RANGE Specified Performance 0 +70 –40 +85 –40/–55 +85/+125 –40 +85 °C Storage –65 +125 –65 +150 –65 +150 –65 +150 °C POWER SUPPLY Operating Range 64.5 616.5 64.5 616.5 64.5 616.5 64.5 616.5 V Positive Supply Current 10 14 10 14 10 14 10 14 mA Negative Supply Current 10 13 10 13 10 13 10 13 mA PACKAGE OPTIONS Plastic (N-16) AD526JN Ceramic DIP (D-16) AD526AD AD526BD AD526SD AD526CD AD526SD/883B NOTES 1 Refer to Figure 25 for definitions. FSR = Full Scale Range = 20 V. RTI = Referred to Input. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. –3– REV. D AD526–Typical Performance Characteristics 20 20 30 15 15 +258C 20 R = 2kV L @ V = 615V S V = 0 IN 10 10 10 5 5 0 0 0 05 10 15 20 05 10 15 20 100 1k 10k SUPPLY VOLTAGE – 6V SUPPLY VOLTAGE – 6V LOAD RESISTANCE – V Figure 3. Input Bias Current vs. Figure 1. Output Voltage Swing vs. Figure 2. Output Voltage Swing vs. Supply Voltage Supply Voltage, G = 16 Load Resistance 100nA 75 20 16 10 8 10nA V = 615V S 50 4 1nA 2 1 100pA 25 1 10pA 0 1pA –60 –20 20 60 100 140 –10 –5 0 5 10 10 100 1k 10k 100k 1M 10M INPUT VOLTAGE – V TEMPERATURE – 8C FREQUENCY – Hz Figure 6. Gain vs. Frequency Figure 4. Input Bias Current vs. Figure 5. Input Bias Current vs. Input Temperature Voltage 25 100 1.0002 615V WITH 1V p-p SINE WAVE 80 20 GAIN = 8, 16 1.0001 +SUPPLY 60 15 GAIN = 1, 2, 4 1.0000 40 10 –SUPPLY 0.9999 20 5 10 0.9998 0 –60 –20 20 60 100 140 1 10 100 1k 10k 100k 1M 1k 10k 100k 1M 10M TEMPERATURE – 8C FREQUENCY – Hz FREQUENCY – Hz Figure 9. Normalized Gain vs. Figure 7. Large Signal Frequency Figure 8. PSRR vs. Frequency Temperature, Gain = 1 Response –4– REV. D INPUT BIAS CURRENT FULL POWER RESPONSE – V p-p OUTPUT VOLTAGE SWING – 6V INPUT BIAS CURRENT – pA OUTPUT VOLTAGE SWING – 6V POWER SUPPLY REJECTION – dB NORMALIZED GAIN INPUT BIAS CURRENT – pA GAIN AD526 0.006 1000 0.004 0.002 100 0.000 –0.002 –0.004 10 –60 –20 20 60 100 140 10 100 1k 10k 100k TEMPERATURE – 8C FREQUENCY – Hz Figure 11. Nonlinearity vs. Figure 10. Noise Spectral Density Figure 12. Wideband Output Noise, Temperature, Gain = 1 G = 16 (Amplified by 10) Figure 14. Small Signal Pulse Figure 13. Large Signal Pulse Figure 15. Large Signal Pulse Response and Settling Time,* Response, G = 1 Response and Settling Time,* G = 1 G = 2 Figure 16. Small Signal Pulse Figure 17. Large Signal Pulse Figure 18. Small Signal Pulse Response, G = 2 Response and Settling Time,* Response, G = 4 G = 4 *For Settling Time Traces, 0.01% = 1/2 Vertical Division REV. D –5– INPUT NOISE VOLTAGE – nV/ Hz NONLINEARITY – %FSR AD526 Figure 19. Large Signal Pulse Figure 20. Small Signal Pulse Figure 21. Large Signal Pulse Response and Settling Time,* G = 8 Response, G = 8 Response and Settling Time,* G = 16 –60 10 –70 5 –80 0 –90 –5 –100 –10 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY – Hz FREQUENCY – Hz Figure 22. Small Signal Pulse Figure 23. Total Harmonic Distortion Figure 24. Phase Distortion vs. Response, Gain = 16 vs. Frequency Gain = 16 Frequency, Gain = 16 100 G = 2, 8 G = 4, 16 G = 1 10 1 10k 100k 1M 10M FREQUENCY – Hz Figure 25. Output Impedance vs. Figure 26. Gain Change Settling Figure 27. Gain Change Settling Frequency Time,** Gain Change: 1 to 2 Time,** Gain Change 1 to 4 *For Settling Time Traces, 0.01% = 1/2 Vertical Division **Scope Traces are: Top: Output Transition; Middle: Output Settling; Bottom: Digital Input. REV. D –6– OUTPUT IMPEDANCE – V TOTAL HARMONIC DISTORTION – dB PHASE DISTORTION – Dedrees AD526 Figure 28. Gain Change Settling Figure 29. Gain Change Settling Time,* Gain Change 1 to 8 Time,* Gain Change 1 to 16 +15V –15V +15V –15V 10mF10mF + + 10mF10mF TEKTRONIX + + 7000 SERIES SCOPE 7A13 PREAMP AD526 5MHz BW G = 16 OP37 900V G = 10 V = 160 3 e 10mF 100V o p-p +5V SHIELD NOTE: COAX CABLE 1 FT. OR LESS Figure 30. Wideband Noise Test Circuit +15V –15V 10mF10mF + + DATA DYNAMICS +15V –15V 5109 (OR EQUIVALENT 10mF10mF 5kV FLAT-TOP PULSE + + GENERATOR) AD526 TEKTRONIX 1pF 7000 SERIES V ERROR SCOPE 2kV + 7A13 V 3 5 POT. ERROR PREAMP – AD711 5kV 5MHz BW AD3554 – 1pF + G R IN 5kV 5.6kV IN6263 1 5.6kV 2 2.8kV R 2 2 10mF10mF IN T = TMEAS – T 4 1.4kV SET X 5pF – 8 715V IN6263 5kV 1.25kV G T 16 348V AD3554 X 50V –15V +15V + 1 1.2ms 2 1.2ms 4 1.2ms 10mF10mF 8 1.4ms + 16 1.8ms –15V +15V Figure 31. Settling Time Test Circuit *Scope Traces are: Top: Output Transition Middle: Output Settling Bottom: Digital Input REV. D –7– + + + + AD526 THEORY OF OPERATION TRANSPARENT MODE OF OPERATION The AD526 is a complete software programmable gain amplifier In the transparent mode of operation, the AD526 will respond (SPGA) implemented monolithically with a drift-trimmed directly to level changes at the gain code inputs (A0, A1, A2) if BiFET amplifier, a laser wafer trimmed resistor network, JFET B is tied high and both CS and CLK are allowed to float low. analog switches and TTL compatible gain code latches. After the gain codes are changed, the AD526’s output voltage A particular gain is selected by applying the appropriate gain typically requires 5.5 ms to settle to within 0.01% of the final code (see Table I) to the control logic. The control logic turns value. Figures 26 to 29 show the performance of the AD526 for on the JFET switch that connects the correct tap on the gain positive gain code changes. network to the inverting input of the amplifier; all unselected A2 JFET gain switches are off (open). The “on” resistance of the A1 gain switches causes negligible gain error since only the A0 +V amplifier’s input bias current, which is less than 150 pA, actu- S ally flows through these switches. 0.1mF +5V The AD526 is capable of storing the gain code, (latched mode), OUT B, A0, A1, A2, under the direction of control inputs CLK and FORCE 16 15 14 13 12 11 10 9 CS. Alternatively, the AD526 can respond directly to gain code A1 A0 CS CLK A2 B changes if the control inputs are tied low (transparent mode). LOGIC AND LATCHES For gains of 8 and 16, a fraction of the frequency compensation 16 84 21 capacitance (C1 in Figure 32) is automatically switched out of V OUT GAIN NETWORK the circuit. This increases the amplifier’s bandwidth and im- – proves its signal settling time and slew rate. AD526 + 12 34 56 78 OUT AMPLIFIER SENSE +V S 0.1mF C1 V IN –V S C2 V IN OUT Figure 33. Transparent Mode FORCE LATCHED MODE OF OPERATION N1 N2 The latched mode of operation is shown in Figure 34. When –V OUT S SENSE either CS or CLK go to a Logic “1,” the gain code (A0, A1, A2, B) signals are latched into the registers and held until both CS A0 and CLK return to “0.” Unused CS or CLK inputs should be tied C O 14kV to ground . The CS and CLK inputs are functionally and electri- A1 N T cally equivalent. L G = 8 R A A2 3.4kV O T RESISTOR L C TIMING SIGNAL NETWORK H B G = 2 A2 L E O S A1 1kV G CLK A0 I G = 16 +V S C 1.7kV CS 0.1mF +5V G = 4 DIGITAL OUT 1kV 1.7kV GND FORCE 16 15 14 13 12 11 10 9 ANALOG ANALOG GND2 GND1 A1 A0 CS CLK A2 B LOGIC AND LATCHES Figure 32. Simplified Schematic of the AD526 16 84 21 V OUT GAIN NETWORK – AD526 + 12 34 56 78 OUT SENSE 0.1mF V IN –V S Figure 34. Latched Mode REV. D –8– AD526 TIMING AND CONTROL DIGITAL FEEDTHROUGH With either CS or CLK or both held high, the AD526 gain state Table I. Logic Input Truth Table will remain constant regardless of the transitions at the A0, A1, A2 or B inputs. However, high speed logic transitions will un- Gain Code Control Condition avoidably feed through to the analog circuitry within the AD526 A2 A1 A0 B CLK (CS = 0) Gain Condition causing spikes to occur at the signal output. XXXX 1 Previous State Latched This feedthrough effect can be completely eliminated by operat- 0001 0 1 Transparent ing the AD526 in the transparent mode and latching the gain 0011 0 2 Transparent code in an external bank of latches (Figure 36). 0101 0 4 Transparent To operate the AD526 using serial inputs, the configuration 0111 0 8 Transparent shown in Figure 36 can be used with the 74LS174 replaced by a 1 X X 1 0 16 Transparent serial-in/parallel-out latch, such as the 54LS594. XXX0 0 1 Transparent XXX0 1 1 Latched A1 A0 A2 B +5V 0001 1 1 Latched 0011 1 2 Latched 1mF TIMING 0101 1 4 Latched 74LS174 SIGNAL 0111 1 8 Latched 1 X X 1 1 16 Latched +V S NOTE: X = Don’t Care. 0.1mF The specifications on page 3, in combination with Figure 35, give the timing requirements for loading new gain codes. OUT FORCE 16 15 14 13 12 11 10 9 A1 A0 CS CLK A2 B LOGIC AND LATCHES GAIN CODE VALID DATA INPUTS 16 84 21 T C V OUT GAIN NETWORK CLK OR CS – T T S H AD526 + T = MINIMUM CLOCK CYCLE NOTE: THRESHOLD LEVEL FOR C 12 34 56 78 OUT T = DATA SETUP TIME GAIN CODE, CS, AND CLK IS 1.4V. S SENSE T = DATA HOLD TIME H 0.1mF V IN Figure 35. AD526 Timing –V S Figure 36. Using an External Latch to Minimize Digital Feedthrough REV. D –9– AD526 GROUNDING AND BYPASSING Utilizing the force and sense outputs of the AD526, as shown in Proper signal and grounding techniques must be applied in Figure 38, avoids signal drops along etch runs to low impedance board layout so that specified performance levels of precision loads. data acquisition components, such as the AD526, are not Table II. Logic Table for Figure 38 degraded. V /V A2 A1 A0 As is shown in Figure 37, logic and signal grounds should be OUT IN separate. By connecting the signal source ground locally to the 10 0 0 AD526 analog ground Pins 5 and 6, gain accuracy of the 20 0 1 AD526 is maintained. This ground connection should not be 40 1 0 corrupted by currents associated with other elements within the 80 1 1 system. 16 1 0 0 32 1 0 1 +15V –15V 64 1 1 0 128 1 1 1 0.1mF 0.1mF AD574 V 12-BIT IN 0.1mF 0.1mF A/D CONVERTER ANALOG ANALOG +V –V S S GROUND 1 GROUND 2 V OUT FORCE AMP AD526 V OUT SENSE GAIN NETWORK DIGITAL 1mF GROUND LATCHES AND LOGIC +5V Figure 37. Grounding and Bypassing CLK A2 A1 A0 +V +V S S 0.1mF 0.1mF +5V +5V OUT OUT FORCE FORCE 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 A1 A0 CS CLK A2 B A1 A0 CS CLK A2 B LOGIC AND LATCHES LOGIC AND LATCHES 16 84 21 16 84 21 V OUT GAIN NETWORK GAIN NETWORK – – AD526 + AD526 + 12 34 56 78 12 34 56 78 OUT OUT SENSE SENSE 0.1mF V IN 0.1mF –V S –V S Figure 38. Cascaded Operation REV. D –10– AD526 OFFSET NULLING CASCADED OPERATION Input voltage offset nulling of the AD526 is best accomplished A cascade of two AD526s can be used to achieve binarily at a gain of 16, since the referred-to-input (RTI) offset is ampli- weighted gains from 1 to 256. If gains from 1 to 128 are needed, fied the most at this gain and therefore is most easily trimmed. no additional components are required. This is accomplished by The resulting trimmed value of RTI voltage offset typically using the B pin as shown in Figure 38. When the B pin is low, varies less than 3 mV across all gain ranges. the AD526 is held in a unity gain stage independent of the other gain code values. Note that the low input current of the AD526 minimizes RTI voltage offsets due to source resistance. OFFSET NULLING WITH A D/A CONVERTER Figure 41 shows the AD526 with offset nulling accomplished +V S with an 8-bit D/A converter (AD7524) circuit instead of the 0.1mF potentiometer shown in Figure 39. The calibration procedure is the same as before except that instead of adjusting the potenti- OUT FORCE ometer, the D/A converter corrects for the offset error. This 16 15 14 13 12 11 10 9 calibration circuit has a number of benefits in addition to elimi- A1 A0 CS CLK A2 B LOGIC AND LATCHES nating the trimpot. The most significant benefit is that calibra- tion can be under the control of a microprocessor and therefore 16 84 21 V can be implemented as part of an autocalibration scheme. Sec- OUT GAIN NETWORK ondly, dip switches or RAM can be used to hold the 8-bit word – after its value has been determined. In Figure 42 the offset null AD526 + sensitivity, at a gain of 16, is 80 mV per LSB of adjustment, 12 34 56 78 OUT which guarantees dc accuracy to the 16-bit performance level. SENSE V IN 0.1mF +V S 20kV 0.1mF –V S Figure 39. Offset Voltage Null Circuit OUT FORCE 16 15 14 13 12 11 10 9 A1 A0 CS CLK A2 B OUTPUT CURRENT BOOSTER LOGIC AND LATCHES The AD526 is rated for a full –10 V output voltage swing into 16 84 21 2 kW. In some applications, the need exists to drive more cur- V OUT rent into heavier loads. As shown in Figure 40, a high current GAIN NETWORK booster may be connected “inside the loop” of the SPGA to – AD526 + provide the required current boost without significantly degrad- ing overall performance. Nonlinearities, offset and gain inaccu- 1 2 34 56 7 8 OUT SENSE racies of the buffer are minimized by the loop gain of the V IN +V 0.1mF AD526 output amplifier. S AD581 OR 3.3MV AD587 7.5MV –V +10V S +V V S REF ALL BYPASS CAPACITORS ARE 0.1mF 0.1mF +V S 1kV 0.01mF MSB 10mF LSB OUT 1 OUT AD7524 – FORCE 16 15 14 13 12 11 10 9 0.01mF CS AD548 OUT 2 + WR A1 A0 CS CLK A2 B 0.01mF LOGIC AND LATCHES 16 84 21 HOS-100 –V GND S GAIN NETWORK Figure 41. Offset Nulling Using a DAC 0.01mF – AD526 + 12 34 56 78 OUT SENSE 0.1mF V IN R L –V S Figure 40. Current Output Boosting REV. D –11– AD526 FLOATING-POINT CONVERSION the input falls within, relative to full scale. Once the AD526 has High resolution converters are used in systems to obtain high settled to the appropriate level, then the second sample/hold accuracy, improve system resolution or increase dynamic range. amplifier can be put into hold which holds the amplified signal There are a number of high resolution converters available with while the AD7572 perform its conversion routine. The acquisi- throughput rates of 66.6 kHz that can be purchased as a single tion time for the AD585 is 3 ms, and the conversion time for the component solution; however in order to achieve higher through- AD7572 is 5 ms for a total of 8 ms, or 125 kHz. This performance put rates, alternative conversion techniques must be employed. relies on the fast settling characteristics of the AD526 after the A floating point A/D converter can improve both throughput flash autoranging (comparator) circuit quantizes the input sig- rate and dynamic range of a system. nal. A 16-bit register holds the 3-bit output from the flash autor- anger and the 12-bit output of the AD7572. In a floating point A/D converter (Figure 42), the output data is presented as a 16-bit word, the lower 12 bits from the A/D The A/D converter in Figure 42 has a dynamic range of 96 dB. converter form the mantissa and the upper 4 bits from the digi- The dynamic range of a converter is the ratio of the full-scale tal signal used to set the gain form the exponent. The AD526 input range to the LSB value. With a floating-point A/D con- programmable gain amplifier in conjunction with the compara- verter the smallest value LSB corresponds to the LSB of the tor circuit scales the input signal to a range between half scale monolithic converter divided by the maximum gain of the PGA. and full scale for the maximum usable resolution. The floating point A/D converter has a full-scale range of 5 V, a maximum gain of 16 V/V from the AD526 and a 12-bit A/D The A/D converter diagrammed in Figure 42 consists of a pair converter; this produces: of AD585 sample/hold amplifiers, a flash converter, a five-range N programmable gain amplifier (the AD526) and a fast 12-bit A/D LSB = ([FSR/2 ]/Gain) = ([5 V/4096]/16) = 76 mV. The converter (the AD7572). The floating-point A/D converter dynamic range in dBs is based on the log of the ratio of the achieves its high throughput rate of 125 kHz by overlapping the full-scale input range to the LSB; dynamic range = 20 log acquisition time of the first sample/hold amplifier and the set- (5 V/76 mV) = 96 dB. tling time of the AD526 with the conversion time of the A/D converter. The first sample/hold amplifier holds the signal for the flash autoranger, which determines which binary quantum –15V +15V + 10mF 10mF +5V +5V –15V +15V + 56 + 1/6 +5V 10mF 10mF + BUSY 30pF 50kV D12 MSB +5V 74- D11 123 1/2 CLOCK D10 1 3 V 74– IN 1/6 1/6 1ms 125MHz S/H LS174 2 4 68pF D9 –15V +15V AD585 D8 + AD7572 2.5MHz 10mF 10mF –15V +15V D7 + + 68pF 10mF 10mF 10kV + F S D6 AD526 47mF V IN D5 +5V B D4 74– S/H LSB LS174 AD585 D3 V A0 A1 A2 IN D2 D1 10kV –15V +15V +5V + A0 10mF 10mF E1 10kV 74ALS86 A1 E2 74– 1 +5V REF 3 12 A2 LS174 2 11 E3 1/4 13 1/4 10kV 10kV 5kV 4 AD588 6 NOTE: ALL BYPASS CAPACITORS ARE 0.1mF 5 1/4 2.5kV 10kV 1 9 3 8 2 1/4 10 1/4 10kV 1.25kV 1mF 11 10 1/6 LM339A 1.25kV Figure 42. Floating-Point A/D Converter REV. D –12– + AD526 HIGH ACCURACY A/D CONVERTERS hunting during the calibration process, the reference offset and Very high accuracy and high resolution floating-point A/D con- gain codes should be different from the endpoint codes. A cali- verters can be achieved by the incorporation of offset and gain bration cycle consists of selecting whether gain or offset is to be calibration routines. There are two techniques commonly used calibrated then selecting the appropriate multiplexer channel to for calibration, a hardware circuit as shown in Figure 43 and/or apply the reference voltage to the signal channel. Once the op- a software routine. In this application the microprocessor is eration has been initiated, the counter, a 74ALS869, drives the functioning as the autoranging circuit, requiring software over- D/A converter in a linear fashion providing a small correction head; therefore, a hardware calibration technique was applied voltage to either the gain or offset trim point of the AD574. The which reduces the software burden. The software is used to set output of the A/D converter is then compared to the value pre- the gain of the AD526. In operation the signal is converted, and set in the 74ALS528 to determine a match. Once a match is if the MSB of the AD574 is not equal to a Logical 1, the gain is detected, the 74ALS528 produces a low going pulse which stops increased by binary steps, up to the maximum gain. This maxi- the counter. The code at the D/A converter is latched until the mizes the full-scale range of the conversion process and insures next calibration cycle. Calibration cycles are under the control a wide dynamic range. of the microprocessor in this application and should be imple- mented only during periods of converter inactivity. The calibration technique uses two point correction, offset and gain. The hardware is simplified by the use of programmable magnitude comparators, the 74ALS528s, which can be “burned” for a particular code. In order to prevent under or over range +5V +15V –15V 10mF 200pF + 10mF + –15V +15V MSB NOISE AD585 REDUCTION 7404 21 1mF +15V DATA AD574 +5V F A3 BUS R8 S –15V +15V AD588 10kV A1 AD7501 AD526 V R4 IN1 R1 V OP27 REF 1kV A4 –5V V IN2 R2 R5 WR V IN3 LSB +V +15V S 50kV 0.1mF V R3 R6 IN4 A2 SYS –15V –V S GND DE- 0.1mF +5V –15V DECODED DECODED CODED WR WR ADDRESS ADDRESS ADD ADDRESS BUS 12 12 +5V CALIBRATION R5 PRESET +5V +5V PIN 15 MSB 20kV AD588 VALUE 2 R6 PIN 28 5kV V REF 20kV AD574 74ALS 2 528 A2 R7 1 GAIN RFB A RFB A RFB A R2 10kV R11 P = Q AD7628 AD712 MSB 1 2 5kV 3 C1 2 7400 INPUT 7475 OUT A A1 LATCH DAC A GAIN AGND 1/2 BUFFER 74ALS AD712 869 ADG221 1 RFB B R4 7475 LSB WR 2 C2 CONTROL OUT B A3 4 LSB LATCH DAC B 6 LOGIC MSB R8 7400 5 7475 AD712 20kV 2 1/2 R9 74ALS AGND 10kV 528 WR A/B +5V A2 2 R10 V P = Q REF OFFSET 20kV R12 AD712 PIN 15 5kV AD588 OFFSET +5V AGND NOTE: ALL BYPASS CAPACITORS ARE 0.1mF LSB +5V Figure 43. High Accuracy A/D Converter REV. D –13– AD526 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Plastic 16-Lead Sided-Brazed DIP Package (N-16) Ceramic Package (D-16) 0.87 (22.1) MAX 0.430 (10.922) 16 9 0.25 0.31 16 (6.25) 9 (7.87) 0.040R 18 0.265 0.290 60.010 0.310 60.01 0.3 (7.62) (6.73) (7.37 60.254) PIN 1 0.035 (7.874 60.254) 1 8 0.18 (0.89) (4.57) PIN 1 MAX 0.18 0.125 (3.18) 0.011 0.800 60.010 (4.57) MIN (0.28) (20.32 60.254) 0.300 SEATING (7.62) 0.018 0.100 0.033 0.035 60.01 PLANE REF (0.46) (2.54) (0.84) (0.889 60.254) 0.095 (2.41) 0.085 (2.159) 0.125 0.180 60.03 (3.175) (4.57 60.762) MIN 0.010 60.002 0.100 0.047 60.007 SEATING (0.254 60.05) (1.19 60.18) +0.003 (2.54) 0.017 PLANE –0.002 BSC +0.076 (0.43 ) –0.05 0.700 (17.78) BSC REV. D –14– PRINTED IN U.S.A. C1103d–0–8/99