ANALOG DEVICES AD524

Precision Instrumentation Amplifier AD524 FEATURES FUNCTIONAL BLOCK DIAGRAM Low noise: 0.3 μV p-p at 0.1 Hz to 10 Hz 1 PROTECTION – INPUT Low nonlinearity: 0.003% (G = 1) 4.44kΩ High CMRR: 120 dB (G = 1000) AD524 13 G = 10 Low offset voltage: 50 μV 404Ω G = 100 12 V Low offset voltage drift: 0.5 μV/°C b 20kΩ 40Ω SENSE G = 1000 11 Gain bandwidth product: 25 MHz 20kΩ 20kΩ Pin programmable gains of 1, 10, 100, 1000 RG 16 1 OUTPUT RG 3 Input protection, power-on/power-off 2 20kΩ 20kΩ 20kΩ No external components required REFERENCE Internally compensated + INPUT 2 PROTECTION MIL-STD-883B and chips available 16-lead ceramic DIP and SOIC packages and 20-terminal Figure 1. leadless chip carrier available Available in tape and reel in accordance with EIA-481A standard Standard military drawing also available GENERAL DESCRIPTION higher linearity C grade are specified from −25°C to +85°C. The AD524 is a precision monolithic instrumentation amplifier The S grade guarantees performance to specification over the designed for data acquisition applications requiring high accu- extended temperature range −55°C to +125°C. The AD524 is racy under worst-case operating conditions. An outstanding available in a 16-lead ceramic DIP, 16-lead SBDIP, 16-lead SOIC combination of high linearity, high common-mode rejection, wide packages, and 20-terminal leadless chip carrier. low offset voltage drift, and low noise makes the AD524 suitable for use in many data acquisition systems. PRODUCT HIGHLIGHTS The AD524 has an output offset voltage drift of less than 1. The AD524 has guaranteed low offset voltage, offset 25 μV/°C, input offset voltage drift of less than 0.5 μV/°C, CMR voltage drift, and low noise for precision high gain above 90 dB at unity gain (120 dB at G = 1000), and maximum applications. nonlinearity of 0.003% at G = 1. In addition to the outstanding 2. The AD524 is functionally complete with pin program- dc specifications, the AD524 also has a 25 kHz bandwidth mable gains of 1, 10, 100, and 1000, and single resistor (G = 1000). To make it suitable for high speed data acquisition programmable for any gain. systems, the AD524 has an output slew rate of 5 V/μs and settles 3. Input and output offset nulling terminals are provided for in 15 μs to 0.01% for gains of 1 to 100. very high precision applications and to minimize offset As a complete amplifier, the AD524 does not require any exter- voltage changes in gain ranging applications. nal components for fixed gains of 1, 10, 100 and 1000. For other 4. The AD524 is input protected for both power-on and gain settings between 1 and 1000, only a single resistor is required. The AD524 input is fully protected for both power-on and power-off fault conditions. power-off fault conditions. 5. The AD524 offers superior dynamic performance with a The AD524 IC instrumentation amplifier is available in four gain bandwidth product of 25 MHz, full power response of 75 kHz and a settling time of 15 μs to 0.01% of a 20 V step different versions of accuracy and operating temperature range. (G = 100). The economical A grade, the low drift B grade, and lower drift, Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 00500-001 AD524 TABLE OF CONTENTS Features .............................................................................................. 1 Input Offset and Output Offset ................................................ 15 Functional Block Diagram .............................................................. 1 Gain .............................................................................................. 16 General Description ......................................................................... 1 Input Bias Currents .................................................................... 17 Product Highlights ........................................................................... 1 Common-Mode Rejection ........................................................ 17 Revision History ............................................................................... 2 Grounding ................................................................................... 18 Specif ica t ions ..................................................................................... 3 Sense Terminal ............................................................................ 18 Absolute Maximum Ratings ............................................................ 8 Reference Terminal .................................................................... 18 Connection Diagrams .................................................................. 8 Programmable Gain ................................................................... 20 ESD Caution .................................................................................. 8 Autozero Circuits ....................................................................... 20 Typical Performance Characteristics ............................................. 9 Error Budget Analysis ................................................................ 21 Test Circuits ................................................................................. 14 Outline Dimensions ....................................................................... 24 Theory of Operation ...................................................................... 15 Ordering Guide .......................................................................... 25 Input Protection .......................................................................... 15 REVISION HISTORY 11/07—Rev. E to Rev. F Updated Format .................................................................. Universal Changes to General Description .................................................... 1 Changes to Figure 1 .......................................................................... 1 Changes to Figure 3 and Figure 4 Captions .................................. 8 Changes to Error Budget Analysis Section ................................. 21 Changes to Ordering Guide .......................................................... 25 4/99—Rev. D to Rev. E Rev. F | Page 2 of 28 AD524 SPECIFICATIONS @ VS = ±15 V, RL = 2 kΩ and TA = +25°C, unless otherwise noted. All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at the final electrical test. Results from those tests are used to calculate outgoing quality levels. Table 1. AD524A AD524B Parameter Min Typ Max Min Typ Max Unit GAIN Gain Equation (External Resistor Gain Programming) ⎡ ⎤ ⎡ ⎤ 40,000 40,000 + 1± 20% + 1± 20% ⎢ ⎥ ⎢ ⎥ R R ⎣ G ⎦ ⎣ G ⎦ Gain Range (Pin Programmable) 1 to 1000 1 to 1000 1 Gain Error G = 1 ±0.05 ±0.03 % G = 10 % ±0.25 ±0.15 G = 100 ±0.5 ±0.35 % G = 1000 ±2.0 ±1.0 % Nonlinearity G = 1 ±0.01 ±0.005 % G = 10, G = 100 ±0.01 ±0.005 % G = 1000 ±0.01 ±0.01 % Gain vs. Temperature G = 1 5 5 ppm/°C G = 10 15 10 ppm/°C G = 100 35 25 ppm/°C G = 1000 100 50 ppm/°C VOLTAGE OFFSET (May be Nulled) Input Offset Voltage 250 100 μV vs. Temperature 2 0.75 μV/°C Output Offset Voltage 5 3 mV vs. Temperature 100 50 μV Offset Referred to the Input vs. Supply G = 1 70 75 dB G = 10 dB 85 95 G = 100 95 105 dB G = 1000 100 110 dB INPUT CURRENT Input Bias Current ±50 ±25 nA vs. Temperature ±100 ±100 pA/°C Input Offset Current ±35 ±15 nA vs. Temperature ±100 ±100 pA/°C Rev. F | Page 3 of 28 AD524 AD524A AD524B Parameter Min Typ Max Min Typ Max Unit INPUT Input Impedance 9 9 Differential Resistance 10 10 Ω Differential Capacitance 10 10 pF 9 9 Common-Mode Resistance 10 10 Ω Common-Mode Capacitance 10 10 pF Input Voltage Range 2 Maximum Differential Input Linear (V ) ±10 ±10 V DL 2 Maximum Common-Mode Linear (V ) V CM G G ⎛ ⎞ ⎛ ⎞ 12 V− × V 12 V− × V ⎜ ⎟ ⎜ ⎟ D D 2 2 ⎝ ⎠ ⎝ ⎠ Common-Mode Rejection DC to 60 Hz with 1 kΩ Source Imbalance V G = 1 70 75 dB G = 10 90 95 dB G = 100 100 105 dB G = 1000 110 115 dB OUTPUT RATING V , R = 2 kΩ ±10 ±10 V OUT L DYNAMIC RESPONSE Small Signal – 3 dB G = 1 1 1 MHz G = 10 400 400 kHz G = 100 150 150 kHz G = 1000 25 25 kHz Slew Rate 5.0 5.0 V/μs Settling Time to 0.01%, 20 V Step G = 1 to 100 15 15 μs G = 1000 75 75 μs NOISE Voltage Noise, 1 kHz RTI 7 7 nV/√Hz RTO 90 90 nV√Hz RTI, 0.1 Hz to 10 Hz G = 1 15 15 μV p-p G = 10 2 2 μV p-p G = 100, 1000 0.3 0.3 μV p-p Current Noise 0.1 Hz to 10 Hz 60 60 pA p-p SENSE INPUT RIN 20 20 kΩ ± 20% IIN 15 15 μA Voltage Range ±10 ±10 V Gain to Output 1 1 % REFERENCE INPUT R 40 40 kΩ ± 20% IN I 15 15 μA IN Voltage Range ±10 ±10 V Gain to Output 1 1 % Rev. F | Page 4 of 28 AD524 AD524A AD524B Parameter Min Typ Max Min Typ Max Unit TEMPERATURE RANGE Specified Performance –25 +85 –25 +85 °C Storage –65 +150 –65 +150 °C POWER SUPPLY Power Supply Range ±6 ±15 ±18 ±6 ±15 ±18 V Quiescent Current 3.5 3.5 mA 5.0 5.0 1 Does not include effects of external resistor, RG. 2 VOL is the maximum differential input voltage at G = 1 for specified nonlinearity. VDL at the maximum = 10 V/G. VD = actual differential input voltage. Example: G = 10, V = 0.50. D VCM = 12 V − (10/2 × 0.50 V) = 9.5 V. @ VS = ±15 V, RL = 2 kΩ and TA = +25°C, unless otherwise noted. All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at the final electrical test. Results from those tests are used to calculate outgoing quality levels. Table 2. AD524C AD524S Parameter Min Typ Max Min Typ Max Unit GAIN Gain Equation (External Resistor Gain Programming) ⎡ ⎤ ⎡ ⎤ 40,000 40,000 + 1± 20% + 1± 20% ⎢ ⎥ ⎢ ⎥ R R ⎣ G ⎦ ⎣ G ⎦ Gain Range (Pin Programmable) 1 to 1000 1 to 1000 1 Gain Error G = 1 ±0.02 ±0.05 % G = 10 % ±0.1 ±0.25 G = 100 ±0.25 ±0.5 % G = 1000 ±0.5 ±2.0 % Nonlinearity G = 1 ±0.003 ±0.01 % G = 10, G = 100 ±0.003 ±0.01 % G = 1000 ±0.01 ±0.01 % Gain vs. Temperature G = 1 5 5 ppm/°C G = 10 10 10 ppm/°C G = 100 25 25 ppm/°C G = 1000 50 50 ppm/°C VOLTAGE OFFSET (May be Nulled) Input Offset Voltage 50 100 μV vs. Temperature 0.5 2.0 μV/°C Output Offset Voltage mV 2.0 3.0 vs. Temperature 25 50 μV Offset Referred to the Input vs. Supply G = 1 80 75 dB G = 10 100 95 dB G = 100 110 105 dB G = 1000 115 110 dB Rev. F | Page 5 of 28 AD524 AD524C AD524S Parameter Min Typ Max Min Typ Max Unit INPUT CURRENT Input Bias Current ±15 ±50 nA vs. Temperature ±100 ±100 pA/°C Input Offset Current ±10 ±35 nA vs. Temperature ±100 ±100 pA/°C INPUT Input Impedance 9 9 Differential Resistance 10 10 Ω Differential Capacitance 10 10 pF 9 9 Common-Mode Resistance 10 10 Ω Common-Mode Capacitance 10 10 pF Input Voltage Range 2 Maximum Differential Input Linear (VDL) ±10 ±10 V 2 Maximum Common-Mode Linear (VCM) V G G ⎛ ⎞ ⎛ ⎞ 12 V− × V 12 V− × V ⎜ ⎟ ⎜ ⎟ D D 2 2 ⎝ ⎠ ⎝ ⎠ Common-Mode Rejection DC to 60 Hz with 1 kΩ Source Imbalance V G = 1 80 70 dB G = 10 100 90 dB G = 100 110 100 dB G = 1000 120 110 dB OUTPUT RATING VOUT, RL = 2 kΩ ±10 ±10 V DYNAMIC RESPONSE Small Signal – 3 dB G = 1 1 1 MHz G = 10 400 400 kHz G = 100 150 150 kHz G = 1000 25 25 kHz Slew Rate 5.0 5.0 V/μs Settling Time to 0.01%, 20 V Step G = 1 to 100 15 15 μs G = 1000 75 75 μs NOISE Voltage Noise, 1 kHz RTI 7 7 nV/√Hz RTO 90 90 nV√Hz RTI, 0.1 Hz to 10 Hz G = 1 15 15 μV p-p G = 10 2 2 μV p-p G = 100, 1000 0.3 0.3 μV p-p Current Noise 0.1 Hz to 10 Hz 60 60 pA p-p SENSE INPUT R 20 20 kΩ ± 20% IN I 15 15 μA IN Voltage Range ±10 ±10 V Gain to Output 1 1 % Rev. F | Page 6 of 28 AD524 AD524C AD524S Parameter Min Typ Max Min Typ Max Unit REFERENCE INPUT R 40 40 kΩ ± 20% IN I 15 15 μA IN Voltage Range 10 10 V Gain to Output 1 1 % TEMPERATURE RANGE Specified Performance –25 +85 –55 +85 °C Storage –65 +150 –65 +150 °C POWER SUPPLY Power Supply Range ±6 ±15 ±18 ±6 ±15 ±18 V Quiescent Current 3.5 5.0 3.5 5.0 mA 1 Does not include effects of external resistor RG. 2 V is the maximum differential input voltage at G = 1 for specified nonlinearity. OL VDL at the maximum = 10 V/G. V = actual differential input voltage. D Example: G = 10, VD = 0.50. V = 12 V − (10/2 × 0.50 V) = 9.5 V. CM Rev. F | Page 7 of 28 AD524 ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAMS Table 3. 16 – INPUT 1 RG Parameter Rating 1 15 + INPUT 2 OUTPUT NULL Supply Voltage ±18 V RG 14 2 3 OUTPUT NULL Internal Power Dissipation 450 mW 1 4 AD524 13 INPUT NULL G = 10 SHORT TO Input Voltage TOP VIEW RG FOR 2 INPUT NULL 5 12 G = 100 (Not to Scale) (Either Input Simultaneously) |VIN| + |VS| <36 V DESIRED REFERENCE 6 11 GAIN G = 1000 Output Short-Circuit Duration Indefinite –V 7 10 SENSE S Storage Temperature Range +V S 8 9 OUTPUT (R) –65°C to +125°C (D, E) –65°C to +150°C 415 –V +V S S Operating Temperature Range 514 INPUT OUTPUT AD524A/AD524B/AD524C –25°C to +85°C OFFSET NULL OFFSET NULL AD524S –55°C to +125°C Figure 3. Ceramic (D) and Lead Temperature (Soldering, 60 sec) +300°C SOIC (RW-16 and D-16) Packages 1 Maximum input voltage specification refers to maximum voltage to which either input terminal may be raised with or without device power applied. For example, with ±18 volt supplies maximum, VIN is ±18 V; with zero supply voltage maximum, V is ±36 V. IN 3 2 1 20 19 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress 4 18 OUTPUT NULL RG 2 INPUT NULL 5 17 G = 10 rating only; functional operation of the device at these or any SHORT TO AD524 NC 6 16 NC RG FOR 2 other conditions above those indicated in the operational TOP VIEW DESIRED INPUT NULL 7 15 G = 100 (Not to Scale) GAIN section of this specification is not implied. Exposure to absolute REFERENCE 8 14 G = 1000 maximum rating conditions for extended periods may affect 9 10 11 12 13 device reliability. NC = NO CONNECT OUTPUT SENSE G = 10 G = 100 G = 1000 NULL 10 13 12 11 14 OUTPUT 719 NULL 9 +V –V 15 S S OUTPUT INPUT OUTPUT 518 8 +V S OFFSET NULL OFFSET NULL RG 16 1 Figure 4. Leadless Chip Carrier (E) 0.103 (2.61) –INPUT 1 +INPUT 2 ESD CAUTION 7 –V S RG 2 3 4 5 6 INPUT INPUT REFERENCE NULL NULL 0.170 (4.33) PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR THE D-16 AND RW-16 16-LEAD CERAMIC PACKAGES. Figure 2. Metallization Photograph Contact factory for latest dimensions; Dimensions shown in inches and (mm) Rev. F | Page 8 of 28 00500-002 –V +INPUT S +V –INPUT S NC NC RG OUTPUT 1 OUTPUT SENSE NULL 00500-003 00500-004 AD524 TYPICAL PERFORMANCE CHARACTERISTICS 20 8 15 6 10 4 +25°C 5 2 0 0 0 5 10 15 20 0 5 10 15 20 SUPPLY VOLTAGE (±V) SUPPLY VOLTAGE (±V) Figure 5. Input Voltage Range vs. Supply Voltage, G = 1 Figure 8. Quiescent Current vs. Supply Voltage 20 16 14 15 12 10 10 8 6 5 4 2 0 0 0 5 10 15 20 0 5 10 15 20 SUPPLY VOLTAGE (±V) SUPPLY VOLTAGE (±V) Figure 6. Output Voltage Swing vs. Supply Voltage Figure 9. Input Bias Current vs. Supply Voltage 30 40 30 20 20 10 0 –10 10 –20 –30 0 –40 10 100 1k 10k –75 –25 25 75 125 LOAD RESISTANCE (Ω) TEMPERATURE (°C) Figure 7. Output Voltage Swing vs. Load Resistance Figure 10. Input Bias Current vs. Temperature Rev. F | Page 9 of 28 OUTPUT VOLTAGE SWING (V p-p) OUTPUT VOLTAGE SWING (±V) INPUT VOLTAGE (±V) 00500-007 00500-006 00500-005 INPUT BIAS CURRENT (nA) INPUT BIAS CURRENT (±nA) QUIESCENT CURRENT (mA) 00500-008 00500-009 00500-010 AD524 16 –140 G = 1000 G = 100 14 –120 12 G = 10 –100 10 G = 1 –80 8 –60 6 –40 4 –20 2 0 0 0 5 10 15 20 0 10 100 1k 10k 100k 1M 10M INPUT VOLTAGE (±V) FREQUENCY (Hz) Figure 11. Input Bias Current vs. Input Voltage Figure 14. CMRR vs. Frequency, RTI, Zero to 1000 Source Imbalance 30 0 G = 1, 10, 100 1 20 2 3 4 10 5 BANDWIDTH LIMITED 6 G = 1000 G = 100 G = 10 0 02134576 8 1k 10k 100k 1M WARM-UP TIME (Minutes) FREQUENCY (Hz) Figure 12. Offset Voltage, RTI, Turn-On Drift Figure 15. Large Signal Frequency Response 10 8 1000 6 100 10 4 1 G = 1000 2 0 0 10 100 1k 10k 100k 1M 10M 1 10 100 1000 FREQUENCY (Hz) GAIN (V/V) Figure 13. Gain vs. Frequency Figure 16. Slew Rate vs. Gain Rev. F | Page 10 of 28 GAIN (V/V) ΔV FROM FINAL VALUE (µV) INPUT BIAS CURRENT (±nA) OS 00500-011 00500-012 00500-013 CMRR (dB) FULL POWER RESPONSE (V p-p) SLEW RATE (V/µs) 00500-016 00500-015 00500-014 G = 1 G = 10 G = 100 G = 10 G = 1 G = 100 G = 1000 G = 1000 AD524 160 100k +V = 15V DC + S 1V p-p SINEWAVE 140 120 10k 100 1k 80 60 100 40 20 0 0 1 10 100 1k 10k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 17. Positive PSRR vs. Frequency Figure 20. Input Current Noise vs. Frequency 160 0.1Hz TO 10Hz –V = –15V DC + S 1V p-p SINEWAVE 140 5mV 1s 120 100 80 60 40 20 0 10 100 1k 10k 100k FREQUENCY (Hz) VERTICAL SCALE; 1 DIVISION = 5µV Figure 18. Negative PSRR vs. Frequency Figure 21. Low Frequency Noise, G = 1 (System Gain = 1000) 1000 0.1Hz TO 10Hz 10mV 1s G = 1 100 G = 10 10 G = 100, 1000 G = 1000 1 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) VERTICAL SCALE; 1 DIVISION = 0.1µV Figure 19. RTI Noise Spectral Density vs. Gain Figure 22. Low Frequency Noise, G = 1000 (System Gain = 100,000) Rev. F | Page 11 of 28 POWER SUPPLY REJECTION RATIO (dB) POWER SUPPLY REJECTION RATIO (dB) VOLT NSD (nV/ Hz) 00500-019 00500-018 00500-017 CURRENT NOISE SPECTRAL DENSITY (fA/ Hz) 00500-022 00500-021 00500-020 AD524 –12 TO +12 1% 0.1% 0.01% –8 TO +8 1mV 10V 10µs –4 TO +4 OUTPUT STEP (V) +4 TO –4 +8 TO –8 1% 0.1% 0.01% +12 TO –12 0 5 10 15 20 SETTLING TIME (µs) Figure 23. Settling Time, Gain = 1 Figure 26. Large Signal Pulse Response and Settling Time, Gain = 10 –12 TO +12 0.1% 0.01% 1% –8 TO +8 1mV 10V 10µs –4 TO +4 OUTPUT STEP (V) +4 TO –4 +8 TO –8 1% 0.01% 0.1% +12 TO –12 0 5 10 15 20 SETTLING TIME (µs) Figure 24. Large Signal Pulse Response and Settling Time, Gain =1 Figure 27. Settling Time, Gain = 100 –12 TO +12 1% 0.1% 0.01% –8 TO +8 1mV 10V 10µs –4 TO +4 OUTPUT STEP (V) +4 TO –4 +8 TO –8 1% 0.1% 0.01% +12 TO –12 0 5 10 15 20 SETTLING TIME (µs) Figure 25. Settling Time, Gain = 10 Figure 28. Large Signal Pulse Response and Settling Time, Gain = 100 Rev. F | Page 12 of 28 00500-024 00500-025 00500-023 00500-028 00500-026 00500-027 AD524 –12 TO +12 1% 0.1% 0.01% –8 TO +8 5mV 10V 20µs –4 TO +4 OUTPUT STEP (V) +4 TO –4 +8 TO –8 1% 0.1% 0.01% +12 TO –12 0 1020 304050 607080 SETTLING TIME (µs) Figure 29. Settling Time, Gain = 1000 Figure 30. Large Signal Pulse Response and Settling Time, Gain = 1000 Rev. F | Page 13 of 28 00500-029 00500-030 AD524 TEST CIRCUITS 10kΩ 1kΩ 10kΩ 0.01% 10T 0.1% V INPUT OUT 100kΩ +V 20V p-p S 0.1% 1 – RG 8 1 16 G = 10 13 10 G = 100 12 AD524 9 11kΩ 1kΩ 100Ω G = 1000 6 0.1% 0.1% 0.1% 11 RG 2 3 7 2 + –V S Figure 31. Settling Time Test Circuit +V S I I 1 2 V B 50µA 50µA R52 A1 A2 20kΩ SENSE ++ R53 C3 C4 20kΩ A3 V R57 O CH , 2 20kΩ R56 R54 CH , CH 3 4 R55 –IN Q1, Q3 20kΩ Q2, Q4 20kΩ 20kΩ 4.44kΩ REFERENCE CH 1 CH , CH , RG 2 3 RG 1 2 404Ω CH 4 G = 100 +IN I 3 I 40Ω 4 50µA G = 1000 CH 50µA 1 –V S Figure 32. Simplified Circuit of Amplifier; Gain Is Defined as ((R56 + R57)/(R )) +1; For a Gain of 1, R Is an Open Circuit G G Rev. F | Page 14 of 28 00500-031 00500-032 AD524 THEORY OF OPERATION The AD524 is a monolithic instrumentation amplifier based from excessive currents. Standard practice is to place series on the classic 3-op amp circuit. The advantage of monolithic limiting resistors in each input, but to limit input current to construction is the closely matched components that enhance below 5 mA with a full differential overload (36 V) requires the performance of the input preamplifier. The preamplifier over 7kΩ of resistance, which adds 10 nV√Hz of noise. To section develops the programmed gain by the use of feedback provide both input protection and low noise, a special series concepts. The programmed gain is developed by varying the protection FET is used. value of R (smaller values increase the gain) while the feedback G A unique FET design was used to provide a bidirectional forces the collector currents (Q1, Q2, Q3, and Q4) to be constant, current limit, thereby protecting against both positive and which impresses the input voltage across RG. negative overloads. Under nonoverload conditions, three As RG is reduced to increase the programmed gain, the channels (CH2, CH3, CH4) act as a resistance (≈1 kΩ) in series transconductance of the input preamplifier increases to the with the input as before. During an overload in the positive transconductance of the input transistors. This has three direction, a fourth channel, CH1, acts as a small resistance important advantages. First, this approach allows the circuit (≈3 kΩ) in series with the gate, which draws only the leakage 8 to achieve a very high open-loop gain of 3 × 10 at a programmed current, and the FET limits I . When the FET enhances under DSS gain of 1000, thus reducing gain-related errors to a negligible a negative overload, the gate current must go through the small 30 ppm. Second, the gain bandwidth product, which is deter- FET formed by CH and when this FET goes into saturation, 1 mined by C3 or C4 and the input transconductance, reaches the gate current is limited and the main FET goes into controlled 25 MHz. Third, the input voltage noise reduces to a value enhancement. The bidirectional limiting holds the maximum determined by the collector current of the input transistors input current to 3 mA over the 36 V range. for an RTI noise of 7 nV/√Hz at G = 1000. INPUT OFFSET AND OUTPUT OFFSET INPUT PROTECTION Voltage offset specifications are often considered a figure of As interface amplifiers for data acquisition systems, instru- merit for instrumentation amplifiers. While initial offset may mentation amplifiers are often subjected to input overloads, be adjusted to zero, shifts in offset voltage due to temperature that is, voltage levels in excess of the full scale for the selected variations causes errors. Intelligent systems can often correct gain range. At low gains (10 or less), the gain resistor acts as a this factor with an autozero cycle, but there are many small- current limiting element in series with the inputs. At high gains, signal high-gain applications that do not have this capability. the lower value of R does not adequately protect the inputs G +V S 1 – 8 16 AD712 +V 10 s 13 10 16.2kΩ 100 12 AD524 9 3 + 1µF 8 1000 6 1/2 1 5 + 11 RG 2 – 2 1/2 7 1µF 9.09kΩ 3 – 4 7 6 2 + 1µF 16.2kΩ G = 1, 10, 100 –V –V G = 1000 S S 1kΩ 100Ω 1.82kΩ 1.62MΩ Figure 33. Noise Test Circuit Rev. F | Page 15 of 28 00500-033 AD524 Voltage offset and drift comprise two components each; input The AD524 can be configured for gains other than those that and output offset and offset drift. Input offset is the component are internally preset; there are two methods to do this. The first of offset that is directly proportional to gain, that is, input offset method uses just an external resistor connected between as measured at the output at G = 100 is 100 times greater than at Pin 3 and Pin 16 (see Figure 35), which programs the gain G = 1. Output offset is independent of gain. At low gains, output according to the following formula: offset drift is dominant, at high gains, input offset drift dominates. 40 kΩ R = Therefore, the output offset voltage drift is normally specified as G G=−1 drift at G = 1 (where input effects are insignificant), whereas For best results, RG should be a precision resistor with a low input offset voltage drift is given by drift specification at a high temperature coefficient. An external RG affects both gain gain (where output offset effects are negligible). All input accuracy and gain drift due to the mismatch between it and related numbers are referred to the input (RTI) that is the effect the internal thin-film resistors. Gain accuracy is determined on the output is G times larger. Voltage offset vs. power supply by the tolerance of the external R and the absolute accuracy G is also specified at one or more gain settings and is also RTI. of the internal resistors (±20%). Gain drift is determined by the By separating these errors, one can evaluate the total error mismatch of the temperature coefficient of RG and the tempera- independent of the gain setting used. In a given gain configura- ture coefficient of the internal resistors (−50 ppm/°C typical). tion, both errors can be combined to give a total error referred +V S to the input (RTI) or output (RTO) by the following formulas: 1 –INPUT 8 Total error RTI = input error + (output error/gain) RG 16 1 13 1.5kΩ 10 Total error RTO = (gain × input error) + output error 2.105kΩ 12 AD524 9 V OUT 6 1kΩ 11 As an illustration, a typical AD524 might have a +250 μV RG REFERENCE 2 3 7 output offset and a −50 μV input offset. In a unity gain 2 +INPUT 40,000 G = + 1 = 20 ±20% configuration, the total output offset would be 200 μV or 2.105 –V S the sum of the two. At a gain of 100, the output offset would Figure 35. Operating Connections for G = 20 be −4.75 mV or: +250 μV + 100(−50 μV) = −4.75 mV. The second method uses the internal resistors in parallel with The AD524 provides for both input and output offset adjustment. an external resistor (see Figure 36). This technique minimizes This simplifies very high precision applications and minimizes the gain adjustment range and reduces the effects of tempera- offset voltage changes in switched gain applications. In such ture coefficient sensitivity. applications, the input offset is adjusted first at the highest +V S programmed gain, then the output offset is adjusted at G = 1. 1 –INPUT 8 GAIN RG 16 1 G = 10 13 10 The AD524 has internal high accuracy pretrimmed resistors 4kΩ 12 V AD524 9 OUT 6 for pin programmable gains of 1, 10, 100, and 1000. One of the 11 RG REFERENCE preset gains can be selected by pin strapping the appropriate 2 3 7 2 +INPUT gain terminal and RG2 together (for G = 1, RG2 is not connected). 40,000 G = + 1 = 20 ±17% *R| = 4444.44Ω –V G = 10 4000||4444.44 S INPUT +V S *R| = 404.04Ω G = 100 OFFSET *R| = 40.04Ω NULL G = 1000 *NOMINAL (±20%) 8 1 10kΩ –INPUT 4 Figure 36. Operating Connections for G = 20, Low Gain RG 16 1 Temperature Coefficient Technique G = 10 13 5 10 G = 100 12 9 V AD524 OUT 6 G = 1000 11 RG 3 OUTPUT 2 7 SIGNAL 2 +INPUT COMMON –V S Figure 34. Operating Connections for G = 100 Rev. F | Page 16 of 28 00500-034 00500-036 00500-035 AD524 +V S The AD524 can also be configured to provide gain in the output 2 + stage. Figure 37 shows an H pad attenuator connected 8 3 to the reference and sense lines of the AD524. R1, R2, and R3 11 10 12 9 AD524 should be made as low as possible to minimize the gain variation 13 6 and reduction of CMRR. Varying R2 precisely sets the gain 16 7 LOAD 1 – without affecting CMRR. CMRR is determined by the match –V of R1 and R3. S TO POWER SUPPLY +V S GROUND R1 –INPUT 1 2.26kΩ Figure 40. Indirect Ground Returns for Bias Currents–AC-Coupled 8 16 RG 1 R2 G = 10 13 Although instrumentation amplifiers have differential inputs, 10 5kΩ 12 G = 100 9 V AD524 OUT there must be a return path for the bias currents. If this is not 6 G = 1000 11 R L provided, those currents charge stray capacitances, causing the RG 3 2 7 R3 2.26kΩ output to drift uncontrollably or to saturate. Therefore, when +INPUT 2 (R2||40kΩ) + R1 + R3 –V amplifying floating input sources such as transformers and S G = (R1 + R2 + R3)||R ≥ 2kΩ L (R2||40kΩ) thermocouples, as well as ac-coupled sources, there must still Figure 37. Gain of 2000 be a dc path from each input to ground. Table 4. Output Gain Resistor Values COMMON-MODE REJECTION Output Gain R2 R1, R3 Nominal Gain Common-mode rejection is a measure of the change in output 2 5 kΩ 2.26 kΩ 2.02 voltage when both inputs are changed equal amounts. These 5 1.05 kΩ 2.05 kΩ 5.01 specifications are usually given for a full-range input voltage 10 1 kΩ 4.42 kΩ 10.1 change and a specified source imbalance. Common-mode rejection ratio (CMRR) is a ratio expression whereas common- INPUT BIAS CURRENTS mode rejection (CMR) is the logarithm of that ratio. For Input bias currents are those currents necessary to bias the example, a CMRR of 10,000 corresponds to a CMR of 80 dB. input transistors of a dc amplifier. Bias currents are an In an instrumentation amplifier, ac common-mode rejection is additional source of input error and must be considered in only as good as the differential phase shift. Degradation of ac a total error budget. The bias currents, when multiplied by common-mode rejection is caused by unequal drops across the source resistance, appear as an offset voltage. What is of differing track resistances and a differential phase shift due concern in calculating bias current errors is the change in bias to varied stray capacitances or cable capacitances. In many current with respect to signal voltage and temperature. Input applications, shielded cables are used to minimize noise. This offset current is the difference between the two input bias technique can create common-mode rejection errors unless the currents. The effect of offset current is an input offset voltage shield is properly driven. Figure 41 and Figure 42 show active whose magnitude is the offset current times the source data guards that are configured to improve ac common-mode impedance imbalance. rejection by bootstrapping the capacitances of the input cabling, +V S thus minimizing differential phase shift. 2 + 8 +V S 3 –INPUT 11 10 1 – 8 12 AD524 9 G = 100 13 6 12 10 100Ω 16 7 9 AD524 V LOAD RG OUT 2 1 – 3 6 AD711 –V S +INPUT REFERENCE 7 TO POWER 2 + SUPPLY GROUND –V S Figure 38. Indirect Ground Returns for Bias Currents—Transformer Coupled Figure 41. Shield Driver, G ≥ 100 +V S +V S –INPUT 1 – 2 + RG 8 AD712 1 8 3 100Ω 16 11 10 10 AD524 12 9 12 AD524 9 V OUT 6 13 6 16 –V S 7 LOAD 3 REFERENCE 1 – 100Ω RG 2 7 2 + –V S +INPUT TO POWER –V S SUPPLY GROUND Figure 42. Differential Shield Driver Figure 39. Indirect Ground Returns for Bias Currents—Thermocouple Rev. F | Page 17 of 28 00500-039 00500-038 00500-037 00500-040 00500-042 00500-041 AD524 GROUNDING SENSE TERMINAL Many data acquisition components have two or more ground The sense terminal is the feedback point for the instrument pins that are not connected together within the device. These amplifier’s output amplifier. Normally, it is connected to the grounds must be tied together at one point, usually at the system instrument amplifier output. If heavy load currents are to be power-supply ground. Ideally, a single solid ground would be drawn through long leads, voltage drops due to current flowing desirable. However, because current flows through the ground through lead resistance can cause errors. The sense terminal can wires and etch stripes of the circuit cards, and because these be wired to the instrument amplifier at the load, thus putting paths have resistance and inductance, hundreds of millivolts can the IxR drops inside the loop and virtually eliminating this be generated between the system ground point and the data error source. acquisition components. Separate ground returns should be V+ (SENSE) OUTPUT provided to minimize the current flow in the path from the CURRENT V + 2 8 IN BOOSTER sensitive points to the system ground point. In this way, supply 10 3 currents and logic-gate return currents are not summed into the 9 X1 AD524 12 6 same return path as analog signals where they would cause R L 7 (REF) V – 1 IN measurement errors. V– Because the output voltage is developed with respect to the Figure 44. AD524 Instrumentation Amplifier with Output Current Booster potential on the reference terminal, an instrumentation amplifier can solve many grounding problems. Typically, IC instrumentation amplifiers are rated for a full ±10 volt output swing into 2 kΩ. In some applications, however, ANALOG P.S. DIGITAL P.S. the need exists to drive more current into heavier loads. +15V C –15V C +5V Figure 44 shows how a high current booster may be connected inside the loop of an instrumentation amplifier to provide the 0.1 0.1 0.1 0.1 1µF 1µF 1µF required current boost without significantly degrading overall µF µF µF µF performance. Nonlinearities and offset and gain inaccuracies of DIG 8 the buffer are minimized by the loop gain of the AD524 output COM 7 7 9 11 15 1 2 10 amplifier. Offset drift of the buffer is similarly reduced. AD583 DIGITAL 9 AD524 AD574A DATA SAMPLE 1 OUTPUT AND HOLD REFERENCE TERMINAL 6 The reference terminal can be used to offset the output by up to ANALOG OUTPUT SIGNAL GROUND* REFERENCE GROUND ±10 V. This is useful when the load is floating or does not share *IF INDEPENDENT; OTHERWISE, RETURN AMPLIFIER REFERENCE a ground with the rest of the system. It also provides a direct TO MECCA AT ANALOG P.S. COMMON. means of injecting a precise offset. It must be remembered that Figure 43. Basic Grounding Practice the total output swing is ±10 V to be shared between signal and reference offset. When the AD524 is of the 3-amplifier configuration it is necessary that nearly zero impedance be presented to the reference terminal. Any significant resistance from the reference terminal to ground increases the gain of the noninverting signal path, thereby upsetting the common-mode rejection of the AD524. In the AD524, a reference source resistance unbalances the CMR trim by the ratio of 20 kΩ/RREF. For example, if the reference source impedance is 1 Ω, CMR is reduced to 86 dB (20 kΩ/1 Ω = 86 dB). An operational amplifier can be used to provide that low impedance reference point, as shown in Figure 45. The input offset voltage characteristics of that amplifier adds directly to the output offset voltage performance of the instrumentation amplifier. Rev. F | Page 18 of 28 00500-043 00500-044 AD524 +V S SENSE 2 +INPUT + SENSE 10 V + 2 8 IN 3 R1 10 9 3 AD524 I L V 9 X AD524 13 6 12 6 –INPUT 1 – LOAD REF 7 REF V – 1 IN A2 AD711 –V S LOAD V V V 40,000 X IN OFFSET AD711 I = = =(1 + ) L R1 R1 R G Figure 45. Use of Reference Terminal to Provide Output Offset Figure 46. Voltage-to-Current Converter An instrumentation amplifier can be turned into a voltage- By establishing a reference at the low side of a current setting to-current converter by taking advantage of the sense and resistor, an output current may be defined as a function of input reference terminals, as shown in Figure 46. voltage, gain, and the value of that resistor. Because only a small current is demanded at the input of the buffer amplifier (A2) the forced current, IL, largely flows through the load. Offset and drift specifications of A2 must be added to the output offset and drift specifications of the AD524. 1 16 –IN PROTECTION OUTPUT G = 100 G = 10 G = 1000 OFFSET K2 K1 K3 +IN 2 PROTECTION 15 TRIM NC R2 +V S 10kΩ 3 14 INPUT 4.44kΩ OFFSET 4 13 TRIM R1 RELAY 20kΩ 20kΩ 10kΩ 404Ω SHIELDS 5 12 20kΩ 20kΩ 20kΩ 40Ω 6 11 +5V 20kΩ –V 7 10 S A1 K1 D1 K2 D2 K3 D3 OUT AD524 8 9 +V S 1µF C1 C2 35V INPUTS 16 16 A 1 1 K1 – K3 = GAIN ANALOG Y0 THERMOSEN DM2C RANGE B 2 15 2 COMMON 4.5V COIL Y1 D1 – D3 = IN4148 3 14 3 7407N 74LS138 Y2 BUFFER DECODER 13 4 4 DRIVER GAIN TABLE 10µF 5 5 AB GAIN 0 0 10 6 6 +5V 0 1 1000 1 0 100 7 7 1 1 1 LOGIC COMMON NC = NO CONNECT Figure 47. Three-Decade Gain Programmable Amplifier Rev. F | Page 19 of 28 00500-045 00500-046 00500-047 AD524 PROGRAMMABLE GAIN +INPUT 1 PROTECTION (–INPUT) Figure 47 shows the AD524 being used as a software program- 4.44kΩ AD524 G = 10 13 mable gain amplifier. Gain switching can be accomplished with 404Ω G = 100 12 V b 20kΩ mechanical switches such as DIP switches or reed relays. It should 40Ω 10 G = 1000 11 be noted that the on resistance of the switch in series with the 20kΩ 20kΩ 16 RG 1 9 V internal gain resistor becomes part of the gain equation and has OUT RG 3 2 20kΩ 20kΩ an effect on gain accuracy. 6 20kΩ The AD524 can also be connected for gain in the output stage. –INPUT 2 PROTECTION (+INPUT) Figure 48 shows an AD711 used as an active attenuator in the +V S output amplifier’s feedback loop. The active attenuation presents 1/2 17 3 AD712 very low impedance to the feedback resistors, therefore 2 4 DAC A minimizing the common-mode rejection ratio degradation. 14 DB0 DATA INPUTS 7 DB7 256:1 1 (+INPUT) CS 15 1 16 –IN PROTECTION AD7528 OUTPUT WR 16 OFFSET (–INPUT) 19 2 15 NULL +IN PROTECTION DAC A/DAC B 6 TO –V 20 +V S 18 DAC B R2 3 14 10kΩ 1/2 INPUT 5 AD712 4.44kΩ OFFSET 4 13 NULL 10kΩ 20kΩ 20kΩ 404Ω 5 12 20kΩ 20kΩ Figure 49. Programmable Output Gain Using a DAC 20kΩ 40Ω 6 11 – + Another method for developing the switching scheme is to 20kΩ –V S 7 10 AD524 use a DAC. The AD7528 dual DAC, which acts essentially as +V 8 9 V S OUT a pair of switched resistive attenuators having high analog 1µF linearity and symmetrical bipolar transmission, is ideal in this 35V 20kΩ application. The multiplying DAC’s advantage is that it can 10pF V V SS DD GND handle inputs of either polarity or zero without affecting the +V S 18 16 programmed gain. The circuit shown uses an AD7528 to set 2 – 15 39.2kΩ 1kΩ the gain (DAC A) and to perform a fine adjustment (DAC B). 13 14 + AD711 28.7kΩ 1kΩ 11 12 –V AUTOZERO CIRCUITS S 316kΩ 1kΩ 9 10 AD7590 In many applications, it is necessary to provide very accurate 34 5 67 data in high gain configurations. At room temperature, the V offset effects can be nulled by the use of offset trim potenti- DD A2 A3 A4 WR ometers. Over the operating temperature range, however, Figure 48. Programmable Output Gain offset nulling becomes a problem. The circuit of Figure 50 shows a CMOS DAC operating in bipolar mode and connected to the reference terminal to provide software controllable offset adjustments. Rev. F | Page 20 of 28 00500-048 00500-049 AD524 +V +V S S +10V +INPUT 2 + 8 8 10kΩ 16 RG 1 2 4 + 350Ω 350Ω G = 10 13 10 RG 16 1 5 G = 100 12 9 AD524 13 14-BIT 10 G = 100 ADC 6 9 11 12 AD524C G = 1000 0V TO 2V 350Ω 350Ω 6 F.S. 11 3 RG 2 7 3 RG –INPUT 1 – 2 7 1 – –V 39kΩ V S REF –V S –V S R3 AD589 +V S R5 20kΩ 20kΩ 15 14 16 C1 +V MSB Figure 52. Typical Bridge Application S 4 1/2 DATA OUT1 R4 AD712 LSB 1 2 – INPUTS 8 10kΩ ERROR BUDGET ANALYSIS 11 AD7524 1 6 – OUT2 12 7 CS 2 3 + To illustrate how instrumentation amplifier specifications are 1/2 5 4 + 13 WR R6 AD712 applied, review a typical case where an AD524 is required to 3 5kΩ –V S amplify the output of an unbalanced transducer. Figure 52 GND shows a differential transducer, unbalanced by 100 Ω, supplying Figure 50. Software Controllable Offset a 0 mV to 20 mV signal to an AD524C. The output of the I A In many applications, complex software algorithms for autozero feeds a 14-bit ADC with a 0 V to 2 V input voltage range. The applications are not available. For those applications, Figure 51 operating temperature range is −25°C to +85°C. Therefore, the provides a hardware solution. largest change in temperature, ΔT, within the operating range is +V from ambient to +85°C (85°C − 25°C = 60°C). S 2 In many applications, differential linearity and resolution are of 8 15 16 RG 1 16 prime importance in cases where the absolute value of a variable is 10 13 V 14 OUT 12 less important than changes in value. In these applications, only AD524 9 13 910 11 0.1µF LOW the irreducible errors (45 ppm = 0.004%) are significant. Further- 6 RG CH 2 LEAKAGE 3 7 more, if a system has an intelligent processor monitoring the 1 1kΩ analog-to-digital output, the addition of an autogain/autozero – –V S 12 11 cycle removes all reducible errors and may eliminate the require- + AD711 ment for initial calibration. This also reduces errors to 0.004%. V 8 DD V 1 AD7510KD SS 2 GND A1 A2 A3 A4 200µs ZERO PULSE Figure 51. Autozero Circuit Rev. F | Page 21 of 28 00500-051 00500-050 00500-052 – + AD524 Table 5. Error Budget Analysis Effect on Effect on Absolute Absolute Effect AD524C Accuracy Accuracy on Error Source Specifications Calculation at T = 25°C at T = 85°C Resolution A A Gain Error ±0.25% ±0.25% = 2500 ppm 2500 ppm 2500 ppm – Gain Instability 25 ppm (25 ppm/°C)(60°C) = 1500 ppm – 1500 ppm – Gain Nonlinearity ±0.003% ±0.003% = 30 ppm – – 30 ppm Input Offset Voltage ±50 μV, RTI ±50 μV/20 mV = ±2500 ppm 2500 ppm 2500 ppm – Input Offset Voltage Drift ±0.5 μV/°C (±0.5 μV/°C)(60°C) = 30 μV – 1500 ppm – – 30 μV/20 mV = 1500 ppm 1 Output Offset Voltage ±2.0 mV ±2.0 mV/20 mV = 1000 ppm 1000 ppm 1000 ppm – 1 Output Offset Voltage Drift ±25 μV/°C (±25 μV/°C)(60°C)= 1500 μV – 750 ppm – 1500 μV/20 mV = 750 ppm Bias Current-Source ±15 nA (±15 nA)(100 Ω ) = 1.5 μV 75 ppm 75 ppm – Imbalance Error 1.5 μV/20 mV = 75 ppm Bias Current-Source ±100 pA/°C (±100 pA/°C)(100 Ω )(60°C) = 0.6 μV – 30 ppm – Imbalance Drift 0.6 μV/20 mV = 30 ppm Offset Current-Source ±10 nA (±10 nA)(100 Ω ) = 1 μV 50 ppm 50 ppm – Imbalance Error 1 μV/20 mV = 50 ppm Offset Current-Source ±100 pA/°C (100 pA/°C)(100 Ω )(60°C) = 0.6 μV – 30 ppm – Imbalance Drift 0.6 μV/20 mV = 30 ppm Offset Current-Source ±10 nA (10 nA)(175 Ω ) = 3.5 μV 87.5 ppm 87.5 ppm – Resistance-Error 3.5 μV/20 mV = 87.5 ppm Offset Current-Source ±100 pA/°C (100 pA/°C)(175 Ω )(60°C) = 1 μV – 50 ppm – Resistance-Drift 1 μV/20 mV = 50 ppm Common Mode Rejection 5 V DC 115 dB 115 dB = 1.8 ppm × 5 V = 8.8 μV 444 ppm 444 ppm – 8.8 μV/20 mV = 444 ppm Noise, RTI (0.1 Hz to 10 Hz) 0.3 μV p-p 0.3 μV p-p/20 mV = 15 ppm – – 15 ppm Total Error 6656.5 ppm 10516.5 ppm 45 ppm 1 Output offset voltage and output offset voltage drift are given as RTI figures. Rev. F | Page 22 of 28 AD524 Figure 53 shows a simple application in which the variation Other thermocouple types may be accommodated with the of the cold-junction voltage of a Type J thermocouple-iron ± standard resistance values shown in Table 5. For other ranges constantan is compensated for by a voltage developed in series of ambient temperature, the equation in Figure 53 may be solved for the optimum values of R and R . by the temperature-sensitive output current of an AD590 T A semiconductor temperature sensor. The microprocessor controlled data acquisition system shown R A REFERENCE in Figure 54 includes both autozero and autogain capability. By NOMINAL JUNCTION +V TYPE VALUE S 7.5V +15°C < T < +35°C A dedicating two of the differential inputs, one to ground and one J 52.3Ω I A T 2.5V to the A/D reference, the proper program calibration cycles can K 41.2Ω A AD580 E 61.4Ω eliminate both initial accuracy errors and accuracy errors over G = 100 T 40.2Ω V AD590 A +V S temperature. The autozero cycle, in this application, converts a S, R 5.76Ω AD524 + R number that appears to be ground and then writes that same A IRON E O V 52.3Ω T CONSTANTAN CU number (8-bit) to the AD7524, which eliminates the zero error. – MEASURING Because its output has an inverted scale, the autogain cycle 8.66kΩ 52.3ΩI + 2.5V JUNCTION –V A S E = V – V + – 2.5V O T A R T converts the A/D reference and compares it with full scale. A 52.3Ω OUTPUT 1 + AMPLIFIER R 1kΩ ~ multiplicative correction factor is then computed and applied OR METER = V T to subsequent readings. NOMINAL VALUE 9135Ω For a comprehensive study of instrumentation amplifier Figure 53. Cold-Junction Compensation design and applications, refer to the Designer’s Guide to The circuit is calibrated by adjusting R for proper output T rd Instrumentation Amplifiers (3 Edition), available free from voltage with the measuring junction at a known reference Analog Devices, Inc. temperature and the circuit near 25°C. If resistors with low temperature coefficients are used, compensation accuracy is to within ±0.5°C, for temperatures between +15°C and +35°C. 2 + V REF AD583 16 RG 2 10 13 AD7507 V 12 AD524 9 AD574A IN 11 6 AGND RG 3 1 1 – –V REF A0, A2, 20kΩ EN, A1 20kΩ 10kΩ – – AD7524 + + 1/2 1/2 5kΩ AD712 AD712 DECODE LATCH CONTROL MICRO- PROCESSOR ADDRESS BUS Figure 54. Microprocessor Controlled Data Acquisition System Rev. F | Page 23 of 28 00500-053 00500-054 AD524 OUTLINE DIMENSIONS 0.005 (0.13) MIN 0.080 (2.03) MAX 16 9 0.310 (7.87) PIN 1 0.220 (5.59) 1 8 0.320 (8.13) 0.290 (7.37) 0.840 (21.34) MAX 0.060 (1.52) 0.200 (5.08) MAX 0.015 (0.38) 0.150 (3.81) 0.200 (5.08) MIN 0.015 (0.38) 0.125 (3.18) SEATING 0.100 0.070 (1.78) 0.008 (0.20) (2.54) PLANE 0.030 (0.76) 0.023 (0.58) BSC 0.014 (0.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 55. 16-Lead Side-Brazed Ceramic Dual In-Line [SBDIP] (D-16) Dimensions shown in inches and (millimeters) 0.200 (5.08) 0.075 (1.91) REF REF 0.100 (2.54) 0.100 (2.54) REF 0.064 (1.63) 0.095 (2.41) 0.015 (0.38) 0.075 (1.90) MIN 19 3 20 18 4 0.028 (0.71) 1 0.358 (9.09) 0.358 0.011 (0.28) 0.022 (0.56) (9.09) BOTTOM 0.342 (8.69) MAX 0.007 (0.18) VIEW SQ 0.050 (1.27) SQ R TYP 14 8 BSC 0.075 (1.91) 13 9 REF 45° TYP 0.088 (2.24) 0.055 (1.40) 0.150 (3.81) 0.054 (1.37) 0.045 (1.14) BSC CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 56. 20-Terminal Ceramic Leadless Chip Carrier [LCC] (E-20) Dimensions shown in inches and (millimeters) 10.50 (0.4134) 10.10 (0.3976) 16 9 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 8 10.00 (0.3937) 1.27 (0.0500) 45° BSC 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) 1.27 (0.0500) 0.33 (0.0130) PLANE 0.31 (0.0122) 0.40 (0.0157) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 57. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) Rev. F | Page 24 of 28 0.75 (0.0295) 0.25 (0.0098) 022106-A 032707-B AD524 ORDERING GUIDE Model Temperature Range Package Description Package Option AD524AD −40°C to +85°C 16-Lead SBDIP D-16 1 AD524ADZ −40°C to +85°C 16-Lead SBDIP D-16 AD524AE −40°C to +85°C 20-Terminal LCC E-20 AD524AR-16 −40°C to +85°C 16-Lead SOIC_W RW-16 AD524AR-16-REEL −40°C to +85°C 16-Lead SOIC_W, 13" Tape and Reel RW-16 AD524AR-16-REEL7 −40°C to +85°C 16-Lead SOIC_W, 7" Tape and Reel RW-16 1 AD524ARZ-16 −40°C to +85°C 16-Lead SOIC_W RW-16 1 AD524ARZ-16-REEL7 −40°C to +85°C 16-Lead SOIC_W, 7”Tape and Reel RW-16 AD524BD −40°C to +85°C 16-Lead SBDIP D-16 1 AD524BDZ −40°C to +85°C 16-Lead SBDIP D-16 AD524BE −40°C to +85°C 20-Terminal LCC E-20 AD524CD −40°C to +85°C 16-Lead SBDIP D-16 1 AD524CDZ −40°C to +85°C 16-Lead SBDIP D-16 AD524SD −55°C to +125°C 16-Lead SBDIP D-16 AD524SD/883B −55°C to +125°C 16-Lead SBDIP D-16 2 5962-8853901EA −55°C to +125°C 16-Lead SBDIP D-16 AD524SE/883B −55°C to +125°C 20-Terminal LCC E-20 AD524SCHIPS −55°C to +125°C Die 1 Z = RoHS Compliant Part. 2 Refer to the official DESC drawing for tested specifications. Rev. F | Page 25 of 28 AD524 NOTES Rev. F | Page 26 of 28 AD524 NOTES Rev. F | Page 27 of 28 AD524 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00500-0-11/07(F) Rev. F | Page 28 of 28