™ 16-Bit V nanoDAC OUT SPI Interface 2.7 V to 5.5 V, in an SOT-23 AD5061 FEATURES FUNCTIONAL BLOCK DIAGRAM V V Single 16-bit DAC, 4 LSB INL REF DD Power-on reset to midscale or zero-scale POWER-ON Guaranteed monotonic by design AD5061 BUF RESET 3 power-down functions OUTPUT BUFFER Low power serial interface with Schmitt-triggered inputs REF(+) DAC V Small 8-lead SOT-23 package, low power REGISTER DAC OUT Fast settling time of 4 μs typically 2.7 V to 5.5 V power supply AGND Low glitch on power-up INPUT POWER-DOWN CONTROL RESISTOR CONTROL LOGIC SYNC interrupt facility LOGIC NETWORK APPLICATIONS Process control SYNC SCLK DIN DACGND Data acquisition systems Figure 1. Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Table 1. Related Devices GENERAL DESCRIPTION Part No. Description The AD5061, a member of ADI’s nanoDAC family, is a low AD5062 2.7 V to 5.5 V, 16-bit nanoDAC D/A, power, single 16-bit buffered voltage-out DAC that operates 1 LSB INL, SOT-23 from a single 2.7 V to 5.5 V supply. The part offers a relative AD5063 2.7 V to 5.5 V, 16-bit nanoDAC D/A, accuracy specification of ±4 LSB and operation is guaranteed 1 LSB INL, MSOP monotonic with a ±1 LSB DNL specification. The part uses a AD5040/AD5060 2.7 V to 5.5 V, 14-bit/16-bit nanoDAC D/A, versatile 3-wire serial interface that operates at clock rates 1 LSB INL, SOT-23 up to 30 MHz, and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The reference for PRODUCT HIGHLIGHTS the AD5061 is supplied from an external V pin. A reference REF buffer is also provided on-chip. The part incorporates a power- 1. Available in a small 8-lead SOT-23 package. on reset circuit that ensures the DAC output powers up to mid- 2. 16-bit resolution, 4 LSB INL. scale or zero scale and remains there until a valid write takes 3. Low glitch on power-up. place to the device. The part contains a power-down feature that reduces the current consumption of the device to typically 4. High speed serial interface with clock speeds up to 30 MHz. 330 nA at 5 V and provides software-selectable output loads 5. Three power-down modes available to the user. while in power-down mode. The part is put into power-down 6. Reset to known output voltage (midscale or zero scale). mode over the serial interface. Total unadjusted error for the part is <3 mV. This part exhibits very low glitch on power-up. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 04762-001 AD5061 TABLE OF CONTENTS Features .............................................................................................. 1 Reference Buffer ......................................................................... 15 Applications....................................................................................... 1 Serial Interface ............................................................................ 15 Functional Block Diagram .............................................................. 1 Input Shift Register .................................................................... 15 General Description ......................................................................... 1 SYNC Interrupt .......................................................................... 15 Product Highlights ........................................................................... 1 Power-On to Zero-Scale or Midscale ...................................... 16 Revision History ............................................................................... 2 Software Reset............................................................................. 16 Specifications..................................................................................... 3 Power-Down Modes .................................................................. 16 Timing Characteristics..................................................................... 5 Microprocessor Interfacing....................................................... 16 Absolute Maximum Ratings............................................................ 6 Applications..................................................................................... 18 ESD Caution.................................................................................. 6 Choosing a Reference ................................................................ 18 Pin Configuration and Function Descriptions............................. 7 Bipolar Operation....................................................................... 18 Typical Performance Characteristics ............................................. 8 Using a Galvanically-Isolated Interface Chip ......................... 19 Terminology .................................................................................... 14 Power Supply Bypassing and Grounding................................ 19 Theory of Operation ...................................................................... 15 Outline Dimensions....................................................................... 20 DAC Architecture....................................................................... 15 Ordering Guide .......................................................................... 20 REVISION HISTORY 5/11—Rev. A to Rev. B Changes to Data Sheet Title and Product Highlights Section.... 1 Changes to Ordering Guide .......................................................... 20 1/06—Rev. 0 to Rev. A Changes to General Description .................................................... 1 Changes to Table 2............................................................................ 3 Changes to Figure 19 Caption....................................................... 10 Added Figure 28 to Figure 36........................................................ 12 Changes to Serial Interface Section.............................................. 15 Changes to Power-Down Modes Section .................................... 16 Changes to Ordering Guide .......................................................... 20 7/05—Revision 0: Initial Version Rev. B | Page 2 of 20 AD5061 SPECIFICATIONS VDD = 5.5 V, VREF = 4.096 V, RL = unloaded, CL= unloaded, TMIN to TMAX, unless otherwise specified. Table 2. 1 B Grade Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 16 Bits 2 Relative Accuracy (INL) ±0.5 ±4 LSB −40°C to +85°C, B grade ±0.5 ±4 −40°C to +125°C, Y grade Total Unadjusted Error (TUE) ±0.5 ±3.0 mV −40°C to +85°C, B grade ±0.5 ±3.0 −40°C to +125°C, Y grade Differential Nonlinearity (DNL) ±0.5 ±1 LSB Guaranteed monotonic, −40°C to +85°C, B grade ±0.5 ±1 Guaranteed monotonic, −40°C to +125°C, Y grade Gain Error ±0.01 ±0.05 % of FSR T = −40°C to +85°C, B grade A ±0.01 ±0.05 T = −40°C to +125°C , Y grade A Gain Error Temperature Coefficient 1 ppm of FSR/°C Offset Error ±0.02 ±3.0 mV TA = −40°C to + 85°C, B grade ±0.02 ±3.0 TA = −40°C to + 125°C, Y grade Offset Error Temperature Coefficient 0.5 μV/°C Full-Scale Error ±0.05 ±3.0 mV All 1s loaded to DAC register, T = −40°C to +85°C, B grade A ±0.05 ±3.0 All 1s loaded to DAC register, TA = −40°C to +125°C , Y grade 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 VREF V Output Voltage Settling Time 4 μs ¼ scale to ¾ scale code transition to ±1LSB, R = 5 KΩ L Output Noise Spectral Density 64 DAC code = midscale, 1 kHz nV/√Hz Output Voltage Noise 6 μV p-p DAC code = midscale , 0.1 Hz to 10 Hz bandwidth Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, RL = 5 KΩ Digital Feedthrough 0.003 nV-s DAC code = full-scale DC Output Impedance (Normal) 0.015 Ω Output impedance tolerance ±10% DC Output Impedance (Power-Down) (Output Connected to 1 kΩ Network) 1 kΩ Output impedance tolerance ±400 Ω (Output Connected to 100 kΩ Network) 100 kΩ Output impedance tolerance ±20 kΩ Capacitive Load Stability 1 nF Loads used: RL = 5 kΩ, RL = 100 kΩ, RL = ∞ Output Slew Rate 1.2 V/μs ¼ scale to ¾ scale code transition to ±1 LSB, R = 5 kΩ, C = 200 pF L L Short-Circuit Current 60 mA DAC code = full-scale, output shorted to GND, TA = 25°C 45 mA DAC code = zero-scale, output shorted to VDD, T = 25°C A DAC Power-Up Time Time to exit power-down mode to normal th mode of AD5061, 24 clock edge to 90% of DAC final value, output unloaded DC Power Supply Rejection Ratio −92 dB VDD ±10%, DAC code = full-scale Wideband Spurious-Free Dynamic Range −67 dB Output frequency = 10 kHz REFERENCE INPUT/OUTPUT 4 VREF Input Range 2 VDD − 50 mV Input Current (Power-Down) ±0.1 μA Zero-scale loaded Input Current (Normal) ±0.5 μA DC Input Impedance 1 MΩ Rev. B | Page 3 of 20 AD5061 1 B Grade Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS 5 Input Current ±1 ±5 μA Input Low Voltage (V) 0.8 V V = 4.5 V to 5.5 V IL DD 0.8 V = 2.7 V to 3.6 V DD Input High Voltage (VIH) 2.0 V VDD = 2.7 V to 5.5 V 1.8 VDD = 2.7 V to 3.6 V Pin Capacitance 4 pF POWER REQUIREMENTS VDD 2.7 5.5 V All digital inputs at 0 V or VDD IDD (Normal Mode) DAC active and excluding load current V = 2.7 V to 5.5 V 1.0 1.2 mA V = V and V = GND, V = 5.5 V, DD IN DD IL DD V = 4.096 V, code = midscale REF 0.89 VIN = VDD and VIL = GND, VDD = 3.0 V, VREF = 4.096 V, code = midscale IDD (All Power-Down Modes) V = 2.5 V to 5.5 V 1 μA V = V and V = GND, V = 5.5 V, DD IH DD IL DD V = 4.096 V, code = midscale REF 0.265 = V and V = GND, V = 3.0 V, VIH DD IL DD VREF = 4.096 V, code = midscale 1 Temperature range for B grade: −40°C to +85°C, typical at 25°C; temperature range for Y grade: −40°C to +125°C. 2 Linearity calculated using a reduced code range (160 to 65535). 3 Guaranteed by design and characterization, not production tested. 4 The typical output supply headroom performance for various reference voltages at −40°C can be seen in Figure 27. 5 Total current flowing into all pins. Rev. B | Page 4 of 20 AD5061 TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V, all specifications TMIN to TMAX unless otherwise specified. , Table 3. 1 Parameter Limit Unit Test Conditions/Comments 2 t1 33 ns min SCLK cycle time t 5 ns min SCLK high time 2 t 3 ns min SCLK low time 3 t 10 ns min SYNC to SCLK falling edge set-up time 4 t 3 ns min Data set-up time 5 t 2 ns min Data hold time 6 t 0 ns min SCLK falling edge to SYNC rising edge 7 t 12 ns min Minimum SYNC high time 8 t 9 ns min SYNC rising edge to next SCLK fall ignore 9 1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V ) and timed from a voltage level of (V + V )/2. DD IL IH 2 Maximum SCLK frequency is 30 MHz. t t t t 4 2 1 9 SCLK t t t 7 3 8 SYNC t 6 t 5 DIN D23 D22 D2 D1 D0 D23 D22 Figure 2. Timing Diagram Rev. B | Page 5 of 20 04762-002 AD5061 ABSOLUTE MAXIMUM RATINGS Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to GND −0.3 V to +7.0 V DD rating only; functional operation of the device at these or any Digital Input Voltage to GND −0.3 V to V + 0.3 V DD other conditions above those indicated in the operational V to GND −0.3 V to V + 0.3 V OUT DD section of this specification is not implied. Exposure to absolute VREF to GND −0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Operating Temperature Range device reliability. Industrial (B Grade) −40°C to + 85°C This device is a high performance integrated circuit with an Extended Automotive Temperature Range (Y Grade) −40°C to +125°C ESD rating of <2 kV, and is ESD-sensitive. Proper precautions Storage Temperature Range −65°C to +150°C should be taken for handling and assembly. Maximum Junction Temperature 150°C SOT-23 Package Power Dissipation (T max − T )/θ J A JA θ Thermal Impedance 206°C/W JA θ Thermal Impedance 44°C/W JC Reflow Soldering (Pb-Free) Peak Temperature 260°C Time-at-Peak Temperature 10 sec to 40 sec ESD 1.5 kV ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 6 of 20 AD5061 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 18 DIN SCLK AD5061 V27 DD TOP VIEW SYNC (Not to Scale) DACGND V36 REF V45 OUT AGND Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 DIN Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 2 V Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and V should be decoupled to GND. DD DD 3 V Reference Voltage Input. REF 4 VOUT Analog Output Voltage from DAC. 5 AGND Ground Reference Point for Analog Circuitry. 6 DACGND Ground Input to the DAC. 7 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 8 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. Rev. B | Page 7 of 20 04762-003 AD5061 TYPICAL PERFORMANCE CHARACTERISTICS 1.6 1.2 V = 5.5V, V = 4.096V T = 25°C DD REF A 1.4 1.0 V = 2.7V, V = 2.0V V = 5V, V = 4.096V DD REF DD REF 1.2 0.8 1.0 0.8 0.6 0.6 MAX DNL ERROR @ V = 2.7V DD 0.4 0.4 0.2 0.2 0 0 –0.2 MAX DNL ERROR @ V = 5.5V –0.2 DD –0.4 –0.4 –0.6 –0.8 –0.6 MIN DNL ERROR @ V = 2.7V –1.0 DD –0.8 MIN DNL ERROR @ V = 5.5V –1.2 DD –1.0 –1.4 –1.6 –1.2 160 10160 20160 30160 40160 50160 60160 –40 –20 0 20 40 60 80 100 120 140 DAC CODE TEMPERATURE (°C) Figure 4. Typical INL Plot Figure 7. DNL vs. Temperature 1.2 0.16 V = 5.5V, V = 4.096V T = 25°C DD REF A 0.14 1.0 V = 2.7V, V = 2.0V V = 5V, V = 4.096V DD REF DD REF 0.12 0.8 0.10 MAX TUE ERROR @ V = 2.7V DD 0.6 0.08 0.06 0.4 0.04 0.2 MAX TUE ERROR @ V = 5.5V 0.02 DD MIN TUE ERROR @ V = 5.5V 0 0 DD –0.02 –0.2 –0.04 –0.4 –0.06 MIN TUE ERROR @ V = 2.7V DD –0.6 –0.08 –0.10 –0.8 –0.12 –1.0 –0.14 –1.2 –0.16 –40 –20 0 20 40 60 80 100 120 140 160 10160 20160 30160 40160 50160 60160 DAC CODE TEMPERATURE (°C) Figure 8. TUE vs. Temperature Figure 5. Typical TUE Plot 1.6 1.6 V = 5.5V, V = 4.096V T = 25°C DD REF A 1.4 1.4 V = 2.7V, V = 2.0V V = 5V, V = 4.096V DD REF DD REF 1.2 1.2 1.0 1.0 MAX INL ERROR @ V = 2.7V DD 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 MAX INL ERROR @ V = 5.5V DD 0 0 MIN INL ERROR @ V = 5.5V DD –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 MIN INL ERROR @ V = 2.7V DD –0.8 –0.8 –1.0 –1.0 –1.2 –1.2 –1.4 –1.4 –1.6 –1.6 –40 –20 0 20 40 60 80 100 120 140 160 10160 20160 30160 40160 50160 60160 DAC CODE TEMPERATURE (°C) Figure 6. Typical DNL Plot Figure 9. INL vs. Temperature Rev. B | Page 8 of 20 DNL ERROR (LSB) TUE ERROR (mV) INL ERROR (LSB) 04762-006 04762-005 04762-004 INL ERROR (LSB) TUE ERROR (mV) DNL ERROR (LSB) 04762-090 04762-008 04762-007 AD5061 1.6 1.5 T = 25°C A V = 5.5V, V = 4.096V 1.4 1.4 DD REF V = 2.7V, V = 2.0V DD REF 1.2 1.3 CODE = FULL-SCALE 1.0 1.2 V = 5.5V 0.8 DD 1.1 0.6 1.0 0.4 MAX DNL ERROR @ V = 5.5V 0.9 DD 0.2 0.8 V = 2.7V DD 0 0.7 –0.2 0.6 MIN DNL ERROR @ V = 5.5V –0.4 DD 0.5 –0.6 0.4 –0.8 0.3 –1.0 0.2 –1.2 –1.4 0.1 –1.6 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –40 –20 0 20 40 60 80 100 120 140 REFERENCE VOLTAGE (V) TEMPERATURE (°C) Figure 13. Supply Current vs. Temperature Figure 10. DNL vs. Reference Input Voltage 1.2 3.00 T = 25°C T = 25°C A A 1.0 2.75 0.8 2.50 0.6 2.25 0.4 2.00 MAX TUE ERROR @ V = 5.5V 0.2 DD 1.75 0 1.50 V = 5.5V, V = 4.096V DD REF MIN TUE ERROR @ V = 5.5V DD –0.2 1.25 –0.4 1.00 –0.6 0.75 V = 3.0V, V = 2.5V DD REF –0.8 0.50 –1.0 0.25 –1.2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 10000 20000 30000 40000 50000 60000 70000 REFERENCE VOLTAGE (V) DAC CODE Figure 14. Supply Current vs. Digital Input Code Figure 11. TUE vs. Reference Input Voltage 2.0 1.6 T = 25°C A V = 2.5V REF 1.4 1.8 T = 25°C A 1.2 CODE = MIDSCALE 1.0 1.6 0.8 1.4 0.6 MAX INL ERROR @ V = 5.5V DD 0.4 1.2 0.2 1.0 0 –0.2 0.8 –0.4 MIN INL ERROR @ V = 5.5V DD –0.6 0.6 –0.8 0.4 –1.0 –1.2 0.2 –1.4 0 –1.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 REFERENCE VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 15. Supply Current vs. Supply Voltage Figure 12. INL vs. Reference Input Voltage Rev. B | Page 9 of 20 INL ERROR (LSB) TUE ERROR (mV) DNL ERROR (LSB) 04762-009 04762-011 04762-010 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 04762-015 04762-014 04762-013 AD5061 1.8 V = 5.5V, V = 4.096V DD REF CH3 = SCLK 1.6 V = 2.7V, V = 2.0V DD REF 1.4 1.2 1.0 0.8 OFFSET ERROR @ V = 5.5V DD 0.6 0.4 CH2 = V OUT 0.2 OFFSET ERROR @ V = 2.7V DD 0 –0.2 CH1 = TRIGGER –0.4 –0.6 CH1 2V/DIV CH2 2V/DIV CH3 2V TIME BASE = 5.00µs –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 16. Offset vs. Temperature Figure 19. Exiting Power-Down Time to Midscale V = 3V DD 24TH CLOCK FALLING DAC = FULL-SCALE V = 2.7V REF T = 25°C A CH1 = SCLK CH2 = V OUT Y AXIS = 2µV/DIV X AXIS = 4s/DIV CH2 50mV/DIV CH1 2V/DIV TIME BASE 400ns/DIV Figure 17. Digital-to-Analog Glitch Impulse; See Figure 21 Figure 20. 0.1 Hz to 10 Hz Noise Plot 300 V = 5V V = 5V DD DD V = 4.096V T = 25°C REF A T = 25°C V = 4.096V A REF 250 10ns/SAMPLE 200 150 FULL-SCALE 100 MIDSCALE ZERO-SCALE 50 0 0 50 100 150 200 250 300 350 400 450 500 100 1000 10000 100000 1000000 SAMPLES FREQUENCY (Hz) Figure 18. Output Noise Spectral Density Figure 21. Glitch Energy Rev. B | Page 10 of 20 OFFSET ERROR (mV) NOISE SPECTRAL DENSITY (nV/ Hz) 04762-017 04762-018 04762-012 AMPLITUDE (200µV/DIV) 04762-020 04762-019 04762-021 AD5061 0.10 V = 5.5V, V = 4.096V DD REF V = 2.7V, V = 2.0V 0.08 DD REF 0.06 0.04 CH1 = V DD GAIN ERROR @ V = 2.7V DD 0.02 0 GAIN ERROR @ V = 5.5V DD –0.02 CH2 = V –0.04 OUT –0.06 V = 5V V = 4.096V DD REF DD RAMP RATE = 200µs –0.08 T = 25°C A –0.10 CH1 2V/DIV CH2 1V/DIV TIME BASE = 100µs –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 22. Gain Error vs. Temperature Figure 25. Hardware Power-Down Glitch 16 CH1 = SCLK 14 12 CH2 = SYNC 10 8 6 CH3 = V OUT 4 V = 5V V = 4.096V 2 DD REF DD T = 25°C CH4 = TRIGGER A 0 CH1 2V/DIV CH2 2V/DIV CH3 20mV/DIV CH4 2V/DIV 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0.91 MORE TIME BASE 1µs/DIV BIN Figure 26. Exiting Software Power-Down Glitch Figure 23. IDD Histogram @ VDD = 3 V 0.50 14 0.45 12 0.40 10 0.35 0.30 8 0.25 6 0.20 0.15 4 0.10 2 0.05 0 0 2.72.93.13.33.53.73.94.14.34.54.74.95.1 5.3 5.5 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11 MORE REFERENCE VOLTAGE (V) BIN Figure 24. I Histogram @ V = 5 V DD DD Figure 27. VDD Headroom vs. Reference Voltage. Rev. B | Page 11 of 20 FREQUENCY FREQUENCY GAIN ERROR (%FSR) 04762-024 04762-023 04762-022 HEADROOM (V) 04762-026 04762-025 04762-091 AD5061 5.05 V = 5.0V DD T = 25°C C4 = 50mV p-p 5.00 A 1kΩ TO GND ZERO-SCALE DAC = FULL-SCALE 4.95 4.90 4.85 4.80 4.75 4.70 4.65 4.60 4.55 4.70 4.72 4.74 4.76 4.78 4.80 4.82 4.84 4.86 4.88 4.90 4.92 4.94 4.96 4.98 5.00 CH4 20.0mV M1.00µs CH1 1.64V V (V) REF Figure 28. Typical Output Voltage vs. Reference Voltage Figure 31. Typical Glitch upon Exiting Software Power-Down to Zero-Scale 5.005 V = 5V REF T = 25°C A 5.000 C2 25mV p-p 4.995 C3 T 4.96V p-p 2 4.990 C3 FALL 935.0µs 4.985 C3 RISE ∞s NO VALID T EDGE 4.980 3 4.975 5.50 5.45 5.40 5.35 5.30 5.25 5.20 5.15 5.10 5.05 5.00 CH3 2.00V CH2 50mV M1.00ms CH3 1.36V V (V) DD Figure 32. Typical Glitch upon Exiting Hardware Power-Down to Three State Figure 29. Typical Output Voltage vs. Supply Voltage C4 = 143mV p-p C2 ZERO-SCALE 1kΩ TO GND 30mV p-p C3 T 2 4.96V p-p C3 FALL ∞s NO VALID EDGE T C3 RISE 946.2µs 3 CH4 50.0mV M4.00µs CH1 1.64V CH3 2.00V CH2 50mV M1.00ms CH3 1.36V Figure 30. Typical Glitch upon Entering Software Power-Down to Zero-Scale Figure 33. Typical Glitch upon Entering Hardware Power-Down to Zero-Scale Rev. B | Page 12 of 20 DAC OUTPUT (V) DAC OUTPUT (V) 04762-047 04762-065 04762-042 04762-050 04762-049 04762-048 AD5061 0.0010 2.1 V = 5.5V DD CODE = MIDSCALE V = 4.096V 2.0 REF 0.0008 V = 5V, V = 4.096V DD REF 10% TO 90% RISE TIME = 0.688µs V = 3V, V = 2.5V DD REF SLEW RATE = 1.16V/µs 1.9 0.0006 2.04V 1.8 0.0004 1.7 0.0002 1.6 1.5 0 DAC 1.4 –0.0002 OUTPUT V = 5.5V DD 1.3 –0.0004 1.2 1.04V –0.0006 1.1 V = 3V DD –0.0008 1.0 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 –10µs –8µs –6µs –4µs –2µs 0 2µs 4µs 6µs 8µs 9.96µs CURRENT (mA) Figure 34. Typical Output Load Regulation Figure 36. Typical Output Slew Rate 0.10 CODE = MIDSCALE V = 5V, V = 4.096V 0.08 DD REF V = 3V, V = 2.5V DD REF 0.06 V = 3V, V = 2.5V DD REF 0.04 0.02 0 –0.02 –0.04 –0.06 V = 5V, V = 4.096V DD REF –0.08 –0.10 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 I (mA) OUT Figure 35. Typical Current Limiting Plot Rev. B | Page 13 of 20 ∆ VOLTAGE (V) ∆ V (V) OUT 04762-063 04762-051 04762-052 AD5061 TERMINOLOGY Relative Accuracy Total Unadjusted Error (TUE) For the DAC, relative accuracy or integral nonlinearity (INL) is Total unadjusted error is a measure of the output error taking a measure of the maximum deviation, in LSBs, from a straight all the various errors into account. A typical TUE vs. code plot line passing through the endpoints of the DAC transfer is shown in Figure 5. function. A typical INL vs. code plot is shown in Figure 4. Zero-Code Error Drift Differential Nonlinearity (DNL) This is a measure of the change in zero-code error with a Differential nonlinearity is the difference between the measured change in temperature. It is expressed in μV/°C. change and the ideal 1 LSB change between any two adjacent codes. Gain Error Drift A specified differential nonlinearity of ±1 LSB maximum ensures This is a measure of the change in gain error with changes in monotonicity. This DAC is guaranteed monotonic by design. A temperature. It is expressed in (ppm of full-scale range)/°C. typical AD5061 DNL vs. code plot is shown in Figure 6. Digital-to-Analog Glitch Impulse Zero-Code Error Digital-to-analog glitch impulse is the impulse injected into the Zero-code error is a measure of the output error when zero analog output when the input code in the DAC register changes code (0x0000) is loaded to the DAC register. Ideally, the output state. It is normally specified as the area of the glitch in nV-s should be 0 V. The zero-code error is always positive in the and is measured when the digital input code is changed by AD5061 because the output of the DAC cannot go below 0 V. 1 LSB at the major carry transition; see Figure 17 and Figure 21. This is due to a combination of the offset errors in the DAC and The expanded view in Figure 17 shows the glitch generated output amplifier. Zero-code error is expressed in mV. following completion of the calibration routine; Figure 21 Full-Scale Error zooms in on this glitch. Full-scale error is a measure of the output error when full-scale Digital Feedthrough code (0xFFFF) is loaded to the DAC register. Ideally, the output Digital feedthrough is a measure of the impulse injected into should be V − 1 LSB. Full-scale error is expressed in percent DD the analog output of the DAC from the digital inputs of the of full-scale range. DAC, but is measured when the DAC output is not updated. It Gain Error is specified in nV-s and measured with a full-scale code change This is a measure of the span error of the DAC. It is the devia- on the data bus; that is, from all 0s to all 1s, and vice versa. tion in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range. Rev. B | Page 14 of 20 AD5061 THEORY OF OPERATION The AD5061 is a single 16-bit, serial input, voltage output DAC. The write sequence begins by bringing the SYNC line low. Data It operates from supply voltages of 2.7 V to 5.5 V. Data is writ- from the DIN line is clocked into the 24-bit shift register on the ten to the AD5061 in a 24-bit word format, via a 3-wire serial falling edge of SCLK. The serial clock frequency can be as high interface. as 30 MHz, making these parts compatible with high speed DSPs. On the 24th falling clock edge, the last data bit is clocked The AD5061 incorporates a power-on reset circuit that ensures in and the programmed function is executed (that is, a change the DAC output powers up to zero-scale or midscale. The in the DAC register contents and/or a change in the mode of device also has a software power-down mode pin that reduces operation). the typical current consumption to less than 1 μA. At this stage, the SYNC line may be kept low or be brought DAC ARCHITECTURE high. In either case, it must be brought high for a minimum of The DAC architecture of the AD5061 consists of two matched 12 ns before the next write sequence so that a falling edge of DAC sections. A simplified circuit diagram is shown in SYNC SYNC can initiate the next write sequence. Because the Figure 37. The four MSBs of the 16-bit data word are decoded buffer draws more current when V = 1.8 V than it does when IH to drive 15 switches, E1 to E15. Each of these switches connects V = 0.8 V, should be idled low between write sequences IH SYNC one of 15 matched resistors to either DACGND or V buffer REF for an even lower power operation of the part. As previously output. The remaining 12 bits of the data word drive switches indicated, however, it must be brought high again just before S0 to S11 of a 12-bit voltage mode R-2R ladder network. the next write sequence. V OUT INPUT SHIFT REGISTER 2R 2R 2R 2R 2R 2R 2R The input shift register is 24 bits wide; see Figure 38. PD1 and S0 S1 S11 E1 E2 E15 PD0 are control bits that control which mode of operation the V REF part is in (normal mode or any one of three power-down modes). There is a more complete description of the various 12-BIT R-2R LADDER FOUR MSBs DECODED INTO modes in the Power-Down Modes section. The next 16 bits are 15 EQUAL SEGMENTS the data bits. These are transferred to the DAC register on the Figure 37. DAC Ladder Structure 24th falling edge of SCLK. REFERENCE BUFFER SYNC INTERRUPT The AD5061 operates with an external reference. The reference In a normal write sequence, the line is kept low for at SYNC input (VREF) has an input range of 2 V to VDD − 50 mV. This least 24 falling edges of SCLK and the DAC is updated on the input voltage is then used to provide a buffered reference for the 24th falling edge. However, if SYNC is brought high before the DAC core. 24th falling edge, this acts as an interrupt to the write sequence. SERIAL INTERFACE The shift register is reset and the write sequence is seen as The AD5061 has a 3-wire serial interface (SYNC, SCLK, and invalid. Neither an update of the DAC register contents nor a DIN), which is compatible with SPI, QSPI, and MICROWIRE change in the operating mode occurs; see Figure 41. interface standards, as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. DB15 (MSB) DB0 (LSB) 00 0 0 0 0 PD1PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS 0 0 NORMAL OPERATION 0 1 3-STATE 1 0 100kΩ TO GND POWER-DOWN MODES 1 1 1kΩ TO GND Figure 38. Input Register Contents Rev. B | Page 15 of 20 047762-027 04762-028 AD5061 OUTPUT BUFFER POWER-ON TO ZERO-SCALE OR MIDSCALE AD5061 V OUT DAC The AD5061 contains a power-on reset circuit that controls the output voltage during power-up. The DAC register is filled with the zero-scale or midscale code and the output voltage is zero- POWER-DOWN scale or midscale. It remains there until a valid write sequence is RESISTOR CIRCUITRY NETWORK made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. Figure 39. Output Stage During Power-Down SOFTWARE RESET The bias generator, the DAC core and other associated linear circuitry are all shut down when the power-down mode is The device can be put into software reset by setting all bits in activated. However, the contents of the DAC register are the DAC register to 1; this includes writing 1s to Bit D23 to unaffected when in power-down. The time to exit power-down Bit D16, which is not the normal mode of operation. Note that is typically 2.5 μs for VDD = 5 V, and 5 μs for VDD = 3 V; the SYNC interrupt command cannot be performed if a see Figure 19. software reset command is started. MICROPROCESSOR INTERFACING POWER-DOWN MODES AD5061-to-ADSP-2101/ADSP-2103 Interface The AD5061 contains four separate modes of operation. These modes are software-programmable by setting two bits (DB17 Figure 40 shows a serial interface between the AD5061 and the and DB16) in the control register. Table 6 shows how the state ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should of the bits corresponds to the mode of operation of the device. be set up to operate in the SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is programmed Table 6. Modes of Operation through the SPORT control register and should be configured DB17 DB16 Operating Mode as follows: internal clock operation, active low framing, 16-bit 0 0 Normal operation word length. Transmission is initiated by writing a word to the Power-down mode: Tx register after the SPORT has been enabled. 0 1 3-state 1 0 100 kΩ to GND ADSP-2101/ AD5061 1 ADSP-2103 1 1 1 kΩ to GND When both bits are set to 0, the part works normally with its TFS SYNC normal power consumption. However, for the three power- DT DIN down modes, the supply current falls to less than 1 μA at 5 V SCLK SCLK (265 nA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the 1 ADDITIONAL PINS OMITTED FOR CLARITY amplifier to a resistor network of known values. This has the Figure 40. AD5061-to-ADSP-2101/ADSP-2103 Interface advantage that the output impedance of the part is known while the part is in power-down mode. There are three different options. The output is connected internally to GND through a 1 kΩ resistor or a 100 kΩ resistor, or it is left open-circuited (3-state). The output stage is illustrated in Figure 39. SCLK SYNC DIN DB23 DB0 DB23 DB0 INVALID WRITE SEQUENCE: VALID WRITE SEQUENCE, OUTPUT UPDATES TH TH SYNC HIGH BEFORE 24 FALLING EDGE ON THE 24 FALLING EDGE Figure 41. SYNC Interrupt Facility Rev. B | Page 16 of 20 04762-029 04762-031 04762-030 AD5061 AD5061-to-80C51/80L51 Interface AD5061-to-68HC11/68L11 Interface Figure 44 shows a serial interface between the AD5061 and the Figure 42 shows a serial interface between the AD5061 and the 80C51/80L51 microcontroller. The setup for the interface is: 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 TxD of the 80C51/80L51 drives SCLK of the AD5061 while drives the SCLK pin of the AD5061, while the MOSI output RxD drives the serial data line of the part. The SYNC signal is drives the serial data line of the DAC. The SYNC signal is again derived from a bit-programmable pin on the port. In this derived from a port line (PC7). The set-up conditions for case, Port Line P3.3 is used. When data is to be transmitted to correct operation of this interface require that the 68HC11/ the AD5061, P3.3 is taken low. The 80C51/80L51 transmits data 68L11 be configured so that its CPOL bit is 0 and its CPHA bit only in 8-bit bytes; thus only eight falling clock edges occur in SYNC is 1. When data is being transmitted to the DAC, the line the transmit cycle. To load data to the DAC, P3.3 is left low after is taken low (PC7). When the 68HC11/68L11 is configured the first eight bits are transmitted, and a second write cycle is where its CPOL bit is 0 and its CPHA bit is 1, data appearing on initiated to transmit the second byte of data. P3.3 is taken high the MOSI output is valid on the falling edge of SCK. Serial data following the completion of this cycle. The 80C51/80L51 out- from the 68HC11/68L11 is transmitted in 8-bit bytes with only puts the serial data in a format that has the LSB first. The eight falling clock edges occurring in the transmit cycle. Data is AD5061 requires its data with the MSB as the first bit received. transmitted MSB first. To load data to the AD5061, PC7 is left The 80C51/80L51 transmit routine should take this into account. low after the first eight bits are transferred, a second serial write operation is performed to the DAC, and PC7 is taken high at 1 1 80C51/80L51 AD5061 the end of this procedure. 68HC11/ P3.3 SYNC 1 AD5061 1 68L11 TxD SCLK RxD DIN PC7 SYNC SCK SCLK 1 ADDITIONAL PINS OMITTED FOR CLARITY MOSI DIN Figure 44. AD5061-to-80C51/80L51 Interface 1 ADDITIONAL PINS OMITTED FOR CLARITY AD5061-to-MICROWIRE Interface Figure 42. AD5061-to-68HC11/68L11 Interface Figure 45 shows an interface between the AD5061 and any MICROWIRE-compatible device. Serial data is shifted out on AD5061-to-Blackfin® ADSP-BF53x Interface the falling edge of the serial clock and is clocked into the Figure 43 shows a serial interface between the AD5061 and the AD5061 on the rising edge of the SK. Blackfin ADSP-53x microprocessor. The ADSP-BF53x proces- sor family incorporates two dual-channel synchronous serial 1 1 AD5061 MICROWIRE ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5061, CS SYNC the setup for the interface is: DT0PRI drives the DIN pin of SK SCLK the AD5061, while TSCLK0 drives the SCLK of the part; the SO DIN SYNC is driven from TFS0. 1 1 1 ADDITIONAL PINS OMITTED FOR CLARITY ADSP-BF53x AD5061 Figure 45. AD5061-to-MICROWIRE Interface DT0PRI DIN TSCLK0 SCLK TFS0 SYNC 1 ADDITIONAL PINS OMITTED FOR CLARITY Figure 43. AD5061-to-Blackfin ADSP-BF53x Interface Rev. B | Page 17 of 20 04762-033 04762-032 04762-035 04762-034 AD5061 APPLICATIONS Table 7 shows examples of recommended precision references CHOOSING A REFERENCE for use as a supply to the AD5061. To achieve the optimum performance from the AD5061, thought should be given to the choice of a precision voltage Table 7. Precision References Part List for the AD5061 reference. The AD5061 has just one reference input, V . The REF Initial 0.1 Hz to Accuracy Temperature Drift 10 Hz Noise voltage on the reference input is used to supply the positive Part No. (mV max) (ppm/°C max) (μV p-p typ) input to the DAC. Therefore, any error in the reference is ADR435 ±2 3 (SO-8) 8 reflected in the DAC. ADR425 ±2 3 (SO-8) 3.4 There are four possible sources of error when choosing a vol- ADR02 ±3 3 (SO-8) 10 tage reference for high accuracy applications: initial accuracy, ADR02 ±3 3 (SC70) 10 ppm drift, long-term drift, and output voltage noise. Initial ADR395 ±5 9 (TSOT-23) 8 accuracy on the output voltage of the DAC leads to a full-scale error in the DAC. To minimize these errors, a reference with BIPOLAR OPERATION high initial accuracy is preferred. Also, choosing a reference The AD5061 has been designed for single-supply operation, but with an output trim adjustment, such as the ADR43x family, a bipolar output range is also possible using the circuit shown in allows a system designer to trim out system errors by setting a Figure 47. The circuit shown yields an output voltage range of reference voltage to a voltage other than the nominal. The trim ±5 V. Rail-to-rail operation at the amplifier output is achievable adjustment can also be used at the operating temperature to using an AD8675/AD820/AD8032 or an OP196/OP295. trim out any errors. The output voltage for any input code can be calculated as Because the supply current required by the AD5061 is follows: extremely low, the parts are ideal for low supply applications. The ADR395 voltage reference is recommended. This requires D R1+R2 R2 ⎡ ⎤ ⎛ ⎞ ⎛ ⎞ ⎛ ⎞ V = V × × −V × less than 100 μA of quiescent current and can, therefore, drive ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ O DD DD ⎢ ⎥ ⎝ 65536⎠ ⎝ R1 ⎠ ⎝ R1⎠ ⎣ ⎦ multiple DACs in one system, if required. It also provides very good noise performance at 8 μV p-p in the 0.1 Hz to 10 Hz range. where D represents the input code in decimal (0 to 65536). 7V With V = 5 V, R1 = R2 = 10 kΩ, REF 5V ADR395 10×D ⎛ ⎞ V = − 5 V ⎜ ⎟ O ⎝ 65536⎠ 3-WIRE SYNC V = 0V TO 5V OUT This is an output voltage range of ±5 V with 0x0000 correspond- SERIAL SCLK AD5061 ing to a −5 V output and 0xFFFF corresponding to a +5 V output. INTERFACE DIN R2 = 10kΩ +5V Figure 46. ADR395 as Reference to the AD5061 +5V R1 = 10kΩ – Long-term drift is a measure of how much the reference drifts AD820/ OP295 ±5V over time. A reference with a tight long-term drift specification + V BF ensures that the overall solution remains relatively stable during –5V V OUT V REF AD5061 its entire lifetime. The temperature coefficient of a reference’s 10µF 0.1µF output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce temperature dependence of the DAC output voltage on ambient conditions. 3-WIRE SERIAL In high accuracy applications, which have a relatively low noise INTERFACE budget, reference output voltage noise needs to be considered. It Figure 47. Bipolar Operation with the AD5061 is important to choose a reference with as low an output noise voltage as practical for the system noise resolution required. Precision voltage references, such as the ADR435, produce low output noise in the 0.1 Hz to 10 Hz region. Rev. B | Page 18 of 20 04762-036 04762-037 AD5061 USING A GALVANICALLY-ISOLATED INTERFACE POWER SUPPLY BYPASSING AND GROUNDING CHIP When accuracy is important in a circuit, it is helpful to carefully In process control applications in industrial environments, it is consider the power supply and ground return layout on the often necessary to use a galvanically-isolated interface to protect board. The printed circuit board containing the AD5061 should have separate analog and digital sections, each having its own and isolate the controlling circuitry from any hazardous area of the board. If the AD5061 is in a system where other common-mode voltages that may occur in the area where the devices require an AGND-to-DGND connection, then the DAC is functioning. iCoupler® provides isolation in excess of connection should be made at one point only. This ground 2.5 kV. Because the AD5061 uses a 3-wire serial logic interface, point should be as close as possible to the AD5061. the ADuM130x family provides an ideal digital solution for the DAC interface. The power supply to the AD5061 should be bypassed with 10 μF and 0.1 μF capacitors. The capacitors should be physically The ADuM130x isolators provide three independent isolation as close as possible to the device with the 0.1 μF capacitor channels in a variety of channel configurations and data rates. ideally right up against the device. The 10 μF capacitors are the They operate across the full range from 2.7 V to 5.5 V, providing tantalum bead type. It is important that the 0.1 μF capacitor has compatibility with lower voltage systems and enabling a voltage low effective series resistance (ESR) and effective series translation functionality across the isolation barrier. inductance (ESI), as do common ceramic types of capacitors. Figure 48 shows a typical galvanically-isolated configuration This 0.1 μF capacitor provides a low impedance path to ground using the AD5061. The power supply to the part also needs to for high frequencies caused by transient currents due to internal be isolated; this is accomplished by using a transformer. On the logic switching. DAC side of the transformer, a 5 V regulator provides the 5 V The power supply line itself should have as large a trace as supply required for the AD5061. possible to provide a low impedance path and reduce glitch 5V effects on the supply line. Clocks and other fast switching REGULATOR 10µF 0.1µF POWER digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals, if possible. When traces cross on opposite sides of the board, V DD ensure that they run at right angles to each other to reduce SCLK V1A V0A SCLK feedthrough effects through the board. The best board layout technique is the microstrip technique where the component ADuM130x AD5061 side of the board is dedicated to the ground plane only, and the signal traces are placed on the solder side. However, this is not V SDI V1B V0B SYNC OUT always possible with a 2-layer board. DATA V1C V0C DIN GND Figure 48. AD5061 with a Galvanically-Isolated Interface Rev. B | Page 19 of 20 04762-038 AD5061 OUTLINE DIMENSIONS 3.00 2.90 2.80 8 76 5 3.00 1.70 2.80 1.60 2.60 1.50 12 34 PIN 1 INDICATOR 0.65 BSC 1.95 BSC 1.30 1.15 0.90 0.22 MAX 1.45 MAX 0.08 MIN 0.95 MIN 0.60 0.15 MAX 8° 0.45 SEATING 0.60 0.05 MIN 4° 0.38 MAX 0.30 PLANE BSC 0° 0.22 MIN COMPLIANT TO JEDEC STANDARDS MO-178-BA Figure 49. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters ORDERING GUIDE Temperature Package Package 1 Model Range INL Description Description Option Branding AD5061BRJZ-1REEL7 −40°C to +85°C 4 LSB 2.7 V to 5.5 V, Reset to 0 V 8-Lead SOT-23 RJ-8 D43 AD5061BRJZ-1500RL7 −40°C to +85°C 4 LSB 2.7 V to 5.5 V, Reset to 0 V 8-Lead SOT-23 RJ-8 D43 AD5061BRJZ-2REEL7 −40°C to +85°C 4 LSB 2.7 V to 5.5 V, Reset to Midscale 8-Lead SOT-23 RJ-8 D44 AD5061BRJZ-2500RL7 −40°C to +85°C 4 LSB 2.7 V to 5.5 V, Reset to Midscale 8-Lead SOT-23 RJ-8 D44 AD5061YRJZ-1500RL7 −40°C to +125°C 4 LSB 2.7 V to 5.5 V, Reset to 0 V 8-Lead SOT-23 RJ-8 D6G AD5061YRJZ-1REEL7 −40°C to +125°C 4 LSB 2.7 V to 5.5 V, Reset to 0 V 8-Lead SOT-23 RJ-8 D6G EVAL-AD5061EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04762-0-5/11(B) Rev. B | Page 20 of 20 12-16-2008-A