Serial Input 16-Bit 4 mA–20 mA, 0 mA–20 mA DAC AD420 FEATURES FUNCTIONAL BLOCK DIAGRAM V CC 4 mA–20 mA, 0 mA–20 mA or 0 mA–24 mA current output V REFERENCE LL 16-bit resolution and monotonicity 4kΩ 40Ω REF OUT BOOST ±0.012% max integral nonlinearity AD420 ±0.05% max offset (trimmable) REF IN ±0.15% max total output error (trimmable) CLOCK DATA OUT I CLEAR OUT Flexible serial digital interface (3.3 MBPS) DATA I/P LATCH V REGISTER OUT 16-BIT SWITCHED On-Chip loop fault detection CLOCK DAC CURRENT 1.25kΩ DATA IN On-chip 5 V reference (25 ppm/°C max) SOURCES FAULT RANGE AND Asynchronous CLEAR function DETECT SELECT 1 FILTERING RANGE Maximum power supply range of 32 V SELECT 2 Output loop compliance of 0 V to V − 2.75 V CC OFFSET CAP 1 CAP 2 GND 24-Lead SOIC and PDIP packages TRIM Figure 1. GENERAL DESCRIPTION The AD420 is a complete digital to current loop output user desires temperature stability exceeding 25 ppm/°C, an converter, designed to meet the needs of the industrial control external precision reference such as the AD586 can be used as market. It provides a high precision, fully integrated, low cost the reference. The AD420 is available in a 24-lead SOIC and single-chip solution for generating current loop signals in a PDIP over the industrial temperature range of −40°C to +85°C. compact 24-lead SOIC or PDIP package. PRODUCT HIGHLIGHTS The output current range can be programmed to 4 mA to 1. The AD420 is a single chip solution for generating 4 mA to 20 mA, 0 mA to 20 mA or to an overrange function of 0 mA to 20 mA or 0 mA to 20 mA signals at the controller end of 24 mA. The AD420 can alternatively provide a voltage output from the current loop. a separate pin that can be configured to provide 0 V to 5 V, 0 V 2. The AD420 is specified with a power supply range from to 10 V, ±5 V, or ±10 V with the addition of a single external 12 V to 32 V. Output loop compliance is 0 V to V − 2.75 V. CC buffer amplifier. 3. The flexible serial input can be used in 3-wire mode The 3.3 M Baud serial input logic design minimizes the cost of with SPI® or MICROWIRE® microcontrollers, or in galvanic isolation and allows for simple connection to commonly asynchronous mode, which minimizes the number of used microprocessors. It can be used in 3-wire or asynchronous control signals required. mode and a serial-out pin is provided to allow daisy chaining of multiple DACs on the current loop side of the isolation barrier. 4. The serial data out pin can be used to daisy chain any number of AD420s together in 3-wire mode. The AD420 uses sigma-delta (Σ-Δ) DAC technology to achieve 16-bit monotonicity at very low cost. Full-scale settling to 0.1% 5. At power-up, the AD420 initializes its output to the low occurs within 3 ms. The only external components that are end of the selected range. required (in addition to normal transient protection circuitry) 6. The AD420 has an asynchronous CLEAR pin, which sends are two low cost capacitors which are used in the DAC out- the output to the low end of the selected range (0 mA, 4 mA, put filter. or 0 V). If the AD420 is used at extreme temperatures and supply 7. The AD420 BOOST pin accommodates an external voltages, an external output transistor can be used to minimize transistor to off-load power dissipation from the chip. power dissipation on the chip via the BOOST pin. The FAULT 8. The offset of ±0.05% and total output error of ±0.15% can DETECT pin signals when an open circuit occurs in the loop. be trimmed if desired, using two external potentiometers. The on-chip voltage reference can be used to supply a precision +5 V to external components in addition to the AD420 or, if the Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©1999–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 00494-001 AD420 TABLE OF CONTENTS Features .............................................................................................. 1  Driving Inductive Loads............................................................ 10  Functional Block Diagram .............................................................. 1  Voltage-Mode Output................................................................ 10  General Description ......................................................................... 1  Optional Span and Zero Trim .................................................. 10  Product Highlights ........................................................................... 1  Three-Wire Interface ................................................................. 11  Revision History ............................................................................... 2  Using Multiple DACS with Fault Detect ................................. 11  Specifications..................................................................................... 3  Asynchronous Interface Using Optocouplers ........................ 11  Absolute Maximum Ratings............................................................ 5  Microprocessor Interface............................................................... 12  ESD Caution.................................................................................. 5  AD420-To-MC68HC11 (SPI Bus) Interface........................... 12  Pin Configuration and Function Descriptions............................. 6  AD420 to Microwire Interface ................................................. 12  Timing Requirements ...................................................................... 7  External Boost Function ........................................................... 13  Three-Wire Interface ................................................................... 7  AD420 Protection........................................................................... 14  Three-Wire Interface Fast Edges on Digital Input................... 7  Transient Voltage Protection .................................................... 14  Asynchronous Interface............................................................... 7  Board Layout And Grounding ................................................. 14  Terminology ...................................................................................... 8  Power Supplies and Decoupling............................................... 14  Theory of Operation ........................................................................ 9  Outline Dimensions....................................................................... 15  Applications Information .............................................................. 10  Ordering Guide .......................................................................... 15  Current Output........................................................................... 10  REVISION HISTORY 1/11—Rev. G to Rev. H Changes to Figure 13...................................................................... 13 Changes to Ordering Guide .......................................................... 15 11/09—Rev. F to Rev. G Updated Format..................................................................Universal Changes to Table 2............................................................................ 5 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 9/99—Rev. E to Rev. F Rev. H | Page 2 of 16 AD420 SPECIFICATIONS TA = TMIN − TMAX, VCC = +24 V, unless otherwise noted. Table 1. AD420-32 Version Parameter Min Typ Max Units Comments RESOLUTION 16 Bits I CHARACTERISTICS R = 500 Ω OUT L Operating Current Ranges 4 20 mA 0 20 mA 0 24 mA Current Loop Voltage Compliance 0 VCC − 2.75 V V 1 Settling Time (to 0.1% of FS) 2.5 3 ms Output Impedance (Current Mode) 25 MΩ 2 Accuracy Monotonicity 16 Bits Integral Nonlinearity ±0.002 ±0.012 % Offset (0 mA or 4 mA) (T = +25°C) ±0.05 % A Offset Drift 20 50 ppm/° C Total Output Error (20 mA or 24 mA) (T = +25°C) ±0.15 % A Total Output Error Drift 20 50 ppm/° C 3 PSRR 5 10 μA/V V CHARACTERISTICS OUT FS Output Voltage Range (Pin 17) 0 5 V VOLTAGE REFERENCE REF OUT Output Voltage (TA = +25° C) 4.995 5.0 5.005 V Drift ±25 ppm/° C Externally Available Current 5 mA Short Circuit Current 7 mA REF IN Resistance 30 kΩ VLL Output Voltage 4.5 V Externally Available Current 5 mA Short Circuit Current 20 mA DIGITAL INPUTS V (Logic 1) 2.4 V IH V (Logic 0) 0.8 V IL I (V = 5.0 V) ±10 μA IH IN IIL (VIN = 0 V) ±10 μA Data Input Rate (3-Wire Mode) No Minimum 3.3 MBPS Data Input Rate (Asynchronous Mode) No Minimum 150 kBPS DIGITAL OUTPUTS FAULT DEFECT V (10 kΩ Pull-Up Resistor to V) 3.6 4.5 V OH LL V (10 kΩ Pull-Up Resistor to V) 0.2 0.4 V OL LL V @ 2.5 mA 0.6 V OL DATA OUT VOH (IOH = −0.8 mA) 3.6 4.3 V VOL (IOL = 1.6 mA) 0.3 0.4 V Rev. H | Page 3 of 16 AD420 AD420-32 Version Parameter Min Typ Max Units Comments POWER SUPPLY Operating Range V 12 32 V CC Quiescent Current 4.2 5.5 mA Quiescent Current (External V ) 3 mA LL TEMPERATURE RANGE Specified Performance −40 +85 °C 1 External capacitor selection must be as described in Figure 6. 2 Total Output Error includes Offset and Gain Error. Total Output Error and Offset Error are with respect to the Full-Scale Output and are measured with an ideal +5 V reference. If the internal reference is used, the reference errors must be added to the Offset and Total Output Errors. 3 PSRR is measured by varying VCC from 12 V to its maximum 32 V. Rev. H | Page 4 of 16 AD420 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Table 3. Truth Table V to GND 32 V Inputs CC I to GND V Range Range OUT CC CLEAR Select 2 Select 1 Operation Digital Inputs to GND −0.5 V to +7 V 0 X X Normal operation Digital Output to GND −0.5 V to VLL + 0.3 V 1 X X Output at bottom of VLL and REF OUT: Outputs Safe for span Indefinite Short to Ground X 0 0 0 V–5 V range Storage Temperature −65°C to +150°C X 0 1 4 mA–20 mA range Lead Temperature (Soldering, 10 sec) +300°C X 1 0 0 mA–20 mA range Lead Temperature, Soldering Reflow +260°C X 1 1 0 mA–24 mA range Thermal Impedance: SOIC (R) Package θJA = 75°C/W PDIP (N) Package θ = 50°C/W JA ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. H | Page 5 of 16 AD420 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 24 NC V V 2 23 LL CC FAULT DETECT 3 22 NC RANGE SELECT 2 4 21 CAP 2 RANGE SELECT 1 5 AD420 20 CAP 1 TOP VIEW CLEAR 6 19 BOOST (Not to Scale) LATCH 7 18 I OUT CLOCK 8 17 V OUT DATA IN 9 16 OFFSET TRIM DATA OUT 10 15 REF IN GND 11 14 REF OUT NC 12 13 NC NC = NO CONNECT Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Function 1, 12, NC No Connection. No internal connections inside device. 13, 24 2 VLL Auxiliary buffered +4.5 V digital logic voltage. This pin is the internal supply voltage for the digital circuitry and can be used as a termination for pull-up resistors. An external +5 V power supply can be connected to V . It will override this buffered voltage, thus reducing the internal power dissipation. The LL VLL pin should be decoupled to GND with a 0.1 μF capacitor. See the Power Supplies and Decoupling section. 3 FAULT DETECT FAULT DETECT, connected to a pull-up resistor, is asserted low when the output current does not match the DAC’s programmed value, for example, in case the current loop is broken. 4 RANGE SELECT 2 Selects the converter’s output operating range. One output voltage range and three 5 RANGE SELECT 1 output current ranges are available. 6 CLEAR Valid VIH unconditionally forces the output to go to the minimum of its programmed range. After CLEAR is removed the DAC output will remain at this value. The data in the input register is unaffected. 7 LATCH In the 3-wire interface mode a rising edge parallel loads the serial input register data into the DAC. To use the asynchronous mode connect LATCH through a current limiting resistor to V . CC 8 CLOCK Data Clock Input. The clock period is equal to the input data bit rate in the 3-wire interface mode and is 16 times the bit rate in asynchronous mode. 9 DATA IN Serial Data Input. 10 DATA OUT Serial Data Output. In the 3-wire interface mode, this output can be used for daisy-chaining multiple AD420s. In the asynchronous mode a positive pulse will indicate a framing error after the stop-bit is received. 11 GND Ground (Common). 14 REF OUT +5 V Reference Output. 15 REF IN Reference Input. 16 OFFSET TRIM Offset Adjust. 17 VOUT Voltage Output. 18 IOUT Current Output. 19 BOOST Connect to an external transistor to reduce the power dissipated in the AD420 output transistor, if desired. 20 CAP 1 These pins are used for internal filtering. Connect capacitors between each of these 21 CAP 2 pins and VCC. Refer to the description of current output operation. 22 NC No Connection. Do not connect anything to this pin. 23 VCC Power Supply Input. The V pin should always be decoupled to GND with a 0.1 μF capacitor. See the CC Power Supplies and Decoupling section. Rev. H | Page 6 of 16 00494-002 AD420 TIMING REQUIREMENTS T = −40°C to +85°C, V = +12 V to +32 V. A CC CLOCK THREE-WIRE INTERFACE 01001 DATA IN CLOCK WORD “N” WORD “N + 1” 101 1 0 0 1 00 111 0 0 1 1 1 0 0 1 DATA IN (INTERNALLY GENERATED LATCH) EXPANDED TIME VIEW BELOW LATCH CLOCK COUNTER STARTS HERE SAMPLE BIT 15 CONFIRM START BIT WORD “N – 1” WORD “N” DATA OUT 11 01 CLOCK 012 8 16 24 t CK t START BIT CL DATA BIT 15 BIT 14 DATA IN CLOCK t CH t DH t EXPANDED TIME VIEW BELOW DS t ACK DATA IN t ACL CLOCK t DW t ACH t LD t t ADS ADH t LL LATCH t ADW t LH DATA IN t SD DATA OUT Figure 4. Timing Diagram for Asynchronous Interface Figure 3. Timing Diagram for 3-Wire Interface Table 6. Timing Specifications for Asynchronous Interface Parameter Label Limit Units Table 5. Timing Specification for 3-Wire Interface Asynchronous Clock Period t 400 ns min ACK Parameter Label Limit Units Asynchronous Clock Low Time t 50 ns min ACL Data Clock Period tCK 300 ns min Asynchronous Clock High Time t 150 ns min ACH Data Clock Low Time t 80 ns min CL Data Stable Width (Critical Clock Edge) tADW 300 ns min Data Clock High Time t 80 ns min CH Data Setup Time (Critical Clock Edge) tADS 60 ns min Data Stable Width tDW 125 ns min Data Hold Time (Critical Clock Edge) tADH 20 ns min Data Setup Time tDS 40 ns min Clear Pulse Width t 50 ns min CLR Data Hold Time tDH 5 ns min Latch Delay Time t 80 ns min LD ASYNCHRONOUS INTERFACE Latch Low Time t 80 ns min LL Note that in the timing diagram for asynchronous mode oper- Latch High Time t 80 ns min LH ation each data word is framed by a START (0) bit and a STOP Serial Output Delay Time tSD 225 ns max (1) bit. The data timing is with respect to the rising edge of the Clear Pulse Width tCLR 50 ns min CLOCK at the center of each bit cell. Bit cells are 16 clocks long, and the first cell (the START bit) begins at the first clock THREE-WIRE INTERFACE FAST EDGES ON DIGITAL following the leading (falling) edge of the START bit. Thus, the INPUT MSB (D15) is sampled 24 clock cycles after the beginning of With a fast rising edge (<10 ns) on one of the serial inputs the START bit, D14 is sampled at clock number 40, and so on. (CLOCK, DATA IN, LATCH) while another input is logic high, During any dead time before writing the next word the DATA the part may be triggered into a test mode and the contents of IN pin must remain at Logic 1. the data register may become corrupted, which may result in the output being loaded with an incorrect value. If fast edges are The DAC output updates when the STOP bit is received. In expected on the digital input lines, it is recommended that the the case of a framing error (the STOP bit sampled as a 0) the latch line remain at Logic 0 during serial loading of the DAC. AD420 will output a pulse at the DATA OUT pin one clock Similarly, the clock line should remain low during updates of period wide during the clock period subsequent to sampling the STOP bit. The DAC output will not update if a framing the DAC via the latch pin. Alternatively, the addition of small error is detected. value capacitors on the digital lines will slow down the edge. Rev. H | Page 7 of 16 (MSB) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (LSB) B15 B15 B14 B14 B13 B13 B12 B12 00494-003 START BIT BIT15 BIT14 BIT13 TO BIT1 BIT0 STOP BIT NEXT START BIT 00494-004 AD420 TERMINOLOGY Gain Error Resolution Gain error is a measure of the output error between an ideal For 16-bit resolution, 1 LSB = 0.0015% of the FSR. In the DAC and the actual device output with all 1s loaded after offset 4 mA–20 mA range 1 LSB = 244 nA. error has been adjusted out. Integral Nonlinearity Offset Error Analog Devices defines integral nonlinearity as the maximum Offset error is the deviation of the output current from its ideal deviation of the actual, adjusted DAC output from the ideal value expressed as a percentage of the fullscale output with all analog output (a straight line drawn from 0 to FS – 1 LSB) for 0s loaded in the DAC. any bit combination. This is also referred to as relative accuracy. Drift Differential Nonlinearity Drift is the change in a parameter (such as gain and offset) over Differential nonlinearity is the measure of the change in the a specified temperature range. The drift temperature coefficient, analog output, normalized to full scale, associated with an LSB specified in ppm/°C, is calculated by measuring the parameter change in the digital input code. Monotonic behavior requires at T , 25°C, and T and dividing the change in the MIN MAX that the differential linearity error be greater than –1 LSB over parameter by the corresponding temperature change. the temperature range of interest. Current Loop Voltage Compliance Monotonicity The voltage compliance is the maximum voltage at the IOUT pin for A DAC is monotonic if the output either increases or remains which the output current will be equal to the programmed value. constant for increasing digital inputs with the result that the output will always be a single-valued function of the input. Rev. H | Page 8 of 16 AD420 THEORY OF OPERATION The AD420 uses a sigma-delta (Σ-Δ) architecture to carry out approximately one volt remaining of drive capability (when the digital-to-analog conversion. This architecture is particularly the gate of the output PMOS transistor nearly reaches ground). well suited for the relatively low bandwidth requirements of the Thus the FAULT DETECT output activates slightly before the industrial control environment because of its inherent compliance limit is reached. Since the comparison is made monotonicity at high resolution. within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain, and no output In the AD420 a second order modulator is used to keep com- error occurs before the fault detect output becomes active. plexity and die size to a minimum. The single bit stream from the modulator controls a switched current source that is then The 3-wire digital interface, comprising DATA IN, CLOCK, filtered by two, continuous time resistor-capacitor sections. and LATCH, interfaces to all commonly used serial micropro- The capacitors are the only external components that have to be cessors without the addition of any external glue logic. Data is added for standard current-out operation. The filtered current loaded into an input register under control of CLOCK and is is amplified and mirrored to the supply rail so that the application loaded to the DAC when LATCH is strobed. If a user wants to simply sees a 4 mA–20 mA, 0 mA–20 mA, or 0 mA–24 mA minimize the number of galvanic isolators in an intrinsically current source output with respect to ground. The AD420 safe application, the AD420 can be configured to run in is manufactured on a BiCMOS process that is well suited to asynchronous mode. This mode is selected by connecting the implementing low voltage digital logic with high performance LATCH pin to V through a current limiting resistor. The data CC and high voltage analog circuitry. must then be combined with a start and stop bit to frame the information and trigger the internal LATCH signal. The AD420 can also provide a voltage output instead of a current V CC loop output if desired. The addition of a single external amplifier 23 allows the user to obtain 0 V–5 V, 0 V–10 V, ±5 V, or ±10 V. V LL 2 REFERENCE 4kΩ 40Ω The AD420 has a loop fault detection circuit that warns if the 14 REF OUT 19 BOOST voltage at I attempts to rise above the compliance range, due OUT AD420 to an open-loop circuit or insufficient power supply voltage. The 15 REF IN 10 CLOCK FAULT DETECT is an active low open drain signal so that one DATA OUT I 18 OUT CLEAR 6 can connect several AD420s together to one pull-up resistor for DATA I/P 17 V OUT 7 LATCH SWITCHED REGISTER global error detection. The pull-up resistor can be tied to the 16-BIT CURRENT 1.25kΩ 8 CLOCK DAC SOURCES VLL pin, or an external +5 V logic supply. FAULT 9 DATA IN AND 3 DETECT FILTERING The I current is controlled by a PMOS transistor and an RANGE OUT 5 SELECT 1 internal amplifier as shown in the functional block diagram. RANGE 4 SELECT 2 The internal circuitry that develops the fault output avoids 16 20 21 11 using a comparator with window limits since this would require OFFSET CAP 1 CAP 2 GND TRIM an actual output error before the FAULT DETECT output Figure 5. Functional Block Diagram becomes active. Instead, the signal is generated when the internal amplifier in the output stage of the AD420 has less than Rev. H | Page 9 of 16 00494-005 AD420 APPLICATIONS INFORMATION CURRENT OUTPUT Table 7. Buffer Amplifier Configuration R1 R2 R3 V OUT The AD420 can provide 4 mA–20 mA, 0 mA–20 mA, or 0 mA– Open Open 0 0 V − 5 V 24 mA output without any active external components. Filter Open R R capacitors C1 and C2 can be any type of low cost ceramic R Open R ±5 V capacitors. To meet the specified full-scale settling time of 3 ms, R 2R 2R ±10 V low dielectric absorption capacitors (NPO) are required. Suitable values are C1 = 0.01 μF and C2 = 0.01 μF. Suitable R = 5 kΩ. V CC 0.1µF 0.1µF OPTIONAL SPAN AND ZERO TRIM V LL C1 C2 For users who would like lower than the specified values of 2 20 21 23 offset and gain error, Figure 8 shows a simple way to trim these RANGE 5 SELECT 1 parameters. Care should be taken to select low drift resistors RANGE 4 because they affect the temperature drift performance of SELECT 2 I (4mA TO 20mA) OUT 6 18 CLEAR the DAC. AD420 R LOAD 7 LATCH The adjustment algorithm is iterative. The procedure for 8 CLOCK trimming the AD420 in the 4 mA–20 mA mode can be 9 accomplished as follows: DATA IN 14 15 11 REF OUT REF IN GND 1. Offset adjust. Load all zeros. Adjust RZERO for 4.00000 mA of output current. Figure 6. Standard Configuration 2. Gain adjust. Load all ones. Adjust RSPAN for 19.99976 mA DRIVING INDUCTIVE LOADS (FS − 1 LSB) of output current. When driving inductive or poorly defined loads ,connect a 0.01 μF Return to Step I and iterate until convergence is obtained. capacitor between I (Pin 18) and GND (Pin 11). This ensures OUT V CC stability of the AD420 with loads beyond 50 mH. There is no V LL maximum capacitance limit. The capacitive component of the 0.1µF 0.1µF C1 C2 load may cause slower settling, though this may be masked by 5kΩ 2 20 21 23 RSPAN2 RANGE the settling time of the AD420. A programmed change in the 5 SELECT 1 current may cause a back EMF voltage on the output that may 19 BOOST RANGE 4 SELECT 2 exceed the compliance of the AD420. To prevent this voltage 6 I (4mA TO 20mA) CLEAR OUT AD420 from exceeding the supply rails connect protective diodes 18 LATCH 7 R LOAD between I and each of V and GND. OUT CC 8 CLOCK VOLTAGE-MODE OUTPUT 9 DATA IN 14 15 16 11 Since the AD420 is a single supply device, it is necessary to add REF OUT an external buffer amplifier to the V pin to obtain a selection OUT 500Ω RSPAN of bipolar output voltage ranges as shown in Figure 7. GND 10kΩ V CC RZERO 0.1µF V LL Figure 8. Offset and Gain Adjust 0.1µF C1 C2 Variation of RZERO between REF OUT (5 V) and GND leads 2 20 21 23 RANGE to an offset adjust range from −1.5 mA to 6 mA, (1.5 mA/V 5 SELECT 1 centered at 1 V). RANGE 4 SELECT 2 V OUT 6 17 CLEAR The 5 kΩ RSPAN2 resistor is connected in parallel with the AD420 V OUT 7 internal 40 W sense resistor, which leads to a gain increase of LATCH R3 +0.8%. 8 CLOCK R1 R2 9 As RSPAN is changed to 500 Ω, the voltage on REF IN is DATA IN 14 15 11 attenuated by the combination of RSPAN and the 30 kΩ REF IN REF OUT REF IN GND input resistance. When added together with RSPAN2 this Figure 7. results in an adjustment range of −0.8% to +0.8%. Rev. H | Page 10 of 16 00494-006 00494-007 00494-008 AD420 THREE-WIRE INTERFACE ASYNCHRONOUS INTERFACE USING OPTOCOUPLERS Figure 9 shows the AD420 connected in the 3-wire interface mode. The AD420 data input block contains a serial input shift The AD420 connected in asynchronous interface mode with register and a parallel latch. The contents of the shift register optocouplers is shown in Figure 10. Asynchronous operation are controlled by the DATA IN signal and the rising edges of the minimizes the number of control signals required for isolation CLOCK. Upon request of the LATCH pin the DAC and internal of the digital system from the control loop. The resistor connected latch are updated from the shift register parallel outputs. The between the LATCH pin and VCC is required to activate this CLOCK should remain inactive while the DAC is updated. mode. For operation with V below 18 V use a 50 kΩ pull-up CC Refer to the timing requirements for 3-wire interface. resistor; from 18 V to 32 V, use 100 kΩ. FAULT DETECT Asynchronous mode requires that the clock run at 16 times the data bit rate, therefore, to operate at the maximum input data rate AD420 AD420 V V CC V CC LL of 150 kBPS, an input clock of 2.4 MHz is required. The actual DAC1 DAC2 10kΩ FAULT FAULT V V data rate achieved may be limited by the type of optocouplers CC CC DETECT DETECT LATCH chosen. The number of control signals can be further reduced LATCH LATCH by creating the appropriate clock signal on the current loop CLOCK CLOCK CLOCK side of the isolation barrier. If optocouplers with relatively slow DATA IN DATA DATA DATA DATA IN OUT IN OUT rise and fall times are used, Schmitt triggers may be required on I I GND OUT GND OUT the digital inputs to prevent erroneous data being presented to R R LOAD LOAD the DAC. +24V Figure 9. Three-Wire Interface Using Multiple DACs with Joint Fault Detect V 23 CC AD420 100kΩ USING MULTIPLE DACS WITH FAULT DETECT 7 LATCH The 3-wire interface mode can utilize the serial DATA OUT for +5V 2 V LL easy interface to multiple DACs. To program the two AD420s in 8 Figure 9, 32 data bits are required. The first 16 bits are clocked CLOCK into the input shift register of DAC1. The next 16 bits CLOCK transmitted pass the first 16 bits from the DATA OUT pin of 9 DATA IN DAC1 to the input register of DAC2. The input shift registers of DATA the two DACs operate as a single 32-bit shift register, with the 11 GND leading 16 bits representing information for DAC2 and the GALVANIC ISOLATION trailing 16 bits serving for DAC1. Each DAC is then updated BARRIER upon request of the LATCH pin. The daisy-chain can be Figure 10. Asynchronous Interface Using Optocouplers extended to as many DACs as required. Rev. H | Page 11 of 16 00494-009 00494-010 AD420 MICROPROCESSOR INTERFACE The SPI data port is configured to process data in 8-bit bytes. AD420-TO-MC68HC11 (SPI BUS) INTERFACE The most significant data byte (MSBY) is retrieved from The AD420 interface to the Motorola serial peripheral interface memory and processed by the SENDAT routine. The SS pin is SS (SPI) is shown in Figure 11. The MOSI, SCK, and pins of the driven low by indexing into the PORTD data register and clear HC11 are respectively connected to the DATA IN, CLOCK, and Bit 5. The MSBY is then sent to the SPI data register where it is LATCH pins of the AD420. The majority of the interfacing automatically transferred to the AD420 internal shift resister. issues are done in the software initialization. A typical routine, The HC11 generates the requisite eight clock pulses with data such as the one shown below, begins by initializing the state of valid on the rising edges. After the MSBY is transmitted, the the various SPI data and control registers. least significant byte (LSBY) is loaded from memory and INIT LDAA #$2F SS ; = 1; SCK = 0; transmitted in a similar fashion. To complete the transfer, the MOSI = 1 LATCH pin is driven high when loading the complete 16-bit STAA PORTD ;SEND TO SPI OUTPUTS word into the AD420. LDAA #$38 SS ; , SCK, MOSI = MOSI DATA IN OUTPUTS 68HC11 SCK CLOCK AD420 ;SEND DATA DIRECTION STAA DDRD LATCH SS INFO LDAA #$50 ;DABL INTRPTS, SPI Figure 11. AD420-to-68HC11 (SPI) Interface IS MASTER & ON AD420 TO MICROWIRE INTERFACE STAA SPCR ;CPOL = 0, CPHA = 0, 1MHZ BAUDRATE The flexible serial interface of the AD420 is also compatible NEXTPT LDAA MSBY ;LOAD ACCUM W/UPPER with the National Semiconductor MICROWIRE interface. The 8 BITS MICROWIRE interface is used in microcontrollers such as the BSR SENDAT ;JUMP TO DAC OUTPUT COP400 and COP800 series of processors. A generic interface ROUTINE to use the MICROWIRE interface is shown in Figure 12. The JMP NEXTPT ;INFINITE LOOP G1, SK, and SO pins of the MICROWIRE interface are ;POINT AT ON-CHIP SENDAT LDY #$1000 respectively connected to the LATCH, CLOCK, and DATA IN REGISTERS pins of the AD420. BCLR $08,Y,$20 SS ;DRIVE (LATCH) LOW SO DATA IN MICROWIRE STAA SPDR ;SEND MS-BYTE TO SPI SK CLOCK AD420 DATA REG LATCH G1 ;CHECK STATUS OF WAIT1 LDAA SPSR Figure 12. AD420-to-MICROWIRE Interface SPIE BPL WAIT1 ;POLL FOR END OF X- MISSION LDAA LSBY ;GET LOW 8 BITS FROM MEMORY ;SEND LS-BYTE TO SPI STAA SPDR DATA REG WAIT2 LDAA SPSR ;CHECK STATUS OF SPIE BPL WAIT2; ;POLL FOR END OF X- MISSION BSET $08,Y,$20 SS ;DRIVE HIGH TO LATCH DATA RTS Rev. H | Page 12 of 16 00494-011 00494-012 AD420 transistor. The plot in Figure 14 shows the safe operating region EXTERNAL BOOST FUNCTION for both package types. The boost transistor can also be used to The external boost transistor reduces the power dissipated in reduce the amount of temperature induced drift in the part. the AD420 by reducing the current flowing in the on-chip This will minimize the temperature induced drift of the on-chip output transistor (dividing it by the current gain of the external voltage reference, which improves drift and linearity. circuit). A discrete NPN transistor with a breakdown voltage, WHEN USING SOIC PACKAGED DEVICES, BV , greater than 32 V can be used as shown in Figure 13. CEO V CC AN EXTERNAL BOOST TRANSISTOR IS REQUIRED FOR OPERATION IN THIS AREA. MJD31C OR 2N3053 19 BOOST 32V AD420 28V 18 I OUT 25V R LOAD 1kΩ 0.022µF 20V AD420 OR AD420-32 Figure 13. External Boost Configuration 12V The external boost capability has been developed for those users who may wish to use the AD420, in the SOIC package, at 4V the extremes of the supply voltage, load current, and temperature range. The PDIP package (because of its lower –60 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) thermal resistance) will operate safely over the entire specified Figure 14. Safe Operating Region voltage, temperature, and load current ranges without the boost Rev. H | Page 13 of 16 00494-013 00494-014 AD420 BOARD LAYOUT AND GROUNDING AD420 PROTECTION The AD420 ground pin, designated GND, is the high quality TRANSIENT VOLTAGE PROTECTION ground reference point for the device. Any external loads on the The AD420 contains ESD protection diodes, which prevent REF OUT and VOUT pins of the AD420 should be returned to damage from normal handling. The industrial control envir- this reference point. Analog and digital ground currents should onment can, however, subject I/O circuits to much higher not share a common path. Each signal should have an appropriate transients. To protect the AD420 from excessively high voltage analog or digital signal return routed close to it. Using this transients, such as those specified in IEC 801, external power approach, signal loops enclose a small area, minimizing the diodes and a surge current limiting resistor may be required, as inductive coupling of noise. Wide PC tracks, large gauge wire, shown in Figure 15. The constraint on the resistor is that during and ground planes are highly recommended to provide low normal operation the output voltage level at I must remain OUT impedance signal paths. within its voltage compliance limit POWER SUPPLIES AND DECOUPLING (I × (Rp + R ) ≤ V − 2.75 V) OUT LOAD CC The AD420 supply pins, VCC (Pin 23) and VLL (Pin 2), should be and the two protection diodes and resistor must have decoupled to GND with 0.1 μF capacitors to eliminate high appropriate power ratings. frequency noise that may otherwise get coupled into the analog V system. High frequency ceramic capacitors are recommended. CC The decoupling capacitors should be located in close proximity to the pins and the ground line to have maximum effect. Further V CC reductions in noise, and improvements in performance, may be R P AD420 I OUT achieved by using a larger value capacitor on the VLL pin. R LOAD GND Figure 15. Output Transient Voltage Protection Rev. H | Page 14 of 16 00494-015 AD420 OUTLINE DIMENSIONS 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 24 13 0.280 (7.11) 0.250 (6.35) 1 0.240 (6.10) 12 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) MAX 0.210 (5.33) 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) MIN 0.130 (3.30) GAUGE PLANE 0.014 (0.36) 0.115 (2.92) SEATING 0.010 (0.25) PLANE 0.008 (0.20) 0.022 (0.56) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 16. 24-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown in inches and (millimeters) 15.60 (0.6142) 15.20 (0.5984) 24 13 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 12 10.00 (0.3937) 45° 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 1.27 (0.0500) 0.51 (0.0201) 1.27 (0.0500) 0.33 (0.0130) PLANE BSC 0.31 (0.0122) 0.40 (0.0157) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 17. 24-Lead Standard Small Outline [SOIC_W] Wide Body (RW-24) Dimensions shown in millimeters and (inches) ORDERING GUIDE 1 Model Temperature Range Max Operating Voltage Package Description Package Option AD420AN-32 −40°C to +85° C 32 V 24-Lead PDIP N-24-1 AD420ANZ-32 −40°C to +85° C 32 V 24-Lead PDIP N-24-1 AD420AR-32 −40°C to +85° C 32 V 24-Lead SOIC_W RW-24 AD420AR-32-REEL −40°C to +85° C 32 V 24-Lead SOIC_W RW-24 AD420ARZ-32 −40°C to +85° C 32 V 24-Lead SOIC_W RW-24 AD420ARZ-32-REEL −40°C to +85° C 32 V 24-Lead SOIC_W RW-24 1 Z = RoHS Compliant Part. Rev. H | Page 15 of 16 0.75 (0.0295) 0.25 (0.0098) 071006-A 06-07-2006-A AD420 NOTES ©1999–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00494-0-1/11(H) Rev. H | Page 16 of 16