Dual-Channel, 12-Bit, 80 MSPS ADC with Analog Input Signal Conditioning AD13280 FEATURES APPLICATIONS Dual 80 MSPS, minimum sample rate Radar processing (optimized for I/Q baseband operation) Channel-to-channel matching, ±1% gain error Phased array receivers 90 dB channel-to-channel isolation Multichannel, multimode receivers DC-coupled signal conditioning GPS antijamming receivers 80 dB spurious-free dynamic range Communications receivers Selectable bipolar inputs (±1 V and ±0.5 V ranges) PRODUCT HIGHLIGHTS Integral single-pole, low-pass Nyquist filter 1. Guaranteed sample rate of 80 MSPS. Twos complement output format 2. Input signal conditioning; gain and impedance match. 3.3 V compatible outputs 3. Single-ended, differential, or off-module filter option. 1.85 W per channel 4. Fully tested/characterized full channel performance. FUNCTIONAL BLOCK DIAGRAM AMP-IN-B-2 AMP-IN-B-1 AMP-IN-A-2 AMP-IN-A-1 AMP-OUT-B AMP-OUT-A A–IN B+IN A+IN B–IN AD13280 DROUTA D0A (LSB) DROUTB D1A ENCODEB D2A TIMING ENCODEB D3A VREF VREF DROUT DROUT D4A D11B (MSB) D5A 12 12 D10B 9 5 D6A 100Ω OUTPUT TERMINATORS 100Ω OUTPUT TERMINATORS D9B D7A D8B 7 3 TIMING D8A D7B ENCODEA ENCODEA D0B D1B D2B D3B D4B D5B D6B D9A D10A D11A (LSB) (MSB) Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 02386-001 AD13280 TABLE OF CONTENTS Features .............................................................................................. 1 Input and Output Stages................................................................ 13 Applications....................................................................................... 1 Theory of Operation ...................................................................... 14 Product Highlights ........................................................................... 1 Using the Single-Ended Input .................................................. 14 Functional Block Diagram .............................................................. 1 Using the Differential Input...................................................... 14 Revision History ............................................................................... 2 Applications Information .............................................................. 15 General Description ......................................................................... 3 Encoding the AD13280 ............................................................. 15 Specifications..................................................................................... 4 Jitter Consideration.................................................................... 15 Timing Diagram ........................................................................... 6 Power Supplies............................................................................ 16 Absolute Maximum Ratings............................................................ 7 Output Loading .......................................................................... 16 Explanation of Test Levels........................................................... 7 Evaluation Board ............................................................................ 17 ESD Caution.................................................................................. 7 Layout Information.................................................................... 17 Pin Configuration and Function Descriptions............................. 8 Bill of Materials List for Evaluation Board.............................. 24 Typical Performance Characteristics ........................................... 10 Outline Dimensions....................................................................... 25 Terminology .................................................................................... 12 Ordering Guide .......................................................................... 26 REVISION HISTORY 4/08—Rev. B to Rev. C 8/02—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 25 Edits to Specifications.......................................................................2 Changes to the Ordering Guide.................................................... 26 Packages Updated........................................................................... 19 11/05—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Features and Product Highlights ............................... 1 Changes to General Description .................................................... 3 Changes to Table 1............................................................................ 4 Changes to Figure 3.......................................................................... 8 Changes to Theory of Operation.................................................. 14 Changes to Equation 1 ................................................................... 15 Changes to Table 5.......................................................................... 18 Changes to Figure 21...................................................................... 19 Changes to Figure 22...................................................................... 20 Changes to Figure 23...................................................................... 21 Changes to Figure 28 and Figure 29............................................. 24 Updated Outline Dimensions ....................................................... 25 Changes to the Ordering Guide.................................................... 26 Rev. C | Page 2 of 28 AD13280 GENERAL DESCRIPTION The AD13280 is a complete, dual-channel, signal processing signal ranges to further minimize additional external signal solution that includes on-board amplifiers, references, ADCs, and conditioning, while remaining general purpose. output termination components to provide optimized system The AD13280 operates with ±5.0 V for the analog signal condi- performance. The AD13280 has on-chip track-and-hold circuitry tioning with a separate 5.0 V supply for the analog-to-digital and uses an innovative multipass architecture to achieve 12-bit, 80 conversion and 3.3 V digital supply for the output stage. Each MSPS performance. The AD13280 uses innovative high density channel is completely independent, allowing operation with circuit design and laser-trimmed thin-film resistor networks to independent encode and analog inputs and maintaining achieve exceptional channel matching, impedance control, and minimal crosstalk and interference. performance while maintaining excellent isolation and The AD13280 is available in a 68-lead, ceramic gull wing package. providing for significant board area savings. The components are manufactured using the Analog Devices, Inc., Multiple options are provided for driving the analog input, high speed complementary bipolar process (XFCB). including single-ended, differential, and optional series fil- tering. The AD13280 also offers users a choice of analog input Rev. C | Page 3 of 28 AD13280 SPECIFICATIONS AVCC = +5 V, AVEE = −5 V, DVCC = +3.3 V; applies to each ADC with front-end amplifier, unless otherwise noted. Table 1. AD13280AZ Parameter Temperature Test Level Min Typ Max Unit RESOLUTION 12 Bits 1 DC ACCURACY No Missing Codes Full IV Guaranteed Offset Error 25°C I −2.2 ±1.0 +2.2 % FS Full VI −2.2 ±1.0 +2.2 % FS Offset Error Channel Match Full VI −1.0 ±0.1 +1.0 % 2 Gain Error 25°C I −3 −1.0 +1 % FS Full VI −5.0 ±2.0 +5.0 % FS Gain Error Channel Match 25°C I −1.5 ±0.5 +1.5 % Max VI −3.0 ±1.0 +3.0 % Min VI −5 ±1.0 +5 % SINGLE-ENDED ANALOG INPUT Input Voltage Range AMP-IN-X-1 Full V ±0.5 V AMP-IN-X-2 Full V ±1.0 V Input Resistance AMP-IN-X-1 Full IV 99 100 101 Ω AMP-IN-X-2 Full IV 198 200 202 Ω Capacitance 25°C V 4.0 7.0 pF 3 Analog Input Bandwidth Full V 143 MHz DIFFERENTIAL ANALOG INPUT Analog Signal Input Range 4 A+IN to A–IN and B+IN to B−IN Full V ±1 V Input Impedance 25°C V 618 Ω Analog Input Bandwidth Full V 50 MHz 1 ENCODE INPUT (ENCODE, ENCODE) Differential Input Voltage Full IV 0.4 V p-p Differential Input Resistance 25°C V 10 kΩ Differential Input Capacitance 25°C V 2.5 pF SWITCHING PERFORMANCE 5 Maximum Conversion Rate Full VI 80 MSPS 5 Minimum Conversion Rate Full IV 30 MSPS Aperture Delay (tA) 25°C V 0.9 ns Aperture Delay Matching 25°C IV 250 500 ps Aperture Uncertainty (Jitter) 25°C V 0.3 ps rms ENCODE Pulse Width High at Max Conversion Rate 25°C IV 4.75 6.25 8 ns ENCODE Pulse Width Low at Max Conversion Rate 25°C IV 4.75 6.25 8 ns Output Delay (tOD) Full V 5 ns Encode, Rising to Data Ready, Rising Delay Full V 8.5 ns 1, 6 SNR Analog Input @ 10 MHz 25°C I 66.5 70 dBFS Min II 64.5 dBFS Max II 66.3 dBFS Analog Input @ 21 MHz 25°C I 66.5 70 dBFS Min II 64 dBFS Max II 66.3 dBFS Rev. C | Page 4 of 28 AD13280 AD13280AZ Parameter Temperature Test Level Min Typ Max Unit Analog Input @ 37 MHz 25°C I 63 65 dBFS Min II 61.5 dBFS Max II 63 dBFS 1, 7 SINAD Analog Input @ 10 MHz 25°C I 66 69 dBFS Min II 63.5 dBFS Max II 66 dBFS Analog Input @ 21 MHz 25°C I 64 68.5 dBFS Min II 63 dBFS Max II 64 dBFS Analog Input @ 37 MHz 25°C I 54 59 dBFS Min II 53 dBFS Max II 54 dBFS 1, 8 SPURIOUS-FREE DYNAMIC RANGE Analog Input @ 10 MHz 25°C I 75 80 dBFS Min II 70 Max II 75 Analog Input @ 21 MHz 25°C I 68 75 dBFS Min II 67 Max II 67 Analog Input @ 37 MHz 25°C I 56 62 dBFS Min II 55 Max II 55 SINGLE-ENDED ANALOG INPUT Pass-Band Ripple to 10 MHz 25°C V 0.07 dB Pass-Band Ripple to 25 MHz 25°C V 0.12 dB DIFFERENTIAL ANALOG INPUT Pass-Band Ripple to 10 MHz 25°C V 0.3 dB Pass-Band Ripple to 25 MHz 25°C V 0.82 dB 9 TWO-TONE IMD REJECTION fIN = 9.1 MHz and 10.1 MHz (f1 and f2 are −7 dBFS) 25°C I 75 80 dBc Min II 71 Max II 74 f = 19.1 MHz and 20.7 MHz (f and f are −7 dBFS) 25°C V 77 dBc IN 1 2 f = 36 MHz and 37 MHz (f and f are −7 dBFS) 25°C V 60 dBc IN 1 2 10 CHANNEL-TO-CHANNEL ISOLATION 25°C IV 90 dB TRANSIENT RESPONSE 25°C V 25 ns 11 DIGITAL OUTPUTS Logic Compatibility CMOS DVCC = 3.3 V Logic 1 Voltage Full I 2.5 DV − 0.2 V CC Logic 0 Voltage Full I 0.2 0.5 V DV = 5 V CC Logic 1 Voltage Full V DVCC − 0.3 V Logic 0 Voltage Full V 0.35 V Output Coding Twos complement POWER SUPPLY 12 AVCC Supply Voltage Full IV 4.85 5.0 5.25 V I (AVCC) Current Full I 313 364 mA 12 AV Supply Voltage Full IV −5.25 −5.0 −4.75 V EE I (AV ) Current Full I 38 49 mA EE 12 DVCC Supply Voltage Full IV 3.135 3.3 3.465 V Rev. C | Page 5 of 28 AD13280 AD13280AZ Parameter Temperature Test Level Min Typ Max Unit I (DVCC) Current Full I 34 46 mA I (Total) Supply Current per Channel Full I 375 459 mA CC Power Dissipation (Total) Full I 3.7 4.3 W Power Supply Rejection Ratio (PSRR) Full V 0.01 % FSR/% VS 1 ENCODE All ac specifications tested by driving ENCODE and differentially. Single-ended input: AMP-IN-x-1 = 1 V p-p, AMP-IN-x-2 = GND. 2 Gain tests are performed on the AMP-IN-x-1 input voltage range. 3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 For differential input: +IN = 1 V p-p and −IN = 1 V p-p (signals are 180 Ω out of phase). For single-ended input: +IN = 2 V p-p and –IN = GND. 5 Minimum and maximum conversion rates allow for variation in encode duty cycle of 50% ± 5%. 6 Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 80 MSPS. SNR is reported in dBFS, related back to converter full scale. 7 Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 80 MSPS. SINAD is reported in dBFS, related back to converter full scale. 8 Analog input signal at –1 dBFS; SFDR is the ratio of converter full scale to worst spur. 9 Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third-order intermodulation product. 10 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel. 11 Digital output logic levels: DV = 3.3 V, C = 10 pF. Capacitive loads >10 pF degrades performance. CC LOAD 12 Supply voltage recommended operating range. AVCC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AV = 5.0 V to 5.25 V. CC TIMING DIAGRAM t A N + 3 N A IN N + 1 N + 2 N + 4 t t t ENC ENCH ENCL ENCODE, N N+1 N+2 N+3 N + 4 ENCODE t E_DR t OD D[11:0] N – 3 N – 2 N – 1 N DRY Figure 2. Rev. C | Page 6 of 28 02386-012 AD13280 ABSOLUTE MAXIMUM RATINGS Table 2. EXPLANATION OF TEST LEVELS Parameter Ratings I. 100% production tested. 1 ELECTRICAL AV Voltage 0 V to 7 V CC II. 100% production tested at 25°C, and sample tested AV Voltage −7 V to 0 V EE at specified temperatures. AC testing done on a DVCC Voltage 0 V to 7 V sample basis. Analog Input Voltage VEE to VCC III. Sample tested only. Analog Input Current −10 mA to +10 mA Digital Input Voltage (ENCODE) 0 to V CC IV. Parameter guaranteed by design and characterization ENCODE, ENCODE Differential Voltage 4 V max testing. Digital Output Current −10 mA to +10 mA 1 ENVIRONMENTAL V. Parameter is a typical value only. Operating Temperature Range (Case) −40°C to +85°C Maximum Junction Temperature 175°C VI. 100% production tested with temperature at 25°C, and Lead Temperature (Soldering, 10 sec) 300°C sample tested at temperature extremes. Storage Temperature Range (Ambient) −65°C to +150°C 1 Typical thermal impedance for ES package: θJC 2.2°C/W; θJA 24.3°C/W. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 7 of 28 AD13280 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 61 AGNDB 43 DGNDB 62 AMP-IN-B-2 42 D3B 63 AMP-IN-B-1 41 D2B AMP-OUT-B 64 40 D1B B+IN 65 39 D0B (LSB) B–IN 66 38 NC AGNDB 67 37 NC 68 AGNDB 36 AD13280 DROUTB 1 TOP VIEW SHIELD 35 SHIELD PIN 1 (Not to Scale) 2 AGNDA 34 DROUTA IDENTIFIER 3 AGNDA 33 D11A (MSB) 4 A–IN 32 D10A 5 A+IN 31 D9A AMP-OUT-A 6 30 D8A 7 AMP-IN-A-1 29 D7A 8 AMP-IN-A-2 28 D6A 9 AGNDA 27 DGNDA 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 NC = NO CONNECT Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1, 35 SHIELD Internal Ground Shield Between Channels. 2, 3, 9, 10, 13, 16 AGNDA A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. 4 A−IN Inverting Differential Input (Gain = +1). 5 A+IN Noninverting Differential Input (Gain = +1). 6 AMP-OUT-A Single-Ended Amplifier Output (Gain = +2). 7 AMP-IN-A-1 Analog Input for A Side ADC (Nominally ±0.5 V). 8 AMP-IN-A-2 Analog Input for A Side ADC (Nominally ±1.0 V). 11 AVEEA A Channel Analog Negative Supply Voltage (Nominally −5.0 V or −5.2 V). 12 AVCCA A Channel Analog Positive Supply Voltage (Nominally +5.0 V). 14 ENCODEA Complement of ENCODEA. Differential input. 15 ENCODEA Encode Input. Conversion initiated on rising edge. 17 DVCCA A Channel Digital Positive Supply Voltage (Nominally +5.0 V/+3.3 V). 18, 19, 37, 38 NC No Connect. 20 to 25, 28 to 33 D0A to Digital Outputs for ADC A. D0 (LSB). D11A 26, 27 DGNDA A Channel Digital Ground. 34 DROUTA Data Ready A Output. 36 DROUTB Data Ready B Output. 39 to 42, 45 to 52 D0B to Digital Outputs for ADC B. D0 (LSB). D11B 43, 44 DGNDB B Channel Digital Ground. 53 DVCCB B Channel Digital Positive Supply Voltage (Nominally +5.0 V/+3.3 V). Rev. C | Page 8 of 28 AGNDA AGNDB AV A AV B EE EE AV A AV B CC CC AGNDA AGNDB ENCODEA ENCODEB ENCODEA ENCODEB AGNDA AGNDB DV A CC DV B CC D11B (MSB) NC D10B NC D9B D0A (LSB) D1A D8B D7B D2A D3A D6B D4A D5B D5A D4B DGNDB DGNDA 02386-002 AD13280 Pin No. Mnemonic Description 54, 57, 60, 61, 67, 68 AGNDB B Channel Analog Ground. A and B grounds should be connected as close to the device as possible. 55 ENCODEB Encode Input. Conversion initiated on rising edge. 56 ENCODEB Complement of ENCODEB. Differential input. 58 AVCCB B Channel Analog Positive Supply Voltage (Nominally +5.0 V). 59 AVEEB B Channel Analog Negative Supply Voltage (Nominally −5.0 V or −5.2 V). 62 AMP-IN-B-2 Analog Input for B Side ADC (Nominally ±1.0 V). 63 AMP-IN-B-1 Analog Input for B Side ADC (Nominally ±0.5 V). 64 AMP-OUT-B Single-Ended Amplifier Output (Gain = +2). 65 B+IN Noninverting Differential Input (Gain = +1). 66 B−IN Inverting Differential Input (Gain = +1). Rev. C | Page 9 of 28 AD13280 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 ENCODE = 80MSPS ENCODE = 80MSPS –10 –10 A = 5MHz (–1dBFS) A = 10MHz (–1dBFS) IN IN –20 –20 SNR = 69.4dBFS SNR = 69.19dBFS SFDR = 81.9dBc SFDR = 79.55dBc –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 3 3 –80 –80 5 2 2 4 5 –90 6 –90 6 4 –100 –100 –110 –110 –120 –120 –130 –130 0 510 15 20 25 30 35 40 0 510 15 20 25 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. Single Tone @ 5 MHz Figure 7. Single Tone @ 10 MHz 0 0 ENCODE = 80MSPS ENCODE = 80MSPS –10 –10 A = 18MHz (–1dBFS) A = 37MHz (–1dBFS) IN IN –20 –20 SNR = 69.79dBFS SNR = 68.38dBFS SFDR = 57.81dBc SFDR = 76.81dBc –30 –30 –40 –40 –50 –50 2 3 –60 –60 –70 –70 –80 –80 5 –90 –90 6 4 –100 –100 –110 –110 –120 –120 –130 –130 0 510 15 20 25 30 35 40 0 510 15 20 25 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Single Tone @ 18 MHz Figure 8. Single Tone @ 37 MHz 0 0 ENCODE = 80MSPS ENCODE = 80MSPS –10 –10 A = 9MHz AND A = 19MHz AND IN IN –20 –20 10MHz (–7dBFS) 20MHz (–7dBFS) SFDR = 82.77dBc SFDR = 74.41dBc –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 0 510 15 20 25 30 35 40 0 510 15 20 25 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Two Tone @ 9 MHz and 10 MHz Figure 9. Two Tone @ 19 MHz and 20 MHz Rev. C | Page 10 of 28 dB dB dB 02386-005 02386-004 02386-003 dB dB dB 02386-008 02386-007 02386-006 AD13280 3.0 3 ENCODE = 80MSPS ENCODE = 80MSPS 2.5 DNL MAX = 0.688 CODES INL MAX = 0.562 CODES 2 DNL MIN = 0.385 CODES INL MIN = 0.703 CODES 2.0 1 1.5 1.0 0 0.5 –1 0 –2 –0.5 –1.0 –3 0 512 1024 1536 2048 2560 3072 3584 4096 512 1024 1536 2048 2560 3072 3584 4096 0 Figure 10. Differential Nonlinearity Figure 12. Integral Nonlinearity 0 –1 ENCODE = 80MSPS –2 ROLL-OFF = 0.0459dB –3 –4 –5 –6 –7 –8 –9 –10 1.0 3.5 6.0 8.5 11.0 13.5 16.0 18.5 21.0 23.5 26.0 FREQUENCY (MHz) Figure 11. Pass-Band Ripple to 25 MHz Rev. C | Page 11 of 28 LSB dBFS 02386-010 02386-009 LSB 02386-011 AD13280 TERMINOLOGY Analog Bandwidth Minimum Conversion Rate The analog input frequency at which the spectral power of the The encode rate at which the SNR of the lowest analog signal fundamental frequency (as determined by the FFT analysis) is frequency drops by no more than 3 dB below the guaranteed reduced by 3 dB. limit. Aperture Delay Maximum Conversion Rate The delay between a differential crossing of the ENCODEA The encode rate at which parametric testing is performed. ENCODEA signal and the signal and the instant at which the Output Propagation Delay analog input is sampled. The delay between a differential crossing of the ENCODEA signal and the ENCODEA signal and the time at which all Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. output data bits are within valid logic levels. Differential Analog Input Resistance, Differential Analog Overvoltage Recovery Time Input Capacitance, and Differential Analog Input Impedance The amount of time required for the converter to recover to The real and complex impedances measured at each analog 0.02% accuracy after an analog input signal of the specified input port. The resistance is measured statically, and the percentage of full scale is reduced to midscale. capacitance and differential input impedances are measured Power Supply Rejection Ratio with a network analyzer. The ratio of a change in input offset voltage to a change in Differential Analog Input Voltage Range power supply voltage. The peak-to-peak differential voltage that must be applied to Signal-to-Noise-and-Distortion (SINAD) the converter to generate a full-scale response. Peak differential The ratio of the rms signal amplitude (set at 1 dB below full voltage is computed by observing the voltage from the other scale) to the rms value of the sum of all other spectral compo- pin, which is 180 degrees out of phase. Peak-to-peak differential nents, including harmonics but excluding dc. SINAD can be is computed by rotating the input phase 180 degrees and taking reported in dB (that is, degrades as signal level is lowered) or the peak measurement again. The difference is then computed in dBFS (always related back to converter full scale). between both peak measurements. Signal-to-Noise Ratio (SNR) (Without Harmonics) Differential Nonlinearity The ratio of the rms signal amplitude (set at 1 dB below full The deviation of any code from an ideal 1 LSB step. scale) to the rms value of the sum of all other spectral com- ENCODE Pulse Width/Duty Cycle ponents, excluding the first five harmonics and dc. SNR can be Pulse width high is the minimum amount of time that the reported in dB (that is, degrades as signal level is lowered) or ENCODE pulse should be left in a Logic 1 state to achieve the in dBFS (always related back to converter full scale). rated performance. Pulse width low is the minimum time the Spurious-Free Dynamic Range (SFDR) ENCODE pulse should be left in a low state. At a given clock The ratio of the rms signal amplitude to the rms value of rate, these specifications define an acceptable encode duty cycle. the peak spurious spectral component. The peak spurious Harmonic Distortion component may or may not be a harmonic. The ratio of the rms signal amplitude to the rms value of the Transient Response worst harmonic component. The time required for the converter to achieve 0.02% accuracy Integral Nonlinearity when a one-half full-scale step function is applied to the analog The deviation of the transfer function from a reference line input. measured in fractions of 1 LSB using a best straight line Two-Tone Intermodulation Distortion Rejection determined by a least square curve fit. The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBc. Rev. C | Page 12 of 28 AD13280 INPUT AND OUTPUT STAGES LOADS AV AV AV AV CC CC CC CC 10kΩ 10kΩ ENCODE ENCODE 10kΩ 10kΩ AMP-IN-X-2 100Ω AMP-IN-X-1 TOAD8045 100Ω LOADS Figure 15. ENCODE Inputs Figure 13. Single-Ended Input Stage DV DV CC CC CURRENT MIRROR CURRENT MIRROR DV DV CC CC V REF V REF 100Ω DROUT D0–D11 CURRENT MIRROR CURRENT MIRROR Figure 14. DR Digital Output Stage Figure 16. Digital Output Stage Rev. C | Page 13 of 28 02386-013 02386-015 02386-016 02386-014 AD13280 THEORY OF OPERATION The AD13280 is a high dynamic range 12-bit, 80 MHz pipeline USING THE SINGLE-ENDED INPUT delay (three pipelines) analog-to-digital converter (ADC). The The AD13280 has been designed with user ease of operation in custom analog input section provides input ranges of 1 V p-p mind. Multiple input configurations have been included on- and 2 V p-p and input impedance configurations of 50 Ω, 100 Ω, board to allow the user a choice of input signal levels and input and 200 Ω. impedance. The standard inputs are ±0.5 V and ±1.0 V. The The AD13280 employs four monolithic Analog Devices com- user can select the input impedance of the AD13280 on any ponents per channel (AD8045, AD8138, AD8031, and a custom input by using the other inputs as alternate locations for the ADC IC), along with multiple passive resistor networks and GND. The following is a summary of the impedance options decoupling capacitors to fully integrate a complete 12-bit available at each input location: analog-to-digital converter (ADC). AMP-IN-x-1 = 100 Ω when AMP-IN-x-2 is open. In the single-ended input configuration, the input signal is passed AMP-IN-x-1 = 50 Ω when AMP-IN-x-2 is shorted to GND. through a precision laser-trimmed resistor divider, allowing the AMP-IN-x-2 = 200 Ω when AMP-IN-x-1 is open. user to externally select operation with a full-scale signal of ±0.5 V or ±1.0 V by choosing the proper input terminal for the applica- Each channel has two analog inputs: AMP-IN-A-1 and tion. The result of the resistor divider is to apply a full-scale AMP-IN-A-2 or AMP-IN-B-1 and AMP-IN-B-2. Use input of approximately 0.4 V to the noninverting input of the AMP-IN-A-1 or AMP-IN-B-1 when an input of ±0.5 V full internal AD8045 amplifier. scale is desired. Use AMP-IN-A-2 or AMP-IN-B-2 when ±1 V full scale is desired. Each channel has an AMP-OUT that must The AD13280 analog input includes an AD8045 amplifier be tied to either a noninverting or inverting input of a featuring an innovative architecture that maximizes the dynamic differential amplifier with the remaining input grounded. For range capability on the amplifier inputs and outputs. The AD8045 example, Side A, AMP-OUT-A (Pin 6) must be tied to A+IN amplifier provides a high input impedance and gain for driving the (Pin 5) with A−IN (Pin 4) tied to ground for noninverting AD8138 in a single-ended to differential amplifier configuration. operation or AMP-OUT-A (Pin 6) tied to A−IN (Pin 4) with The AD8138 has a −3 dB bandwidth at 300 MHz and delivers a A+IN (Pin 5) tied to ground for inverting operation. differential signal with the lowest harmonic distortion available in a differential amplifier. The AD8138 differential outputs help USING THE DIFFERENTIAL INPUT balance the differential inputs to the custom ADC, maximizing Each channel of the AD13280 is designed with two optional the performance of the device. differential inputs, A+IN, A−IN and B+IN, B−IN. The inputs The AD8031 provides the buffer for the internal reference provide system designers with the ability to bypass the AD8045 analog-to-digital converter. The internal reference voltage of amplifier and drive the AD8138 directly. The AD8138 differen- the custom ADC is designed to track the offsets and drifts and tial ADC driver can be deployed in either a single-ended or is used to ensure matching over an extended temperature range differential input configuration. The differential analog inputs of operation. The reference voltage is connected to the output have a nominal input impedance of 620 Ω and nominal full- common-mode input on the AD8138. This reference voltage scale input range of 1.2 V p-p. The AD8138 amplifier drives a sets the output common mode on the AD8138 at 2.4 V, which differential filter and the custom analog-to-digital converter. is the midsupply level for the ADC. The differential input configuration provides the lowest even- order harmonics and signal-to-noise (SNR) performance AIN The custom ADC has complementary analog input pins, improvement of up to 3 dB (SNR = 73 dBFS). Exceptional care and AIN. Each analog input is centered at 2.4 V and should was taken in the layout of the differential input signal paths. AIN swing ±0.55 V around this reference. Because AIN and are The differential input transmission line characteristics are 180 degrees out of phase, the differential analog input signal is matched and balanced. Equal attention to system level signal 2.2 V peak-to-peak. Both analog inputs are buffered prior to paths must be provided in order to realize significant perform- the first track-and-hold. ance improvements. The custom ADC digital outputs drive 100 Ω series resistors (see Figure 16). The result is a 12-bit, parallel digital CMOS- compatible word, coded as a twos complement. Rev. C | Page 14 of 28 AD13280 APPLICATIONS INFORMATION ENCODING THE AD13280 JITTER CONSIDERATION The AD13280 encode signal must be a high quality, extremely The signal-to-noise ratio for any ADC can be predicted. When low phase noise source to prevent degradation of performance. normalized to ADC codes, Equation 1 accurately predicts the Maintaining 12-bit accuracy at 80 MSPS places a premium on SNR based on three terms. These are jitter, average DNL error, encode clock phase noise. SNR performance can easily degrade and thermal noise. Each of these terms contributes to the noise 3 dB to 4 dB with 37 MHz input signals when using a high jitter within the converter. clock source. See Analog Devices Application Note AN-501, 1/ 2 2 2 ⎡ ⎤ V 1+ε ⎛ ⎞ Aperture Uncertainty and ADC System Performance, for com- ⎡ ⎤ NOISErms 2 ⎜ ⎟ SNR=− 20× log⎢ +() 2×π× f ×t + ⎥ ANALOG J rms ⎢ N ⎥ ⎜ N ⎟ 2 2 plete details. For optimum performance, the AD13280 must be ⎣ ⎦ ⎢ ⎥ ⎝ ⎠ ⎣ ⎦ clocked differentially. The encode signal is usually ac-coupled (1) ENCODE into the ENCODE and pins via a transformer or where: capacitors. These pins are biased internally and require no f is the analog input frequency. ANALOG additional bias. t is the rms jitter of the encode (rms sum of encode source J rms Figure 17 shows one preferred method for clocking the AD13280. and internal encode circuitry). The clock source (low jitter) is converted from single-ended to ε is the average DNL of the ADC (typically 0.50 LSB). differential using an RF transformer. The back-to-back Schottky N is the number of bits in the ADC. diodes across the transformer secondary limit clock excursions VNOISE rms is the analog input of the ADC (typically 5 LSB). into the AD13280 to approximately 0.8 V p-p differential. This For a 12-bit analog-to-digital converter like the AD13280, helps prevent the large voltage swings of the clock from feeding aperture jitter can greatly affect the SNR performance as the through to the other portions of the AD13280 and limits the analog frequency is increased. The chart below shows a family noise presented to the ENCODE inputs. A crystal clock of curves that demonstrates the expected SNR performance of oscillator can also be used to drive the RF transformer if an the AD13280 as jitter increases. The chart is derived from appropriate limited resistor (typically 100 Ω) is placed in series Equation 1. with the primary. For a complete discussion of aperture jitter, consult Analog 0.1µF T1-4T 100Ω CLOCK ENCODE Devices Application Note AN-501, Aperture Uncertainty and SOURCE AD13280 ADC System Performance. ENCODE 71 HSMS2812 A = 5MHz IN DIODES 70 69 Figure 17. Crystal Clock Oscillator—Differential Encode 68 A = 10MHz IN 67 If a low jitter ECL/PECL clock is available, another option is to 66 65 ac-couple a differential ECL/PECL signal to the encode input A = 20MHz IN 64 pins as shown below. A device that offers excellent jitter per- 63 formance is the MC100LVEL16 (or within the same family) 62 from Motorola. 61 VT 60 A = 37MHz IN 0.1µF 59 ENCODE 58 AD13280 ECL/PECL CLOCK JITTER (ps) ENCODE 0.1µF Figure 19. SNR vs. Jitter VT Figure 18. Differential ECL for Encode Rev. C | Page 15 of 28 02386-018 02386-017 SNR (–dBFS) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 02386-019 AD13280 POWER SUPPLIES OUTPUT LOADING Care should be taken when selecting a power source. Linear Care must be taken when designing the data receivers for the supplies are strongly recommended. Switching supplies tend AD13280. The digital outputs drive an internal series resistor to have radiated components that may be received by the (for example, 100 Ω) followed by a gate like 75LCX574. To AD13280. Each of the power supply pins should be decoupled minimize capacitive loading, there should be only one gate on as close as possible to the package using 0.1 μF chip capacitors. each output pin. An example of this is shown in the evaluation board schematic (see Figure 20). The digital outputs of the The AD13280 has separate digital and analog power supply AD13280 have a constant output slew rate of 1 V/ns. pins. The analog supplies are denoted AVCC, and the digital supply pins are denoted DVCC. AVCC and DVCC should be A typical CMOS gate combined with a PCB trace has a load of separate power supplies because the fast digital output swings approximately 10 pF. Therefore, as each bit switches, 10 mA can couple switching current back into the analog supplies. (10 pF × 1 V ÷ 1 ns) of dynamic current per bit flows in or out of the device. A full-scale transition can cause up to 120 mA Note that AV must be held within 5% of 5 V. The AD13280 is CC (12 bits × 10 mA/bit) of transient current through the output specified for DV = 3.3 V because this is a common supply for CC stages. These switching currents are confined between ground digital ASICs. and the DVCC pin. Standard TTL gates should be avoided because they can appreciably add to the dynamic switching currents of the AD13280. It should also be noted that extra capacitive loading increases output timing and invalidates timing specifications. Digital output timing is guaranteed with 10 pF loads. Rev. C | Page 16 of 28 AD13280 EVALUATION BOARD The AD13280 evaluation board (see Figure 20) is designed to LAYOUT INFORMATION provide optimal performance for evaluation of the AD13280 The schematics of the evaluation board (Figure 21, Figure 22, analog-to-digital converter. The board encompasses everything and Figure 23) represent a typical implementation of the needed to ensure the highest level of performance for evaluating AD13280. The pinout of the AD13280 is very straightforward the AD13280. The board requires an analog input signal, encode and facilitates ease of use and the implementation of high clock, and power supply inputs. The clock is buffered on-board frequency/high resolution design practices. It is recommended to provide clocks for the latches. The digital outputs and out that high quality ceramic chip capacitors be used to decouple clocks are available at the standard 40-pin connectors J1 and J2. each supply pin to ground directly at the device. All capacitors Power to the analog supply pins is connected via banana jacks. can be standard, high quality ceramic chip capacitors. The analog supply powers the associated components and the Care should be taken when placing the digital output runs. analog section of the AD13280. The digital outputs of the Because the digital outputs have such a high slew rate, the AD13280 are powered via banana jacks with 3.3 V. Contact the capacitive loading on the digital outputs should be minimized. factory if additional layout or applications assistance is required. Circuit traces for the digital outputs should be kept short and should connect directly to the receiving gate. Internal circuitry buffers the outputs of the ADC through a resistor network to eliminate the need to externally isolate the device from the receiving gate. Figure 20. Evaluation Board Mechanical Layout Rev. C | Page 17 of 28 02386-020 AD13280 J13 J6 E68 E67 SMA E66 SMA AGNDA AGNDB J9 J8 LIDA SMA SMA J3 J14 SMA SMA AGNDB AGNDA E50 J4 E53 J7 SMA SMA E51 E54 AGNDA AGNDB E49 E52 E69 E70 E85 E86 AGNDA AGNDB AGNDA AGNDB AGNDA AGNDB –5VAB –5VAA 10 60 C33 C9 AGNDA AGNDA AGNDB AGNDB 11 59 0.1µF 0.1µF AV A AV B EE EE AGENDA AGNDB 12 58 AV A +5VAB +5VAA AV B CC CC 13 57 C17 C38 C34 C35 AGNDA AGNDB AGNDA AGNDB 0.1µF 0.1µF 0.1µF 0.1µF 14 56 ENCODEA ENCODEA ENCODEB ENCODEB 15 55 ENCODEA ENCODEA ENCODEB ENCODEB AGNDA AGNDB 16 54 AGNDA AGNDA AGNDB AGNDB OUT_3.3VDA OUT_3.3VDB 17 53 U1 DV B DV A CC CC 18 52 C18 C37 C36 C10 AD13280AZ D11B(MSB) D11B NC0A NC 0.1µF 0.1µF 0.1µF 0.1µF 19 51 NC1A NC D10B D10B 20 50 D0A(LSB) D9B D0A D9B DGNDB 21 49 DGNDA D1A D1A D8B D8B 22 48 D2A D2A D7B D7B 23 47 D3A D3A D6B D6B 24 46 D4A D4A D5B D5B 25 45 D5A D5A D4B D4B 26 44 DGNDA DGNDA DGNDB DGNDB NC = NO CONNECT DRAOUT DRBOUT E56 E55 LIDB E65 E48 E40 DGNDB DGNDA 47Ω 47Ω 47Ω +3VDA +3VAA –5VAA ±20% ±20% ±20% @100MHz BJ6 BJ10 @100MHz BJ2 @100MHz DUT_3.3VDA +5VAA –5VAA U7 L1 1 1 L3 U1 1 L5 U1 C12 C29 C3 C20 C11 C32 0.1µF 10µF 10µF 0.1µF 10µF 0.1µF AGNDA AGNDA AGNDA AGNDA DGNDA 47Ω 47Ω 47Ω +3VDB +5VAB ±20% –5VAB ±20% ±20% @100MHz BJ9 BJ5 @100MHz BJ1 @100MHz DUT_3.3VDB +5VAB –5VAB 1 U8 L2 1 L4 U1 1 L6 U1 C30 C16 C4 C21 C19 C31 10µF 0.1µF 10µF 0.1µF 10µF 0.1µF AGNDB AGNDB AGNDB AGNDB DGNDB Figure 21. Evaluation Board Rev. C | Page 18 of 28 27 9 DGNDA DGNDA AGNDA 28 8 D6A D6A AMP-IN-A-2 29 7 AMP-IN-A-1 D7A D7A 30 6 E72 E71 D8A D8A AMP-OUT-A 31 5 E74 E73 A+IN D9A D9A 32 4 E77 E75 D10A D10A A–IN 33 3 AGNDA D11A D11A(MSB) E76 34 2 AGNDA DROUTA 35 1 SHIELD SHIELD 36 68 DROUTB AGNDB 37 67 E78 NC0B NC AGNDB E80 38 66 E79 NC1B NC B–IN E82 39 65 E81 B+IN D0B D0B(LSB) E84 40 64 E83 D1B D1B AMP-OUT-B 41 63 D2B D2B AMP-IN-B-1 42 62 D3B D3B AMP-IN-B-2 43 61 DGNDB DGNDB AGNDB 02386-021 AD13280 U8 R47 LE2 OE2 DGNDA 0Ω R18, DNI J1 25 24 115 O15 F0A H40DM R17, DNI 23 26 F1A 114 O14 1 40 R48 22 3.3VDA 27 DGNDA DGNDA GND GND 2 39 0Ω (MSB) B11A R16, DNI 28 21 3 38 NC0A 113 O13 F2A C15 B10A R40, DNI DGNDA 29 20 10µF 4 37 NC1A F3A 112 O12 B9A 19 30 5 36 DUT_3.3VDA VCC VCC DUT_3.3VDA B8A DGNDA R44, 100Ω 18 31 6 35 (LSB) D0A 111 O11 B0A (LSB) B7A R45, 100Ω 7 34 32 17 D1A B6A 110 O10 B1A 8 33 16 33 B5A DGNDA DGNDA GND GND 9 32 R5 R46, 100Ω 15 34 B4A D2A O9 B2A 19 50Ω E61 10 31 R15, 100Ω 35 14 D3A 18 O8 B3A 11 30 E60 E59 R14, 100Ω 36 13 D4A 17 O7 B4A 12 29 R13, 100Ω B3A 37 12 13 28 D5A 16 O6 B5A B2A 11 38 14 27 GND GND DGNDA DGNDA B1A R24, 100Ω 39 10 15 26 D6A 15 O5 B6A (LSB) B0A R23, 100Ω 16 25 9 40 F3A D7A 14 O4 B7A 17 24 8 41 F2A DUT_3.3VDA DUT_3.3VDA VCC VCC 18 23 R22, 100Ω 7 42 F1A D8A 13 O3 B8A 19 22 R21, 100Ω 6 F0A 43 D9A 12 O2 B9A 20 21 DGNDA 44 5 DGNDA GND GND DGNDA R20, 100Ω 45 4 D10A 11 O1 B10A DGNDA R19, 100Ω 3 46 (MSB) D11A 10 O0 B11A (MSB) 2 47 LE1 OE1 DGNDA 48 1 R7 50Ω 74LCX16374 LATCHB E58 U7 R49 LE2 OE2 DGNDB 0Ω R11, DNI J2 25 24 115 O15 F0B H40DN R10, DNI 23 26 F1B 114 O14 1 40 R50 22 3.3VDB 27 DGNDB GND GND DGNDB 2 39 0Ω (MSB) B11B R30, DNI 28 21 3 38 NC0B 113 O13 F2B C14 B10B R29, DNI DGNDB 29 20 10µF 4 37 NC1B F3B 112 O12 B9B 19 30 5 36 DUT_3.3VDB VCC VCC DUT_3.3VDB B8B DGNDB R28, 100Ω 18 31 6 35 (LSB) D0B 111 O11 B0B (LSB) B7B R27, 100Ω 7 34 32 17 D1B B6B 110 O10 B1B 8 33 16 33 B5B DGNDB DGNDB GND GND 9 32 R2 R26, 100Ω 15 34 B4B D2B 19 O9 B2B 50Ω E64 10 31 R12, 100Ω 35 14 D3B 18 O8 B3B 11 30 E63 E62 R9, 100Ω 36 13 D4B 12 29 17 O7 B4B R25, 100Ω B3B 37 12 13 28 D5B 16 O6 B5B B2B 11 38 14 27 GND GND DGNDB DGNDB B1B R36, 100Ω 39 10 15 26 D6B 15 O5 B6B (LSB) B0B R35, 100Ω 16 25 9 40 F3B D7B 14 O4 B7B 17 24 8 41 F2B DUT_3.3VDB VCC VCC DUT_3.3VDB 18 23 R34, 100Ω 7 42 F1B D8B 13 O3 B8B 19 22 R33, 100Ω 43 6 F0B D9B 12 O2 B9B 20 21 DGNDB 44 5 DGNDB GND GND DGNDB R32, 100Ω 45 4 D10B 11 O1 B10B DGNDB R31, 100Ω 3 46 (MSB) D11B 10 O0 B11B (MSB) 2 47 LE1 OE1 DGNDB 48 1 R8 50Ω LATCHB 74LCX16374 E57 Figure 22. Evaluation Board Rev. C | Page 19 of 28 BUFLATB BUFLATA DROUTB DROUTA 02386-022 AD13280 5 NR 3 1 ERR OUT ADP3330 2 U5 +5VAA IN 6 SD GND 4 AGNDA AGNDA R42 C13 100Ω J5 0.47µF ENCODE C1 1 8 C7 NC VCC +3.3VA BJ3 SMA 0.1µF 0.1µF 7 AGNDB 2 ENCODEA 1 D Q U2 3 6 DB BJ4 R1 QB ENCODEA 4 50Ω 5 C8 AGNDA AGNDA R43 VBB VEE 1 0.1µF 100Ω AGNDA BJ7 AGNDA MC10EP16 DGNDB NC = NO CONNECT 1 AGNDA DGNDB R56 DGNDA 33kΩ BJ8 J12 R55 DGNDA C2 C6 DGNDA 1 SMA 0.1µF 33kΩ 0.1µF DGND C5 DGNDA 0.1µF 1 8 R3 R41 +3.3VDA NC VCC 100Ω 1 8 25Ω 2 7 E15 E16 +3.3VDA D Q D0 VCC U3 LATCHA E7 E12 3 6 2 7 DB QB D0 Q0 E23 U4 6 4 5 3 AGNDA R4 Q1 DGNDA DGNDB D1 E19 VBB VEE 100Ω BUFLATA 4 5 DGNDA D1 GND MC10EP16 E11 E8 NC = NO CONNECT DGNDA E39 E47 DGNDA MC100EPT23 NC = NO CONNECT AGNDB AGNDA 5 E17 E18 NR E27 E28 3 1 ERR OUT E25 E26 ADP3330 E21 E20 2 E32 E31 U6 +5VAB IN 6 E44 E43 SD GND E42 E41 4 E10 E9 E33 E34 AGNDB AGNDB E6 E5 R52 C27 100Ω J10 0.47µF DGNDA AGNDA 8 ENCODE C22 1 C24 NC VCC +3.3VB SMA 0.1µF 0.1µF 7 2 ENCODEB D Q U11 E38 E37 3 6 DB QB ENCODEB R54 E29 E30 4 50Ω 5 C28 AGNDB E1 E2 R51 VBB VEE 0.1µF 100Ω E36 E35 AGNDB AGNDB MC10EP16 E14 E13 NC = NO CONNECT E45 E46 AGNDB E3 E4 R38 DGNDB 33kΩ DGNDB AGNDB J11 R39 C23 C25 DGNDB SMA 0.1µF 33kΩ 0.1µF DGNDB C26 SO1 SO4 0.1µF SO5 SO2 1 8 R37 R53 +3.3VDB NC VCC SO3 SO6 100Ω 1 8 25Ω 2 7 +3.3VDA D Q D0 VCC U9 LATCHB 3 6 2 7 DB QB D0 Q0 E24 U10 4 5 6 3 AGNDB R6 Q1 D1 E22 VBB VEE 100Ω BUFLATB 4 5 DGNDB D1 GND MC10EP16 NC = NO CONNECT DGNDB DGNDB MC100EPT23 NC = NO CONNECT Figure 23. Evaluation Board Rev. C | Page 20 of 28 02386-023 AD13280 Figure 24. Top Silk Figure 25. Top Layer Rev. C | Page 21 of 28 02386-025 02386-024 AD13280 Figure 26. GND1 Figure 27. GND2 Rev. C | Page 22 of 28 02386-027 02386-026 AD13280 Figure 28. Bottom Silk Figure 29. Bottom Layer Rev. C | Page 23 of 28 02386-029 02386-028 AD13280 BILL OF MATERIALS LIST FOR EVALUATION BOARD Table 4. Component Qty Name Reference Value Description Manufacturing Part Number 2 74LCX16374MTD U7, U8 Latch 74LCX16374MTD (Fairchild) 1 AD13280AZ U1 AD13280 AD13280AZ 2 ADP3330 U5, U6 Regulator ADP3330ART-3.3RL7 10 BJACK BJ1 to BJ10 Banana jacks 108-0740-001 (Johnson Components) 2 BRES0805 R41, R53 25 Ω 0805 SM resistor ERJ-6GEYJ 240V (Panasonic) 4 BRES0805 R38, R39, R55, R56 33 kΩ 0805 SM resistor ERJ-6GEYJ 333V (Panasonic) 28 CAP2 C1, C2, C5 to C10, 0.1 μF 0805 SM capacitor GRM 40X7R104K025BL C12, C16 to C18, C20 to C26, C28, C31 to C38 2 CAP2 C13, C27 0.47 μF 0805 SM capacitor VJ1206U474MFXMB (Vishay) 2 H40DM J1, J2 2 × 20, 40-pin male connector TSW-120-08-G-D 6 IND2 L1 to L6 47 Ω SM inductor 2743019447 4 MC10EP16 U2, U3, U9, U11 Clock drivers MC10EP16D (ON Semiconductor) 2 MC100EPT23 U4, U10 ECL/TTL clock drivers SY100EP23L (ON Semiconductor) 8 POLCAP2 C3, C4, C11, C14, 10 μF Tantalum polar capacitor T491C106M016AT (Kemet) C15, C19, C29, C30 4 RES2 R47 to R50 0 Ω 0805 SM resistor ERJ-6GEY OR 00V (Panasonic) 6 RES2 R1, R2, R5, R7, R8, R54 50 Ω 0805 SM resistor ERJ-6GEYJ 510V (Panasonic) 32 RES2 R3, R4, R6, R9, R12 to 100 Ω 0805 SM resistor ERJ-6GEYJ 101V (Panasonic) R15, R19 to R28, R31 to R37, R42, R43, R44 to R46, R51, R52 12 SMA J3 to J14 SMA connectors 142-0701-201 4 Standoff Standoff 313-2477-016 (Johnson Components) 4 Screws Screws (standoff) MPMS 004 0005 PH (Building Fasteners) 1 PCB AD13280 evaluation board GS03361 Rev. C | Page 24 of 28 AD13280 OUTLINE DIMENSIONS 2.00 (50.80) 0.035 (0.889) TYP MAX 0.350 0.040 (1.02) (8.89) DETAIL A TYP × 45° PIN 1 TOE DOWN ANGLE 0–8 DEGREES 0.960 (24.38) 0.800 (20.32) 0.010 (0.254) BSC 0.950 (24.13) SQ TOP VIEW (PINS DOWN) 0.940 (23.88) 30° 0.050 (1.27) 0.020 (0.508) DETAIL A ROTATED 90° CCW 0.040 0.015 (0.30) (1.02) R × 45° 0.010 (0.25) TYP 3 PLS 0.008 (0.20) 0.007 (0.18) 0.235 (5.97) 0.020 (0.508) 0.055 (1.40) MAX 0.017 (0.432) 0.050 (1.27) 0.014 (0.356) 0.045 (1.14) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 30. 68-Lead Ceramic Leaded Chip Carrier with Nonconductive Tie-Bar [CLCC] (ES-68-1) Dimensions shown in inches and (millimeters) 0.235 (5.97) 0.960 (24.38) MAX 0.010 (0.25) 0.950 (24.13) SQ 0.008 (0.20) 0.940 (23.88) 0.007 (0.18) 9 61 10 60 PIN 1 TOP VIEW 1.190 (30.23) 1.070 0.800 (PINS DOWN) (27.18) (20.32) 1.180 (29.97) SQ MIN BSC TOE DOWN 1.170 (29.72) ANGLE 0–8 DEGREES 0.010 (0.254) 26 44 30° 27 43 0.050 (1.27) 0.060 (1.52) DETAIL A 0.020 (0.508) 0.050 (1.27) 0.055 (1.40) 0.020 (0.508) 0.040 (1.02) DETAIL A 0.050 (1.27) 0.175 (4.45) 0.017 (0.432) ROTATED 90° CCW MAX 0.045 (1.14) 0.014 (0.356) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 31. 68-Lead Ceramic Leaded Chip Carrier [CLCC] (ES-68-C) Dimensions shown in inches and (millimeters) Rev. C | Page 25 of 28 012908- A 022608-B AD13280 ORDERING GUIDE 1 Model Temperature Range Package Description Package Option 2 AD13280AZ −25°C to +85°C 68-Lead Ceramic Leaded Chip Carrier [CLCC] ES-68-C AD13280AF −25°C to +85°C 68-Lead Ceramic Leaded Chip Carrier with Nonconductive Tie-Bar [CLCC] ES-68-1 AD13280/PCB Evaluation Board with AD13280AZ 1 Referenced temperature is case temperature. 2 Z is a package indicator; the part is not RoHS compliant. Rev. C | Page 26 of 28 AD13280 NOTES Rev. C | Page 27 of 28 AD13280 NOTES ©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02386–0–4/08(C) Rev. C | Page 28 of 28