Dual, 12-Bit, 40 MSPS MCM A/D Converter a with Analog Input Signal Conditioning AD10242 FEATURES The AD10242 operates with ±5.0 V for the analog signal condi- 2 Matched ADCs with Input Signal Conditioning tioning with a separate 5.0 V supply for the analog-to-digital Selectable Bipolar Input Voltage Range conversion. Each channel is completely independent, allowing (�0.5 V, �1.0 V, �2.0 V) operation with independent encode or analog inputs. The AD10242 Full MIL-STD-883B Compliant also offers the user a choice of analog input signal ranges to mini- 80 dB Spurious-Free Dynamic Range mize additional signal conditioning required for multiple functions Trimmed Channel-Channel Matching within a single system. The heart of the AD10242 is the AD9042, which is designed specifically for applications requiring wide APPLICATIONS dynamic range. Radar Processing The AD10242 is manufactured on Analog Devices’ Communications Receivers MIL-PRF-38534 MCM line and is completely qualified. Units FLIR Processing are packaged in a custom, cofired, ceramic 68-lead gull wing Secure Communications package and specified for operation from –55°C to +125°C. Any I/Q Signal Processing Application Contact the factory for additional custom options including those that allow the user to ac couple the ADC directly, bypassing the front end amplifier section. Also see the AD9042 data sheet for additional details on ADC performance. GENERAL DESCRIPTION The AD10242 is a complete dual signal chain solution including PRODUCT HIGHLIGHTS on-board amplifiers, references, ADCs, and output buffering 1. Guaranteed sample rate of 40 MSPS. providing unsurpassed total system performance. Each channel is 2. Dynamic performance specified over entire Nyquist band; laser trimmed for gain and offset matching and provides channel- spurious signals @ 80 dBc for –1 dBFS input signals. to-channel crosstalk performance better than 80 dB. The AD10242 utilizes two each of the AD9632, OP279, and AD9042 in a cus- 3. Low power dissipation: <2 W off ±5.0 V supplies. tom MCM to gain space, performance, and cost advantages over 4. User defined input amplitude. solutions previously available. 5. Packaged in 68-lead ceramic leaded chip carrier. FUNCTIONAL BLOCK DIAGRAM A 3 A2A 1 A 2 A 1 A 3 IN IN IN UNEG UCOM UPOS IN IN IN UPOS OP279 OP279 AD9632 AD9632 UCOM UNEG OP279 OP279 AD9042 AD9042 ENC (LSB) D0A TIMING ENC D1A V V REF REF D2A D11B (MSB) D3A 12 AD10242 12 D10B D4A 9 5 OUTPUT BUFFERING D9B OUTPUT BUFFERING D5A D8B D6A 7 D7B D7A TIMING D8A ENC ENC D9A D10A D11A D0B D1B D2B D3B D4B D5B D6B (MSB) (LSB) REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies. AD10242–SPECIFICATIONS (AV = +5 V; AV = –5.0 V; DV = +5 V; applies to each ADC, unless otherwise noted.) Electrical Characteristics CC EE CC Test Mil AD10242BZ/TZ Parameter Temp Level Subgroup Min Typ Max Unit RESOLUTION 12 Bits DC ACCURACY No Missing Codes Full VI 1, 2, 3 Guaranteed Offset Error 25°CI 1 –0.5 ±0.05 +0.5 % FS Full VI 2, 3 –2.0 ±1.0 +2.0 % FS Offset Error Channel Match Full V ±0.1 % 1 Gain Error 25°CI 1 –1.0 ±0.5 +1.0 % FS Full VI 2, 3 –1.5 ±0.8 +1.5 % FS Gain Error Channel Match Full V ±0.1 % ANALOG INPUT (A ) IN Input Voltage Range A 1 Full I ±0.5 V IN A 2 Full I ±1.0 V IN A 3 Full I ±2V IN Input Resistance A 1 Full IV 12 99 100 101 Ω IN A 2 Full IV 12 198 200 202 Ω IN A 3 Full IV 12 396 400 404 Ω IN 2 Input Capacitance 25°CIV 12 0 4.0 7.0 pF 3 Analog Input Bandwidth Full V 60 MHz 4, 5 ENCODE INPUT Logic Compatibility TTL/CMOS Logic “1” Voltage Full I 1, 2, 3 2.0 5.0 V Logic “0” Voltage Full I 1, 2, 3 0 0.8 V Logic “1” Current (V = 5 V) Full I 1, 2, 3 625 800 µA INH Logic “0” Current (V = 0 V) Full I 1, 2, 3 –400 –300 µA INL Input Capacitance 25°CV 12 7.0 pF SWITCHING PERFORMANCE 6 Maximum Conversion Rate Full VI 4, 5, 6 40 50 MSPS 6 Minimum Conversion Rate Full V 12 5 MSPS Aperture Delay (t)25°CV 1.0 ns A Aperture Delay Matching 25°CV ±2.0 ns Aperture Uncertainty (Jitter) 25°CV 1 ps rms ENCODE Pulsewidth High 25°CIV 12 12 10 ns ENCODE Pulsewidth Low 25°CIV 12 10 41 ns Output Delay (t ) Full IV 12 10 12 14 ns OD 7 SNR Analog Input @ 1.2 MHz 25°CV 68 dB @ 4.85 MHz 25°CI 4 63 66 dB Full II 5, 6 62 66 dB @ 9.9 MHz 25°CI 4 63 65 dB Full II 5, 6 62 65 dB @ 19.5 MHz 25°CI 4 60 63 dB Full II 5, 6 59 62 dB 8 SINAD Analog Input @ 1.2 MHz 25°CV 67 dB @ 4.85 MHz 25°CI 4 62 65 dB Full II 5, 6 61 64 dB @ 9.9 MHz 25°CI 4 60 64 dB Full II 5, 6 60 63 dB @ 19.5 MHz 25°CI 4 58 61 dB Full II 5, 6 58 60 dB –2– REV. C AD10242 Test Mil AD10242BZ/TZ Parameter Temp Level Subgroup Min Typ Max Unit 9 SPURIOUS-FREE DYNAMIC RANGE Analog Input @ 1.2 MHz 25°CI 81 dBFS @ 4.85 MHz 25°CI 47080 dBFS Full II 5, 6 70 79 dBFS @ 9.9 MHz 25°CI 46370 dBFS Full II 5, 6 63 69 dBFS @ 19.5 MHz 25°CI 46067 dBFS Full II 5, 6 60 66 dBFS 10 TWO-TONE IMD REJECTION F1, F2 @ –7 dBFS Full II 4, 5, 6 70 76 dBc 11 CHANNEL-TO-CHANNEL ISOLATION 25°CIV 12 75 80 dB TRANSIENT RESPONSE 25°CV 10 ns LINEARITY Differential Nonlinearity 25°CIV 12 0.3 1.0 LSB (Encode = 20 MHz) Full IV 12 0.5 1.25 LSB Integral Nonlinearity 25°CV 0.3 LSB (Encode = 20 MHz) Full V 0.5 LSB 12 OVERVOLTAGE RECOVERY TIME V = 2.0 × FS Full IV 12 50 100 ns IN V = 4.0 × FS Full IV 12 75 200 ns IN DIGITAL OUTPUTS Logic Compatibility CMOS 13 Logic “1” Voltage Full I 1, 2, 3 3.5 4.2 V 14 Logic “0” Voltage Full I 1, 2, 3 0.45 0.65 V Output Coding Twos Complement POWER SUPPLY AV Supply Voltage Full VI 5.0 V CC I (AV ) Current Full V 260 mA CC AV Supply Voltage Full VI –5.0 V EE I (AV ) Current Full V 55 mA EE DV Supply Voltage Full VI 5.0 V CC I (DV ) Current Full V 25 mA CC I (Total) Supply Current Full I 1, 2, 3 350 400 mA CC Power Dissipation (Total) Full I 1, 2, 3 1.75 2.0 W Power Supply Rejection Ratio (PSRR) Full I 7, 8 0.01 0.02 % FSR/% V S Pass-Band Ripple to 10 MHz Full IV 12 0.2 dB NOTES 1 Gain tests are performed on A 3 over specified input voltage range. IN 2 Input capacitance specifications combine AD9632 die capacitance and ceramic package capacitance. 3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 µF capacitor. 5 ENCODE may also be driven differentially in conjunction with ENCODE; see Encoding the AD10242 section for details. 6 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%. 7 Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 40.0 MSPS. 8 Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 40.0 MSPS. 9 Analog Input signal equals –1 dBFS; SFDR is the ratio of converter full scale to worst spur. 10 Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = 10.0 MHz ± 100 kHz, 50 kHz ≤ f1 – f2 ≤ 300 kHz. 11 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel (A 1). IN 12 Input driven to 2× and 4× A 1 range for >4 clock cycles. Output recovers in band in specified time with Encode = 40 MSPS. No foldover guaranteed. IN 13 Outputs are sourcing 10 µA. 14 Outputs are sinking 10 µA. All specifications guaranteed within 100 ms of initial power-up regardless of sequencing. Specifications subject to change without notice. REV. C –3– AD10242 1 Table I. Output Coding ABSOLUTE MAXIMUM RATINGS Parameter Min Max Unit MSB LSB Base 10 Input ELECTRICAL 0111111111111 2047 +FS V Voltage 0 7 V CC 0000000000001 +1 V Voltage –7 0 V EE 0000000000000 0 0.0 V Analog Input Voltage V V V EE CC 1111111111111 –1, 4095 Analog Input Current –10 +10 mA 1000000000000 –2047, 2048 –FS Digital Input Voltage (ENCODE) 0 V V CC ENCODE, ENCODE Differential Voltage 4 V Digital Output Current –40 +40 mA EXPLANATION OF TEST LEVELS Test Level 2 ENVIRONMENTAL I– 100% Production Tested. Operating Temperature (Case) –55 +125 °C Maximum Junction Temperature 175 °C II – 100% production tested at 25°C, and sample tested at Lead Temperature (Soldering, 10 sec) 300 °C specified temperatures. AC testing done on sample basis. Storage Temperature Range (Ambient) –65 +150 °C III – Sample Tested Only. NOTES IV – Parameter is guaranteed by design and characterization 1 Absolute maximum ratings are limiting values to be applied individually, and beyond testing. which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an V– Parameter is a typical value only. extended period of time may affect device reliability. 2 VI – All devices are 100% production tested at 25°C; sample Typical thermal impedances for “Z” package: θ = 11°C/W; θ = 30°C/W. JC JA tested at temperature extremes. ORDERING GUIDE Model Temperature Range Package Description Package Option AD10242BZ –40°C to +85°C (Case) 68-Lead Ceramic Leaded Chip Carrier Z-68A AD10242TZ –55°C to +125°C (Case) 68- Ceramic Carrier Z-68A Lead Leaded Chip AD10242TZ/883B –55°C to +125°C (Case) 68-Lead Ceramic Leaded Chip Carrier Z-68A 5962-9581501HXA –55°C to +125°C (Case) 68- Ceramic Carrier Z-68A Lead Leaded Chip AD10242/PCB 25°C Evaluation Board with AD10242BZ CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD10242 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality. REV. C –4– AD10242 PIN CONFIGURATION 68-Lead Ceramic Leaded Chip Carrier 96 87 65 43 21 686766 65 64 63 621 10 GNDA PIN 1 60 GNDB IDENTIFIER 11 GNDA 59 GNDB UPOSA 12 58 GNDB AV 13 57 UPOSB EE AV 14 56 UNEGB CC 15 NC 55 UCOMB 16 NC 54 GNDB 17 (LSB) D0A AD10242 53 GNDB 18 TOP VIEW D1A 52 ENCODEB (Not to Scale) 19 D2A 51 ENCODEB 20 D3A 50 DV CC D4A 21 49 D11B (MSB) 22 D5A 48 D10B 23 D6A 47 D9B 24 D7A 46 D8B 25 D8A 45 D7B 26 GNDA 44 GNDB 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 SHIELD Internal Ground Shield between Channels. 2, 5, 9–11, 26–27 GNDA A Channel Ground. A and B grounds should be connected as close to the device as possible. 3 UNEGA Unipolar Negative. 4 UCOMA Unipolar Common. 6A A1 Analog Input for A Side ADC (Nominally ±0.5 V). IN 7A A2 Analog Input for A Side ADC (Nominally ±1.0 V). IN 8A A3 Analog Input for A Side ADC (Nominally ±2.0 V). IN 12 UPOSA Unipolar Positive. 13 AV Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V). EE 14 AV Analog Positive Supply Voltage (Nominally 5.0 V). CC 15, 16, 34, 35 NC No Connect. 17–25, 31–33 D0A–D11A Digital Outputs for ADC A. (D0 LSB.) 28 ENCODEA ENCODE is the complement of ENCODE. 29 ENCODEA Data conversion is initiated on the rising edge of the ENCODE input. 30, 50 DV Digital Positive Supply Voltage (Nominally 5.0 V). CC 36–42, 45–49 D0B–D11B Digital Outputs for ADC B. (D0 LSB.) 43–44, 53–54, GNDB B Channel Ground. A and B grounds should be connected as close to the device 58–61, 65, 68 as possible. 51 ENCODEB Data conversion is initiated on the rising edge of the ENCODE input. 52 ENCODEB ENCODE is the complement of ENCODE. 55 UCOMB Unipolar Common. 56 UNEGB Unipolar Negative. 57 UPOSB Unipolar Positive. 62 A B1 Analog Input for B Side ADC (Nominally ±0.5 V). IN 63 A B2 Analog Input for B Side ADC (Nominally ±1.0 V). IN 64 A B3 Analog Input for B Side ADC (Nominally ±2.0 V). IN 66 AV Analog Positive Supply Voltage (Nominally 5.0 V). CC 67 AV Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V). EE REV. C –5– GNDA GNDA A A3 ENCODEA IN ENCODEA A A2 IN DV A A1 CC IN D9A GNDA D10A UCOMA UNEGA (MSB) D11A NC GNDA NC SHIELD GNDB (LSB) D0B AV D1B EE AV D2B CC D3B GNDB D4B A B3 IN D5B A B2 IN A B1 D6B IN GNDB GNDB AD10242 Overvoltage Recovery Time DEFINITION OF SPECIFICATIONS The amount of time required for the converter to recover to Analog Bandwidth 0.02% accuracy after an analog input signal of the specified The analog input frequency at which the spectral power of the percentage of full scale is reduced to midscale. fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power Aperture Delay supply voltage. The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input Signal-to-Noise and Distortion (SINAD) is sampled. The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo- Aperture Uncertainty (Jitter) nents, including harmonics but excluding dc. The sample-to-sample variation in aperture delay. Signal-to-Noise Ratio (SNR, without Harmonics) Differential Nonlinearity The ratio of the rms signal amplitude (set at 1 dB below full The deviation of any code from an ideal 1 LSB step. scale) to the rms value of the sum of all other spectral compo- Encode Pulsewidth/Duty Cycle nents, excluding the first five harmonics and dc. Pulsewidth high is the minimum amount of time that the Spurious-Free Dynamic Range (SFDR) ENCODE pulse should be left in Logic “1” state to achieve rated The ratio of the rms signal amplitude to the rms value of the performance; pulsewidth low is the minimum time that the peak spurious spectral component. The peak spurious compo- ENCODE pulse should be left in low state. At a given clock nent may or may not be a harmonic. SFDR may be reported in rate, these specifications define an acceptable encode duty cycle. dBc (i.e., degrades as signal levels are lowered) or in dBFS Harmonic Distortion (always related back to converter full scale). The ratio of the rms signal amplitude to the rms value of the Transient Response worst harmonic component. The time required for the converter to achieve 0.02% accu- Integral Nonlinearity racy when a one-half full-scale step function is applied to the The deviation of the transfer function from a reference line analog input. measured in fractions of 1 LSB using a “best straight line” deter- Two-Tone Intermodulation Distortion Rejection mined by a least square curve fit. The ratio of the rms value of either input tone to the rms value of Minimum Conversion Rate the worst third order intermodulation product; reported in dBc. The encode rate at which the SNR of the lowest analog signal Two-Tone SFDR frequency drops by no more than 3 dB below the guaranteed limit. The ratio of the rms value of either input tone to the rms value of Maximum Conversion Rate the peak spurious component. The peak spurious component The encode rate at which parametric testing is performed. may or may not be an IMD product. Two-tone SFDR may be Output Propagation Delay reported in dBc (i.e., degrades as signal levels are lowered) or The delay between the 50% point of the rising edge of the ENCODE in dBFS (always related back to converter full scale). command and the time when all output data bits are within valid logic levels. REV. C –6– AD10242 N N + 1 N + 2 N + 3 N + 4 N + 5 ENC D11 TTL CLOCK D10 f 10MHz ENC D9 A IN D8 3 D7 A IN 1/2 D6 D5 AD10242 t = 1.0ns TYP 2 A A IN D4 SHOWN D3 ENCODE 1 D2 A IN D1 D0 t = 12ns TYP OD DIGITAL N – 2 N – 1 N N + 1 N + 2 OUTPUTS ALL 5V SUPPLY PINS BYPASSED TO GND WITH A 0.1�F CAPACITOR Figure 2. Equivalent Burn-In Circuit Figure 1. Timing Diagram EQUIVALENT CIRCUITS DV CC A 3 IN R4 200� A 2 IN CURRENT R3 MIRROR 100� A 1 IN R2 21� TO AD9632 R1 79� DV CC V REF Figure 3. Analog Input Stage D0–D11 AV CC AV AV CC CC R1 R1 17k� 17k� CURRENT ENCODE ENCODE MIRROR TIMING R2 R2 CIRCUITS 8k� 8k� Figure 5. Digital Output Stage Figure 4. Encode Inputs REV. C –7– AD10242–Typical Performance Characteristics 0 0 ENCODE = 40MSPS ENCODE = 40MSPS A = 4.85MHz –10 A 1 = 9.8MHz –10 IN IN A = –1dBFS A 1 = –7dBFS IN IN –20 –20 SNR = 66.4dB A 2 = 10.1MHz IN SFDR = 72.8dBc A 2 = –7dBFS –30 IN –30 SFDR = 76.0dBc –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 02 2468 10 12 14 16 18002 246 8 10 121416180 FREQUENCY – MHz FREQUENCY – MHz TPC 1. Single Tone @ 4.85 MHz TPC 4. Two-Tone FFT @ 9.8 MHz/10.1 MHz 0 0 ENCODE = 40MSPS ENCODE = 40MSPS A 1 = 19.5MHz A = 9.9MHz –10 IN –10 IN A 1 = –7dBFS A = –1dBFS IN IN –20 A 2 = 19.7MHz –20 SNR = 66.0dB IN SFDR = 65.7dBc A 2 = –7dBFS IN –30 –30 SFDR = 70.6dBc –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 02 2468 10 12 14 16 180 0 2468 10 12 14 16 18 20 FREQUENCY – MHz FREQUENCY – MHz TPC 2. Single Tone @ 9.9 MHz TPC 5. Two-Tone FFT @ 19.5 MHz/19.7 MHz 0 76 ENCODE = 40MSPS ENCODE = 40MSPS –10 A = 19.5MHz IN 74 A = –1dBFS IN A = –1dBFS IN –20 SNR = 64.3dB 72 SFDR = 63.3dBc –30 70 –40 T = +125 C 68 –50 T = +25 C 66 –60 T = –55 C 64 –70 62 –80 60 –90 –100 58 0 2468 10 12 14 16 18 2052 100 ANALOG INPUT FREQUENCY – MHz FREQUENCY – MHz TPC 3. Single Tone @ 19.5 MHz TPC 6. Harmonics vs. A IN REV. C –8– POWER RELATIVE TO FULL SCALE – dB POWER RELATIVE TO FULL SCALE – dB POWER RELATIVE TO FULL SCALE – dB POWER RELATIVE TO FULL SCALE – dB WORST-CASE HARMONIC – dB POWER RELATIVE TO FULL SCALE – dB AD10242 67.0 –90 IN A1 IN B1 66.5 T = –55 C –80 66.0 –70 65.5 IN B3 T = +25 C IN A3 –60 65.0 64.5 –50 T = +125 C 64.0 –40 63.5 –30 ENCODE = 40MSPS 63.0 ENCODE = 40MSPS A = –1dBFS IN –20 A = –1dBFS 62.5 IN –10 62.0 61.5 0 20 25 30 35 40 52 100 10 15 ANALOG INPUT FREQUENCY – MHz ANALOG INPUT FREQUENCY – MHz TPC 7. SNR vs. A TPC 10. Isolation vs. Frequency IN 90 70 A = 9.9MHz IN A = –1dBFS 80 IN SFDR (dBFS) 68 SFDR 70 66 60 SNR 50 SFDR (dBc) 64 40 SFDR = 75dB 62 30 20 60 ENCODE = 40MSPS 10 A = 9.98MHz IN 58 0 55 10 15 20 25 30 35 40 450 –60 –50 –40 –30 –20 –10 0 –70 SAMPLE RATE – MSPS ANALOG INPUT POWER LEVEL – dBFS TPC 8. SNR and Harmonics vs. Encode Rate TPC 11. Single Tone SFDR (A @ 9.98) vs. Power Level IN 2.0 100 90 1.5 80 1.0 SFDR (dBFS) GAIN 70 0.5 60 SFDR (dBc) 0 50 40 –0.5 OFFSET SFDR = 75dB 30 –1.0 20 ENCODE = 40MSPS –1.5 10 A = 19.9MHz IN –2.0 0 –55 –35 –15 5 25 45 65 85 105 125 –70 –60 –50 –40 –30 –20 –10 0 TEMPERATURE – C ANALOG INPUT POWER LEVEL – dBFS TPC 9. Offset and Gain Error vs. Temperature TPC 12. Single Tone SFDR (A @ 19.9) vs. Power Level IN REV. C –9– ERROR – % FS SNR – dB SNR, WORST SPUR – dB, dBc WORST-CASE SPURIOUS – dBc, dBFS WORST-CASE SPURIOUS – dBc, dBFS ISOLATION – dB AD10242 80 –0.5 ENCODE = 40MSPS 70 0 SNR (dB) 60 0.5 50 SFDR (dBFS) 1.0 40 1.5 30 2.0 20 ENCODE = 40MSPS 2.5 10 A = 1dBFS IN 3.0 0 05 10 15 20 25 30 35 40 45 50 55 510 20 29.2 34.5 52.5 60.95 INPUT FREQUENCY – MHz ANALOG INPUT FREQUENCY – MHz TPC 13. SNR/Harmonics to A > Nyquist MSPS TPC 14. Gain Flatness vs. Input Frequency IN THEORY OF OPERATION APPLYING THE AD10242 Refer to the functional block diagram. The AD10242 employs Encoding the AD10242 The AD10242 is designed to interface with TTL and CMOS three monolithic ADI components per channel (AD9632, OP279, and AD9042), along with multiple passive resistor networks logic families. The source used to drive the ENCODE pin(s) and decoupling capacitors to fully integrate a complete 12-bit must be clean and free from jitter. Sources with excessive jitter analog-to-digital converter. will limit SNR and overall performance. The input signal is first passed through a precision laser trimmed AD10242 resistor divider, allowing the user to externally select operation TTL OR CMOS ENCODE with a full-scale signal of ±0.5 V, ±1.0 V, or ±2.0 V by choosing SOURCE the proper input terminal for the application. The result of ENCODE the resistor divider is to apply a full-scale input of approximately 0.01�F 0.4 V to the noninverting input of the internal AD9632 amplifier. The AD9632 provides the dc-coupled level shift circuit required Figure 6. Single-Ended TTL/CMOS Encode for operation with the AD9042 ADC. Configuring the amplifier The AD10242 encode inputs are connected to a differential in a noninverting mode, the ac signal gain can be trimmed to input stage (see Figure 4). With no input connected to either provide a constant input to the ADC centered around the inter- the ENCODE or ENCODE input, the voltage dividers bias the nal reference voltage of the AD9042. This allows the converter inputs to 1.6 V. For TTL or CMOS usage, the encode source to be used in multiple system applications without the need for should be connected to ENCODE (Pins 29 and/or 51). ENCODE external gain and level shift circuitry normally requiring trim. (Pins 28 and/or 52) should be decoupled using a low inductance The AD9632 was chosen for its superior ac performance and or microwave chip capacitor to ground. Devices such as AVX input drive capabilities. These two specifications have limited 05085C103MA15, a 0.01 µF capacitor, work well. the ability of many amplifiers to drive high performance ADCs. Performance Improvements As new amplifiers are developed, pin compatible improve- It is possible to improve the performance of the AD10242 ments are planned to incorporate the latest operational ampli- slightly by taking advantage of the internal characteristics of the fier technology. amplifier and converter combination. By increasing the 5 V The OP279 provides the buffer and inversion of the internal supply slightly, the user may be able to gain up to a 5 dB improve- reference of the AD9042 in order to supply the summing node ment in SFDR over the entire frequency range of the converter. of the AD9632 input amplifier. This dc voltage is then summed It is not recommended to exceed 5.5 V on the analog supplies with the input voltage and applied to the input of the AD9042 since there are no performance benefits beyond that range and ADC. The reference voltage of the AD9042 is designed to track care should be taken to avoid the absolute maximum ratings. internal offsets and drifts of the ADC and is used to ensure matching over an extended temperature range of operation. REV. C –10– SNR, WORST SPUR – dB, dBc FUNDAMENTAL LEVELS – dBFS AD10242 If a logic threshold other than the nominal 1.6 V is required, If no TTL source is available, a clean sine wave may be substi- the following equations show how to use an external resistor, tuted. In the case of the sine source, the matching network is Rx, to raise or lower the trip point (see Figure 4, R1 = 17 kΩ, shown below. Since the matching transformer specified is a 1:1 R2 = 8 kΩ). impedance ratio, the load resistor R should be selected to match the source impedance. The input impedance of the AD9042 52 RRx is negligible in most cases. V = to lower logic threshold. 1 RR 12++ RR 1 x R2Rx T1–1T SINE ENCODE SOURCE ENCODE 5V ENCODE R AD10242 SOURCE R1 V l ENCODE ENCODE 0.01�F Rx R2 AD10242 Figure 10. Sine Source—Differential Encode If a low jitter ECL clock is available, another option is to ac-couple Figure 7. Lower Threshold for Encode a differential ECL signal to the encode input pins, as shown in Figure 11. The capacitors shown here should be chip capaci- 52 R to raise logic threshold. tors but do not need to be of the low inductance variety. V = 1 RR 1 x R2 + RR 1+ x 0.1�F ENCODE AV ECL CC AD10242 0.1�F GATE ENCODE Rx 5V 510� 510� ENCODE ENCODE SOURCE R1 ENCODE V l –V S R2 0.01�F AD10242 Figure 11. Differential ECL for Encode As a final alternative, the ECL gate may be replaced by an ECL Figure 8. Raise Logic Threshold for Encode comparator. The input to the comparator could then be a logic While the single-ended encode will work well for many applica- signal or a sine signal. tions, driving the encode differentially will provide increased performance. Depending on circuit layout and system noise, a AD96687 (1/2) 0.1�F 1 dB to 3 dB improvement in SNR can be realized. It is recom- ENCODE mended that the encode signal be ac-coupled into the ENCODE AD10242 0.1�F 50� and ENCODE pins. ENCODE The simplest option is shown below. The low jitter TTL signal 510� 510� is coupled with a limiting resistor, typically 100 Ω, to the primary side of an RF transformer (these transformers are inexpensive –V S and readily available; part number in Figures 9 and 10 is from Figure 12. ECL Comparator for Encode Mini-Circuits). The secondary side is connected to the ENCODE and ENCODE pins of the converter. Since both encode inputs Care should be taken not to overdrive the encode input pin when are self-biased, no additional components are required. ac-coupled. Although the input circuitry is electrically protected from overvoltage or undervoltage conditions, improper circuit operations may result from overdriving the encode input pin. 100� T1–1T TTL ENCODE AD10242 ENCODE Figure 9. TTL Source—Differential Encode REV. C –11– AD10242 USING THE FLEXIBLE INPUT A 1 IN The AD10242 has been designed with the user’s ease of opera- A 2 IN A 3 tion in mind. Multiple input configurations have been included on IN AD10242 UNEG board to allow the user a choice of input signal levels and input 2.67k� impedance. While the standard inputs are ±0.5 V, ±1.0 V, and UCOM ±2.0 V, the user can select the input impedance of the AD10242 Figure 14. Unipolar Negative on any input by using the other inputs as alternate locations for GND or an external resistor. The following chart summarizes the GROUNDING AND DECOUPLING impedance options available at each input location: Analog and Digital Grounding A 1 = 100 Ω when A 2 and A 3 are open. IN IN IN Proper grounding is essential in any high speed, high resolution A 1 = 75 Ω when A 3 is shorted to GND. IN IN system. Multilayer printed circuit boards (PCBs) are recom- A 1 = 50 Ω when A 2 is shorted to GND. IN IN mended to provide optimal grounding and power schemes. The A 2 = 200 Ω when A 3 is open. IN IN use of ground and power planes offers distinct advantages: A 2 = 100 Ω when A 3 is shorted to GND. IN IN 1. The minimization of the loop area encompassed by a signal A 2 = 75 Ω when A 2 to A 3 has an external resistor of IN IN IN and its return path. A 2 = 300 Ω, with A 3 shorted to GND. IN IN 2. The minimization of the impedance associated with ground A 2 = 50 Ω when A 2 to A 3 has an external resistor of A 2 IN IN IN IN and power paths. = 100 Ω, with A 3 shorted to GND. IN A 3 = 400 Ω. 3. The inherent distributed capacitor formed by the power IN A 3 = 100 Ω when A 3 has an external resistor of 133 Ω to GND. plane, PCB insulation, and ground plane. IN IN A 3 = 75 Ω when A 3 has an external resistor of 92 Ω to GND. IN IN These characteristics result in both a reduction of electro- A 3 = 50 Ω when A 3 has an external resistor of 57 Ω to GND. IN IN magnetic interference (EMI) and an overall improvement in While the analog inputs of the AD10242 are designed for performance. dc- coupled bipolar inputs, the AD10242 has the ability to It is important to design a layout that prevents noise from cou- use unipolar inputs in a user selectable mode through the addi- pling to the input signal. Digital signals should not be run in tion of an external resistor. This allows for 1 V, 2 V, and 4 V parallel with input signal traces and should be routed away from full-scale unipolar signals to be applied to the various inputs the input circuitry. The AD10242 does not distinguish between (A 1, A 2, and A 3, respectively). Placing a 2.43 kΩ resis- IN IN IN analog and digital ground pins as the AD10242 should always tor (typical, offset calibration required) between UPOS and be treated like an analog component. All ground pins should be UCOM shifts the reference voltage setpoint to allow a unipolar connected together directly under the AD10242. The PCB positive voltage to be applied at the inputs of the device. To cali- should have a ground plane covering all unused portions of the brate offset, apply a midscale dc voltage to the converter while component side of the board to provide a low impedance path adjusting the unipolar resistor for a midscale output transition. and manage the power and ground currents. The ground plane should be removed from the area near the input pins to reduce A 1 stray capacitance. IN A 2 IN A 3 IN AD10242 LAYOUT INFORMATION UPOS 2.43k� The schematic of the evaluation board (Figure 15) represents a UCOM typical implementation of the AD10242. The pinout of the AD10242 is very straightforward and facilitates ease of use Figure 13. Unipolar Positive and the implementation of high frequency/high resolution To operate with –1 V, –2 V, or –4 V full-scale unipolar signals, design practices. It is recommended that high quality ceramic place a 2.67 kΩ resistor (typical, offset calibration required) chip capacitors be used to decouple each supply pin to ground between UNEG and UCOM. This again shifts the reference volt- directly at the device. All capacitors except the one placed on age setpoint to allow a unipolar negative voltage to be applied at ENCODE can be standard high quality ceramic chip capacitors. the inputs of the device. To calibrate offset, apply a midscale dc The capacitor used on the ENCODE pin must be a low induc- voltage to the converter while adjusting the unipolar resistor for tance chip capacitor as referenced previously. a midscale output transition. REV. C –12– AD10242 5VA SMA SMA SMA 5VA SMA SMA SMA J1 JA JC J8 JB JD C1 C2 14 14 0.1�F 0.1�F V V CC CC H2DM H2DM 8 8 J15 J16 OUT U1 OUT U2 12 12 K1115 K1115 V V EE EE U5 U5 7 AD9696KN 7 AD9696KN 5VA 5VA 51� 51� 8 8 2 2 H2DM H2DM R11 R9 E5 E5 J17 J18 470� 470� 3 3 12 12 BUFLATB BUFLATA 7 7 R10 C14 R12 C5 T2 5 T1 5 470� 0.1�F 470� 0.1�F T1–1T T1–1T 4 3 4 3 GND GND ENCBB ENCAB 2 2 R1 R2 B SECTION A SECTION 100� 100� 1 1 6 6 ENCB ENCA 1 : 1 1 : 1 PULSE A PULSE A PULSE B PULSE B IN OUT IN OUT H40DM U3 U4 B JACKS E4 SMA VHIGH SMA VHIGH J9 AD8036Q AD8036Q SMA SMA E1 E3 J11 J13 140 3 8 3 8 J12 J14 5VD GND 239 6 6 +5VA +5VA GND GND (MSB) D11A GND 2 2 338 D10A GND R7 R8 5 5 437 E2 VLOW VLOW 49.9� 49.9� D9A GND 536 VLOW VLOW –5.2V VHIGH VHIGH –5.2V D8A GND 635 D7A GND 734 R3 R5 R4 R6 D6A GND 833 470� 470� 470� 470� D5A GND 932 D4A GND 10 31 VHIGH GND +5V BUFLATA 11 30 U4 U3 GND U4 U3 DUT DUT U5 U6 12 29 C22 C21 C23 C17 C18 C9 C12 C3 C8 D3A GND 10�F 0.1�F 0.1�F 12 13 8 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F D2A GND 14 27 D1A GND –5.2V 15 26 VLOW (LSB) D0A GND U3 U4 DUT U5 DUT U6 16 25 U3 U4 C24 C15 C16 C10 C13 C4 C11 GND GND C19 C20 10�F 17 24 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F GND GND 0.1�F 0.1µF 18 23 GND GND 19 22 +5VD GND GND DUT DUT 20 21 C25 GND GND C7 C6 SMA SMA SMA SMA SMA SMA 10�F 0.1�F 0.1�F J2 J3 J4 J5 J6 J7 A A1 A A2 A A3 A B1 A B2 A B3 IN IN IN IN IN IN H40DM J10 140 +5VD GND 239 (MSB) D11B GND 338 D10B GND 437 D9B GND 536 96 8765 4321 686766656463621 D8B GND 635 NOTES; D7B GND 734 1) UNIPOLAR OPERATION D6B GND 833 A SIDE + CONNECT 2.43k� RES. FROM TP1 TO TP5. D5B GND A SIDE – CONNECT 2.67k� RES. FROM TP5 TO TP6. 932 10 60 GND GNDA GNDB GND D4B GND B SIDE + CONNECT 2.43k� RES. FROM TP2 TO TP4. 10 31 11 59 GND GNDA GNDB GND GND B SIDE – CONNECT 2.67k� RES. FROM TP4 TO TP3. 12 58 BUFLATB 11 30 TP1 UNIPOSA GNDB GND GND 13 57 12 29 –5.2V UNIPOSB –5.2VAA TP2 D3B GND 2) ABOVE UNIPOLAR RESISTOR VALUES ARE +5VA 14 56 13 28 +5VAA UNINEGB TP3 NOMINAL AND MAY HAVE TO BE ADJUSTED D2B GND 15 55 27 GND NCA UNICOMB TP4 14 DEPENDING ON OFFSET OF DUT. D1B GND 16 54 GND NCA GNDB GND 15 26 (LSB) D0B GND 17 D0A D0A (LSBA) GNDB 53 GND 16 25 3) ENCODE SOURCES DUT GND GND 18 D1A D1A 52 ENCB ENCB 17 24 A)FOR NORMAL OPERATION, A 40MHz TTL CLOCK AD10242 GND GND 19 51 OSCILLATOR IS INSTALLED IN U1 AND U2. THERE D2A D2A ENCB ENCB 18 23 GND GND 20 50 IS A 51� RESISTOR BETWEEN J15 AND J16. D3A D3A +5VDB +5VD 19 22 GND GND 21 49 J17 AND J18 ARE OPEN. D4A D4A (MSBB) D11B D11B 20 21 GND GND B)FOR EXTERNAL SQUARE WAVE ENCODE, INPUT 22 48 D5A D5A D10B D10B SIGNAL AT J1 AND J8, REMOVE U1, U2, JUMPERS 23 D6A D6A D9B 47 D9B J15 AND J16. CONNECT JUMPERS J17 AND J18. 24 46 D7A D7A D8B D8B C)FOR EXTERNAL SINE WAVE ENCODE, INPUT 25 45 D8A D8A D7B D7B TEST POINTS SIGNAL AT J1 AND J8, REMOVE U1, U2, R9, R11, 26 44 GND GNDA GNDB GND TP1 TP1 TP6 TP6 JUMPERS J15 AND J16. CONNECT JUMPERS J17 AND J18. TP2 TP2 TP7 ENCAB TP3 TP3 TP8 ENCA 4) POWER (5VD) FOR DIGITAL OUTPUTS OF THE 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 AD10242 IS SUPPLIED VIA PIN 1 OF EITHER J9 OR J10 TP4 TP4 TP9 ENCBB (THE DIGITAL INTERFACES). TO POWER THE EVAL. TP5 TP5 TP10 ENCB BOARD WITH ONE 5V SUPPLY, JUMPER A WIRE FROM E1 TO E4 (CONNECTED AT FACTORY). Figure 15. Evaluation Board Schematic REV. C –13– GND GNDA GNDA GND A A3 A A3 ENCA IN ENCA IN ENCA ENCA A A2 A A2 IN IN +5VD +5VDA A A1 A A1 IN IN D9A GNDA D9A GND D10A UNICOMA D10A TP5 D11A D11A (MSBA) UNINEGA TP6 GNDA GND NCB GND GND NCB SHIELD GND D0B D0B (LSBB) GNDB GND D1B –5.2V D1B –5.2VAB D2B D2B +5VAB +5VA D3B D3B GNDB GND A B3 D4B D4B A B3 IN IN A B2 D5B IN A B2 D5B IN A B1 D6B IN A B1 D6B IN GNDB GND GNDB GND AD10242 Care should be taken when placing the digital output runs. analog-to-digital converter. The board encompasses everything Because the digital outputs have such a high slew rate, the needed to ensure the highest level of performance for evaluating capacitive loading on the digital outputs should be minimized. the AD10242. Circuit traces for the digital outputs should be kept short and Power to the analog supply pins is connected via banana jacks. connect directly to the receiving gate. Internal circuitry buffers The analog supply powers the crystal oscillator, the associated the outputs of the AD9042 ADC through a resistor network to components and amplifiers, and the analog section of the eliminate the need to externally isolate the device from the AD10242. The digital outputs of the AD10242 are powered via receiving gate. Pin 1 of either J9 or J10 found on the digital interface con- nector. To power the evaluation board with one 5 V supply, a EVALUATION BOARD jumper wire is required from test point E1 to E4. Contact the The AD10242 evaluation board (see Figure 16) is designed to factory if additional layout or applications assistance is required. provide optimal performance for evaluation of the AD10242 Figure 16. Evaluation Board Mechanical Layout REV. C –14– AD10242 OUTLINE DIMENSIONS 68-Lead Ceramic Leaded Chip Carrier [CLCC] (Z-68A) Dimensions shown in inches and (millimeters) 0.235 (5.97) 0.960 (24.38) MAX 0.010 (0.25) 0.950 (24.13) SQ 0.008 (0.20) 0.940 (23.88) 0.007 (0.18) 61 9 10 60 PIN 1 DETAIL A 1.190 (30.23) 1.070 0.800 TOP VIEW (27.18) (20.32) 1.180 (29.97) SQ (PINS DOWN) MIN BSC 1.170 (29.72) TOE DOWN ANGLE 0–8 DEGREES 26 44 27 43 0.060 (1.52) DETAIL A 0.050 (1.27) 0.055 (1.40) 0.020 (0.51) 0.040 (1.02) 0.050 (1.27) 0.017 (0.44) 0.045 (1.14) 0.014 (0.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History Location Page 1/03—Data Sheet changed from REV. B to REV. C. Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Change to Encoding the AD10242 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6/01—Data Sheet changed from REV. A to REV. B. AD9631 references changed to AD9632 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal REV. C –15– –16– PRINTED IN U.S.A. C00665–0–1/03(C)