Section I. Cyclone FPGA Family Data Sheet This section provides designers with the data sheet specifications for ® Cyclone devices. The chapters contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Cyclone devices. This section contains the following chapters: ■ Chapter 1. Introduction ■ Chapter 2. Cyclone Architecture ■ Chapter 3. Configuration & Testing ■ Chapter 4. DC & Switching Characteristics ■ Chapter 5. Reference & Ordering Information Refer to each chapter for its own specific revision history. For information Revision History on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. Altera Corporation Section I–1 Preliminary Revision History Cyclone Device Handbook, Volume 1 Section I–2 Altera Corporation Preliminary 1. Introduction C51001-1.4 ® The Cyclone field programmable gate array family is based on a 1.5-V, Introduction 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase- locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices. The following shows the main sections in the Cyclone FPGA Family Data Sheet: Section Page Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12 Embedded Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18 Global Clock Network & Phase-Locked Loops. . . . . . . . . . . 2–29 I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39 Power Sequencing & Hot Socketing . . . . . . . . . . . . . . . . . . . . 2–55 IEEE Std. 1149.1 (JTAG) Boundary Scan Support . . . . . . . . . . 3–1 SignalTap II Embedded Logic Analyzer . . . . . . . . . . . . . . . . . 3–5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8 Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 Altera Corporation 1–1 January 2007 Preliminary Cyclone Device Handbook, Volume 1 The Cyclone device family offers the following features: Features ■ 2,910 to 20,060 LEs, see Table 1–1 ■ Up to 294,912 RAM bits (36,864 bytes) ■ Supports configuration through low-cost serial configuration device ■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards ■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard ■ High-speed (640 Mbps) LVDS I/O support ■ Low-speed (311 Mbps) LVDS I/O support ■ 311-Mbps RSDS I/O support ■ Up to two PLLs per device provide clock multiplication and phase shifting ■ Up to eight global clock lines with six clock resources available per logic array block (LAB) row ■ Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM ■ Support for multiple intellectual property (IP) cores, including ® ® Altera MegaCore functions and Altera Megafunctions Partners SM Program (AMPP ) megafunctions. Table 1–1. Cyclone Device Features Feature EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 LEs 2,910 4,000 5,980 12,060 20,060 M4K RAM blocks (128 ×36bits) 1317205264 Total RAM bits 59,904 78,336 92,160 239,616 294,912 PLLs 12222 Maximum user I/O pins (1) 104 301 185 249 301 Note to Table 1–1: (1) This parameter includes global clock pins. 1–2 Altera Corporation Preliminary January 2007 Features Cyclone devices are available in quad flat pack (QFP) and space-saving ® FineLine BGA packages (see Table 1–2 through 1–3). Table 1–2. Cyclone Package Options & I/O Pin Counts 100-Pin TQFP 144-Pin TQFP 240-Pin PQFP 256-Pin 324-Pin 400-Pin Device (1) (1), (2) (1) FineLine BGA FineLine BGA FineLine BGA EP1C3 65 104 EP1C4 249 301 EP1C6 98 185 185 EP1C12 173 185 249 EP1C20 233 301 Notes to Table 1–2: (1) TQFP: thin quad flat pack. PQFP: plastic quad flat pack. (2) Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the EP1C3 device in the 144-pin TQFP package and the EP1C6 device in the same package) Vertical migration means you can migrate a design from one device to another that has the same dedicated pins, JTAG pins, and power pins, and are subsets or supersets for a given package across device densities. The largest density in any package has the highest number of power pins; you must use the layout for the largest planned density in a package to provide the necessary power pins for migration. For I/O pin migration across densities, cross-reference the available I/O pins using the device pin-outs for all planned densities of a given package ® type to identify which I/O pins can be migrated. The Quartus II software can automatically cross-reference and place all pins for you when given a device migration list. If one device has power or ground pins, but these same pins are user I/O on a different device that is in the migration path,the Quartus II software ensures the pins are not used as user I/O in the Quartus II software. Ensure that these pins are connected to the appropriate plane on the board. The Quartus II software reserves I/O pins as power pins as necessary for layout with the larger densities in the same package having more power pins. Altera Corporation 1–3 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Table 1–3. Cyclone QFP & FineLine BGA Package Sizes 256-Pin 324-Pin 400-Pin 100-Pin 144-Pin 240-Pin Dimension FineLine FineLine FineLine TQFP TQFP PQFP BGA BGA BGA Pitch (mm) 0.5 0.5 0.5 1.0 1.0 1.0 2 256 484 1,024 289 361 441 Area (mm ) Length × width 16 × 16 22 × 22 34.6 × 34.6 17 × 17 19 × 19 21 × 21 (mm × mm) Table 1–4 shows the revision history for this document. Document Revision History Table 1–4. Document Revision History Date & Document Changes Made Summary of Changes Version January 2007 Added document revision history. v1.4 August 2005 Minor updates. v1.3 October 2003 Added 64-bit PCI support information. v1.2 September ● Updated LVDS data rates to 640 Mbps from 311 Mbps. 2003 v1.1 ● Updated RSDS feature information. May 2003 v1.0 Added document to Cyclone Device Handbook. 1–4 Altera Corporation Preliminary January 2007 2. Cyclone Architecture C51002-1.5 ® Cyclone devices contain a two-dimensional row- and column-based Functional architecture to implement custom logic. Column and row interconnects Description of varying speeds provide signal interconnects between LABs and embedded memory blocks. The logic array consists of LABs, with 10 LEs in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. Cyclone devices range between 2,910 to 20,060 LEs. M4K RAM blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 250 MHz. These blocks are grouped into columns across the device in between certain LABs. Cyclone devices offer between 60 to 288 Kbits of embedded RAM. Each Cyclone device I/O pin is fed by an I/O element (IOE) located at the ends of LAB rows and columns around the periphery of the device. I/O pins support various single-ended and differential I/O standards, such as the 66- and 33-MHz, 64- and 32-bit PCI standard and the LVDS I/O standard at up to 640 Mbps. Each IOE contains a bidirectional I/O buffer and three registers for registering input, output, and output-enable signals. Dual-purpose DQS, DQ, and DM pins along with delay chains (used to phase-align DDR signals) provide interface support with external memory devices such as DDR SDRAM, and FCRAM devices at up to 133 MHz (266 Mbps). Cyclone devices provide a global clock network and up to two PLLs. The global clock network consists of eight global clock lines that drive throughout the entire device. The global clock network can provide clocks for all resources within the device, such as IOEs, LEs, and memory blocks. The global clock lines can also be used for control signals. Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as external outputs for high-speed differential I/O support. Figure 2–1 shows a diagram of the Cyclone EP1C12 device. Altera Corporation 2–1 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Figure 2–1. Cyclone EP1C12 Device Block Diagram IOEs Logic Array EP1C12 Device PLL M4K Blocks The number of M4K RAM blocks, PLLs, rows, and columns vary per device. Table 2–1 lists the resources available in each Cyclone device. Table 2–1. Cyclone Device Resources M4K RAM Device PLLs LAB Columns LAB Rows Columns Blocks EP1C3 1 13 1 24 13 EP1C4 1 17 2 26 17 EP1C6 1 20 2 32 20 EP1C12 2 52 2 48 26 EP1C20 2 64 2 64 32 2–2 Altera Corporation Preliminary January 2007 Logic Array Blocks Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local Logic Array interconnect, look-up table (LUT) chain, and register chain connection Blocks lines. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the output of one LE's LUT to the adjacent LE for fast sequential LUT connections within the same LAB. Register chain connections transfer the output of one LE's register to the ® adjacent LE's register within an LAB. The Quartus II Compiler places associated logic within an LAB or adjacent LABs, allowing the use of local, LUT chain, and register chain connections for performance and area efficiency. Figure 2–2 details the Cyclone LAB. Figure 2–2. Cyclone LAB Structure Row Interconnect Column Interconnect Direct link interconnect from Direct link adjacent block interconnect from adjacent block Direct link Direct link interconnect to interconnect to adjacent block adjacent block LAB Local Interconnect LAB Interconnects The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM blocks from the left and right can also drive an LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher Altera Corporation 2–3 January 2007 Preliminary Cyclone Device Handbook, Volume 1 performance and flexibility. Each LE can drive 30 other LEs through fast local and direct link interconnects. Figure 2–3 shows the direct link connection. Figure 2–3. Direct Link Connection Direct link interconnect from Direct link interconnect from left LAB, M4K memory right LAB, M4K memory block, PLL, or IOE output block, PLL, or IOE output Direct link Direct link interconnect interconnect to left to right Local LAB Interconnect LAB Control Signals Each LAB contains dedicated logic for driving control signals to its LEs. The control signals include two clocks, two clock enables, two asynchronous clears, synchronous clear, asynchronous preset/load, synchronous load, and add/subtract control signals. This gives a maximum of 10 control signals at a time. Although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. Each LAB can use two clocks and two clock enable signals. Each LAB's clock and clock enable signals are linked. For example, any LE in a particular LAB using the labclk1 signal will also use labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses both LAB-wide clock signals. De-asserting the clock enable signal will turn off the LAB-wide clock. Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. The asynchronous load acts as a preset when the asynchronous load data input is tied high. 2–4 Altera Corporation Preliminary January 2007 Logic Elements With the LAB-wide addnsub control signal, a single LE can implement a one-bit adder and subtractor. This saves LE resources and improves performance for logic functions such as DSP correlators and signed multipliers that alternate between addition and subtraction depending on data. The LAB row clocks [5..0] and LAB local interconnect generate the LAB- TM wide control signals. The MultiTrack interconnect's inherent low skew allows clock and control signal distribution in addition to data. Figure 2–4 shows the LAB control signal generation circuit. Figure 2–4. LAB-Wide Control Signals Dedicated 6 LAB Row Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local labclkena2 Interconnect labclkena1 syncload labclr2 addnsub Local labclk1 labclk2 asyncload labclr1 synclr Interconnect or labpre The smallest unit of logic in the Cyclone architecture, the LE, is compact Logic Elements and provides advanced features with efficient logic utilization. Each LE contains a four-input LUT, which is a function generator that can implement any function of four variables. In addition, each LE contains a programmable register and carry chain with carry select capability. A single LE also supports dynamic single bit addition or subtraction mode selectable by an LAB-wide control signal. Each LE drives all types of interconnects: local, row, column, LUT chain, register chain, and direct link interconnects. See Figure 2–5. Altera Corporation 2–5 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Figure 2–5. Cyclone LE Register chain routing from previous LE LAB-wide Register Bypass Synchronous LAB Carry-In Load Programmable LAB-wide Packed Carry-In1 Register addnsub Synchronous Register Select Carry-In0 Clear LUT chain routing to next LE data1 Row, column, data2 PRN/ALD Look-Up Synchronous and direct link Carry D Q data3 Table Load and routing Chain ADATA (LUT) Clear Logic data4 ENA CLRN Row, column, and direct link routing labclr1 labclr2 Asynchronous labpre/aload Clear/Preset/ Local Routing Load Logic Chip-Wide Reset Register chain Clock & Register output Clock Enable Feedback Select labclk1 labclk2 labclkena1 labclkena2 Carry-Out0 Carry-Out1 LAB Carry-Out Each LE's programmable register can be configured for D, T, JK, or SR operation. Each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any internal logic can drive the register's clock and clear control signals. Either general-purpose I/O pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous data. The asynchronous load data input comes from the data3 input of the LE. For combinatorial functions, the LUT output bypasses the register and drives directly to the LE outputs. Each LE has three outputs that drive the local, row, and column routing resources. The LUT or register output can drive these three outputs independently. Two LE outputs drive column or row and direct link routing connections and one drives local interconnect resources. This allows the LUT to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and the LUT for unrelated 2–6 Altera Corporation Preliminary January 2007 Logic Elements functions. Another special packing mode allows the register output to feed back into the LUT of the same LE so that the register is packed with its own fan-out LUT. This provides another mechanism for improved fitting. The LE can also drive out registered and unregistered versions of the LUT output. LUT Chain & Register Chain In addition to the three general routing outputs, the LEs within an LAB have LUT chain and register chain outputs. LUT chain connections allow LUTs within the same LAB to cascade together for wide input functions. Register chain outputs allow registers within the same LAB to cascade together. The register chain output allows an LAB to use LUTs for a single combinatorial function and the registers to be used for an unrelated shift register implementation. These resources speed up connections between LABs while saving local interconnect resources. “MultiTrack Interconnect” on page 2–12 for more information on LUT chain and register chain connections. addnsub Signal The LE's dynamic adder/subtractor feature saves logic resources by using one set of LEs to implement both an adder and a subtractor. This feature is controlled by the LAB-wide control signal addnsub. The addnsub signal sets the LAB to perform either A + B or A − B. The LUT computes addition; subtraction is computed by adding the two's complement of the intended subtractor. The LAB-wide signal converts to two's complement by inverting the B bits within the LAB and setting carry-in = 1 to add one to the least significant bit (LSB). The LSB of an adder/subtractor must be placed in the first LE of the LAB, where the LAB-wide addnsub signal automatically sets the carry-in to 1. The Quartus II Compiler automatically places and uses the adder/subtractor feature when using adder/subtractor parameterized functions. LE Operating Modes The Cyclone LE can operate in one of the following modes: ■ Normal mode ■ Dynamic arithmetic mode Each mode uses LE resources differently. In each mode, eight available inputs to the LE⎯ the four data inputs from the LAB local interconnect, carry-in0 and carry-in1 from the previous LE, the LAB carry-in from the previous carry-chain LAB, and the register chain connection⎯ are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous Altera Corporation 2–7 January 2007 Preliminary Cyclone Device Handbook, Volume 1 preset/load, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all LE modes. The addnsub control signal is allowed in arithmetic mode. The Quartus II software, in conjunction with parameterized functions such as library of parameterized modules (LPM) functions, automatically chooses the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. If required, you can also create special-purpose functions that specify which LE operating mode to use for optimal performance. Normal Mode The normal mode is suitable for general logic applications and combinatorial functions. In normal mode, four data inputs from the LAB local interconnect are inputs to a four-input LUT (see Figure 2–6). The Quartus II Compiler automatically selects the carry-in or the data3 signal as one of the inputs to the LUT. Each LE can use LUT chain connections to drive its combinatorial output directly to the next LE in the LAB. Asynchronous load data for the register comes from the data3 input of the LE. LEs in normal mode support packed registers. Figure 2–6. LE in Normal Mode sload sclear aload (LAB Wide) (LAB Wide) (LAB Wide) Register chain connection addnsub (LAB Wide) ALD/PRE (1) ADATA Row, column, and Q direct link routing D data1 data2 Row, column, and ENA direct link routing data3 4-Input CLRN LUT cin (from cout of previous LE) clock (LAB Wide) Local routing data4 ena (LAB Wide) aclr (LAB Wide) LUT chain connection Register Register Feedback chain output Note to Figure 2–6: (1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain. 2–8 Altera Corporation Preliminary January 2007 Logic Elements Dynamic Arithmetic Mode The dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. An LE in dynamic arithmetic mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first two 2-input LUTs compute two summations based on a possible carry-in of 1 or 0; the other two LUTs generate carry outputs for the two chains of the carry select circuitry. As shown in Figure 2–7, the LAB carry-in signal selects either the carry-in0 or carry-in1 chain. The selected chain's logic level in turn determines which parallel sum is generated as a combinatorial or registered output. For example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 + data2 + carry-in0 or data1 + data2 + carry-in1 The other two LUTs use the data1 and data2 signals to generate two possible carry-out signals⎯ one for a carry of 1 and the other for a carry of 0. The carry-in0 signal acts as the carry select for the carry-out0 output and carry-in1 acts as the carry select for the carry-out1 output. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. The dynamic arithmetic mode also offers clock enable, counter enable, synchronous up/down control, synchronous clear, synchronous load, and dynamic adder/subtractor options. The LAB local interconnect data inputs generate the counter enable and synchronous up/down control signals. The synchronous clear and synchronous load options are LAB- wide signals that affect all registers in the LAB. The Quartus II software automatically places any registers that are not used by the counter into other LABs. The addnsub LAB-wide signal controls whether the LE acts as an adder or subtractor. Altera Corporation 2–9 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Figure 2–7. LE in Dynamic Arithmetic Mode LAB Carry-In sload sclear aload Carry-In0 (LAB Wide) (LAB Wide) (LAB Wide) Carry-In1 Register chain addnsub connection (LAB Wide) (1) ALD/PRE data1 LUT ADATA Q Row, column, and data2 direct link routing data3 D LUT Row, column, and ENA direct link routing CLRN clock (LAB Wide) LUT ena (LAB Wide) Local routing aclr (LAB Wide) LUT chain LUT connection Register chain output Register Feedback Carry-Out0 Carry-Out1 Note to Figure 2–7: (1) The addnsub signal is tied to the carry input for the first LE of a carry chain only. Carry-Select Chain The carry-select chain provides a very fast carry-select function between LEs in dynamic arithmetic mode. The carry-select chain uses the redundant carry calculation to increase the speed of carry functions. The LE is configured to calculate outputs for a possible carry-in of 0 and carry- in of 1 in parallel. The carry-in0 and carry-in1 signals from a lower- order bit feed forward into the higher-order bit via the parallel carry chain and feed into both the LUT and the next portion of the carry chain. Carry- select chains can begin in any LE within an LAB. The speed advantage of the carry-select chain is in the parallel pre- computation of carry chains. Since the LAB carry-in selects the precomputed carry chain, not every LE is in the critical path. Only the propagation delays between LAB carry-in generation (LE 5 and LE 10) are now part of the critical path. This feature allows the Cyclone architecture to implement high-speed counters, adders, multipliers, parity functions, and comparators of arbitrary width. 2–10 Altera Corporation Preliminary January 2007 Logic Elements Figure 2–8 shows the carry-select circuitry in an LAB for a 10-bit full adder. One portion of the LUT generates the sum of two bits using the input signals and the appropriate carry-in bit; the sum is routed to the output of the LE. The register can be bypassed for simple adders or used for accumulator functions. Another portion of the LUT generates carry- out bits. An LAB-wide carry-in bit selects which chain is used for the addition of given inputs. The carry-in signal for each chain, carry-in0 or carry-in1, selects the carry-out to carry forward to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it is fed to local, row, or column interconnects. Figure 2–8. Carry Select Chain LAB Carry-In 01 LAB Carry-In Sum1 A1 LE1 B1 Carry-In0 Carry-In1 A2 Sum2 LE2 LUT B2 data1 Sum data2 Sum3 A3 LUT LE3 B3 A4 Sum4 LUT LE4 B4 LUT Sum5 A5 LE5 B5 01 Carry-Out0 Carry-Out1 Sum6 A6 LE6 B6 Sum7 A7 LE7 B7 Sum8 A8 LE8 B8 Sum9 A9 LE9 B9 Sum10 A10 LE10 B10 LAB Carry-Out Altera Corporation 2–11 January 2007 Preliminary Cyclone Device Handbook, Volume 1 The Quartus II Compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. Parameterized functions such as LPM functions automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 10 LEs by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically allowing fast horizontal connections to M4K memory blocks. A carry chain can continue as far as a full column. Clear & Preset Logic Control LAB-wide signals control the logic for the register's clear and preset signals. The LE directly supports an asynchronous clear and preset function. The register preset is achieved through the asynchronous load of a logic high. The direct asynchronous preset does not require a NOT- gate push-back technique. Cyclone devices support simultaneous preset/ asynchronous load and clear signals. An asynchronous clear signal takes precedence if both signals are asserted simultaneously. Each LAB supports up to two clears and one preset signal. In addition to the clear and preset ports, Cyclone devices provide a chip- wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin. This chip-wide reset overrides all other control signals. In the Cyclone architecture, connections between LEs, M4K memory MultiTrack blocks, and device I/O pins are provided by the MultiTrack interconnect Interconnect TM structure with DirectDrive technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different speeds used for inter- and intra-design block connectivity. The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance. DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement within the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycles that typically follow design changes and additions. The MultiTrack interconnect consists of row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when 2–12 Altera Corporation Preliminary January 2007 MultiTrack Interconnect migrating through different device densities. Dedicated row interconnects route signals to and from LABs, PLLs, and M4K memory blocks within the same row. These row resources include: ■ Direct link interconnects between LABs and adjacent blocks ■ R4 interconnects traversing four blocks to the right or left The direct link interconnect allows an LAB or M4K memory block to drive into the local interconnect of its left and right neighbors. Only one side of a PLL block interfaces with direct link and row interconnects. The direct link interconnect provides fast communication between adjacent LABs and/or blocks without using row interconnect resources. The R4 interconnects span four LABs, or two LABs and one M4K RAM block. These resources are used for fast row connections in a four-LAB region. Every LAB has its own set of R4 interconnects to drive either left or right. Figure 2–9 shows R4 interconnect connections from an LAB. R4 interconnects can drive and be driven by M4K memory blocks, PLLs, and row IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4 interconnect. For R4 interconnects that drive to the right, the primary LAB and right neighbor can drive on to the interconnect. For R4 interconnects that drive to the left, the primary LAB and its left neighbor can drive on to the interconnect. R4 interconnects can drive other R4 interconnects to extend the range of LABs they can drive. R4 interconnects can also drive C4 interconnects for connections from one row to another. Altera Corporation 2–13 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Figure 2–9. R4 Interconnect Connections Adjacent LAB can R4 Interconnect Drive onto Another C4 Column Interconnects (1) Driving Right LAB's R4 Interconnect R4 Interconnect Driving Left LAB Primary LAB Neighbor LAB (2) Neighbor Notes to Figure 2–9: (1) C4 interconnects can drive R4 interconnects. (2) This pattern is repeated for every LAB in the LAB row. The column interconnect operates similarly to the row interconnect. Each column of LABs is served by a dedicated column interconnect, which vertically routes signals to and from LABs, M4K memory blocks, and row and column IOEs. These column resources include: ■ LUT chain interconnects within an LAB ■ Register chain interconnects within an LAB ■ C4 interconnects traversing a distance of four blocks in an up and down direction Cyclone devices include an enhanced interconnect structure within LABs for routing LE output to LE input connections faster using LUT chain connections and register chain connections. The LUT chain connection allows the combinatorial output of an LE to directly drive the fast input of the LE right below it, bypassing the local interconnect. These resources can be used as a high-speed connection for wide fan-in functions from LE 1 to LE 10 in the same LAB. The register chain connection allows the register output of one LE to connect directly to the register input of the next LE in the LAB for fast shift registers. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. Figure 2–10 shows the LUT chain and register chain interconnects. 2–14 Altera Corporation Preliminary January 2007 MultiTrack Interconnect Figure 2–10. LUT Chain & Register Chain Interconnects Local Interconnect Routing Among LEs in the LAB LE 1 LUT Chain Register Chain Routing to Routing to Adjacent Adjacent LE LE's Register Input LE 2 Local LE 3 Interconnect LE 4 LE 5 LE 6 LE 7 LE 8 LE 9 LE 10 The C4 interconnects span four LABs or M4K blocks up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. Figure 2–11 shows the C4 interconnect connections from an LAB in a column. The C4 interconnects can drive and be driven by all types of architecture blocks, including PLLs, M4K memory blocks, and column and row IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. Altera Corporation 2–15 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Figure 2–11. C4 Interconnect Connections Note (1) C4 Interconnect Drives Local and R4 Interconnects Up to Four Rows C4 Interconnect Driving Up LAB Row Interconnect Adjacent LAB can drive onto neighboring LAB's C4 interconnect Local Interconnect C4 Interconnect Driving Down Note to Figure 2–11: (1) Each C4 interconnect can drive either up or down four rows. 2–16 Altera Corporation Preliminary January 2007 MultiTrack Interconnect All embedded blocks communicate with the logic array similar to LAB- to-LAB interfaces. Each block (i.e., M4K memory or PLL) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. Table 2–2 shows the Cyclone device's routing scheme. Table 2–2. Cyclone Device Routing Scheme Destination Source LUT Chain v Register Chain v Local Interconnect vvvvv Direct Link v Interconnect R4 Interconnect vv v C4 Interconnect vv v LE vvvvvv M4K RAM Block vvvv PLL vvv Column IOE v Row IOE vvv Altera Corporation 2–17 January 2007 Preliminary LUT Chain Register Chain Local Interconnect Direct Link Interconnect R4 Interconnect C4 Interconnect LE M4K RAM Block PLL Column IOE Row IOE Cyclone Device Handbook, Volume 1 The Cyclone embedded memory consists of columns of M4K memory Embedded blocks. EP1C3 and EP1C6 devices have one column of M4K blocks, while Memory EP1C12 and EP1C20 devices have two columns (see Table 1–1 on page 1–2 for total RAM bits per density). Each M4K block can implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. The M4K blocks support the following features: ■ 4,608 RAM bits ■ 250 MHz performance ■ True dual-port memory ■ Simple dual-port memory ■ Single-port memory ■ Byte enable ■ Parity bits ■ Shift register ■ FIFO buffer ■ ROM ■ Mixed clock mode 1 Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. Memory Modes The M4K memory blocks include input registers that synchronize writes and output registers to pipeline designs and improve system performance. M4K blocks offer a true dual-port mode to support any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. Figure 2–12 shows true dual-port memory. Figure 2–12. True Dual-Port Memory Configuration AB data [ ] data [ ] A B address [ ] address [ ] A B wren wren A B clock clock A B clocken clocken A B q [ ] q [ ] A B aclr aclr A B 2–18 Altera Corporation Preliminary January 2007 Embedded Memory In addition to true dual-port memory, the M4K memory blocks support simple dual-port and single-port RAM. Simple dual-port memory supports a simultaneous read and write. Single-port memory supports non-simultaneous reads and writes. Figure 2–13 shows these different M4K RAM memory port configurations. Figure 2–13. Simple Dual-Port & Single-Port Memory Configurations Simple Dual-Port Memory data[ ] rdaddress[ ] wraddress[ ] rden wren q[ ] inclock outclock inclocken outclocken inaclr outaclr Single-Port Memory (1) data[ ] address[ ] wren q[ ] inclock outclock inclocken outclocken inaclr outaclr Note to Figure 2–13: (1) Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size. The memory blocks also enable mixed-width data ports for reading and writing to the RAM ports in dual-port RAM configuration. For example, the memory block can be written in ×1 mode at port A and read out in ×16 mode from port B. The Cyclone memory architecture can implement fully synchronous RAM by registering both the input and output signals to the M4K RAM block. All M4K memory block inputs are registered, providing synchronous write cycles. In synchronous operation, the memory block generates its own self-timed strobe write enable (wren) signal derived from a global clock. In contrast, a circuit using asynchronous RAM must generate the RAM wren signal while ensuring its data and address signals meet setup and hold time specifications relative to the wren Altera Corporation 2–19 January 2007 Preliminary Cyclone Device Handbook, Volume 1 signal. The output registers can be bypassed. Pseudo-asynchronous reading is possible in the simple dual-port mode of M4K blocks by clocking the read enable and read address registers on the negative clock edge and bypassing the output registers. When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents. Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size. The Quartus II software automatically implements larger memory by combining multiple M4K memory blocks. For example, two 256×16-bit RAM blocks can be combined to form a 256×32-bit RAM block. Memory performance does not degrade for memory blocks using the maximum number of words allowed. Logical memory blocks using less than the maximum number of words use physical blocks in parallel, eliminating any external control logic that would increase delays. To create a larger high-speed memory block, the Quartus II software automatically combines memory blocks with LE control logic. Parity Bit Support The M4K blocks support a parity bit for each byte. The parity bit, along with internal LE logic, can implement parity checking for error detection to ensure data integrity. You can also use parity-size data words to store user-specified control bits. Byte enables are also available for data input masking during write operations. Shift Register Support You can configure M4K memory blocks to implement shift registers for DSP applications such as pseudo-random number generators, multi- channel filtering, auto-correlation, and cross-correlation functions. These and other DSP applications require local data storage, traditionally implemented with standard flip-flops, which can quickly consume many logic cells and routing resources for large shift registers. A more efficient alternative is to use embedded memory as a shift register block, which saves logic cell and routing resources and provides a more efficient implementation with the dedicated circuitry. The size of a w × m × n shift register is determined by the input data width (w), the length of the taps (m), and the number of taps (n). The size of a w × m × n shift register must be less than or equal to the maximum number of memory bits in the M4K block (4,608 bits). The total number of shift 2–20 Altera Corporation Preliminary January 2007 Embedded Memory register outputs (number of taps n × width w) must be less than the maximum data width of the M4K RAM block (×36). To create larger shift registers, multiple memory blocks are cascaded together. Data is written into each address location at the falling edge of the clock and read from the address at the rising edge of the clock. The shift register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. Figure 2–14 shows the M4K memory block in the shift register mode. Figure 2–14. Shift Register Memory Configuration w × m × n Shift Register m-Bit Shift Register w w m-Bit Shift Register w w n Number of Taps m-Bit Shift Register w w m-Bit Shift Register w w Memory Configuration Sizes The memory address depths and output widths can be configured as 4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or 256 × 18 bits), and 128 × 32 (or 128 × 36 bits). The 128 × 32- or 36-bit configuration Altera Corporation 2–21 January 2007 Preliminary Cyclone Device Handbook, Volume 1 is not available in the true dual-port mode. Mixed-width configurations are also possible, allowing different read and write widths. Tables 2–3 and 2–4 summarize the possible M4K RAM block configurations. Table 2–3. M4K RAM Block Configurations (Simple Dual-Port) Write Port Read Port 4K × 12K × 21K × 4 512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 128 × 36 4K × 1 vvv v v v 2K × 2 vvv v v v 1K × 4 vvv v v v 512 × 8 vvv v v v 256 × 16 vvv v v v 128 × 32 vvv v v v 512 × 9 vv v 256 × 18 vv v 128 × 36 vv v Table 2–4. M4K RAM Block Configurations (True Dual-Port) Port B Port A 4K × 12K × 21K × 4 512 × 8 256 × 16 512 × 9 256 × 18 4K × 1 vvvvv 2K × 2 vvvvv 1K × 4 vvvvv 512 × 8 vvvvv 256 × 16 vvvvv 512 × 9 vv 256 × 18 vv When the M4K RAM block is configured as a shift register block, you can create a shift register up to 4,608 bits (w × m × n). 2–22 Altera Corporation Preliminary January 2007 Embedded Memory Byte Enables M4K blocks support byte writes when the write port has a data width of 16, 18, 32, or 36 bits. The byte enables allow the input data to be masked so the device can write to specific bytes. The unwritten bytes retain the previous written value. Table 2–5 summarizes the byte selection. Table 2–5. Byte Enable for M4K Blocks Notes (1), (2) byteena[3..0] datain × 18 datain × 36 [0] = 1 [8..0] [8..0] [1] = 1 [17..9] [17..9] [2] = 1 – [26..18] [3] = 1 – [35..27] Notes to Table 2–5: (1) Any combination of byte enables is possible. (2) Byte enables can be used in the same manner with 8-bit words, i.e., in × 16 and × 32 modes. Control Signals & M4K Interface The M4K blocks allow for different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M4K block registers (renwe, address, byte enable, datain, and output registers). Only the output register can be bypassed. The six labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K block. LEs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure 2–15. The R4, C4, and direct link interconnects from adjacent LABs drive the M4K block local interconnect. The M4K blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 10 direct link input connections to the M4K block are possible from the left adjacent LABs and another 10 possible from the right adjacent LAB. M4K block outputs can also connect to left and right LABs through 10 direct link interconnects each. Figure 2–16 shows the M4K block to logic array interface. Altera Corporation 2–23 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Figure 2–15. M4K RAM Block Control Signals Dedicated 6 LAB Row Clocks Local Local Interconnect Interconnect Local Local Interconnect Interconnect Local Local Interconnect Interconnect Local Local Interconnect Interconnect clocken_a alcr_a renwe_b clock_b Local Local Interconnect Interconnect clock_a renwe_a alcr_b clocken_b Figure 2–16. M4K RAM Block LAB Row Interface C4 Interconnects R4 Interconnects 10 Direct link Direct link interconnect interconnect to adjacent LAB to adjacent LAB dataout M4K RAM Block Direct link Direct link interconnect interconnect from adjacent LAB from adjacent LAB Byte enable Control Signals Clocks address datain 6 M4K RAM Block Local LAB Row Clocks Interconnect Region 2–24 Altera Corporation Preliminary January 2007 Embedded Memory Independent Clock Mode The M4K memory blocks implement independent clock mode for true dual-port memory. In this mode, a separate clock is available for each port (ports A and B). Clock A controls all registers on the port A side, while clock B controls all registers on the port B side. Each port, A and B, also supports independent clock enables and asynchronous clear signals for port A and B registers. Figure 2–17 shows an M4K memory block in independent clock mode. Figure 2–17. Independent Clock Mode Notes (1), (2) 6 LAB Row Clocks AB Memory Block 256 ´ 16 (2) 6 6 data [ ] 512 ´ 8 data [ ] A Data In Q D B D Q Data In 1,024 ´ 4 ENA ENA 2,048 ´ 2 4,096 ´ 1 byteena [ ] byteena [ ] A Byte Enable A Q D B D Q Byte Enable B ENA ENA address [ ] address [ ] Address A Address B Q D A D Q B ENA ENA wren wren A B Write/Read Write/Read D Q Write Write Q D clken Enable Enable clken A B Pulse Pulse ENA ENA Generator Generator clock clock A B Data Out Data Out D Q Q D ENA ENA q [ ] q [ ] A B Notes to Figure 2–17: (1) All registers shown have asynchronous clear ports. (2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. Input/Output Clock Mode Input/output clock mode can be implemented for both the true and simple dual-port memory modes. On each of the two ports, A or B, one clock controls all registers for inputs into the memory block: data input, wren, and address. The other clock controls the block's data output registers. Each memory block port, A or B, also supports independent clock enables and asynchronous clear signals for input and output registers. Figures 2–18 and 2–19 show the memory block in input/output clock mode. Altera Corporation 2–25 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Figure 2–18. Input/Output Clock Mode in True Dual-Port Mode Note (1), (2) 6 LAB Row Clocks 6 6 AB Memory Block 256 × 16 (2) data [ ] data [ ] A Data In Q D B D Q Data In 512 × 8 ENA ENA 1,024 × 4 2,048 × 2 4,096 × 1 byteena [ ] byteena [ ] A D Q Byte Enable A Byte Enable B Q D B ENA ENA address [ ] address [ ] A D Q Address A Address B Q D B ENA ENA wren A wren B Write/Read Write/Read D Q Write Write Q D clken Enable Enable A Pulse Pulse ENA ENA Generator Generator clock A Data Out Data Out clken B D Q Q D clock B ENA ENA q [ ] q [ ] A B Notes to Figure 2–18: (1) All registers shown have asynchronous clear ports. (2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. 2–26 Altera Corporation Preliminary January 2007 Embedded Memory Figure 2–19. Input/Output Clock Mode in Simple Dual-Port Mode Notes (1), (2) 6 LAB Row Clocks Memory Block 6 256 ´ 16 data[ ] D Q Data In 512 ´ 8 ENA 1,024 ´ 4 2,048 ´ 2 4,096 ´ 1 address[ ] Read Address D Q ENA To MultiTrack Interconnect Data Out D Q byteena[ ] ENA Byte Enable D Q ENA wraddress[ ] Write Address D Q ENA rden Read Enable D Q ENA wren outclken D Q Write Write Enable inclken ENA Pulse Generator inclock outclock Notes to Figure 2–19: (1) All registers shown except the rden register have asynchronous clear ports. (2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. Altera Corporation 2–27 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Read/Write Clock Mode The M4K memory blocks implement read/write clock mode for simple dual-port memory. You can use up to two clocks in this mode. The write clock controls the block's data inputs, wraddress, and wren. The read clock controls the data output, rdaddress, and rden. The memory blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. Figure 2–20 shows a memory block in read/write clock mode. Figure 2–20. Read/Write Clock Mode in Simple Dual-Port Mode Notes (1), (2) 6 LAB Row Clocks Memory Block 256 × 16 6 512 × 8 1,024 × 4 data[ ] D Q Data In 2,048 × 2 ENA 4,096 × 1 To MultiTrack Interconnect Data Out D Q ENA address[ ] D Q Read Address ENA wraddress[ ] Write Address D Q ENA byteena[ ] D Q Byte Enable ENA rden Read Enable D Q ENA wren rdclken Write D Q Write Enable wrclken Pulse ENA Generator wrclock rdclock Notes to Figure 2–20: (1) All registers shown except the rden register have asynchronous clear ports. (2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. 2–28 Altera Corporation Preliminary January 2007 Global Clock Network & Phase-Locked Loops Single-Port Mode The M4K memory blocks also support single-port mode, used when simultaneous reads and writes are not required. See Figure 2–21. A single M4K memory block can support up to two single-port mode RAM blocks if each RAM block is less than or equal to 2K bits in size. Figure 2–21. Single-Port Mode Note (1) 6 LAB Row Clocks RAM/ROM 6 256 × 16 512 × 8 1,024 × 4 data[ ] D Q Data In 2,048 × 2 ENA 4,096 × 1 To MultiTrack Interconnect Data Out D Q ENA address[ ] Address D Q ENA wren Write Enable outclken D Q inclken Write ENA Pulse inclock Generator outclock Note to Figure 2–21: (1) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. Cyclone devices provide a global clock network and up to two PLLs for a Global Clock complete clock management solution. Network & Phase-Locked Global Clock Network Loops There are four dedicated clock pins (CLK[3..0], two pins on the left side and two pins on the right side) that drive the global clock network, as shown in Figure 2–22. PLL outputs, logic array, and dual-purpose clock (DPCLK[7..0]) pins can also drive the global clock network. Altera Corporation 2–29 January 2007 Preliminary Cyclone Device Handbook, Volume 1 The eight global clock lines in the global clock network drive throughout the entire device. The global clock network can provide clocks for all resources within the device ⎯ IOEs, LEs, and memory blocks. The global clock lines can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin, or DQS signals for DDR SDRAM or FCRAM interfaces. Internal logic can also drive the global clock network for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. Figure 2–22 shows the various sources that drive the global clock network. Figure 2–22. Global Clock Generation Note (1) DPCLK2 DPCLK3 Cyclone Device Global Clock Network 8 DPCLK1 DPCLK4 From logic From logic array array 44 CLK0 CLK2 PLL2 PLL1 CLK1 (3) CLK3 (3) (2) 4 4 2 2 DPCLK0 DPCLK5 DPCLK7 DPCLK6 Notes to Figure 2–22: (1) The EP1C3 device in the 100-pin TQFP package has five DPCLK pins (DPCLK2, DPCLK3, DPCLK4, DPCLK6, and DPCLK7). (2) EP1C3 devices only contain one PLL (PLL 1). (3) The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins CLK1 and CLK3. 2–30 Altera Corporation Preliminary January 2007 Global Clock Network & Phase-Locked Loops Dual-Purpose Clock Pins Each Cyclone device except the EP1C3 device has eight dual-purpose clock pins, DPCLK[7..0] (two on each I/O bank). EP1C3 devices have five DPCLK pins in the 100-pin TQFP package. These dual-purpose pins can connect to the global clock network (see Figure 2–22) for high-fanout control signals such as clocks, asynchronous clears, presets, and clock enables, or protocol control signals such as TRDY and IRDY for PCI, or DQS signals for external memory interfaces. Combined Resources Each Cyclone device contains eight distinct dedicated clocking resources. The device uses multiplexers with these clocks to form six-bit buses to drive LAB row clocks, column IOE clocks, or row IOE clocks. See Figure 2–23. Another multiplexer at the LAB level selects two of the six LAB row clocks to feed the LE registers within the LAB. Figure 2–23. Global Clock Network Multiplexers Column I/O Region IO_CLK]5..0] Global Clock Network Global Clocks [3..0] Dual-Purpose Clocks [7..0] Clock [7..0] LAB Row Clock [5..0] PLL Outputs [3..0] Core Logic [7..0] Row I/O Region IO_CLK[5..0] IOE clocks have row and column block regions. Six of the eight global clock resources feed to these row and column regions. Figure 2–24 shows the I/O clock regions. Altera Corporation 2–31 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Figure 2–24. I/O Clock Regions Column I/O Clock Region IO_CLK[5..0] 6 I/O Clock Regions Cyclone Logic Array LAB Row Clocks LAB Row Clocks labclk[5..0] labclk[5..0] 6 6 LAB Row Clocks LAB Row Clocks labclk[5..0] labclk[5..0] 6 Global Clock 6 Network 8 Row I/O Regions LAB Row Clocks LAB Row Clocks labclk[5..0] labclk[5..0] 6 6 I/O Clock Regions 6 Column I/O Clock Region IO_CLK[5..0] PLLs Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as outputs for differential I/O support. Cyclone devices contain two PLLs, except for the EP1C3 device, which contains one PLL. 2–32 Altera Corporation Preliminary January 2007 Global Clock Network & Phase-Locked Loops Table 2–6 shows the PLL features in Cyclone devices. Figure 2–25 shows a Cyclone PLL. Table 2–6. Cyclone PLL Features Feature PLL Support Clock multiplication and division m/(n × post-scale counter) (1) Phase shift Down to 125-ps increments (2), (3) Programmable duty cycle Yes Number of internal clock outputs 2 Number of external clock outputs One differential or one single-ended (4) Notes to Table 2–6: (1) The m counter ranges from 2 to 32. The n counter and the post-scale counters range from 1 to 32. (2) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by 8. (3) For degree increments, Cyclone devices can shift all output frequencies in increments of 45°. Smaller degree increments are possible depending on the frequency and divide parameters. (4) The EP1C3 device in the 100-pin TQFP package does not support external clock output. The EP1C6 device in the 144-pin TQFP package does not support external clock output from PLL2. Figure 2–25. Cyclone PLL Note (1) VCO Phase Selection Selectable at Each PLL Output Port Post-Scale Counters Global clock CLK0 or ÷g0 LVDSCLK1p (2) Charge Loop ÷n Δt PFD (3) VCO ÷g1 Global clock Pump Filter CLK1 or LVDSCLK1n (2) ÷e I/O buffer Δt ÷m Notes to Figure 2–25: (1) The EP1C3 device in the 100-pin TQFP package does not support external outputs or LVDS inputs. The EP1C6 device in the 144-pin TQFP package does not support external output from PLL2. (2) LVDS input is supported via the secondary function of the dedicated clock pins. For PLL 1, the CLK0 pin’s secondary function is LVDSCLK1p and the CLK1 pin’s secondary function is LVDSCLK1n. For PLL 2, the CLK2 pin’s secondary function is LVDSCLK2p and the CLK3 pin’s secondary function is LVDSCLK2n. (3) PFD: phase frequency detector. Altera Corporation 2–33 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Figure 2–26 shows the PLL global clock connections. Figure 2–26. Cyclone PLL Global Clock Connections G1 G3 G5 G7 G0 G2 G4 G6 g0 g0 CLK0 CLK2 PLL1 g1 g1 PLL2 CLK1 (1) CLK3 (2) e e PLL1_OUT (3), (4) PLL2_OUT (3), (4) Notes to Figure 2–26: (1) PLL 1 supports one single-ended or LVDS input via pins CLK0 and CLK1. (2) PLL2 supports one single-ended or LVDS input via pins CLK2 and CLK3. (3) PLL1_OUT and PLL2_OUT support single-ended or LVDS output. If external output is not required, these pins are available as regular user I/O pins. (4) The EP1C3 device in the 100-pin TQFP package does not support external clock output. The EP1C6 device in the 144-pin TQFP package does not support external clock output from PLL2. Table 2–7 shows the global clock network sources available in Cyclone devices. Table 2–7. Global Clock Network Sources (Part 1 of 2) Source GCLK0 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7 PLL Counter PLL1 G0 vv Output PLL1 G1 vv PLL2 G0 (1) vv PLL2 G1 (1) vv Dedicated CLK0 vv Clock Input CLK1 (2) vv Pins CLK2 vv CLK3 (2) vv 2–34 Altera Corporation Preliminary January 2007 Global Clock Network & Phase-Locked Loops Table 2–7. Global Clock Network Sources (Part 2 of 2) Source GCLK0 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7 Dual-Purpose DPCLK0 (3) v Clock Pins DPCLK1 (3) v DPCLK2 v DPCLK3 v DPCLK4 v DPCLK5 (3) v DPCLK6 v DPCLK7 v Notes to Table 2–7: (1) EP1C3 devices only have one PLL (PLL 1). (2) EP1C3 devices in the 100-pin TQFP package do not have dedicated clock pins CLK1 and CLK3. (3) EP1C3 devices in the 100-pin TQFP package do not have the DPCLK0, DPCLK1, or DPCLK5 pins. Clock Multiplication & Division Cyclone PLLs provide clock synthesis for PLL output ports using m/(n × post scale counter) scaling factors. The input clock is divided by a pre-scale divider, n, and is then multiplied by the m feedback factor. The control loop drives the VCO to match f × (m/n). Each output port has IN a unique post-scale counter to divide down the high-frequency VCO. For multiple PLL outputs with different frequencies, the VCO is set to the least-common multiple of the output frequencies that meets its frequency specifications. Then, the post-scale dividers scale down the output frequency for each output port. For example, if the output frequencies required from one PLL are 33 and 66 MHz, the VCO is set to 330 MHz (the least-common multiple in the VCO's range). Each PLL has one pre-scale divider, n, that can range in value from 1 to 32. Each PLL also has one multiply divider, m, that can range in value from 2 to 32. Global clock outputs have two post scale G dividers for global clock outputs, and external clock outputs have an E divider for external clock output, both ranging from 1 to 32. The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered. Altera Corporation 2–35 January 2007 Preliminary Cyclone Device Handbook, Volume 1 External Clock Inputs Each PLL supports single-ended or differential inputs for source- synchronous receivers or for general-purpose use. The dedicated clock pins (CLK[3..0]) feed the PLL inputs. These dual-purpose pins can also act as LVDS input pins. See Figure 2–25. Table 2–8 shows the I/O standards supported by PLL input and output pins. Table 2–8. PLL I/O Standards I/O Standard CLK Input EXTCLK Output 3.3-V LVTTL/LVCMOS vv 2.5-V LVTTL/LVCMOS vv 1.8-V LVTTL/LVCMOS vv 1.5-V LVCMOS vv 3.3-V PCI vv LVDS vv SSTL-2 class I vv SSTL-2 class II vv SSTL-3 class I vv SSTL-3 class II vv Differential SSTL-2 v For more information on LVDS I/O support, see “LVDS I/O Pins” on page 2–54. External Clock Outputs Each PLL supports one differential or one single-ended output for source- synchronous transmitters or for general-purpose external clocks. If the PLL does not use these PLL_OUT pins, the pins are available for use as general-purpose I/O pins. The PLL_OUT pins support all I/O standards shown in Table 2–8. and ground voltage The external clock outputs do not have their own V CC supplies. Therefore, to minimize jitter, do not place switching I/O pins next to these output pins. The EP1C3 device in the 100-pin TQFP package 2–36 Altera Corporation Preliminary January 2007 Global Clock Network & Phase-Locked Loops does not have dedicated clock output pins. The EP1C6 device in the 144-pin TQFP package only supports dedicated clock outputs from PLL 1. Clock Feedback Cyclone PLLs have three modes for multiplication and/or phase shifting: ■ Zero delay buffer mode⎯ The external clock output pin is phase- aligned with the clock input pin for zero delay. ■ Normal mode⎯ If the design uses an internal PLL clock output, the normal mode compensates for the internal clock delay from the input clock pin to the IOE registers. The external clock output pin is phase shifted with respect to the clock input pin if connected in this mode. You defines which internal clock output from the PLL should be phase-aligned to compensate for internal clock delay. ■ No compensation mode⎯ In this mode, the PLL will not compensate for any clock networks. Phase Shifting Cyclone PLLs have an advanced clock shift capability that enables programmable phase shifts. You can enter a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. You can perform phase shifting in time units with a resolution range of 125 to 250 ps. The finest resolution equals one eighth of the VCO period. The VCO period is a function of the frequency input and the multiplication and division factors. Each clock output counter can choose a different phase of the VCO period from up to eight taps. You can use this clock output counter along with an initial setting on the post-scale counter to achieve a phase-shift range for the entire period of the output clock. The phase tap feedback to the m counter can shift all outputs to a single phase. The Quartus II software automatically sets the phase taps and counter settings according to the phase shift entered. Lock Detect Signal The lock output indicates that there is a stable clock output signal in phase with the reference clock. Without any additional circuitry, the lock signal may toggle as the PLL begins tracking the reference clock. Therefore, you may need to gate the lock signal for use as a system- control signal. For correct operation of the lock circuit below > 200 MHz. –20 C, f IN/N Altera Corporation 2–37 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Programmable Duty Cycle The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature is supported on each PLL post-scale counter (g0, g1, e). The duty cycle setting is achieved by a low- and high- time count setting for the post-scale dividers. The Quartus II software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. Control Signals There are three control signals for clearing and enabling PLLs and their outputs. You can use these signals to control PLL resynchronization and the ability to gate PLL output clocks for low-power applications. The pllenable signal enables and disables PLLs. When the pllenable signal is low, the clock output ports are driven by ground and all the PLLs go out of lock. When the pllenable signal goes high again, the PLLs relock and resynchronize to the input clocks. An input pin or LE output can drive the pllenable signal. The areset signals are reset/resynchronization inputs for each PLL. Cyclone devices can drive these input signals from input pins or from LEs. When areset is driven high, the PLL counters will reset, clearing the PLL output and placing the PLL out of lock. When driven low again, the PLL will resynchronize to its input as it relocks. The pfdena signals control the phase frequency detector (PFD) output with a programmable gate. If you disable the PFD, the VCO will operate at its last set value of control voltage and frequency with some drift, and the system will continue running when the PLL goes out of lock or the input clock disables. By maintaining the last locked frequency, the system has time to store its current settings before shutting down. You can either use their own control signal or gated locked status signals to trigger the pfdena signal. f For more information on Cyclone PLLs, see Chapter 6, Using PLLs in Cyclone Devices. 2–38 Altera Corporation Preliminary January 2007 I/O Structure IOEs support many features, including: I/O Structure ■ Differential and single-ended I/O standards ■ 3.3-V, 64- and 32-bit, 66- and 33-MHz PCI compliance ■ Joint Test Action Group (JTAG) boundary-scan test (BST) support ■ Output drive strength control ■ Weak pull-up resistors during configuration ■ Slew-rate control ■ Tri-state buffers ■ Bus-hold circuitry ■ Programmable pull-up resistors in user mode ■ Programmable input and output delays ■ Open-drain outputs ■ DQ and DQS I/O pins Cyclone device IOEs contain a bidirectional I/O buffer and three registers for complete embedded bidirectional single data rate transfer. Figure 2–27 shows the Cyclone IOE structure. The IOE contains one input register, one output register, and one output enable register. You can use the input registers for fast setup times and output registers for fast clock- to-output times. Additionally, you can use the output enable (OE) register for fast clock-to-output enable timing. The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins. IOEs can be used as input, output, or bidirectional pins. Altera Corporation 2–39 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Figure 2–27. Cyclone IOE Structure Logic Array OE Register OE DQ Output Register Output DQ Combinatorial input (1) Input Input Register DQ Note to Figure 2–27: (1) There are two paths available for combinatorial inputs to the logic array. Each path contains a unique programmable delay chain. The IOEs are located in I/O blocks around the periphery of the Cyclone device. There are up to three IOEs per row I/O block and up to three IOEs per column I/O block (column I/O blocks span two columns). The row I/O blocks drive row, column, or direct link interconnects. The column I/O blocks drive column interconnects. Figure 2–28 shows how a row I/O block connects to the logic array. Figure 2–29 shows how a column I/O block connects to the logic array. 2–40 Altera Corporation Preliminary January 2007 I/O Structure Figure 2–28. Row I/O Block Connection to the Interconnect R4 Interconnects C4 Interconnects I/O Block Local Interconnect 21 Data and Control Signals from Logic Array (1) 21 LAB Row I/O Block io_datain[2..0] and comb_io_datain[2..0] (2) Direct Link Direct Link Interconnect Interconnect from Adjacent LAB Row I/O Block to Adjacent LAB Contains up to io_clk[5:0] Three IOEs LAB Local Interconnect Notes to Figure 2–28: (1) The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output enables, io_coe[2..0], three input clock enables, io_cce_in[2..0], three output clock enables, io_cce_out[2..0], three clocks, io_cclk[2..0], three asynchronous clear signals, io_caclr[2..0], and three synchronous clear signals, io_csclr[2..0]. (2) Each of the three IOEs in the row I/O block can have one io_datain input (combinatorial or registered) and one comb_io_datain (combinatorial) input. Altera Corporation 2–41 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Figure 2–29. Column I/O Block Connection to the Interconnect Column I/O Block Contains Column I/O Block 21 Data & up to Three IOEs Control Signals from Logic Array (1) IO_datain[2:0] & 21 comb_io_datain[2..0] io_clk[5..0] (2) I/O Block Local Interconnect R4 Interconnects LAB LAB LAB LAB Local C4 Interconnects Interconnect Notes to Figure 2–29: (1) The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output enables, io_coe[2..0], three input clock enables, io_cce_in[2..0], three output clock enables, io_cce_out[2..0], three clocks, io_cclk[2..0], three asynchronous clear signals, io_caclr[2..0], and three synchronous clear signals, io_csclr[2..0]. (2) Each of the three IOEs in the column I/O block can have one io_datain input (combinatorial or registered) and one comb_io_datain (combinatorial) input. 2–42 Altera Corporation Preliminary January 2007 I/O Structure The pin's datain signals can drive the logic array. The logic array drives the control and data signals, providing a flexible routing resource. The row or column IOE clocks, io_clk[5..0], provide a dedicated routing resource for low-skew, high-speed clocks. The global clock network generates the IOE clocks that feed the row or column I/O regions (see “Global Clock Network & Phase-Locked Loops” on page 2–29). Figure 2–30 illustrates the signal paths through the I/O block. Figure 2–30. Signal Path through the I/O Block Row or Column To Other io_clk[5..0] IOEs io_datain To Logic Array comb_io_datain oe ce_in io_csclr ce_out io_coe Data and aclr/preset IOE io_cce_in Control Signal sclr Selection io_cce_out From Logic Array clk_in io_caclr clk_out io_cclk dataout io_dataout Each IOE contains its own control signal selection for the following control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset, clk_in, and clk_out. Figure 2–31 illustrates the control signal selection. Altera Corporation 2–43 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Figure 2–31. Control Signal Selection per IOE Dedicated I/O Clock [5..0] io_coe Local Interconnect io_csclr Local Interconnect io_caclr Local Interconnect io_cce_out Local Interconnect io_cce_in Local ce_out clk_out sclr/preset Interconnect io_cclk Local clk_in ce_in aclr/preset oe Interconnect In normal bidirectional operation, you can use the input register for input data requiring fast setup times. The input register can have its own clock input and clock enable separate from the OE and output registers. The output register can be used for data requiring fast clock-to-output performance. The OE register is available for fast clock-to-output enable timing. The OE and output register share the same clock source and the same clock enable source from the local interconnect in the associated LAB, dedicated I/O clocks, or the column and row interconnects. Figure 2–32 shows the IOE in bidirectional configuration. 2–44 Altera Corporation Preliminary January 2007 I/O Structure Figure 2–32. Cyclone IOE in Bidirectional I/O Configuration ioe_clk[5..0] Column or Row Interconect OE OE Register PRN DQ V CCIO clkout ENA Optional PCI Clamp CLRN ce_out V CCIO Programmable aclr/prn Pull-Up Resistor Chip-Wide Reset Output Register Output PRN Pin Delay DQ ENA Drive Strength Control Open-Drain Output sclr/preset CLRN Slew Control comb_datain Input Pin to Logic Array Delay data_in Bus Hold Input Pin to Input Register Input Register Delay or Input Pin to PRN Logic Array Delay DQ ENA clkin CLRN ce_in The Cyclone device IOE includes programmable delays to ensure zero hold times, minimize setup times, or increase clock to output times. A path in which a pin directly drives a register may require a programmable delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. Programmable delays decrease input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can program these delays Altera Corporation 2–45 January 2007 Preliminary Cyclone Device Handbook, Volume 1 to automatically minimize setup time while providing a zero hold time. Programmable delays can increase the register-to-pin delays for output registers. Table 2–9 shows the programmable delays for Cyclone devices. Table 2–9. Cyclone Programmable Delay Chain Programmable Delays Quartus II Logic Option Input pin to logic array delay Decrease input delay to internal cells Input pin to input register delay Decrease input delay to input registers Output pin delay Increase delay to output pin There are two paths in the IOE for a combinatorial input to reach the logic array. Each of the two paths can have a different delay. This allows you adjust delays from the pin to internal LE registers that reside in two different areas of the device. The designer sets the two combinatorial input delays by selecting different delays for two different paths under the Decrease input delay to internal cells logic option in the Quartus II software. When the input signal requires two different delays for the combinatorial input, the input register in the IOE is no longer available. The IOE registers in Cyclone devices share the same source for clear or preset. The designer can program preset or clear for each individual IOE. The designer can also program the registers to power up high or low after configuration is complete. If programmed to power up low, an asynchronous clear can control the registers. If programmed to power up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of another device's active-low input upon power up. If one register in an IOE uses a preset or clear signal then all registers in the IOE must use that same signal if they require preset or clear. Additionally a synchronous reset signal is available to the designer for the IOE registers. External RAM Interfacing Cyclone devices support DDR SDRAM and FCRAM interfaces at up to 133 MHz through dedicated circuitry. DDR SDRAM & FCRAM Cyclone devices have dedicated circuitry for interfacing with DDR SDRAM. All I/O banks support DDR SDRAM and FCRAM I/O pins. However, the configuration input pins in bank 1 must operate at 2.5 V because the SSTL-2 V level is 2.5 V. Additionally, the configuration CCIO 2–46 Altera Corporation Preliminary January 2007 I/O Structure output pins (nSTATUS and CONF_DONE) and all the JTAG pins in I/O bank 3 must operate at 2.5 V because the V level of SSTL-2 is 2.5 V. CCIO I/O banks 1, 2, 3, and 4 support DQS signals with DQ bus modes of × 8. For × 8 mode, there are up to eight groups of programmable DQS and DQ pins, I/O banks 1, 2, 3, and 4 each have two groups in the 324-pin and 400-pin FineLine BGA packages. Each group consists of one DQS pin, a set of eight DQ pins, and one DM pin (see Figure 2–33). Each DQS pin drives the set of eight DQ pins within that group. Figure 2–33. Cyclone Device DQ & DQS Groups in × 8 Mode Note (1) Top, Bottom, Left, or Right I/O Bank DQ Pins DQS Pin DM Pin Note to Figure 2–33: (1) Each DQ group consists of one DQS pin, eight DQ pins, and one DM pin. Table 2–10 shows the number of DQ pin groups per device. Table 2–10. DQ Pin Groups (Part 1 of 2) Number of × 8 DQ Total DQ Pin Device Package Pin Groups Count EP1C3 100-pin TQFP (1) 324 144-pin TQFP 4 32 EP1C4 324-pin FineLine BGA 8 64 400-pin FineLine BGA 8 64 Altera Corporation 2–47 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Table 2–10. DQ Pin Groups (Part 2 of 2) Number of × 8 DQ Total DQ Pin Device Package Pin Groups Count EP1C6 144-pin TQFP 4 32 240-pin PQFP 4 32 256-pin FineLine BGA 4 32 EP1C12 240-pin PQFP 4 32 256-pin FineLine BGA 4 32 324-pin FineLine BGA 8 64 EP1C20 324-pin FineLine BGA 8 64 400-pin FineLine BGA 8 64 Note to Table 2–10: (1) EP1C3 devices in the 100-pin TQFP package do not have any DQ pin groups in I/O bank 1. A programmable delay chain on each DQS pin allows for either a 90° phase shift (for DDR SDRAM), or a 72° phase shift (for FCRAM) which automatically center-aligns input DQS synchronization signals within the data window of their corresponding DQ data signals. The phase-shifted DQS signals drive the global clock network. This global DQS signal clocks DQ signals on internal LE registers. These DQS delay elements combine with the PLL’s clocking and phase shift ability to provide a complete hardware solution for interfacing to high-speed memory. The clock phase shift allows the PLL to clock the DQ output enable and output paths. The designer should use the following guidelines to meet 133 MHz performance for DDR SDRAM and FCRAM interfaces: ■ The DQS signal must be in the middle of the DQ group it clocks ■ Resynchronize the incoming data to the logic array clock using successive LE registers or FIFO buffers ■ LE registers must be placed in the LAB adjacent to the DQ I/O pin column it is fed by Figure 2–34 illustrates DDR SDRAM and FCRAM interfacing from the I/O through the dedicated circuitry to the logic array. 2–48 Altera Corporation Preliminary January 2007 I/O Structure Figure 2–34. DDR SDRAM & FCRAM Interfacing DQS OE OE LE DQ Register OE OE LE Output LE Register OE LE Register Register V CC Output LE Δ t Registers clk OE LE Input LE Adjacent DataA Register Registers LAB LEs Output LE Register -90˚ clk GND Output LE Registers Input LE DataB Registers Programmable Delay Chain PLL Global Clock Phase Shifted -90˚ LE Register LE Register Resynchronizing Adjacent LAB LEs Global Clock Programmable Drive Strength The output buffer for each Cyclone device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL and LVCMOS standards have several levels of drive strength that the designer can control. SSTL-3 class I and II, and SSTL-2 class I and II support a minimum setting, the lowest drive strength that guarantees the I /I OH OL Altera Corporation 2–49 January 2007 Preliminary Cyclone Device Handbook, Volume 1 of the standard. Using minimum settings provides signal slew rate control to reduce system noise and signal overshoot. Table 2–11 shows the possible settings for the I/O standards with drive strength control. Table 2–11. Programmable Drive Strength Note (1) I /I Current Strength Setting (mA) I/O Standard OH OL LVTTL (3.3 V) 4 8 12 16 24(2) LVCMOS (3.3 V) 2 4 8 12(2) LVTTL (2.5 V) 2 8 12 16(2) LVTTL (1.8 V) 2 8 12(2) LVCMOS (1.5 V) 2 4 8(2) Notes to Table 2–11: (1) SSTL-3 class I and II, SSTL-2 class I and II, and 3.3-V PCI I/O Standards do not support programmable drive strength. (2) This is the default current strength setting in the Quartus II software. Open-Drain Output Cyclone devices provide an optional open-drain (equivalent to an open- collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write- enable signals) that can be asserted by any of several devices. 2–50 Altera Corporation Preliminary January 2007 I/O Structure Slew-Rate Control The output buffer for each Cyclone device I/O pin has a programmable output slew-rate control that can be configured for low noise or high- speed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay to rising and falling edges. Each I/O pin has an individual slew-rate control, allowing the designer to specify the slew rate on a pin-by-pin basis. The slew-rate control affects both the rising and falling edges. Bus Hold Each Cyclone device I/O pin provides an optional bus-hold feature. The bus-hold circuitry can hold the signal on an I/O pin at its last-driven state. Since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not necessary to hold a signal level when the bus is tri-stated. The bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. The designer can select this feature individually for each I/O pin. The bus-hold output will drive no higher than V to prevent CCIO overdriving signals. If the bus-hold feature is enabled, the device cannot use the programmable pull-up option. Disable the bus-hold feature when the I/O pin is configured for differential signals. The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately 7 kΩ to pull the signal level to the last-driven state. Table 4–15 on page 4–6 gives the specific sustaining current for each V voltage level driven through this resistor and overdrive current CCIO used to identify the next-driven input level. The bus-hold circuitry is only active after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. Programmable Pull-Up Resistor Each Cyclone device I/O pin provides an optional programmable pull- up resistor during user mode. If the designer enables this feature for an I/O pin, the pull-up resistor (typically 25 kΩ) holds the output to the V level of the output pin's bank. Dedicated clock pins do not have the CCIO optional programmable pull-up resistor. Altera Corporation 2–51 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Advanced I/O Standard Support Cyclone device IOEs support the following I/O standards: ■ 3.3-V LVTTL/LVCMOS ■ 2.5-V LVTTL/LVCMOS ■ 1.8-V LVTTL/LVCMOS ■ 1.5-V LVCMOS ■ 3.3-V PCI ■ LVDS ■ RSDS ■ SSTL-2 class I and II ■ SSTL-3 class I and II ■ Differential SSTL-2 class II (on output clocks only) Table 2–12 describes the I/O standards supported by Cyclone devices. Table 2–12. Cyclone I/O Standards Board Input Reference Output Supply Termination I/O Standard Type Voltage (V ) (V) Voltage (V ) (V) REF CCIO Voltage (V ) (V) TT 3.3-V LVTTL/LVCMOS Single-ended N/A 3.3 N/A 2.5-V LVTTL/LVCMOS Single-ended N/A 2.5 N/A 1.8-V LVTTL/LVCMOS Single-ended N/A 1.8 N/A 1.5-V LVCMOS Single-ended N/A 1.5 N/A 3.3-V PCI (1) Single-ended N/A 3.3 N/A LVDS (2) Differential N/A 2.5 N/A RSDS (2) Differential N/A 2.5 N/A SSTL-2 class I and II Voltage-referenced 1.25 2.5 1.25 SSTL-3 class I and II Voltage-referenced 1.5 3.3 1.5 Differential SSTL-2 (3) Differential 1.25 2.5 1.25 Notes to Table 2–12: (1) There is no megafunction support for EP1C3 devices for the PCI compiler. However, EP1C3 devices support PCI by using the LVTTL 16-mA I/O standard and drive strength assignments in the Quartus II software. The device requires an external diode for PCI compliance. (2) EP1C3 devices in the 100-pin TQFP package do not support the LVDS and RSDS I/O standards. (3) This I/O standard is only available on output clock pins (PLL_OUT pins). EP1C3 devices in the 100-pin package do not support this I/O standard as it does not have PLL_OUT pins. Cyclone devices contain four I/O banks, as shown in Figure 2–35. I/O banks 1 and 3 support all the I/O standards listed in Table 2–12. I/O banks 2 and 4 support all the I/O standards listed in Table 2–12 except the 3.3-V PCI standard. I/O banks 2 and 4 contain dual-purpose DQS, DQ, 2–52 Altera Corporation Preliminary January 2007 I/O Structure and DM pins to support a DDR SDRAM or FCRAM interface. I/O bank 1 can also support a DDR SDRAM or FCRAM interface, however, the configuration input pins in I/O bank 1 must operate at 2.5 V. I/O bank 3 can also support a DDR SDRAM or FCRAM interface, however, all the JTAG pins in I/O bank 3 must operate at 2.5 V. Figure 2–35. Cyclone I/O Banks Notes (1), (2) I/O Bank 2 I/O Bank 1 I/O Bank 3 Also Supports Also Supports the 3.3-V PCI the 3.3-V PCI All I/O Banks Support I/O Standard I/O Standard ■ 3.3-V LVTTL/LVCMOS ■ 2.5-V LVTTL/LVCMOS ■ 1.8-V LVTTL/LVCMOS ■ 1.5-V LVCMOS I/O Bank 1 I/O Bank 3 ■ LVDS ■ RSDS ■ SSTL-2 Class I and II ■ SSTL-3 Class I and II Individual Power Bus I/O Bank 4 Notes to Figure 2–35: (1) Figure 2–35 is a top view of the silicon die. (2) Figure 2–35 is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations. Each I/O bank has its own VCCIO pins. A single device can support 1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces; each individual bank can support a different standard with different I/O voltages. Each bank also has dual- purpose VREF pins to support any one of the voltage-referenced standards (e.g., SSTL-3) independently. If an I/O bank does not use voltage-referenced standards, the V pins are available as user I/O pins. REF Altera Corporation 2–53 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Each I/O bank can support multiple standards with the same V for CCIO input and output pins. For example, when V is 3.3-V, a bank can CCIO support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs. LVDS I/O Pins A subset of pins in all four I/O banks supports LVDS interfacing. These dual-purpose LVDS pins require an external-resistor network at the transmitter channels in addition to 100-Ω termination resistors on receiver channels. These pins do not contain dedicated serialization or deserialization circuitry; therefore, internal logic performs serialization and deserialization functions. Table 2–13 shows the total number of supported LVDS channels per device density. Table 2–13. Cyclone Device LVDS Channels Device Pin Count Number of LVDS Channels EP1C3 100 (1) 144 34 EP1C4 324 103 400 129 EP1C6 144 29 240 72 256 72 EP1C12 240 66 256 72 324 103 EP1C20 324 95 400 129 Note to Table 2–13: (1) EP1C3 devices in the 100-pin TQFP package do not support the LVDS I/O standard. MultiVolt I/O Interface The Cyclone architecture supports the MultiVolt I/O interface feature, which allows Cyclone devices in all packages to interface with systems of different supply voltages. The devices have one set of V pins for CC internal operation and input buffers (V ), and four sets for I/O CCINT output drivers (V ). CCIO 2–54 Altera Corporation Preliminary January 2007 Power Sequencing & Hot Socketing The Cyclone V pins must always be connected to a 1.5-V power CCINT supply. If the V level is 1.5 V, then input pins are 1.5-V, 1.8-V, 2.5-V, CCINT and 3.3-V tolerant. The V pins can be connected to either a 1.5-V, 1.8-V, CCIO 2.5-V, or 3.3-V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as the power supply (i.e., when V pins are connected to a 1.5-V power CCIO supply, the output levels are compatible with 1.5-V systems). When V CCIO pins are connected to a 3.3-V power supply, the output high is 3.3-V and is compatible with 3.3-V or 5.0-V systems. Table 2–14 summarizes Cyclone MultiVolt I/O support. Table 2–14. Cyclone MultiVolt I/O Support Note (1) Input Signal Output Signal V (V) CCIO 1.5 V1.8 V2.5 V3.3 V5.0 V1.5 V1.8 V2.5 V3.3 V5.0 V 1.5 v (2) v (2) vv v 1.8 v (3) vv v (2) v (2) v 2.5 v (5) v (5) vv v 3.3 v (4) v (6) v (7) v (7) v (7) v (8) v v Notes to Table 2–14: (1) The PCI clamping diode must be disabled to drive an input with voltages higher than V . CCIO (2) When V = 1.5-V or 1.8-V and a 2.5-V or 3.3-V input signal feeds an input pin, higher pin leakage current is CCIO expected. Turn on Allow voltage overdrive for LVTTL / LVCMOS input pins in the Assignments > Device > Device and Pin Options > Pin Placement tab when a device has this I/O combinations. (3) When V = 1.8-V, a Cyclone device can drive a 1.5-V device with 1.8-V tolerant inputs. CCIO (4) When V = 3.3-V and a 2.5-V input signal feeds an input pin, the V supply current will be slightly larger CCIO CCIO than expected. (5) When V = 2.5-V, a Cyclone device can drive a 1.5-V or 1.8-V device with 2.5-V tolerant inputs. CCIO (6) Cyclone devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode. (7) When V = 3.3-V, a Cyclone device can drive a 1.5-V, 1.8-V, or 2.5-V device with 3.3-V tolerant inputs. CCIO (8) When V = 3.3-V, a Cyclone device can drive a device with 5.0-V LVTTL inputs but not 5.0-V LVCMOS inputs. CCIO Because Cyclone devices can be used in a mixed-voltage environment, Power they have been designed specifically to tolerate any possible power-up Sequencing & sequence. Therefore, the V and V power supplies may be CCIO CCINT powered in any order. Hot Socketing Signals can be driven into Cyclone devices before and during power up without damaging the device. In addition, Cyclone devices do not drive out during power up. Once operating conditions are reached and the device is configured, Cyclone devices operate as specified by the user. Altera Corporation 2–55 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Table 2–15 shows the revision history for this document. Document Revision History Table 2–15. Document Revision History Date & Document Changes Made Summary of Changes Version January 2007 ● Added document revision history. v1.5 ● Updated Figures 2–17, 2–18, 2–19, 2–20, 2–21, and 2–32. August 2005 Minor updates. v1.4 February 2005 ● Updated JTAG chain limits. Added test vector information. v1.3 ● Corrected Figure 2-12. ● Added a note to Tables 2-17 through 2-21 regarding violating the setup or hold time. October 2003 ● Updated phase shift information. v1.2 ● Added 64-bit PCI support information. September Updated LVDS data rates to 640 Mbps from 311 Mbps. 2003 v1.1 May 2003 v1.0 Added document to Cyclone Device Handbook. 2–56 Altera Corporation Preliminary January 2007 3. Configuration & Testing C51003-1.3 ® All Cyclone devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1 IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be (JTAG) Boundary performed either before or after, but not during configuration. Cyclone devices can also use the JTAG port for configuration together with either Scan Support ® the Quartus II software or hardware using either Jam Files (.jam) or Jam Byte-Code Files (.jbc). Cyclone devices support reconfiguring the I/O standard settings on the IOE through the JTAG BST chain. The JTAG chain can update the I/O standard for all input and output pins any time before or during user mode. Designers can use this ability for JTAG testing before configuration when some of the Cyclone pins drive or receive from other devices on the board using voltage-referenced standards. Since the Cyclone device might not be configured before JTAG testing, the I/O pins might not be configured for appropriate electrical standards for chip-to-chip communication. Programming those I/O standards via JTAG allows designers to fully test I/O connection to other devices. The JTAG pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O standards. The TDO pin voltage is determined by the V of the bank where it resides. CCIO The bank V selects whether the JTAG inputs are 1.5-V, 1.8-V, 2.5-V, or CCIO 3.3-V compatible. Cyclone devices also use the JTAG port to monitor the operation of the ® device with the SignalTap II embedded logic analyzer. Cyclone devices support the JTAG instructions shown in Table 3–1. Table 3–1. Cyclone JTAG Instructions (Part 1 of 2) JTAG Instruction Instruction Code Description 00 0000 0101 Allows a snapshot of signals at the device pins to be captured and SAMPLE/PRELOAD examined during normal device operation, and permits an initial data pattern to be output at the device pins. Also used by the SignalTap II embedded logic analyzer. 00 0000 0000 Allows the external circuitry and board-level interconnects to be EXTEST (1) tested by forcing a test pattern at the output pins and capturing test results at the input pins. 11 1111 1111 Places the 1-bit bypass register between the TDI and TDO pins, BYPASS which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation. Altera Corporation 3–1 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Table 3–1. Cyclone JTAG Instructions (Part 2 of 2) JTAG Instruction Instruction Code Description USERCODE 00 0000 0111 Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. IDCODE 00 0000 0110 Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. HIGHZ (1) 00 0000 1011 Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins. CLAMP (1) 00 0000 1010 Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding I/O pins to a state defined by the data in the boundary-scan register. ICR instructions Used when configuring a Cyclone device via the JTAG port with a TM TM MasterBlaster or ByteBlasterMV download cable, or when using a Jam File or Jam Byte-Code File via an embedded processor. PULSE_NCONFIG 00 0000 0001 Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected. CONFIG_IO 00 0000 1101 Allows configuration of I/O standards through the JTAG chain for JTAG testing. Can be executed before, after, or during configuration. Stops configuration if executed during configuration. Once issued, the CONFIG_IO instruction will hold nSTATUS low to reset the configuration device. nSTATUS is held low until the device is reconfigured. SignalTap II Monitors internal device operation with the SignalTap II embedded instructions logic analyzer. Note to Table 3–1: (1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST. In the Quartus II software, there is an Auto Usercode feature where you can choose to use the checksum value of a programming file as the JTAG user code. If selected, the checksum is automatically loaded to the USERCODE register. Choose Assignments > Device > Device and Pin Options > General. Turn on Auto Usercode. 3–2 Altera Corporation Preliminary January 2007 IEEE Std. 1149.1 (JTAG) Boundary Scan Support The Cyclone device instruction register length is 10 bits and the USERCODE register length is 32 bits. Tables 3–2 and 3–3 show the boundary-scan register length and device IDCODE information for Cyclone devices. Table 3–2. Cyclone Boundary-Scan Register Length Device Boundary-Scan Register Length EP1C3 339 EP1C4 930 EP1C6 582 EP1C12 774 EP1C20 930 Table 3–3. 32-Bit Cyclone Device IDCODE IDCODE (32 bits) (1) Device Manufacturer Identity Version (4 Bits) Part Number (16 Bits) LSB (1 Bit) (2) (11 Bits) EP1C3 0000 0010 0000 1000 0001 000 0110 1110 1 EP1C4 0000 0010 0000 1000 0101 000 0110 1110 1 EP1C6 0000 0010 0000 1000 0010 000 0110 1110 1 EP1C12 0000 0010 0000 1000 0011 000 0110 1110 1 EP1C20 0000 0010 0000 1000 0100 000 0110 1110 1 Notes to Table 3–3: (1) The most significant bit (MSB) is on the left. (2) The IDCODE’s least significant bit (LSB) is always 1. Altera Corporation 3–3 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Figure 3–1 shows the timing requirements for the JTAG signals. Figure 3–1. Cyclone JTAG Waveforms TMS TDI t JCP t t t JCH JCL t JPSU JPH TCK t t t JPXZ JPZX JPCO TDO t t JSSU JSH Signal to Be Captured t t t JSCO JSZX JSXZ Signal to Be Driven Table 3–4 shows the JTAG timing parameters and values for Cyclone devices. Table 3–4. Cyclone JTAG Timing Parameters & Values Symbol Parameter Min Max Unit t 100 ns TCK clock period JCP t 50 ns TCK clock high time JCH t TCK clock low time 50 ns JCL t JTAG port setup time 20 ns JPSU t JTAG port hold time 45 ns JPH t JTAG port clock to output 25 ns JPCO t JTAG port high impedance to valid output 25 ns JPZX t JTAG port valid output to high impedance 25 ns JPXZ t Capture register setup time 20 ns JSSU t Capture register hold time 45 ns JSH t Update register clock to output 35 ns JSCO t Update register high impedance to valid output 35 ns JSZX t Update register valid output to high impedance 35 ns JSXZ 3–4 Altera Corporation Preliminary January 2007 SignalTap II Embedded Logic Analyzer 1 Cyclone devices must be within the first 8 devices in a JTAG chain. All of these devices have the same JTAG controller. If any of the Cyclone devices are in the 9th or after they will fail ® configuration. This does not affect the SignalTap II logic analyzer. f For more information on JTAG, see the following documents: ■ AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices ■ Jam Programming & Test Language Specification Cyclone devices feature the SignalTap II embedded logic analyzer, which SignalTap II monitors design operation over a period of time through the IEEE Embedded Logic Std. 1149.1 (JTAG) circuitry. A designer can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is Analyzer particularly important for advanced packages, such as FineLine BGA packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured. The logic, circuitry, and interconnects in the Cyclone architecture are Configuration configured with CMOS SRAM elements. Altera FPGAs are reconfigurable and every device is tested with a high coverage production test program so the designer does not have to perform fault testing and can instead focus on simulation and design verification. Cyclone devices are configured at system power-up with data stored in an Altera configuration device or provided by a system controller. The Cyclone device's optimized interface allows the device to act as controller in an active serial configuration scheme with the new low-cost serial configuration device. Cyclone devices can be configured in under 120 ms using serial data at 20 MHz. The serial configuration device can be programmed via the ByteBlaster II download cable, the Altera Programming Unit (APU), or third-party programmers. In addition to the new low-cost serial configuration device, Altera offers in-system programmability (ISP)-capable configuration devices that can configure Cyclone devices via a serial data stream. The interface also enables microprocessors to treat Cyclone devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy. After a Cyclone device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Real-time changes can be made during system operation, enabling innovative reconfigurable computing applications. Altera Corporation 3–5 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Operating Modes The Cyclone architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called configuration. During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. Together, the configuration and initialization processes are called command mode. Normal device operation is called user mode. SRAM configuration elements allow Cyclone devices to be reconfigured in-circuit by loading new configuration data into the device. With real- time reconfiguration, the device is forced into command mode with a device pin. The configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. Designers can perform in-field upgrades by distributing new configuration files either within the system or remotely. A built-in weak pull-up resistor pulls all user I/O pins to V before CCIO and during device configuration. The configuration pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O standards. The voltage level of the configuration output pins is determined by the V of the bank where the pins reside. The bank CCIO V selects whether the configuration inputs are 1.5-V, 1.8-V, 2.5-V, or CCIO 3.3-V compatible. Configuration Schemes Designers can load the configuration data for a Cyclone device with one of three configuration schemes (see Table 3–5), chosen on the basis of the target application. Designers can use a configuration device, intelligent controller, or the JTAG port to configure a Cyclone device. A low-cost configuration device can automatically configure a Cyclone device at system power-up. 3–6 Altera Corporation Preliminary January 2007 Document Revision History Multiple Cyclone devices can be configured in any of the three configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device. Table 3–5. Data Sources for Configuration Configuration Scheme Data Source Active serial Low-cost serial configuration device Passive serial (PS) Enhanced or EPC2 configuration device, MasterBlaster or ByteBlasterMV download cable, or serial data source JTAG MasterBlaster or ByteBlasterMV download cable or a microprocessor with a Jam or JBC file Table 3–6 shows the revision history for this document. Document Revision History Table 3–6. Document Revision History Date & Document Changes Made Summary of Changes Version January 2007 ● Added document revision history. v1.3 ● Updated handpara note below Table 3–4. August 2005 Minor updates. V1.2 February 2005 Updated JTAG chain limits. Added information concerning test V1.1 vectors. May 2003 v1.0 Added document to Cyclone Device Handbook. Altera Corporation 3–7 January 2007 Preliminary Cyclone Device Handbook, Volume 1 3–8 Altera Corporation Preliminary January 2007 4. DC & Switching Characteristics C51004-1.6 ® Cyclone devices are offered in both commercial, industrial, and Operating extended temperature grades. However, industrial-grade and extended- Conditions temperature-grade devices may have limited speed-grade availability. Tables 4–1 through 4–16 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for Cyclone devices. Table 4–1. Cyclone Device Absolute Maximum Ratings Notes (1), (2) Symbol Parameter Conditions Minimum Maximum Unit V Supply voltage With respect to ground (3) –0.5 2.4 V CCINT V –0.5 4.6 V CCIO V Supply voltage With respect to ground (3) –0.5 2.4 V CCA V DC input voltage –0.5 4.6 V I I DC output current, per pin –25 25 mA OUT T Storage temperature No bias –65 150 ° C STG T Ambient temperature Under bias –65 135 ° C AMB T Junction temperature BGA packages under bias 135 ° C J Table 4–2. Cyclone Device Recommended Operating Conditions (Part 1 of 2) Symbol Parameter Conditions Minimum Maximum Unit V Supply voltage for internal logic (4) 1.425 1.575 V CCINT and input buffers V Supply voltage for output buffers, (4) 3.00 3.60 V CCIO 3.3-V operation Supply voltage for output buffers, (4) 2.375 2.625 V 2.5-V operation Supply voltage for output buffers, (4) 1.71 1.89 V 1.8-V operation Supply voltage for output buffers, (4) 1.4 1.6 V 1.5-V operation V Input voltage (3), (5) –0.5 4.1 V I Altera Corporation 4–1 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Table 4–2. Cyclone Device Recommended Operating Conditions (Part 2 of 2) Symbol Parameter Conditions Minimum Maximum Unit V Output voltage 0 V V O CCIO T Operating junction temperature For commercial 085 ° C J use For industrial use –40 100 ° C For extended- –40 125 ° C temperature use Table 4–3. Cyclone Device DC Operating Conditions Note (6) Typica Symbol Parameter Conditions Minimum Maximum Unit l I Input pin leakage current V = V to 0 V (8) –10 10 μA I I CCIOmax I Tri-stated I/O pin leakage V = V to 0 V (8) –10 10 μA OZ O CCIOmax current I V supply current (standby) EP1C3 4 mA CC0 CC (All M4K blocks in power-down EP1C4 6 mA mode) (7) EP1C6 6 mA EP1C12 8 mA EP1C20 12 mA R (9) Value of I/O pin pull-up resistor V = 0 V; V = 3.3 V 15 25 50 kΩ CONF I CCI0 before and during configuration V = 0 V; V = 2.5 V 20 45 70 kΩ I CCI0 V = 0 V; V = 1.8 V 30 65 100 kΩ I CCI0 V = 0 V; V = 1.5 V 50 100 150 kΩ I CCI0 Recommended value of I/O pin 12 kΩ external pull-down resistor before and during configuration Table 4–4. LVTTL Specifications (Part 1 of 2) Symbol Parameter Conditions Minimum Maximum Unit V Output supply voltage 3.0 3.6 V CCIO V High-level input voltage 1.7 4.1 V IH V Low-level input voltage –0.5 0.7 V IL 4–2 Altera Corporation Preliminary January 2007 Operating Conditions Table 4–4. LVTTL Specifications (Part 2 of 2) Symbol Parameter Conditions Minimum Maximum Unit V High-level output voltage I = –4 to –24 mA (11) 2.4 V OH OH V Low-level output voltage I = 4 to 24 mA (11) 0.45 V OL OL Table 4–5. LVCMOS Specifications Symbol Parameter Conditions Minimum Maximum Unit V Output supply voltage 3.0 3.6 V CCIO V High-level input voltage 1.7 4.1 V IH V Low-level input voltage –0.5 0.7 V IL V High-level output voltage V = 3.0, V – 0.2 V OH CCIO CCIO I = –0.1 mA OH V Low-level output voltage V = 3.0, 0.2 V OL CCIO I = 0.1 mA OL Table 4–6. 2.5-V I/O Specifications Symbol Parameter Conditions Minimum Maximum Unit V Output supply voltage 2.375 2.625 V CCIO V High-level input voltage 1.7 4.1 V IH V Low-level input voltage –0.5 0.7 V IL V High-level output voltage I = –0.1 mA 2.1 V OH OH I = –1 mA 2.0 V OH I = –2 to –16 mA (11) 1.7 V OH V Low-level output voltage I = 0.1 mA 0.2 V OL OL I = 1 mA 0.4 V OH I = 2 to 16 mA (11) 0.7 V OH Altera Corporation 4–3 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Table 4–7. 1.8-V I/O Specifications Symbol Parameter Conditions Minimum Maximum Unit V Output supply voltage 1.65 1.95 V CCIO V High-level input voltage 0.65 × V 2.25 (12) V IH CCIO V Low-level input voltage –0.3 0.35 × V V IL CCIO V High-level output voltage I = –2 to –8 mA (11) V – 0.45 V OH OH CCIO V Low-level output voltage I = 2 to 8 mA (11) 0.45 V OL OL Table 4–8. 1.5-V I/O Specifications Symbol Parameter Conditions Minimum Maximum Unit V Output supply voltage 1.4 1.6 V CCIO V High-level input voltage 0.65 × V V + 0.3 V IH CCIO CCIO (12) V Low-level input voltage –0.3 0.35 × V V IL CCIO V High-level output voltage I = –2 mA (11) 0.75 × V V OH OH CCIO V Low-level output voltage I = 2 mA (11) 0.25 × V V OL OL CCIO Table 4–9. 2.5-V LVDS I/O Specifications Note (13) Symbol Parameter Conditions Minimum Typical Maximum Unit V I/O supply voltage 2.375 2.5 2.625 V CCIO V Differential output voltage R = 100 Ω 250 550 mV OD L Δ V Change in V between R = 100 Ω 50 mV OD OD L high and low V Output offset voltage R = 100 Ω 1.125 1.25 1.375 V OS L Δ V Change in V between R = 100 Ω 50 mV OS OS L high and low V Differential input threshold V = 1.2 V –100 100 mV TH CM V Receiver input voltage 0.0 2.4 V IN range R Receiver differential input 90 100 110 Ω L resistor 4–4 Altera Corporation Preliminary January 2007 Operating Conditions Table 4–10. 3.3-V PCI Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 3.0 3.3 3.6 V CCIO V High-level input voltage 0.5 × V + V IH CCIO V 0.5 CCIO V Low-level input voltage –0.5 0.3 × V IL V CCIO V High-level output voltage I = –500 μA0.9 × V OH OUT V CCIO V Low-level output voltage I = 1,500 μA0.1 × V OL OUT V CCIO Table 4–11. SSTL-2 Class I Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 2.375 2.5 2.625 V CCIO V Termination voltage V – 0.04 V V + 0.04 V TT REF REF REF V Reference voltage 1.15 1.25 1.35 V REF V High-level input voltage V + 0.18 3.0 V IH REF V Low-level input voltage –0.3 V – 0.18 V IL REF V High-level output voltage I = –8.1 mA V + 0.57 V OH OH TT (11) V Low-level output voltage I = 8.1 mA (11) V – 0.57 V OL OL TT Table 4–12. SSTL-2 Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 2.3 2.5 2.7 V CCIO V Termination voltage V – 0.04 V V + 0.04 V TT REF REF REF V Reference voltage 1.15 1.25 1.35 V REF V High-level input voltage V + 0.18 V + 0.3 V IH REF CCIO V Low-level input voltage –0.3 V – 0.18 V IL REF V High-level output voltage I = –16.4 mA V + 0.76 V OH OH TT (11) V Low-level output voltage I = 16.4 mA V – 0.76 V OL OL TT (11) Altera Corporation 4–5 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Table 4–13. SSTL-3 Class I Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 3.0 3.3 3.6 V CCIO V Termination voltage V – 0.05 V V + 0.05 V TT REF REF REF V Reference voltage 1.3 1.5 1.7 V REF V High-level input voltage V + 0.2 V + 0.3 V IH REF CCIO V Low-level input voltage –0.3 V – 0.2 V IL REF V High-level output voltage I = –8 mA (11) V + 0.6 V OH OH TT V Low-level output voltage I = 8 mA (11) V – 0.6 V OL OL TT Table 4–14. SSTL-3 Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 3.0 3.3 3.6 V CCIO V Termination voltage V – 0.05 V V + 0.05 V TT REF REF REF V Reference voltage 1.3 1.5 1.7 V REF V High-level input voltage V + 0.2 V + 0.3 V IH REF CCIO V Low-level input voltage –0.3 V – 0.2 V IL REF V High-level output voltage I = –16 mA V + 0.8 V OH OH TT (11) V Low-level output voltage I = 16 mA (11) V – 0.8 V OL OL TT Table 4–15. Bus Hold Parameters V Level CCIO Parameter Conditions Unit 1.5 V1.8 V2.5 V3.3 V Min Max Min Max Min Max Min Max Low sustaining V > V 30 50 70 μA IN IL current (maximum) High sustaining V < V –30 –50 –70 μA IN IH current (minimum) Low overdrive 0 V < V < 200 300 500 μA IN current V CCIO High overdrive 0 V < V < –200 –300 –500 μA IN current V CCIO 4–6 Altera Corporation Preliminary January 2007 Operating Conditions Table 4–16. Cyclone Device Capacitance Note (14) Symbol Parameter Typical Unit C Input capacitance for user I/O pin 4.0 pF IO C Input capacitance for dual-purpose LVDS/user I/O pin 4.7 pF LVDS C Input capacitance for dual-purpose V /user I/O pin. 12.0 pF VREF REF C 4.4 pF Input capacitance for dual-purpose DPCLK/user I/O pin. DPCLK C Input capacitance for CLK pin. 4.7 pF CLK Notes to Tables 4–1 through 4–16: (1) Refer to the Operating Requirements for Altera Devices Data Sheet. (2) Conditions beyond those listed in Table 4–1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V for input currents less than 100 mA and periods shorter than 20 ns. (4) Maximum V rise time is 100 ms, and V must rise monotonically. CC CC (5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V and V are CCINT CCIO powered. (6) Typical values are for T = 25° C, V = 1.5 V, and V = 1.5 V, 1.8 V, 2.5 V, and 3.3 V. A CCINT CCIO (7) V = ground, no load, no toggling inputs. I (8) This value is specified for normal device operation. The value may vary during power-up. This applies for all V settings (3.3, 2.5, 1.8, and 1.5 V). CCIO (9) R is the measured value of internal pull-up resistance when the I/O pin is tied directly to GND. R value CONF CONF will be lower if an external source drives the pin higher than V . CCIO (10) Pin pull-up resistance values will lower if an external source drives the pin higher than V . CCIO (11) Drive strength is programmable according to values in Chapter 2, Cyclone Architecture, Table 2–11. (12) Overdrive is possible when a 1.5 V or 1.8 V and a 2.5 V or 3.3 V input signal feeds an input pin. Turn on “Allow voltage overdrive” for LVTTL/LVCMOS input pins in the Assignments > Device > Device and Pin Options > Pin Placement tab when a device has this I/O combination. However, higher leakage current is expected. (13) The Cyclone LVDS interface requires a resistor network outside of the transmitter channels. (14) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within ±0.5 pF. Altera Corporation 4–7 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Designers can use the Altera web Early Power Estimator to estimate the Power device power. Consumption Cyclone devices require a certain amount of power-up current to successfully power up because of the nature of the leading-edge process on which they are fabricated. Table 4–17 shows the maximum power-up current required to power up a Cyclone device. Table 4–17. Cyclone Maximum Power-Up Current (I ) Requirements (In-Rush Current) CCINT Device Commercial Specification Industrial Specification Unit EP1C3 150 180 mA EP1C4 150 180 mA EP1C6 175 210 mA EP1C12 300 360 mA EP1C20 500 600 mA Notes to Table 4–17: (1) The Cyclone devices (except for the EP1C20 device) meet the power up specification for Mini PCI. (2) The lot codes 9G0082 to 9G2999, or 9G3109 and later comply to the specifications in Table 4–17 and meet the Mini PCI specification. Lot codes appear at the top of the device. (3) The lot codes 9H0004 to 9H29999, or 9H3014 and later comply to the specifications in this table and meet the Mini PCI specification. Lot codes appear at the top of the device. Designers should select power supplies and regulators that can supply this amount of current when designing with Cyclone devices. This specification is for commercial operating conditions. Measurements were performed with an isolated Cyclone device on the board. Decoupling capacitors were not used in this measurement. To factor in the current for decoupling capacitors, sum up the current for each capacitor using the following equation: I = C (dV/dt) The exact amount of current that is consumed varies according to the process, temperature, and power ramp rate. If the power supply or regulator can supply more current than required, the Cyclone device may consume more current than the maximum current specified in Table 4–17. However, the device does not require any more current to successfully power up than what is listed in Table 4–17. The duration of the I power-up requirement depends on the V CCINT CCINT voltage supply rise time. The power-up current consumption drops when the V supply reaches approximately 0.75 V. For example, if the CCINT V rise time has a linear rise of 15 ms, the current consumption spike CCINT drops by 7.5 ms. 4–8 Altera Corporation Preliminary January 2007 Timing Model Typically, the user-mode current during device operation is lower than the power-up current in Table 4–17. Altera recommends using the Cyclone Power Calculator, available on the Altera web site, to estimate the user-mode I consumption and then select power supplies or CCINT regulators based on the higher value. The DirectDrive technology and MultiTrack interconnect ensure Timing Model predictable performance, accurate simulation, and accurate timing analysis across all Cyclone device densities and speed grades. This section describes and specifies the performance, internal, external, and PLL timing specifications. All specifications are representative of worst-case supply voltage and junction temperature conditions. Preliminary & Final Timing Timing models can have either preliminary or final status. The ® Quartus II software issues an informational message during the design compilation if the timing models are preliminary. Table 4–18 shows the status of the Cyclone device timing models. Preliminary status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible. Final timing numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under worst-case voltage and junction temperature conditions. Table 4–18. Cyclone Device Timing Model Status Device Preliminary Final EP1C3 v EP1C4 v EP1C6 v EP1C12 v EP1C20 v Altera Corporation 4–9 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Performance The maximum internal logic array clock tree frequency is limited to the specifications shown in Table 4–19. Table 4–19. Clock Tree Maximum Performance Specification -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter Definition Units Min Typ Max Min Typ Max Min Typ Max Clock tree Maximum frequency 405 320 275 MHz f that the clock tree MAX can support for clocking registered logic Table 4–20 shows the Cyclone device performance for some common designs. All performance values were obtained with the Quartus II software compilation of library of parameterized modules (LPM) functions or megafunctions. These performance values are based on EP1C6 devices in 144-pin TQFP packages. Table 4–20. Cyclone Device Performance Resources Used Performance Resource Design Size & M4K M4K -6 Speed -7 Speed -8 Speed Mode Used Function LEs Memory Memory Grade Grade Grade Bits Blocks (MHz) (MHz) (MHz) LE 16-to-1 - 21 - - 405.00 320.00 275.00 multiplexer 32-to-1 - 44 - - 317.36 284.98 260.15 multiplexer 16-bit counter - 16 - - 405.00 320.00 275.00 64-bit counter (1) - 66 - - 208.99 181.98 160.75 4–10 Altera Corporation Preliminary January 2007 Timing Model Table 4–20. Cyclone Device Performance Resources Used Performance Resource Design Size & M4K M4K -6 Speed -7 Speed -8 Speed Mode Used Function LEs Memory Memory Grade Grade Grade Bits Blocks (MHz) (MHz) (MHz) M4K RAM 128 × 36 bit Single port - 4,608 1 256.00 222.67 197.01 memory RAM 128 × 36 bit Simple - 4,608 1 255.95 222.67 196.97 block dual-port mode RAM 256 × 18 bit True dual- - 4,608 1 255.95 222.67 196.97 port mode FIFO 128 × 36 bit - 40 4,608 1 256.02 222.67 197.01 Shift register Shift 11 4,536 1 255.95 222.67 196.97 9×4×128 register Note to Table 4–20: (1) The performance numbers for this function are from an EP1C6 device in a 240-pin PQFP package. Internal Timing Parameters Internal timing parameters are specified on a speed grade basis independent of device density. Tables 4–21 through 4–24 describe the Cyclone device internal timing microparameters for LEs, IOEs, M4K memory structures, and MultiTrack interconnects. Table 4–21. LE Internal Timing Microparameter Descriptions Symbol Parameter t LE register setup time before clock SU t LE register hold time after clock H t LE register clock-to-output delay CO t LE combinatorial LUT delay for data-in to data-out LUT t Minimum clear pulse width CLR t Minimum preset pulse width PRE t Minimum clock high or low time CLKHL Altera Corporation 4–11 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Table 4–22. IOE Internal Timing Microparameter Descriptions Symbol Parameter t IOE input and output register setup time before clock SU t IOE input and output register hold time after clock H t IOE input and output register clock-to-output delay CO t Row input pin to IOE combinatorial output PIN2COMBOUT_R t Column input pin to IOE combinatorial output PIN2COMBOUT_C t Row IOE data input to combinatorial output pin COMBIN2PIN_R t Column IOE data input to combinatorial output pin COMBIN2PIN_C t Minimum clear pulse width CLR t Minimum preset pulse width PRE t Minimum clock high or low time CLKHL Table 4–23. M4K Block Internal Timing Microparameter Descriptions Symbol Parameter t Synchronous read cycle time M4KRC t Synchronous write cycle time M4KWC t Write or read enable setup time before clock M4KWERESU t Write or read enable hold time after clock M4KWEREH t Byte enable setup time before clock M4KBESU t Byte enable hold time after clock M4KBEH t A port data setup time before clock M4KDATAASU t A port data hold time after clock M4KDATAAH t A port address setup time before clock M4KADDRASU t A port address hold time after clock M4KADDRAH t B port data setup time before clock M4KDATABSU t B port data hold time after clock M4KDATABH t B port address setup time before clock M4KADDRBSU t B port address hold time after clock M4KADDRBH t Clock-to-output delay when using output registers M4KDATACO1 t Clock-to-output delay without output registers M4KDATACO2 t Minimum clock high or low time M4KCLKHL t Minimum clear pulse width M4KCLR 4–12 Altera Corporation Preliminary January 2007 Timing Model Table 4–24. Routing Delay Internal Timing Microparameter Descriptions Symbol Parameter t Delay for an R4 line with average loading; covers a distance R4 of four LAB columns t Delay for an C4 line with average loading; covers a distance C4 of four LAB rows t Local interconnect delay LOCAL Figure 4–1 shows the memory waveforms for the M4K timing parameters shown in Table 4–23. Figure 4–1. Dual-Port RAM Timing Microparameter Waveform wrclock t t WEREH WERESU wren t t WADDRSU WADDRH wraddress an-1 an a0 a1 a2 a3 a4 a5 a6 tDATAH data-in din-1 din4 din5 din6 din t DATASU rdclock t tWEREH WERESU rden t RC rdaddress bn b0 b1 b2 b3 tDATACO1 doutn-1 doutn dout0 reg_data-out doutn-2 t DATACO2 doutn unreg_data-out doutn-1 dout0 Altera Corporation 4–13 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Internal timing parameters are specified on a speed grade basis independent of device density. Tables 4–25 through 4–28 show the internal timing microparameters for LEs, IOEs, TriMatrix memory structures, DSP blocks, and MultiTrack interconnects. Table 4–25. LE Internal Timing Microparameters -6 -7 -8 Symbol Unit MinMax MinMax MinMax t 29 33 37 ps SU t 12 13 15 ps H t 173 198 224 ps CO t 454 522 590 ps LUT t 129 148 167 ps CLR t 129 148 167 ps PRE t 1,234 1,562 1,818 ps CLKHL Table 4–26. IOE Internal Timing Microparameters -6 -7 -8 Symbol Unit MinMax MinMax MinMax t 348 400 452 ps SU t 00 0 ps H t 511 587 664 ps CO t 1,130 1,299 1,469 ps PIN2COMBOUT_R t 1,135 1,305 1,475 ps PIN2COMBOUT_C t 2,627 3,021 3,415 ps COMBIN2PIN_R t 2,615 3,007 3,399 ps COMBIN2PIN_C t 280 322 364 ps CLR t 280 322 364 ps PRE t 1,234 1,562 1,818 ps CLKHL 4–14 Altera Corporation Preliminary January 2007 Timing Model Table 4–27. M4K Block Internal Timing Microparameters -6 -7 -8 Symbol Unit MinMax MinMax MinMax t 4,379 5,035 5,691 ps M4KRC t 2,910 3,346 3,783 ps M4KWC t 72 82 93 ps M4KWERESU t 43 49 55 ps M4KWEREH t 72 82 93 ps M4KBESU t 43 49 55 ps M4KBEH t 72 82 93 ps M4KDATAASU t 43 49 55 ps M4KDATAAH t 72 82 93 ps M4KADDRASU t 43 49 55 ps M4KADDRAH t 72 82 93 ps M4KDATABSU t 43 49 55 ps M4KDATABH t 72 82 93 ps M4KADDRBSU t 43 49 55 ps M4KADDRBH t 621 714 807 ps M4KDATACO1 t 4,351 5,003 5,656 ps M4KDATACO2 t 1,234 1,562 1,818 ps M4KCLKHL t 286 328 371 ps M4KCLR Table 4–28. Routing Delay Internal Timing Microparameters -6 -7 -8 Symbol Unit MinMax MinMax MinMax t 261 300 339 ps R4 t 338 388 439 ps C4 t 244 281 318 ps LOCAL External Timing Parameters External timing parameters are specified by device density and speed grade. Figure 4–2 shows the timing model for bidirectional IOE pin timing. All registers are within the IOE. Altera Corporation 4–15 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Figure 4–2. External Timing in Cyclone Devices OE Register PRN DQ t XZ Dedicated t ZX Clock t INSU t INH CLRN t OUTCO Output Register PRN Bidirectional DQ Pin CLRN Input Register PRN DQ CLRN All external I/O timing parameters shown are for 3.3-V LVTTL I/O standard with the maximum current strength and fast slew rate. For external I/O timing using standards other than LVTTL or for different current strengths, use the I/O standard input and output delay adders in Tables 4–40 through 4–44. Table 4–29 shows the external I/O timing parameters when using global clock networks. Table 4–29. Cyclone Global Clock External I/O Timing Parameters Notes (1), (2) (Part 1 of 2) Symbol Parameter Conditions t Setup time for input or bidirectional pin using IOE input INSU register with global clock fed by CLK pin t Hold time for input or bidirectional pin using IOE input IN H register with global clock fed by CLK pin t Clock-to-output delay output or bidirectional pin using IOE C = 10 pF OUTCO LOAD output register with global clock fed by CLK pin t Setup time for input or bidirectional pin using IOE input INSUPLL register with global clock fed by Enhanced PLL with default phase setting t Hold time for input or bidirectional pin using IOE input INHPLL register with global clock fed by enhanced PLL with default phase setting 4–16 Altera Corporation Preliminary January 2007 Timing Model Table 4–29. Cyclone Global Clock External I/O Timing Parameters Notes (1), (2) (Part 2 of 2) Symbol Parameter Conditions t Clock-to-output delay output or bidirectional pin using IOE C = 10 pF OUTCOPLL LOAD output register with global clock enhanced PLL with default phase setting Notes to Table 4–29: (1) These timing parameters are sample-tested only. (2) These timing parameters are for IOE pins using a 3.3-V LVTTL, 24-mA setting. Designers should use the Quartus II software to verify the external timing for any pin. Tables 4–30 through 4–31 show the external timing parameters on column and row pins for EP1C3 devices. Table 4–30. EP1C3 Column Pin Global Clock External I/O Timing Parameters -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Unit Min Max Min Max Min Max t 3.085 3.547 4.009 ns INSU t 0.000 0.000 0.000 ns IN H t 2.000 4.073 2.000 4.682 2.000 5.295 ns OUTCO t 1.795 2.063 2.332 ns INSUPLL t 0.000 0.000 0.000 ns INHPLL t 0.500 2.306 0.500 2.651 0.500 2.998 ns OUTCOPLL Table 4–31. EP1C3 Row Pin Global Clock External I/O Timing Parameters -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Unit Min Max Min Max Min Max t 3.157 3.630 4.103 ns INSU t 0.000 0.000 0.000 ns IN H t 2.000 3.984 2.000 4.580 2.000 5.180 ns OUTCO t 1.867 2.146 2.426 ns INSUPLL t 0.000 0.000 0.000 ns INHPLL t 0.500 2.217 0.500 2.549 0.500 2.883 ns OUTCOPLL Altera Corporation 4–17 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Tables 4–32 through 4–33 show the external timing parameters on column and row pins for EP1C4 devices. Table 4–32. EP1C4 Column Pin Global Clock External I/O Timing Parameters Note (1) -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Unit Min Max Min Max Min Max t 2.471 2.841 3.210 ns INSU t 0.000 0.000 0.000 ns IN H t 2.000 3.937 2.000 4.526 2.000 5.119 ns OUTCO t 1.471 1.690 1.910 ns INSUPLL t 0.000 0.000 0.000 ns INHPLL t 0.500 2.080 0.500 2.392 0.500 2.705 ns OUTCOPLL Table 4–33. EP1C4 Row Pin Global Clock External I/O Timing Parameters Note (1) -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Unit Min Max Min Max Min Max t 2.600 2.990 3.379 ns INSU t 0.000 0.000 0.000 ns IN H t 2.000 3.991 2.000 4.388 2.000 5.189 ns OUTCO t 1.300 1.494 1.689 ns INSUPLL t 0.000 0.000 0.000 ns INHPLL t 0.500 2.234 0.500 2.569 0.500 2.905 ns OUTCOPLL Note to Tables 4–32 and 4–33: (1) Contact Altera Applications for EP1C4 device timing parameters. 4–18 Altera Corporation Preliminary January 2007 Timing Model Tables 4–34 through 4–35 show the external timing parameters on column and row pins for EP1C6 devices. Table 4–34. EP1C6 Column Pin Global Clock External I/O Timing Parameters -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Unit Min Max Min Max Min Max t 2.691 3.094 3.496 ns INSU t 0.000 0.000 0.000 ns IN H t 2.000 3.917 2.000 4.503 2.000 5.093 ns OUTCO t 1.513 1.739 1.964 ns INSUPLL t 0.000 0.000 0.000 ns INHPLL t 0.500 2.038 0.500 2.343 0.500 2.651 ns OUTCOPLL Table 4–35. EP1C6 Row Pin Global Clock External I/O Timing Parameters -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Unit Min Max Min Max Min Max t 2.774 3.190 3.605 ns INSU t 0.000 0.000 0.000 ns IN H t 2.000 3.817 2.000 4.388 2.000 4.963 ns OUTCO t 1.596 1.835 2.073 ns INSUPLL t 0.000 0.000 0.000 ns INHPLL t 0.500 1.938 0.500 2.228 0.500 2.521 ns OUTCOPLL Tables 4–36 through 4–37 show the external timing parameters on column and row pins for EP1C12 devices. Table 4–36. EP1C12 Column Pin Global Clock External I/O Timing Parameters (Part 1 of 2) -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Unit Min Max Min Max Min Max t 2.510 2.885 3.259 ns INSU t 0.000 0.000 0.000 ns IN H tO 2.000 3.798 2.000 4.367 2.000 4.940 ns UTCO t 1.588 1.824 2.061 ns INSUPLL Altera Corporation 4–19 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Table 4–36. EP1C12 Column Pin Global Clock External I/O Timing Parameters (Part 2 of 2) -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Unit Min Max Min Max Min Max t 0.000 0.000 0.000 ns INHPLL t 0.500 1.663 0.500 1.913 0.500 2.164 ns OUTCOPLL Table 4–37. EP1C12 Row Pin Global Clock External I/O Timing Parameters -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Unit Min Max Min Max Min Max t 2.620 3.012 3.404 ns INSU t 0.000 0.000 0.000 ns IN H t 2.000 3.671 2.000 4.221 2.000 4.774 ns OUTCO t 1.698 1.951 2.206 ns INSUPLL t 0.000 0.000 0.000 ns INHPLL t 0.500 1.536 0.500 1.767 0.500 1.998 ns OUTCOPLL Tables 4–38 through 4–39 show the external timing parameters on column and row pins for EP1C20 devices. Table 4–38. EP1C20 Column Pin Global Clock External I/O Timing Parameters -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Unit Min Max Min Max Min Max t 2.417 2.779 3.140 ns INSU t 0.000 0.000 0.000 ns IN H t 2.000 3.724 2.000 4.282 2.000 4.843 ns OUTCO t 1.417 1.629 1.840 ns INSUPLL t 0.000 0.000 0.000 ns INHPLL t 0.500 1.667 0.500 1.917 0.500 2.169 ns OUTCOPLL 4–20 Altera Corporation Preliminary January 2007 Timing Model Table 4–39. EP1C20 Row Pin Global Clock External I/O Timing Parameters -6 Speed Grade -7 Speed Grade -8 Speed Grade Symbol Unit Min Max Min Max Min Max t 2.417 2.779 3.140 ns INSU t 0.000 0.000 0.000 ns IN H t 2.000 3.724 2.000 4.282 2.000 4.843 ns OUTCO t 3.645 4.191 4.740 ns XZ t 3.645 4.191 4.740 ns ZX t 1.417 1.629 1.840 ns INSUPLL t 0.000 0.000 0.000 ns INHPLL t 0.500 1.667 0.500 1.917 0.500 2.169 ns OUTCOPLL t 1.588 1.826 2.066 ns XZPLL t 1.588 1.826 2.066 ns ZXPLL External I/O Delay Parameters External I/O delay timing parameters for I/O standard input and output adders and programmable input and output delays are specified by speed grade independent of device density. Tables 4–40 through 4–45 show the adder delays associated with column and row I/O pins for all packages. If an I/O standard is selected other than LVTTL 4 mA with a fast slew rate, add the selected delay to the and t I/O parameters shown in Tables 4–25 through external t CO SU 4–28. Table 4–40. Cyclone I/O Standard Column Pin Input Delay Adders (Part 1 of 2) -6 Speed Grade -7 Speed Grade -8 Speed Grade I/O Standard Unit Min Max Min Max Min Max LVCMOS 000ps 3.3-V LVTTL 0 0 0 ps 2.5-V LVTTL 27 31 35 ps 1.8-V LVTTL 182 209 236 ps 1.5-V LVTTL 278 319 361 ps SSTL-3 class I − 250 − 288 − 325 ps SSTL-3 class II − 250 − 288 − 325 ps SSTL-2 class I − 278 − 320 − 362 ps Altera Corporation 4–21 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Table 4–40. Cyclone I/O Standard Column Pin Input Delay Adders (Part 2 of 2) -6 Speed Grade -7 Speed Grade -8 Speed Grade I/O Standard Unit Min Max Min Max Min Max SSTL-2 class II − 278 − 320 − 362 ps LVDS − 261 − 301 − 340 ps Table 4–41. Cyclone I/O Standard Row Pin Input Delay Adders -6 Speed Grade -7 Speed Grade -8 Speed Grade I/O Standard Unit Min Max Min Max Min Max LVCMOS 000ps 3.3-V LVTTL 0 0 0 ps 2.5-V LVTTL 27 31 35 ps 1.8-V LVTTL 182 209 236 ps 1.5-V LVTTL 278 319 361 ps 3.3-V PCI (1) 000ps SSTL-3 class I − 250 − 288 − 325 ps SSTL-3 class II − 250 − 288 − 325 ps SSTL-2 class I − 278 − 320 − 362 ps SSTL-2 class II − 278 − 320 − 362 ps LVDS − 261 − 301 − 340 ps Table 4–42. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2) -6 Speed Grade -7 Speed Grade -8 Speed Grade Standard Unit Min Max Min Max Min Max LVCMOS 2 mA 0 0 0 ps 4 mA − 489 − 563 − 636 ps 8 mA − 855 − 984 − 1,112 ps 12 mA − 993 − 1,142 − 1,291 ps 3.3-V LVTTL 4 mA 0 0 0 ps 8 mA − 347 − 400 − 452 ps 12 mA − 858 − 987 − 1,116 ps 16 mA − 819 − 942 − 1,065 ps 24 mA − 993 − 1,142 − 1,291 ps 4–22 Altera Corporation Preliminary January 2007 Timing Model Table 4–42. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 2 of 2) -6 Speed Grade -7 Speed Grade -8 Speed Grade Standard Unit Min Max Min Max Min Max 2.5-V LVTTL 2 mA 329 378 427 ps 8 mA − 661 − 761 − 860 ps 12 mA − 655 − 754 − 852 ps 16 mA − 795 − 915 − 1034 ps 1.8-V LVTTL 2 mA 4 4 5 ps 8 mA − 208 − 240 − 271 ps 12 mA − 208 − 240 − 271 ps 1.5-V LVTTL 2 mA 2,288 2,631 2,974 ps 4 mA 608 699 790 ps 8 mA 292 335 379 ps SSTL-3 class I − 410 − 472 − 533 ps SSTL-3 class II − 811 − 933 − 1,055 ps SSTL-2 class I − 485 − 558 − 631 ps SSTL-2 class II − 758 − 872 − 986 ps LVDS − 998 − 1, 148 − 1,298 ps Table 4–43. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 1 of 2) -6 Speed Grade -7 Speed Grade -8 Speed Grade Standard Unit Min Max Min Max Min Max LVCMOS 2 mA 0 0 0 ps 4 mA − 489 − 563 − 636 ps 8 mA − 855 − 984 − 1,112 ps 12 mA − 993 − 1,142 − 1,291 ps 3.3-V LVTTL 4 mA 0 0 0 ps 8 mA − 347 − 400 − 452 ps 12 mA -858 − 987 − 1,116 ps 16 mA − 819 − 942 − 1,065 ps 24 mA − 993 − 1,142 − 1,291 ps 2.5-V LVTTL 2 mA 329 378 427 ps 8 mA − 661 − 761 − 860 ps 12 mA − 655 − 754 − 852 ps 16 mA − 795 − 915 − 1,034 ps Altera Corporation 4–23 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Table 4–43. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 2 of 2) -6 Speed Grade -7 Speed Grade -8 Speed Grade Standard Unit Min Max Min Max Min Max 1.8-V LVTTL 2 mA 1,290 1,483 1,677 ps 8 mA 4 4 5 ps 12 mA − 208 − 240 − 271 ps 1.5-V LVTTL 2 mA 2,288 2,631 2,974 ps 4 mA 608 699 790 ps 8 mA 292 335 379 ps 3.3-V PCI (1) − 877 − 1,009 − 1,141 ps SSTL-3 class I − 410 − 472 − 533 ps SSTL-3 class II − 811 − 933 − 1,055 ps SSTL-2 class I − 485 − 558 − 631 ps SSTL-2 class II − 758 − 872 − 986 ps LVDS − 998 − 1,148 − 1,298 ps Table 4–44. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 1 of 2) -6 Speed Grade -7 Speed Grade -8 Speed Grade I/O Standard Unit Min Max Min Max Min Max LVCMOS 2 mA 1,800 2,070 2,340 ps 4 mA 1,311 1,507 1,704 ps 8 mA 945 1,086 1,228 ps 12 mA 807 928 1,049 ps 3.3-V LVTTL 4 mA 1,831 2,105 2,380 ps 8 mA 1,484 1,705 1,928 ps 12 mA 973 1,118 1,264 ps 16 mA 1,012 1,163 1,315 ps 24 mA 838 963 1,089 ps 2.5-V LVTTL 2 mA 2,747 3,158 3,570 ps 8 mA 1,757 2,019 2,283 ps 12 mA 1,763 2,026 2,291 ps 16 mA 1,623 1,865 2,109 ps 1.8-V LVTTL 2 mA 5,506 6,331 7,157 ps 8 mA 4,220 4,852 5,485 ps 12 mA 4,008 4,608 5,209 ps 4–24 Altera Corporation Preliminary January 2007 Timing Model Table 4–44. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 2 of 2) -6 Speed Grade -7 Speed Grade -8 Speed Grade I/O Standard Unit Min Max Min Max Min Max 1.5-V LVTTL 2 mA 6,789 7,807 8,825 ps 4 mA 5,109 5,875 6,641 ps 8 mA 4,793 5,511 6,230 ps SSTL-3 class I 1,390 1,598 1,807 ps SSTL-3 class II 989 1,137 1,285 ps SSTL-2 class I 1,965 2,259 2,554 ps SSTL-2 class II 1,692 1,945 2,199 ps LVDS 802 922 1,042 ps Table 4–45. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 1 of 2) -6 Speed Grade -7 Speed Grade -8 Speed Grade I/O Standard Unit Min Max Min Max Min Max LVCMOS 2 mA 1,800 2,070 2,340 ps 4 mA 1,311 1,507 1,704 ps 8 mA 945 1,086 1,228 ps 12 mA 807 928 1,049 ps 3.3-V LVTTL 4 mA 1,831 2,105 2,380 ps 8 mA 1,484 1,705 1,928 ps 12 mA 973 1,118 1,264 ps 16 mA 1,012 1,163 1,315 ps 24 mA 838 963 1,089 ps 2.5-V LVTTL 2 mA 2,747 3,158 3,570 ps 8 mA 1,757 2,019 2,283 ps 12 mA 1,763 2,026 2,291 ps 16 mA 1,623 1,865 2,109 ps 1.8-V LVTTL 2 mA 5,506 6,331 7,157 ps 8 mA 4,220 4,852 5,485 ps 12 mA 4,008 4,608 5,209 ps 1.5-V LVTTL 2 mA 6,789 7,807 8,825 ps 4 mA 5,109 5,875 6,641 ps 8 mA 4,793 5,511 6,230 ps 3.3-V PCI 923 1,061 1,199 ps Altera Corporation 4–25 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Table 4–45. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 2 of 2) -6 Speed Grade -7 Speed Grade -8 Speed Grade I/O Standard Unit Min Max Min Max Min Max SSTL-3 class I 1,390 1,598 1,807 ps SSTL-3 class II 989 1,137 1,285 ps SSTL-2 class I 1,965 2,259 2,554 ps SSTL-2 class II 1,692 1,945 2,199 ps LVDS 802 922 1,042 ps Note to Tables 4–40 through 4–45: (1) EP1C3 devices do not support the PCI I/O standard. Tables 4–46 through 4–47 show the adder delays for the IOE programmable delays. These delays are controlled with the Quartus II software options listed in the Parameter column. Table 4–46. Cyclone IOE Programmable Delays on Column Pins -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter Setting Unit Min Max Min Max Min Max Decrease input delay to Off 155 178 201 ps internal cells Small 2,122 2,543 2,875 ps Medium 2,639 3,034 3,430 ps Large 3,057 3,515 3,974 ps On 155 178 201 ps Decrease input delay to Off 000ps input register On 3,057 3,515 3,974 ps Increase delay to output Off 000ps pin On 552 634 717 ps 4–26 Altera Corporation Preliminary January 2007 Timing Model Table 4–47. Cyclone IOE Programmable Delays on Row Pins -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter Setting Unit Min Max Min Max Min Max Decrease input delay to Off 154 177 200 ps internal cells Small 2,212 2,543 2,875 ps Medium 2,639 3,034 3,430 ps Large 3,057 3,515 3,974 ps On 154 177 200 ps Decrease input delay to input Off 000ps register On 3,057 3,515 3,974 ps Increase delay to output pin Off 0 0 0 ps On 556 639 722 ps Note to Table 4–47: (1) EPC1C3 devices do not support the PCI I/O standard Maximum Input & Output Clock Rates Tables 4–48 and 4–49 show the maximum input clock rate for column and row pins in Cyclone devices. Table 4–48. Cyclone Maximum Input Clock Rate for Column Pins -6 Speed -7 Speed -8 Speed I/O Standard Unit Grade Grade Grade LVTTL 464 428 387 MHz 2.5 V 392 302 207 MHz 1.8 V 387 311 252 MHz 1.5 V 387 320 243 MHz LVCMOS 405 374 333 MHz SSTL-3 class I 405 356 293 MHz SSTL-3 class II 414 365 302 MHz SSTL-2 class I 464 428 396 MHz SSTL-2 class II 473 432 396 MHz LVDS 567 549 531 MHz Altera Corporation 4–27 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Table 4–49. Cyclone Maximum Input Clock Rate for Row Pins -6 Speed -7 Speed -8 Speed I/O Standard Unit Grade Grade Grade LVTTL 464 428 387 MHz 2.5 V 392 302 207 MHz 1.8 V 387 311 252 MHz 1.5 V 387 320 243 MHz LVCMOS 405 374 333 MHz SSTL-3 class I 405 356 293 MHz SSTL-3 class II 414 365 302 MHz SSTL-2 class I 464 428 396 MHz SSTL-2 class II 473 432 396 MHz 3.3-V PCI (1) 464 428 387 MHz LVDS 567 549 531 MHz Note to Tables 4–48 through 4–49: (1) EP1C3 devices do not support the PCI I/O standard. These parameters are only available on row I/O pins. Tables 4–50 and 4–51 show the maximum output clock rate for column and row pins in Cyclone devices. Table 4–50. Cyclone Maximum Output Clock Rate for Column Pins -6 Speed -7 Speed -8 Speed I/O Standard Unit Grade Grade Grade LVTTL 304 304 304 MHz 2.5 V 220 220 220 MHz 1.8 V 213 213 213 MHz 1.5 V 166 166 166 MHz LVCMOS 304 304 304 MHz SSTL-3 class I 100 100 100 MHz SSTL-3 class II 100 100 100 MHz SSTL-2 class I 134 134 134 MHz SSTL-2 class II 134 134 134 MHz LVDS 320 320 275 MHz Note to Table 4–50: (1) EP1C3 devices do not support the PCI I/O standard. 4–28 Altera Corporation Preliminary January 2007 Timing Model Table 4–51. Cyclone Maximum Output Clock Rate for Row Pins -6 Speed -7 Speed -8 Speed I/O Standard Unit Grade Grade Grade LVTTL 296 285 273 MHz 2.5 V 381 366 349 MHz 1.8 V 286 277 267 MHz 1.5 V 219 208 195 MHz LVCMOS 367 356 343 MHz SSTL-3 class I 169 166 162 MHz SSTL-3 class II 160 151 146 MHz SSTL-2 class I 160 151 142 MHz SSTL-2 class II 131 123 115 MHz 3.3-V PCI (1) 66 66 66 MHz LVDS 320 303 275 MHz Note to Tables 4–50 through 4–51: (1) EP1C3 devices do not support the PCI I/O standard. These parameters are only available on row I/O pins. PLL Timing Table 4–52 describes the Cyclone FPGA PLL specifications. Table 4–52. Cyclone PLL Specifications (Part 1 of 2) Symbol Parameter Min Max Unit f Input frequency (-6 speed 15.625 464 MHz IN grade) Input frequency (-7 speed 15.625 428 MHz grade) Input frequency (-8 speed 15.625 387 MHz grade) f DUTY Input clock duty cycle 40.00 60 % IN t JITTER Input clock period jitter ps IN ± 200 f (external PLL PLL output frequency 15.625 320 MHz OUT_EXT (-6 speed grade) clock output) PLL output frequency 15.625 320 MHz (-7 speed grade) PLL output frequency 15.625 275 MHz (-8 speed grade) Altera Corporation 4–29 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Table 4–52. Cyclone PLL Specifications (Part 2 of 2) Symbol Parameter Min Max Unit f (to global clock) PLL output frequency 15.625 405 MHz OUT (-6 speed grade) PLL output frequency 15.625 320 MHz (-7 speed grade) PLL output frequency 15.625 275 MHz (-8 speed grade) t DUTY Duty cycle for external clock 45.00 55 % OUT output (when set to 50%) t (1) Period jitter for external clock ±300 (2) ps JITTER output t (3) Time required to lock from end 10.00 100 μs LOCK of device configuration f PLL internal VCO operating 500.00 1,000 MHz VCO range - Minimum areset time 10 ns N, G0, G1, E Counter values 1 32 integer Notes to Table 4–52: (1) The t specification for the PLL[2..1]_OUT pins are dependent on the I/O pins in its V bank, how many JITTER CCIO of them are switching outputs, how much they toggle, and whether or not they use programmable current strength or slow slew rate. (2) f ≥ 100 MHz. When the PLL external clock output frequency (f ) is smaller than 100 MHz, the jitter OUT OUT specification is 60 mUI. (3) f must be greater than 200 MHz to ensure correct lock detect circuit operation below –20 C. Otherwise, the PLL IN/N operates with the specified parameters under the specified conditions. 4–30 Altera Corporation Preliminary January 2007 Document Revision History Table 4–53 shows the revision history for this document. Document Revision History Table 4–53. Document Revision History Date & Document Changes Made Summary of Changes Version January 2007 ● Added document revision history. v1.6 ● Added new row for V details in Table 4–1. CCA ● Updated R information in Table 4–3. CONF ● Added new Note (12) on voltage overdrive information to Table 4–7 and Table 4–8. ● Updated Note (9) on R information to Table 4–3. CONF ● Updated information in “External I/O Delay Parameters” section. ● Updated speed grade information in Table 4–46 and Table 4–47. ● Updated LVDS information in Table 4–51. August 2005 Minor updates. v1.5 February 2005 ● Updated information on Undershoot voltage. Updated Table v1.4 4-2. ● Updated Table 4-3. ● Updated the undershoot voltage from 0.5 V to 2.0 V in Note 3 of Table 4-16. ● Updated Table 4-17. January 2004 ● Added extended-temperature grade device information. v.1.3 Updated Table 4-2. ● Updated I information in Table 4-3. CC0 October 2003 ● Added clock tree information in Table 4-19. v.1.2 ● Finalized timing information for EP1C3 and EP1C12 devices. Updated timing information in Tables 4-25 through 4-26 and Tables 4-30 through 4-51. ● Updated PLL specifications in Table 4-52. July 2003 v1.1 Updated timing information. Timing finalized for EP1C6 and EP1C20 devices. Updated performance information. Added PLL Timing section. May 2003 v1.0 Added document to Cyclone Device Handbook. Altera Corporation 4–31 January 2007 Preliminary Cyclone Device Handbook, Volume 1 4–32 Altera Corporation Preliminary January 2007 5. Reference & Ordering Information C51005-1.3 ® ® ® Cyclone devices are supported by the Altera Quartus II design Software software, which provides a comprehensive environment for system-on-a- programmable-chip (SOPC) design. The Quartus II software includes HDL and schematic design entry, compilation and logic synthesis, full ® simulation and advanced timing analysis, SignalTap II logic analysis, and device configuration. Refer to the Design Software Selector Guide for more details on the Quartus II software features. The Quartus II software supports the Windows 2000/NT/98, Sun Solaris, Linux Red Hat v7.1 and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the ® NativeLink interface. Device pin-outs for Cyclone devices are available on the Altera web site Device Pin-Outs (www.altera.com) and in the Cyclone FPGA Device Handbook. Figure 5–1 describes the ordering codes for Cyclone devices. For more Ordering information on a specific package, refer to Chapter 15, Package Information Information for Cyclone Devices. Figure 5–1. Cyclone Device Packaging Ordering Information EP1C 20FE 400 C 7S Family Signature Optional Suffix EP1C: Cyclone Indicates specific device options or shipment method. ES: Engineering sample Device Type 3 Speed Grade 4 6, 7, or 8 , with 6 being the fastest 6 12 20 Operating Temperature Package Type C: Commercial temperature (t = 0˚ C to 85˚ C) J Industrial temperature (t = -40˚ C to 100˚ C) I: J T: Thin quad flat pack (TQFP) Pin Count Q: Plastic quad flat pack (PQFP) F: FineLine BGA Number of pins for a particular package Altera Corporation 5–1 January 2007 Preliminary Cyclone Device Handbook, Volume 1 Table 5–1 shows the revision history for this document. Document Revision History Table 5–1. Document Revision History Date & Document Changes Made Summary of Changes Version January 2007 Added document revision history. v1.3 August 2005 Minor updates. v1.2 February 2005 Updated Figure 5-1. v1.1 May 2003 v1.0 Added document to Cyclone Device Handbook. 5–2 Altera Corporation Preliminary January 2007