Section I. Arria GX Device Data Sheet This section provides designers with the data sheet specifications for Arria™ GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Arria GX devices. This section includes the following chapters: ■ Chapter 1, Arria GX Device Family Overview ■ Chapter 2, Arria GX Architecture ■ Chapter 3, Configuration and Testing ■ Chapter 4, DC & Switching Characteristics ■ Chapter 5, Reference and Ordering Information Refer to each chapter for its own specific revision history. For information Revision History on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. Altera Corporation Section I–1 Arria GX Device Data Sheet Arria GX Device Handbook, Volume 1 Section I–2 Altera Corporation 1. Arria GX Device Family Overview AGX51001-1.1 TM The Arria GX family of devices combines protocol-optimized serial Introduction transceivers with reliable packaging technology and a proven logic array. Arria GX devices include 4 to 12 high-speed transceiver channels, each incorporating clock/data recovery (CDR) technology and embedded SERDES circuitry optimally designed to support PCI-Express, Gigabit Ethernet, and Serial RapidIO protocols. The transceivers build upon the ® success of Stratix II GX family and have been optimized to simply and efficiently implement bridging and endpoint applications. The Arria GX FPGA technology offers a 1.2-V logic array with the right level of performance and dependability needed to support these mainstream protocols. The key device features for the Arria GX include: Features ■ Transceiver block features ● High-speed serial transceiver channels with clock/data recovery support ● Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver channels ● Support for the following CDR-based bus standards - PCI Express, Gigabit Ethernet and Serial RapidIO ● Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation ● 1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter output buffers ● Receiver indicator for loss of signal (available only in PCI Express (PIPE) mode) ● Hot socketing feature for hot plug-in or hot swap and power sequencing support without the use of external devices ● Dedicated circuitry that is compliant with PIPE, GIGE, and Serial RapidIO ● 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding ● Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array Altera Corporation 1–1 June 2007 Arria GX Device Family Overview ■ Main device features: TM ● TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers with performance up to 380 MHz ● Up to 16 global clock networks with up to 32 regional clock networks per device ● High-speed DSP blocks provide dedicated implementation of multipliers, multiply-accumulate functions, and finite impulse response (FIR) filters ● Up to four enhanced PLLs per device provide spread spectrum, programmable bandwidth, clock switch-over, and advanced multiplication and phase shifting ● Support for numerous single-ended and differential I/O standards ● High-speed source-synchronous differential I/O support on up to 47 channels ● Support for source-synchronous bus standards, including SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1 ● Support for high-speed external memory including double data rate (DDR and DDR2) SDRAM, and single data rate (SDR) SDRAM ● Support for multiple intellectual property megafunctions from ® ® Altera MegaCore functions and Altera Megafunction Partners SM Program (AMPP ) ® Table 1–1 lists Arria GX device features for FineLine BGA (FBGA) with flip-chip packages. Table 1–1. Arria GX Device Features (Part 1 of 2) Feature EP1AGX20C EP1AGX35C/D EP1AGX50C/D EP1AGX60C/D/E EP1AGX90E CC D C D C D E E Package 484-pin, 484-pin 780-pin 484-pin 780-pin, 484- 780- 1152- 1152-pin 780-pin (Flip- (Flip- (Flip- (Flip- 1152- pin pin pin (Flip-chip) chip) chip) chip) chip) pin (Flip- (Flip- (Flip- (Flip- chip) chip) chip) chip) ALMs 8,632 13,408 20,064 24,040 36,088 Equivalent 21,580 33,520 50,160 60,100 90,220 LEs Transceiver 44 8 4 8 4 8 12 12 channels Transceiver 1.25Gbps, 1.25Gbps, 2.5Gbps 1.25Gbps, 1.25Gbps, 2.5Gbps 1.25Gbps, data rate 2.5Gbps 2.5Gbps 2.5Gbps 1–2 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Features Table 1–1. Arria GX Device Features (Part 2 of 2) Feature EP1AGX20C EP1AGX35C/D EP1AGX50C/D EP1AGX60C/D/E EP1AGX90E CC D C D C D E E Source- 31 31 31 31 31, 42 31 31 42 47 synchronous receive channels Source- 29 29 29 29 29, 42 29 29 42 45 synchronous transmit channels M512 RAM 166 197 313 326 478 blocks (32 x18bits) M4K RAM 118 140 242 252 400 blocks (128 x36bits) M-RAM 11 2 2 4 blocks (4096 x 144 bits) Total RAM 1,229,184 1,348,416 2,475,072 2,528,640 4,477,824 bits Embedded 40 56 104 128 176 multipliers (18 x18) DSP blocks 10 14 26 32 44 PLLs 4 4 4 4, 8 4 8 8 Maximum 230, 341 230 341 229 350, 229 350 514 538 user I/O pins 514 Arria GX devices are available in space-saving FBGA packages (refer to Table 1–2). All Arria GX devices support vertical migration within the same package. With vertical migration support, designers can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For I/O pin migration across densities, the designer must cross-reference the available I/O pins using the device pin-outs for all planned densities of a given package type to identify which I/O pins are migratable. Altera Corporation 1–3 June 2007 Arria GX Device Handbook, Volume 1 Arria GX Device Family Overview Table 1–2. Arria GX Package Options (Pin Counts & Transceiver Channels) Source-Synchronous Maximum User I/O Pin Count Channels Transceiver Device Channels 484-Pin FBGA 780-Pin FBGA 1152-Pin FBGA Receive Transmit (23mm) (29mm) (35mm) EP1AGX20C 4 31 29 230 341 — EP1AGX35C 4 31 29 230 — — EP1AGX50C 4 31 29 229 — — EP1AGX60C 4 31 29 229 — — EP1AGX35D 8 31 29 — 341 — EP1AGX50D 8 31, 42 29, 42 — 350 514 EP1AGX60D 8 31 29 — 350 — EP1AGX60E 12 42 42 — — 514 EP1AGX90E 12 47 45 — — 538 Table 1–3 lists the Arria GX device package sizes. Table 1–3. Arria GX FBGA Package Sizes Dimension 484 Pins 780 Pins 1152 Pins Pitch (mm) 1.00 1.00 1.00 2 529 841 1225 Area (mm ) Length × width 23 × 23 29 × 29 35 × 35 (mm × mm) 1–4 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Document Revision History Table 1–4 shows the revision history for this chapter. Document Revision History Table 1–4. Document Revision History Date and Document Changes Made Summary of Changes Version June 2007, v1.1 Included GIGE information. — May 2007, v1.0 Initial Release — Altera Corporation 1–5 June 2007 Arria GX Device Handbook, Volume 1 Arria GX Device Family Overview 1–6 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 2. Arria GX Architecture AGX51002-1.1 Arria™ GX devices incorporate up to 12 high-speed serial transceiver Transceivers ® channels that build on the success of the Stratix II GX device family. Arria GX transceivers are structured into full-duplex (transmitter and receiver) four-channel groups called transceiver blocks located on the right side of the device. The transceiver blocks have dedicated circuitry to support the following serial connectivity protocols (functional modes): ■ PCI Express (PIPE) ■ Gigabit Ethernet (GIGE) ■ Serial RapidIO (1.25 Gbps and 2.5 Gbps) You can configure each transceiver block to one of the three supported functional modes. For Arria GX devices that offer more than one transceiver block, you can configure each transceiver block to a different functional mode, for example one transceiver block can be configured as a four GIGE ports and the other configured as four Serial RapidIO ports. Table 2–1 shows the number of transceiver channels for each member of the Arria GX family. Table 2–1. Arria GX Transceiver Channels Device Number of Transceiver Channels EP1AGX20C 4 EP1AGX35C 4 EP1AGX35D 8 EP1AGX50C 4 EP1AGX50D 8 EP1AGX60C 4 EP1AGX60D 8 EP1AGX60E 12 EP1AGX90E 12 Altera Corporation 2–1 June 2007 Transceivers Figure 2–1 shows a high-level diagram of the transceiver block architecture divided into four channels. Figure 2–1. Transceiver Block Transceiver Block RX1 Channel 1 TX1 RX0 Channel 0 Arria GX TX0 Logic Array Supporting Blocks REFCLK_1 (PLLs, State Machines, Programming) REFCLK_0 RX2 Channel 2 TX2 RX3 Channel 3 TX3 Each transceiver block has: ■ Four transceiver channels with dedicated physical coding sub-layer (PCS) and physical media attachment (PMA) circuitry ■ One transmitter PLL that takes in a reference clock and generates high-speed serial clock depending on the functional mode ■ Four receiver PLLs and clock recovery unit (CRU) to recover clock and data from the received serial data stream ■ State machines and other logic to implement special features required to support each protocol 2–2 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–2 shows functional blocks that make up a transceiver channel. Figure 2–2. Arria GX Transceiver Channel Block Diagram Transmitter PCS Transmitter PMA TX Phase Compe- Byte 8B/10B PIPE Serializer Interface nsation Serializer Encoder FIFO Reference Clocks PLD CMU Reset Logic State Machines Logic Array Receiver PCS Receiver PMA Clock Recove RX Phase De- Rate ry Unit Compe- Byte De - 8B/10B Word PIPE Serializ Match Interface nsation serializer Decoder Aligner er Reference FIFO FIFO Receiver Clocks PLL Each transceiver channel is full-duplex and consists of a transmitter channel and a receiver channel. The transmitter channel contains the following sub-blocks: ■ Transmitter phase compensation FIFO buffer ■ Byte serializer ■ 8B/10B encoder ■ Serializer (parallel to serial converter) ■ Differential output buffer The receiver channel contains the following sub-blocks: ■ Differential input buffer ■ Receiver PLL ■ Clock recovery unit (CRU) ■ Deserializer (serial to parallel converter) ■ Word aligner ■ Rate matcher ■ 8B/10B decoder ■ Byte deserializer ■ Receiver phase compensation FIFO buffer Altera Corporation 2–3 June 2007 Arria GX Device Handbook, Volume 1 Transceivers You can configure the transceiver channels to the desired functional ® modes using ALT2GXB MegaCore instance in the Quartus II MegaWizard Plug-in Manager for the Arria GX device family. Depending on the selected functional mode, the Quartus II software automatically configures the transceiver channels to employ a subset of the sub-blocks listed above. Table 2–2 lists which sub-blocks are used when configured in each supported functional mode. Table 2–2. Transceiver Protocol Support Serial RapidIO PCI Express Gigabit Ethernet Transceiver Protocol Support PIPE GIGE 1.25Gbps 2.5Gbps 2.5 1.25 1.25 2.5 Data rates (Gbps) ×1, ×4 ×1 1× 1× Link Widths ×4 PIPE None None None Channel Bonding 100 62.5, 125 62.5, 78.125, 125, 156.25, Available reference clock (MHz) 125, 156.25 250, 312.5 16 8 16 16 PLD-Transceiver interface bus width (bits) PIPE Interface GMII Like None None Special FPGA/transceiver interface vv v v Dedicated synchronization state machine vv v v 8B/10B encode/decode vv v v Word align vv Rate match vvv Byte serialize/deserialize vv v v Phase compensation FIFO buffer vv v v IP v Dedicated development Complete kit solution vv v v Generic development kit vv v v Characterization 2–4 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Transmitter Path This section describes the data path through the Arria GX transmitter. The sub-blocks are described in order from the PLD-transmitter parallel interface to the serial transmitter buffer. Clock Multiplier Unit Each transceiver block has a clock multiplier unit (CMU) that takes in a reference clock and synthesizes two clocks: a high-speed serial clock to serialize the data and a low-speed parallel clock to clock the transmitter digital logic (PCS). The CMU is further divided into three sub-blocks: ■ One transmitter PLL ■ One central clock divider block ■ Four local clock divider blocks (one per channel) Figure 2–3 shows the block diagram of the clock multiplier unit. Figure 2–3. Clock Multiplier Unit CMU Block Transmitter High-Speed Serial Transmitter Channels [3:2] and Low-Speed Parallel Clocks Local Clock TX Clock Divider Block Gen Block Reference Clock Central Clock Transmitter from REFCLKs, Divider PLL Global Clock (1), Block Inter-Transceiver Lines Transmitter High-Speed Serial and Low-Speed Parallel Clocks Local Clock TX Clock Divider Block Gen Block Transmitter Channels [1:0] The transmitter PLL multiplies the input reference clock to generate the high-speed serial clock required to support the intended protocol. It implements a half-rate voltage controlled oscillator (VCO) that generates a clock at half the frequency of the serial data rate for which it is configured. Altera Corporation 2–5 June 2007 Arria GX Device Handbook, Volume 1 Transceivers Figure 2–4 shows the block diagram of the transmitter PLL. Figure 2–4. Transmitter PLL Transmitter PLL (1) /M To Inter-Transceiver Lines up Dedicated /2 Phase Charge Voltage REFCLK0 High Speed (1) Frequency /L Pump + Loop Controlled Serial Clock down Dedicated Detector INCLK Filter Oscillator /2 REFCLK1 Inter-Transceiver Lines[2:0] (2) Global Clock Notes to Figure 2–4: (1) You only need to select the protocol and the available input reference clock frequency in the Quartus II MegaWizard Plug-In Manager.Based on your selections, the Plug-In Manager automatically selects the necessary /M and /L dividers (clock multiplication factors). (2) The global clock line must be driven from an input pin only. The reference clock input to the transmitter PLL can be derived from: ■ One of two available dedicated reference clock input pins (REFCLK0 or REFCLK1) of the associated transceiver block ■ PLD global clock network (must be driven directly from an input clock pin and cannot be driven by user logic or enhanced PLL) ■ Inter-transceiver block lines driven by reference clock input pins of other transceiver blocks ® 1 Altera recommends using the dedicated reference clock input pins (REFCLK0 or REFCLK1) to provide reference clock for the transmitter PLL. Table 2–3 lists the supported reference clock frequencies and the corresponding transmitter PLL multiplication factors for each supported protocol. Table 2–3. Transmitter PLL Input Reference Clock Frequencies Note (1) (Part 1 of 2) Supported Input Reference Transmitter PLL Functional Mode Clock Frequencies (MHz) Multiplication Factor PCI Express (PIPE) 100 25 2–6 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Table 2–3. Transmitter PLL Input Reference Clock Frequencies Note (1) (Part 2 of 2) Supported Input Reference Transmitter PLL Functional Mode Clock Frequencies (MHz) Multiplication Factor 62.5 10 GIGE 125 5 62.5 10 78.125 8 Serial RapidIO (1.25 Gbps) 125 5 156.25 4 125 10 156.25 8 Serial RapidIO (2.5 Gbps) 250 5 312.5 4 Note to Table 2–3: (1) In PCI Express (PIPE) mode, the reference clock is divided by two before being fed to the transmitter PLL. The transmitter PLL output feeds the central clock divider block and the local clock divider blocks. These clock divider blocks divide the high-speed serial clock to generate the low-speed parallel clock for the transceiver PCS logic and the PLD-transceiver interface clock. In ×4 PCI Express (PIPE) mode, the low-speed parallel clock generated by the central clock divider block is used to clock the transceiver PCS logic in all channels within the transceiver block. This low-speed parallel clock is divided by two before being forwarded to the PLD logic array on the coreclkout port. In all other modes, the low-speed parallel clock generated by the local clock divider block is used to clock the transceiver PCS logic in its associated channel. This low-speed parallel clock (or its divide-by-two version if the functional mode uses the byte serializer) is also forwarded to the PLD logic array on the tx_clkout port. Transmitter Phase Compensation FIFO Buffer A transmitter phase compensation FIFO is located at each transmitter channel’s logic array interface. It compensates for the phase difference between the transmitter PCS clock and the local PLD clock. The transmitter phase compensation FIFO is used in all supported functional modes. The transmitter phase compensation FIFO buffer is eight words deep in PCI Express (PIPE) mode and four words deep in all other modes. Altera Corporation 2–7 June 2007 Arria GX Device Handbook, Volume 1 Transceivers f For more details about architecture and clocking, refer to the Arria GX Transceiver Architecture chapter in volume 2 of the Arria GX Device Handbook. Byte Serializer In PCI Express (PIPE) and Serial RapidIO functional modes, the byte serializer takes in two-byte wide data from the transmitter phase compensation FIFO buffer and serializes it into a one-byte wide data at twice the speed. This allows clocking the PLD-transceiver interface at half the speed as compared to the transmitter PCS logic. The byte serializer is bypassed in GIGE mode. After serialization, the byte serializer transmits the least significant byte (LSByte) first and the most significant byte (MSByte) last. Figure 2–5 shows byte serializer input and output. datain[15:0] is the input to the byte serializer from the transmitter phase compensation FIFO and dataout[7:0] is the output of the byte serializer. Figure 2–5. Byte Serializer Operation D1 D2 D3 datain[15:0] {8'h00,8'h01} {8'h02,8'h03} xxxx D1 D1 D2 D2 LSByte MSByte LSByte MSByte xxxxxxxxxx xxxxxxxxxx 8'h01 8'h00 8'h03 8'h02 dataout[7:0] 8B/10B Encoder The 8B/10B encoder block is used in all supported functional modes. The 8B/10B encoder block takes in 8-bit data from the byte serializer (in PCI Express [PIPE] and Serial RapidIO modes) or transmitter phase compensation FIFO buffer (in GIGE mode). It generates a 10-bit code group with proper running disparity from the 8-bit character and a 1-bit control identifier (tx_ctrlenable). When tx_ctrlenable is low, the 8-bit character is encoded as data code group (Dx.y). When tx_ctrlenable is high, the 8-bit character is encoded as a control code group (Kx.y). The 10-bit code group is fed to the serializer. The 8B/10B encoder conforms to the IEEE 802.3 1998 edition standard. Figure 2–6 shows the 8B/10B conversion format. f For additional information regarding 8B/10B encoding rules, refer to the Specifications and Additional Information chapter in volume 2 of the Arria GX Device Handbook. 2–8 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–6. 8B/10B Encoder 76 5 4 3 2 1 0 Ctrl HG F E D C B A 8B-10B Conversion jh g f i e d c b a 98 76 5 4 3 2 1 0 MSB LSB During reset (tx_digitalreset), the running disparity and the data registers are cleared and the 8B/10B encoder outputs a K28.5 pattern from the RD- column continuously. Once out of reset, the 8B/10B encoder starts with a negative disparity (RD-) and transmits three K28.5 code groups for synchronizing before it starts encoding the input data or control character. In GIGE mode, any /Dx.y/ following a /K28.5/ comma is replaced with either a /D5.6/ (/I1/ ordered set) or a /D16.2/ (/I2/ ordered set), depending on the current running disparity. The exception is when the data following the /K28.5/ is /D21.5/ (/C1/ ordered set) or /D2.2/ (/C2/) ordered set. If the running disparity before the /K28.5/ is positive, a /I1/ ordered set is generated. If the running disparity is negative, a /I2/ ordered set is generated. f For more details about idle ordered set generation, refer to the Arria GX Transceiver Architecture chapter in volume 2 of the Arria GX Device Handbook. Serializer (Parallel-to-Serial Converter) The serializer block clocks in 10-bit encoded data from the 8B/10B encoder using the low-speed parallel clock and clocks out serial data using the high-speed serial clock from the central or local clock divider blocks. The serializer feeds the data LSB to MSB to the transmitter output buffer. Altera Corporation 2–9 June 2007 Arria GX Device Handbook, Volume 1 Transceivers Figure 2–7 shows the serializer block diagram. Figure 2–7. Serializer D9 D9 D8 D8 D7 D7 D6 D6 10 D5 D5 8B/10B From D4 D4 Encoder D3 D3 D2 D2 D1 D1 To Transmitter D0 D0 Output Buffer Low-speed parallel clock CMU Central / Local Clock High-speed serial clock Divider Transmitter Buffer The transmitter buffer takes in serial data from the serializer and drives it on the tx_dataout port of the associated transceiver channel. Table 2–4 shows available transmitter buffer settings in each functional mode. Table 2–4. Transmitter Buffer Settings On-Chip Differential Common Mode Supported I/O Mode Termination with Output Voltage Voltage Pre-Emphasis Standard Calibration (V ) (V ) OD CM PCI Express 100 Ω 1.2 V-PCML 800 mV 600 mV Enabled (1) (PIPE) GIGE 100 Ω 1.5 V-PCML 800 mV 600 mV Disabled Serial RapidIO 100 Ω 1.5 V-PCML 800 mV 600 mV Disabled Note to Table 2–4: (1) In PCI Express (PIPE) mode, 49% pre-emphasis is used to meet the PCI Express de-emphasis specification. 2–10 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–8 shows the transmitter buffer circuitry. Figure 2–8. Transmitter Buffer 50Ω Transmitter +VTT- From Output Pins Serializer 50Ω RX Detect The transmitter buffer supports the Electrical Idle and Receiver Detect features in PCI Express (PIPE) mode. Receiver Path This section describes the data path through the Arria GX receiver. The sub-blocks are described in order from the receiver buffer to the PLD-receiver parallel interface. Receiver Buffer The receiver buffer receives serial data from the rx_datain port and feeds it to the clock recovery unit (CRU). Table 2–5 shows available receiver buffer settings in each functional mode. Table 2–5. Receiver Buffer Settings On-Chip Common Mode Mode Termination with Supported I/O Standard Voltage Coupling Calibration (RX V ) CM PCI Express (PIPE), 100 Ω 1.2 V-PCML, 850 mV AC GIGE, 1.5 V-PCML, Serial RapidIO 3.3 V-PCML, Differential LVPECL, LVDS Altera Corporation 2–11 June 2007 Arria GX Device Handbook, Volume 1 Transceivers The receiver buffer also incorporates signal threshold detection circuitry only in PCI Express (PIPE) mode. Figure 2–9 shows the receiver buffer circuitry. Figure 2–9. Receiver Buffer 50Ω +VTT- To CRU RX Input Pins 50Ω Signal Detect (1) Note to Figure 2–9: (1) The signal detect circuitry is available only in PCI Express (PIPE) mode. Receiver PLL and Clock Recovery Unit (CRU) Each transceiver block has four receiver PLLs and CRU units, each of which is dedicated to a receiver channel. The receiver PLL is fed by an input reference clock. The receiver PLL in conjunction with the CRU generates two clocks: a high-speed serial recovered clock that clocks the deserializer and a low-speed parallel recovered clock that clocks the receiver's digital logic. 2–12 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–10 shows a block diagram of the receiver PLL and CRU circuits. Figure 2–10. Receiver PLL and Clock Recovery Unit (CRU) /M rx_pll_locked Dedicated /2 REFCLK0 up PFD Dedicated dn /2 REFCLK1 rx_cruclk VCO /L CP+LF up Inter-Transceiver Lines [2:0] dn Global Clock (2) rx_freqlocked rx_locktorefclk ( ) Clock Recovery Unit CRU Control rx_locktodata High-speed serial recovered clk rx_datain Low-speed parallel recovered clk Notes to Figure 2–10: (1) You only need to select the protocol and the available input reference clock frequency in the Quartus II MegaWizard Plug-In Manager. Based on your selections, the Plug-In Manager automatically selects the necessary /M and /L dividers. (2) The global clock line must be driven from an input pin only. The reference clock input to the receiver PLL can be derived from: ■ One of the two available dedicated reference clock input pins (REFCLK0 or REFCLK1) of the associated transceiver block ■ PLD global clock network (must be driven directly from an input clock pin and cannot be driven by user logic or enhanced PLL) ■ Inter-transceiver block lines driven by reference clock input pins of other transceiver blocks Table 2–6 lists the supported reference clock frequencies and the corresponding receiver PLL multiplication factors for each supported protocol. Table 2–6. Receiver PLL Input Reference Clock Frequencies Note (1) (Part 1 of 2) Supported Input Receiver PLL Multiplication Functional Mode Reference Clock Factor Frequencies (MHz) PCI Express (PIPE) 100 25 62.5 10 GIGE 125 5 Altera Corporation 2–13 June 2007 Arria GX Device Handbook, Volume 1 Transceivers Table 2–6. Receiver PLL Input Reference Clock Frequencies Note (1) (Part 2 of 2) Supported Input Receiver PLL Multiplication Functional Mode Reference Clock Factor Frequencies (MHz) 62.5 10 78.125 8 Serial RapidIO (1.25 Gbps) 125 5 156.25 4 125 10 156.25 8 Serial RapidIO (2.5 Gbps) 250 5 312.5 4 Note to Table 2–6: (1) In PCI Express (PIPE) mode, the reference clock is divided by two before being fed to the receiver PLL. The clock recovery unit controls whether the receiver PLL locks to the input reference clock (lock-to-reference mode) or the incoming serial data (lock-to data mode). You can set the CRU to switch between lock-to-data and lock-to-reference modes automatically or manually. In automatic lock mode, the phase detector and dedicated parts per million (PPM) detector within each receiver channel control the switch between lock-to-data and lock-to-reference modes based on some pre-set conditions. In manual lock mode, you control the switch manually using the rx_locktorefclk and rx_locktodata signals. f For more details, refer to the Clock Recovery Unit section in Chapter 2, volume 2, of the Arria GX Device Handbook. Table 2–7 show the behavior of CRU block with respect to the rx_locktorefclk and rx_locktodata signals. Table 2–7. CRU Manual Lock Signals rx_locktorefclk rx_locktodata CRU Mode 1 0 Lock-to-reference clock x 1 Lock-to-data 00 Automatic 2–14 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture If the rx_locktorefclk and rx_locktodata ports are not used, the default is automatic lock mode. Deserializer The deserializer block clocks in serial input data from the receiver buffer using the high-speed serial recovered clock and deserializes into 10-bit parallel data using the low-speed parallel recovered clock. The serial data is assumed to be received with LSB first, followed by MSB. It feeds the deserialized 10-bit data to the word aligner as shown in Figure 2–11. Figure 2–11. Deserializer Received Data D9 D9 D8 D8 D7 D7 D6 D6 10 To Word D5 D5 Aligner D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Clock High-speed serial recovered clock Recovery Unit Low -speed parallel recovered clock Word Aligner The word aligner block is used in all supported functional modes. The word aligner clocks in 10-bit received data from the deserializer. It restores the byte boundary of the upstream transmitter based on the pre-defined word alignment character for the selected protocol. Besides restoring the byte boundary, the word aligner also implements a synchronization state machine in all functional modes to achieve lane synchronization. Altera Corporation 2–15 June 2007 Arria GX Device Handbook, Volume 1 Transceivers The word aligner consists of three sub-modules: ■ Pattern detector module ■ Pattern aligner module ■ Run-length violation detector module The pattern detector looks for the configured word alignment pattern in the data clocked into the word aligner. When the pattern detector detects the word alignment pattern for the first time, it asserts the rx_patterndetect signal. The pattern aligner aligns the byte boundary to the received word alignment pattern. Any subsequent word alignment pattern found in the same byte boundary causes the rx_patterndetect signal to assert for one parallel clock cycle. 1 The Quartus II software automatically selects both disparities of K28.5 control word (10'b0101111100 and 10'b1010000011) as the word alignment pattern in all three functional modes. The pattern aligner module, in conjunction with the pattern detector, aligns the received data to the pre-defined word alignment pattern. The pattern aligner incorporates an automatic synchronization state machine to indicate lane synchronization in all supported functional modes. The synchronization state machine offers automatic detection of a pre-defined number of valid alignment patterns to indicate lane synchronization and detection of code group errors for falling out of synchronization. The synchronization state machine indicates lane synchronization status on the rx_syncstatus port. A high on the rx_syncstatus port indicates that the lane synchronization has been achieved and a low indicates that the lane is not synchronized. Depending on the functional mode, the Quartus II software automatically configures the synchronization state machine parameters; for example, number of valid synchronization characters received and number of invalid code groups received to fall out of synchronization. 2–16 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Table 2–8 shows the synchronization state machine parameters that the Quartus II software selects for each functional mode. Table 2–8. Synchronization State Machine Parameters PCI Serial Functional Mode Express GIGE RapidIO (PIPE) Number of valid synchronization code 4 3 127 groups or ordered sets received to achieve synchronization (1) Number of bad code groups received to 17 4 3 lose synchronization Number of continuous good code groups 16 4 255 received to reduce the error count by 1 Note for Table 2–8: (1) For information about synchronization code groups, refer to the Word Aligner section in chapter 2, volume 2, of the Arria GX Device Handbook. The word aligner supports a programmable run length violation counter. Whenever the number of the continuous '0' (or '1') exceeds a user programmable value, the rx_rlv signal goes high for a minimum pulse width of two recovered clock cycles. The maximum configurable run values supported are shown in Table 2–9. Table 2–9. Maximum Configurable Run Lengths PCI Express 160 (PIPE) GIGE 160 Serial RapidIO 160 Rate Matcher In asynchronous systems, the upstream transmitter and the local receiver may be clocked with independent reference clock sources. Frequency differences in the order of a few hundred PPM can potentially corrupt the data at the receiver. The rate matcher compensates for small clock frequency differences between the upstream transmitter and the local receiver clocks by inserting or removing skip characters from the inter packet gap (IPG) or idle streams. It inserts a skip character if the local receiver is running of a faster clock than the upstream transmitter. It deletes a skip character if the Altera Corporation 2–17 June 2007 Arria GX Device Handbook, Volume 1 Transceivers local receiver is running a slower clock than the upstream transmitter. The Quartus II software automatically configures the appropriate skip character as specified in the IEEE 802.3 for GIGE mode and PCI-Express Base Specification for PCI Express (PIPE) mode. The rate matcher is bypassed in Serial RapidIO and must be implemented in the PLD logic array or external circuits depending on your system design. Table 2–10 shows the maximum frequency difference that the rate matcher can tolerate in PCI Express (PIPE) and GIGE functional modes. Table 2–10. Rate Matcher PPM Tolerance Function Mode PPM PCI Express (PIPE) ± 300 GIGE ± 100 PCI Express (PIPE) Mode Rate Matcher In PCI Express (PIPE) mode, the rate matcher can compensate up to ± 300 PPM (600 PPM total) frequency difference between the upstream transmitter and the receiver. The rate matcher logic looks for skip ordered sets (SKP), which contains a /K28.5/ comma followed by three /K28.0/ skip characters. The rate matcher logic deletes or inserts /K28.0/ skip characters as necessary from/to the rate matcher FIFO. The rate matcher in PCI Express (PIPE) mode has a FIFO buffer overflow and underflow protection. In the event of a FIFO buffer overflow, the rate matcher deletes any data after detecting the overflow condition to prevent FIFO pointer corruption until the rate matcher is not full. In an underflow condition, the rate matcher inserts 9'h1FE (/K30.7/) until the FIFO buffer is not empty. These measures ensure that the FIFO buffer can gracefully exit the overflow and underflow condition without requiring a FIFO reset. The rate matcher FIFO overflow and underflow condition is indicated on the pipestatus port. You can bypass the rate matcher in PCI Express (PIPE) mode if you have a synchronous system where the upstream transmitter and local receiver derive their reference clocks from the same source. GIGE Mode Rate Matcher In GIGE mode, the rate matcher can compensate up to ± 100 PPM (200 PPM total) frequency difference between the upstream transmitter and the receiver. The rate matcher logic inserts or deletes /I2/ idle ordered sets to/from the rate matcher FIFO during the inter-frame or inter-packet gap (IFG or IPG). /I2/ is selected as the rate matching ordered set since it maintains the running disparity unlike /I1/ that alters 2–18 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture the running disparity. Since the /I2/ ordered-set contains two 10-bit code groups (/K28.5/, /D16.2/), twenty bits are inserted or deleted at a time for rate matching. 1 The rate matcher logic does not have capability to insert or delete /C1/ or /C2/ configuration ordered-sets. If the frequency PPM difference between the upstream transmitter and the local receiver is high or if the packet size is too large, the rate matcher FIFO buffer can face an overflow or underflow situation. 8B/10B Decoder The 8B/10B decoder is used in all supported functional modes. The 8B/10B decoder takes in 10-bit data from the rate matcher and decodes it into 8-bit data + 1-bit control identifier, thereby restoring the original transmitted data at the receiver. The 8B/10B decoder indicates whether the received 10-bit character is a data or control code through the rx_ctrldetect port. If the received 10-bit code group is a control character (Kx.y), the rx_ctrldetect signal is driven high and if it is a data character (Dx.y), the rx_ctrldetect signal is driven low. Figure 2–12 shows a 10-bit code group decoded to an 8-bit data and a 1-bit control indicator. Figure 2–12. 10-Bit to 8-Bit Conversion jh g f i e d c b a 98 76 5 4 3 2 1 0 MSB Received Last LSB Received First 8B/10B Conversion Parallel Data ctrl 76 5 4 3 2 1 0 HG F E D C B A Altera Corporation 2–19 June 2007 Arria GX Device Handbook, Volume 1 Transceivers If the received 10-bit code is not a part of valid Dx.y or Kx.y code groups, the 8B/10B decoder block asserts an error flag on the rx_errdetect port. If the received 10-bit code is detected with incorrect running disparity, the 8B/10B decoder block asserts an error flag on the rx_disperr and rx_errdetect ports. The error flag signals (rx_errdetect and rx_disperr) have the same data path delay from the 8B/10B decoder to the PLD-transceiver interface as the bad code group. Byte Deserializer In PCI Express (PIPE) and Serial RapidIO functional modes, the byte serializer takes in one-byte wide data from the 8B/10B decoder and deserializes it into a two-byte wide data at half the speed. This allows clocking the PLD-receiver interface at half the speed as compared to the receiver PCS logic. The byte deserializer is bypassed in GIGE mode. In PCI Express (PIPE) and Serial RapidIO modes, the byte ordering at the receiver output might be different than what was transmitted. This is a non-deterministic swap, because it depends on PLL lock times and link delay. If required, you must implement byte-ordering logic in the PLD to correct this situation. f For more details, refer to the Arria GX Transceiver Architecture chapter in volume 2 of Arria GX Device Handbook. Receiver Phase Compensation FIFO Buffer A receiver phase compensation FIFO buffer is located at each receiver channel’s logic array interface. It compensates for the phase difference between the receiver PCS clock and the local PLD receiver clock. The receiver phase compensation FIFO is used in all supported functional modes. The receiver phase compensation FIFO buffer is eight words deep in PCI Express (PIPE) mode and four words deep in all other modes. f For more details about architecture and clocking, refer to the Arria GX Transceiver Architecture chapter in volume 2 of Arria GX Device Handbook. Loopback Modes Arria GX transceivers support the following loopback configurations for diagnostic purposes: ■ Serial Loopback—available in GIGE and Serial RapidIO modes ■ PCI Express Reverse Parallel Loopback—available in PCI Express (PIPE) mode 2–20 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Serial Loopback Figure 2–13 shows the transceiver data path in serial loopback. Figure 2–13. Transceiver Data Path in Serial Loopback Transmitter PCS Transmitter PMA TX Phase Byte Compen- 8B/10B Serializer Serializer sation Encoder FIFO PLD Logic Serial Loopback Array Receiver PCS Receiver PMA RX Phase Clock Byte Rate De- 8B/10B Word Compen- Recovery De- Match Serializer Decoder Aligner sation Unit Serializer FIFO FIFO In GIGE and Serial RapidIO modes, you can dynamically put each transceiver channel individually in serial loopback by controlling the rx_seriallpbken port. A high on the rx_seriallpbken port puts the transceiver into serial loopback and a low takes the transceiver out of serial loopback. As seen in Figure 2–13, the serial data output from the transmitter serializer is looped back to the receiver clock recovery unit (CRU) in serial loopback. The transmitter data path from the PLD interface to the serializer in serial loopback is the same as in non-loopback mode. The receiver data path from the clock recovery unit to the PLD interface in serial loopback is the same as in non-loopback mode. Since the entire transceiver data path is available in serial loopback, this option is often used to diagnose the data path as a probable cause of link errors. 1 When the serial loopback is enabled, the transmitter output buffer is still active and drives the serial data out on the tx_dataout port. PCI Express (PIPE) Reverse Parallel Loopback Figure 2–14 shows the data path for the PCI Express (PIPE) reverse parallel loopback. The reverse parallel loopback configuration is compliant with the PCI Express (PIPE) specification and is available only on PCI Express (PIPE) mode. Altera Corporation 2–21 June 2007 Arria GX Device Handbook, Volume 1 Transceivers Figure 2–14. PCI Express (PIPE) Reverse Parallel Loopback Transmitter PCS Transmitter PMA TX Phase Compe- Byte 8B/10B Serializer nsation Serializer Encoder FIFO PIPE PIPE Reverse Interface Parallel Loopback Receiver PCS Receiver PMA RX Phase Clock Byte Rate De- Compe- 8B/10B Word Recovery De- Match Serializer nsation Decoder Aligner Unit Serializer FIFO FIFO You can dynamically put the PCI Express (PIPE) mode transceiver in reverse parallel loopback by controlling the tx_detectrxloopback port instantiated in the MegaWizard Plug-In Manager. A high on the tx_detectrxloopback port in P0 power state puts the transceiver in reverse parallel loopback. A high on the tx_detectrxloopback port in any other power state does not put the transceiver in reverse parallel loopback. As seen in Figure 2–14, the serial data received on the rx_datain port in reverse parallel loopback goes through the CRU, deserializer, word aligner, and the rate matcher blocks. The parallel data at the output of the receiver rate matcher block is looped back to the input of the transmitter serializer block. The serializer converts the parallel data to serial data and feeds it to the transmitter output buffer that drives the data out on the tx_dataout port. The data at the output of the rate matcher also goes through the 8B/10B decoder, byte deserializer, and receiver phase compensation FIFO before being fed to the PLD on the rx_dataout port. Reset and Powerdown Arria GX transceivers offer a power saving advantage with their ability to shut off functions that are not needed. The following three reset signals are available per transceiver channel and can be used to individually reset the digital and analog portions within each channel: ■ tx_digitalreset ■ rx_analogreset ■ rx_digitalreset 2–22 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture The following two powerdown signals are available per transceiver block and can be used to shut down an entire transceiver block that is not being used: ■ gxb_powerdown ■ gxb_enable Table 2–11 shows the reset signals available in Arria GX and the transceiver circuitry affected by each signal. Table 2–11. Reset Signal Map to Arria GX Blocks Reset Signal rx_digitalreset vv vv rx_analogreset vvv tx_digitalreset vv gxb_powerdown v v vvv vvv vv vvv gxb_enable v v vvv vvv vv vvv Altera Corporation 2–23 June 2007 Arria GX Device Handbook, Volume 1 Transmitter Phase Compensation FIFO Module/ Byte Serializer Transmitter 8B/10B Encoder Transmitter Serializer Transmitter Analog Circuits Transmitter PLL Transmitter Analog Circuits Receiver Deserializer Receiver Word Aligner Receiver Rate Matcher Receiver 8B/10B Decoder Receiver Phase Comp FIFO Module/ Byte Deserializer Receiver PLL / CRU Receiver Analog Circuits Transceivers Transceiver Clocking This section describes the clock distribution within an Arria GX transceiver channel and the PLD clock resource utilization by the transceiver blocks. Transceiver Channel Clock Distribution Each transceiver block has one transmitter PLL and four receiver PLLs. The transmitter PLL multiplies the input reference clock to generate a high-speed serial clock at a frequency that is half the data rate of the configured functional mode. This high-speed serial clock (or its divide-by-two version if the functional mode uses byte serializer) is fed to the CMU clock divider block. Depending on the configured functional mode, the CMU clock divider block divides the high-speed serial clock to generate the low-speed parallel clock that clocks the transceiver PCS logic in the associated channel. The low-speed parallel clock is also forwarded to the PLD logic array on tx_clkout or coreclkout ports. The receiver PLL in each channel is also fed by an input reference clock. The receiver PLL along with the clock recovery unit generates a high-speed serial recovered clock and a low-speed parallel recovered clock. The low-speed parallel recovered clock feeds the receiver PCS logic until the rate matcher (in PCI Express [PIPE] and GIGE modes). The CMU low-speed parallel clock clocks the rest of the logic from the rate matcher until the receiver phase compensation FIFO. In Serial RapidIO mode that does not use a rate matcher, the receiver PCS logic is clocked by the recovered clock until the receiver phase compensation FIFO. The input reference clock to the transmitter and receiver PLLs can be derived from: ■ One of two available dedicated reference clock input pins (REFCLK0 or REFCLK1) of the associated transceiver block ■ PLD clock network (must be driven directly from an input clock pin and cannot be driven by user logic or enhanced PLL) ■ Inter-transceiver block lines driven by reference clock input pins of other transceiver blocks 2–24 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–15 shows the input reference clock sources for the transmitter and receiver PLL. Figure 2–15. Input Reference Clock Sources Inter-Transceiver Lines [2] Transceiver Block 2 Inter-Transceiver Lines [1] Transceiver Block 1 Transceiver Block 0 Inter-Transceiver Lines [0] Dedicated /2 REFCLK0 Transmitter Dedicated /2 PLL REFCLK1 Inter-Transceiver Lines [2:0] Global Clock (1) Four Receiver PLLs Global Clock (1) f For detailed transceiver clocking in all supported functional modes, refer to the Arria GX Transceiver Architecture chapter in volume 2 of the Arria GX Device Handbook. PLD Clock Utilization by Transceiver Blocks Arria GX devices have up to 16 global clock (GCLK) lines and 16 regional clock (RCLK) lines that are used to route the transceiver clocks. The following transceiver clocks utilize the available global and regional clock resources: ■ pll_inclk (if driven from an FPGA input pin) ■ rx_cruclk (if driven from an FPGA input pin) ■ tx_clkout/coreclkout (CMU low-speed parallel clock forwarded to the PLD) ■ Recovered clock from each channel (rx_clkout) in non-rate matcher mode (Serial RapidIO) Altera Corporation 2–25 June 2007 Arria GX Device Handbook, Volume 1 Transceivers ■ Calibration clock (cal_blk_clk) ■ Fixed clock (fixedclk used for receiver detect circuitry in PCI Express [PIPE] mode only) Figures 2–16 and 2–17 show the available global and regional clock resources in Arria GX devices. Figure 2–16. Global Clock Resources in Arria GX CLK[15..12] 11 5 7 Arria GX GCLK[15..12] Transceiver Block GCLK[11..8] 1 GCLK[3..0] CLK[3..0] 2 Arria GX Transceiver Block GCLK[4..7] 8 12 6 CLK[7..4] 2–26 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–17. Regional Clock Resources in Arria GX CLK[15..12] 11 5 7 RCLK RCLK [31..28] [27..24] Arria GX Transceiver Block RCLK RCLK [3..0] [23..20] 1 CLK[3..0] 2 RCLK RCLK Arria GX [7..4] [19..16] Transceiver Block RCLK RCLK [11..8] [15..12] 8 12 6 CLK[7..4] For the regional or global clock network to route into the transceiver, a local route input output (LRIO) channel is required. Each LRIO clock region has up to eight clock paths and each transceiver block has a maximum of eight clock paths for connecting with LRIO clocks. These resources are limited and determine the number of clocks that can be used between the PLD and transceiver blocks. Table 2–12 gives the number of LRIO resource available for Arria GX devices with different number of transceiver blocks. Table 2–12. Available Clocking Connections for Transceivers in EP1AGX35D, EP1AGX50D, and EP1AGX60D Clock Resource Transceiver Source Regional Bank13 Bank14 Global Clock Clock 8 Clock I/O 8 Clock I/O Region0 RCLK 20-27 v v 8 LRIO clock Region1 RCLK 12-19 v v 8 LRIO clock Altera Corporation 2–27 June 2007 Arria GX Device Handbook, Volume 1 Logic Array Blocks Table 2–13. Available Clocking Connections for Transceivers in EP1AGX60E and EP1AGX90E Clock Resource Transceiver Source Regional Bank13 Bank14 Bank15 Global Clock Clock 8 Clock I/O 8 Clock I/O 8 Clock I/O Region0 RCLK 20-27 v v 8 LRIO clock Region1 RCLK 20-27 v v v 8 LRIO clock Region2 RCLK 12-19 vv v 8 LRIO clock Region3 RCLK 12-19 v v 8 LRIO clock Each logic array block (LAB) consists of eight adaptive logic modules Logic Array (ALMs), carry chains, shared arithmetic chains, LAB control signals, local Blocks interconnects, and register chain connection lines. The local interconnect transfers signals between ALMs in the same LAB. Register chain connections transfer the output of an ALM register to the adjacent ALM ® register in a LAB. The Quartus II Compiler places associated logic in a LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency. Table 2–14 shows Arria GX device resources. Figure 2–18 shows the Arria GX LAB structure. Table 2–14. Arria GX Device Resources M512 RAM M4K RAM M-RAM DSP Block Device Columns/Blocks Columns/Blocks Blocks Columns/Blocks EP1AGX20 166 118 1 10 EP1AGX35 197 140 1 14 EP1AGX50 313 242 2 26 EP1AGX60 326 252 2 32 EP1AGX90 478 400 4 44 2–28 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–18. Arria GX LAB Structure Row Interconnects of Variable Speed & Length ALMs Direct link interconnect from adjacent block Direct link interconnect from adjacent block Direct link Direct link interconnect to interconnect to adjacent block adjacent block Local Interconnect LAB Local Interconnect is Driven Column Interconnects of from Either Side by Columns & LABs, Variable Speed & Length & from Above by Rows LAB Interconnects The LAB local interconnect can drive all eight ALMs in the same LAB. It is driven by column and row interconnects and ALM outputs in the same LAB. Neighboring LABs, M512 RAM blocks, M4K RAM blocks, M-RAM blocks, or digital signal processing (DSP) blocks from the left and right can also drive a LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each ALM can drive 24 ALMs through fast local and direct link interconnects. Altera Corporation 2–29 June 2007 Arria GX Device Handbook, Volume 1 Logic Array Blocks Figure 2–19 shows the direct link connection. Figure 2–19. Direct Link Connection Direct link interconnect from Direct link interconnect from TM left LAB, TriMatrix memory right LAB, TriMatrix memory block, DSP block, or block, DSP block, or IOE output input/output element (IOE) ALMs Direct link Direct link interconnect interconnect to left to right Local Interconnect LAB LAB Control Signals Each LAB contains dedicated logic for driving control signals to its ALMs. The control signals include three clocks, three clock enables, two asynchronous clears, synchronous clear, asynchronous preset/load, and synchronous load control signals, providing a maximum of 11 control signals at a time. Although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. Each LAB can use three clocks and three clock enable signals. However, there can only be up to two unique clocks per LAB, as shown in the LAB control signal generation circuit in Figure 2–20. Each LAB’s clock and clock enable signals are linked. For example, any ALM in a particular LAB using the labclk1 signal also uses labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses two LAB-wide clock signals. De-asserting the clock enable signal turns off the corresponding LAB-wide clock. Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. The asynchronous 2–30 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture load acts as a preset when the asynchronous load data input is tied high. When the asynchronous load/preset signal is used, the labclkena0 signal is no longer available. The LAB row clocks [5..0] and LAB local interconnect generate the LAB-wide control signals. The MultiTrack™ interconnects have inherently low skew. This low skew allows the MultiTrack interconnects to distribute clock and control signals in addition to data. Figure 2–20 shows the LAB control signal generation circuit. Figure 2–20. LAB-Wide Control Signals There are two unique clock signals per LAB. 6 Dedicated Row LAB Clocks 6 6 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclr1 labclk0 labclk1 labclk2 syncload labclkena0 labclkena1 labclkena2 labclr0 synclr or asyncload or labpreset Altera Corporation 2–31 June 2007 Arria GX Device Handbook, Volume 1 Adaptive Logic Modules The basic building block of logic in the Arria GX architecture is the ALM. Adaptive Logic The ALM provides advanced features with efficient logic utilization. Each Modules ALM contains a variety of look-up table (LUT)-based resources that can be divided between two adaptive LUTs (ALUTs). With up to eight inputs to the two ALUTs, one ALM can implement various combinations of two functions. This adaptability allows the ALM to be completely backward- compatible with four-input LUT architectures. One ALM can also implement any function of up to six inputs and certain seven-input functions. In addition to the adaptive LUT-based resources, each ALM contains two programmable registers, two dedicated full adders, a carry chain, a shared arithmetic chain, and a register chain. Through these dedicated resources, the ALM can efficiently implement various arithmetic functions and shift registers. Each ALM drives all types of interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, and direct link interconnects. Figure 2–21 shows a high-level block diagram of the Arria GX ALM while Figure 2–22 shows a detailed view of all the connections in the ALM. Figure 2–21. High-Level Block Diagram of the Arria GX ALM carry_in shared_arith_in reg_chain_in To general or local routing dataf0 To general or adder0 DQ datae0 local routing dataa reg0 datab Combinational Logic datac datad To general or adder1 DQ local routing datae1 reg1 dataf1 To general or local routing carry_out shared_arith_out reg_chain_out 2–32 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–22. Arria GX ALM Details Altera Corporation 2–33 June 2007 Arria GX Device Handbook, Volume 1 reg_chain_in sclr asyncload shared_arith_in carry_in syncload ena[2..0] dataf0 Local Interconnect Local datae0 Interconnect 4-Input LUT PRN/ALD Row, column & D Q Local direct link routing datac ADATA Interconnect 3-Input ENA Row, column & LUT CLRN direct link routing dataa Local Local 3-Input Interconnect Interconnect LUT Local datab 4-Input Interconnect LUT PRN/ALD Row, column & D Q datad direct link routing ADATA 3-Input ENA Row, column & LUT CLRN direct link routing Local 3-Input Interconnect LUT V CC Local datae1 Interconnect Local dataf1 Interconnect carry_out reg_chain_out clk[2..0] shared_arith_out aclr[1..0] Local Interconnect Adaptive Logic Modules One ALM contains two programmable registers. Each register has data, clock, clock enable, synchronous and asynchronous clear, asynchronous load data, and synchronous and asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any internal logic can drive the register's clock and clear control signals. Either general-purpose I/O pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous load data. The asynchronous load data input comes from the datae or dataf input of the ALM, which are the same inputs that can be used for register packing. For combinational functions, the register is bypassed and the output of the LUT drives directly to the outputs of the ALM. Each ALM has two sets of outputs that drive the local, row, and column routing resources. The LUT, adder, or register output can drive these output drivers independently (see Figure 2–22). For each set of output drivers, two ALM outputs can drive column, row, or direct link routing connections, and one of these ALM outputs can also drive local interconnect resources. This allows the LUT or adder to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and the combinational logic for unrelated functions. Another special packing mode allows the register output to feed back into the LUT of the same ALM so that the register is packed with its own fan-out LUT. This feature provides another mechanism for improved fitting. The ALM can also drive out registered and unregistered versions of the LUT or adder output. ALM Operating Modes The Arria GX ALM can operate in one of the following modes: ■ Normal mode ■ Extended LUT mode ■ Arithmetic mode ■ Shared arithmetic mode Each mode uses ALM resources differently. Each mode has 11 available inputs to the ALM (see Figure 2–21)⎯ the eight data inputs from the LAB local interconnect; carry-in from the previous ALM or LAB; the shared arithmetic chain connection from the previous ALM or LAB; and the register chain connection⎯ are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset/load, synchronous clear, synchronous load, and clock enable control for the register. These LAB 2–34 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture wide signals are available in all ALM modes. Refer to “LAB Control Signals” on page 2–30 for more information about the LAB-wide control signals. The Quartus II software and supported third-party synthesis tools, in conjunction with parameterized functions such as library of parameterized modules (LPM) functions, automatically choose the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. If required, the designer can also create special-purpose functions that specify which ALM operating mode to use for optimal performance. Normal Mode The normal mode is suitable for general logic applications and combinational functions. In this mode, up to eight data inputs from the LAB local interconnect are inputs to the combinational logic. The normal mode allows two functions to be implemented in one Arria GX ALM, or an ALM to implement a single function of up to six inputs. The ALM can support certain combinations of completely independent functions and various combinations of functions which have common inputs. Figure 2–23 shows the supported LUT combinations in normal mode. Altera Corporation 2–35 June 2007 Arria GX Device Handbook, Volume 1 Adaptive Logic Modules Figure 2–23. ALM in Normal Mode Note (1) dataf0 dataf0 4-Input datae0 datae0 5-Input combout0 datac combout0 datac LUT LUT dataa dataa datab datab 4-Input datad combout1 5-Input datae1 LUT datad combout1 LUT dataf1 datae1 dataf1 dataf0 datae0 5-Input dataf0 datac combout0 LUT datae0 dataa 6-Input dataa datab combout0 datab LUT datac datad datad 3-Input datae1 combout1 LUT dataf1 dataf0 datae0 6-Input dataa combout0 datab LUT dataf0 datac datae0 5-Input datad datac combout0 LUT dataa datab 6-Input combout1 datad 4-Input LUT combout1 datae1 datae1 LUT dataf1 dataf1 Note to Figure 2–23: (1) Combinations of functions with less inputs than those shown are also supported. For example, combinations of functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2, etc. The normal mode provides complete backward compatibility with four-input LUT architectures. Two independent functions of four inputs or less can be implemented in one Arria GX ALM. In addition, a five-input function and an independent three-input function can be implemented without sharing inputs. 2–36 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture To pack two five-input functions into one ALM, the functions must have at least two common inputs. The common inputs are dataa and datab. The combination of a four-input function with a five-input function requires one common input (either dataa or datab). To implement two six-input functions in one ALM, four inputs must be shared and the combinational function must be the same. For example, a 4 × 2 crossbar switch (two 4-to-1 multiplexers with common inputs and unique select lines) can be implemented in one ALM, as shown in Figure 2–24. The shared inputs are dataa, datab, datac, and datad, while the unique select lines are datae0 and dataf0 for function0, and datae1 and dataf1 for function1. This crossbar switch consumes four LUTs in a four-input LUT-based architecture. Figure 2–24. 4 × 2 Crossbar Switch Example 4 × 2 Crossbar Switch Implementation in 1 ALM sel0[1..0] dataf0 inputa datae0 Six-Input inputb out0 dataa combout0 LUT datab inputc (Function0) datac inputd datad out1 sel1[1..0] Six-Input combout1 LUT (Function1) datae1 dataf1 In a sparsely used device, functions that could be placed into one ALM can be implemented in separate ALMs. The Quartus II Compiler spreads a design out to achieve the best possible performance. As a device begins to fill up, the Quartus II software automatically utilizes the full potential of the Arria GX ALM. The Quartus II Compiler automatically searches for functions of common inputs or completely independent functions to be placed into one ALM and to make efficient use of the device resources. In addition, the designer can manually control resource usage by setting location assignments. Any six-input function can be implemented utilizing inputs dataa, datab, datac, datad, and either datae0 and dataf0 or datae1 and dataf1. If datae0 and dataf0 are utilized, the output is driven to register0, and/or register0 is bypassed and the data drives out to the interconnect using the top set of output drivers (see Figure 2–25). If datae1 and dataf1 are utilized, the output drives to register1 and/or bypasses register1 and drives to the interconnect Altera Corporation 2–37 June 2007 Arria GX Device Handbook, Volume 1 Adaptive Logic Modules using the bottom set of output drivers. The Quartus II Compiler automatically selects the inputs to the LUT. Asynchronous load data for the register comes from the datae or dataf input of the ALM. ALMs in normal mode support register packing. Figure 2–25. 6-Input Function in Normal Mode Notes (1), (2) To general or dataf0 local routing datae0 6-Input dataa To general or datab LUT DQ local routing datac datad reg0 datae1 dataf1 To general or DQ (2) local routing These inputs are available for register packing. reg1 Notes to Figure 2–25: (1) If datae1 and dataf1 are used as inputs to the six-input function, datae0 and dataf0 are available for register packing. (2) The dataf1 input is available for register packing only if the six-input function is un-registered. Extended LUT Mode The extended LUT mode is used to implement a specific set of seven-input functions. The set must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four inputs. Figure 2–26 shows the template of supported seven-input functions utilizing extended LUT mode. In this mode, if the seven-input function is unregistered, the unused eighth input is available for register packing. Functions that fit into the template shown in Figure 2–26 occur naturally in designs. These functions often appear in designs as “if-else” statements in Verilog HDL or VHDL code. 2–38 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–26. Template for Supported Seven-Input Functions in Extended LUT Mode datae0 datac dataa 5-Input datab To general or LUT datad local routing dataf0 combout0 To general or DQ local routing 5-Input reg0 LUT datae1 dataf1 (1) This input is available for register packing. Note to Figure 2–26: (1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available. Arithmetic Mode The arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. An ALM in arithmetic mode uses two sets of two four-input LUTs along with two dedicated full adders. The dedicated adders allow the LUTs to be available to perform pre-adder logic; therefore, each adder can add the output of two four-input functions. The four LUTs share the dataa and datab inputs. As shown in Figure 2–27, the carry-in signal feeds to adder0, and the carry-out from adder0 feeds to carry-in of adder1. The carry-out from adder1 drives to adder0 of the next ALM in the LAB. ALMs in arithmetic mode can drive out registered and/or unregistered versions of the adder outputs. Altera Corporation 2–39 June 2007 Arria GX Device Handbook, Volume 1 Adaptive Logic Modules Figure 2–27. ALM in Arithmetic Mode carry_in datae0 adder0 4-Input To general or LUT local routing To general or DQ local routing dataf0 4-Input reg0 datac datab LUT dataa adder1 4-Input To general or LUT datad local routing datae1 To general or DQ local routing 4-Input reg1 LUT dataf1 carry_out While operating in arithmetic mode, the ALM can support simultaneous use of the adder’s carry output along with combinational logic outputs. In this operation, the adder output is ignored. This usage of the adder with the combinational logic output provides resource savings of up to 50% for functions that can use this ability. An example of such functionality is a conditional operation, such as the one shown in Figure 2–28. The equation for this example is: R = (X < Y) ? Y : X To implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If ‘X’ is less than ‘Y,’ the carry_out signal will be ‘1.’ The carry_out signal is fed to an adder where it drives out to the LAB local interconnect. It then feeds to the LAB-wide syncload signal. When asserted, syncload selects the syncdata input. In this case, the data ‘Y’ drives the syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’ the syncload signal is de-asserted and ‘X’ drives the data port of the registers. 2–40 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–28. Conditional Operation Example Adder output is not used. ALM 1 X[0] Comb & X[0] R[0] Adder To general or DQ Y[0] Logic local routing reg0 syncdata syncload X[1] Comb & X[1] R[1] Adder To general or DQ Y[1] local routing Logic reg1 syncload Carry Chain ALM 2 X[2] Comb & X[2] Adder R[2] To general or DQ Y[2] Logic local routing reg0 syncload Comb & To local routing & carry_out then to LAB-wide Adder syncload Logic The arithmetic mode also offers clock enable, counter enable, synchronous up/down control, add/subtract control, synchronous clear, synchronous load. The LAB local interconnect data inputs generate the clock enable, counter enable, synchronous up/down and add/subtract control signals. These control signals may be used for the inputs that are shared between the four LUTs in the ALM. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. The Quartus II software automatically places any registers that are not used by the counter into other LABs. Carry Chain The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic mode. Carry chains can begin in either the first ALM or the fifth ALM in a LAB. The final carry-out signal is routed to an ALM, where it is fed to local, row, or column interconnects. Altera Corporation 2–41 June 2007 Arria GX Device Handbook, Volume 1 Adaptive Logic Modules The Quartus II Compiler automatically creates carry chain logic during compilation, or the designer can create it manually during design entry. Parameterized functions such as LPM functions automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 16 (8 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks. A carry chain can continue as far as a full column. To avoid routing congestion in one small area of the device when a high fan-in arithmetic function is implemented, the LAB can support carry chains that only utilize either the top half or the bottom half of the LAB before connecting to the next LAB. The other half of the ALMs in the LAB is available for implementing narrower fan-in functions in normal mode. Carry chains that use the top four ALMs in the first LAB will carry into the top half of the ALMs in the next LAB within the column. Carry chains that use the bottom four ALMs in the first LAB will carry into the bottom half of the ALMs in the next LAB within the column. Every other column of the LABs are top-half bypassable, while the other LAB columns are bottom-half bypassable. Refer to “MultiTrack Interconnect” on page 2–47 for more information about carry chain interconnect. Shared Arithmetic Mode In shared arithmetic mode, the ALM can implement a three-input add. In this mode, the ALM is configured with four 4-input LUTs. Each LUT either computes the sum of three inputs or the carry of three inputs. The output of the carry computation is fed to the next adder (either to adder1 in the same ALM or to adder0 of the next ALM in the LAB) using a dedicated connection called the shared arithmetic chain. This shared arithmetic chain can significantly improve the performance of an adder tree by reducing the number of summation stages required to implement an adder tree. Figure 2–29 shows the ALM in shared arithmetic mode. 2–42 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–29. ALM in Shared Arithmetic Mode shared_arith_in carry_in 4-Input To general or LUT local routing To general or DQ local routing datae0 reg0 datac 4-Input datab LUT dataa 4-Input To general or LUT datad local routing datae1 To general or DQ local routing 4-Input reg1 LUT carry_out shared_arith_out Note to Figure 2–29: (1) Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode. Adder trees are used in many different applications. For example, the summation of the partial products in a logic-based multiplier can be implemented in a tree structure. Another example is a correlator function that can use a large adder tree to sum filtered data samples in a given time frame to recover or to de-spread data which was transmitted utilizing spread spectrum technology. An example of a three-bit add operation utilizing the shared arithmetic mode is shown in Figure 2–30. The partial sum (S[2..0]) and the partial carry (C[2..0]) is obtained using the LUTs, while the result (R[2..0]) is computed using the dedicated adders. Altera Corporation 2–43 June 2007 Arria GX Device Handbook, Volume 1 Adaptive Logic Modules Figure 2–30. Example of a 3-Bit Add Utilizing Shared Arithmetic Mode shared_arith_in = '0' carry_in = '0' 3-Bit Add Example ALM Implementation ALM 1 X2 X1 X0 3-Input S0 1st stage add is Y2 Y1 Y0 LUT implemented in LUTs. + Z2 Z1 Z0 R0 2nd stage add is S2 S1 S0 X0 implemented in adders. 3-Input + C0 C2 C1 C0 Y0 LUT Z0 R3 R2 R1 R0 X1 S1 3-Input Decimal Y1 Equivalents Binary Add LUT Z1 R1 1 1 0 6 1 0 1 5 C1 3-Input + 0 1 0 + 2 LUT 0 0 1 1 + + 1 1 0 2 x 6 ALM 2 1 1 0 1 13 S2 3-Input LUT R2 X2 3-Input C2 Y2 LUT Z2 3-Input '0' LUT R3 3-Input LUT Shared Arithmetic Chain In addition to the dedicated carry chain routing, the shared arithmetic chain available in shared arithmetic mode allows the ALM to implement a three-input add, which significantly reduces the resources necessary to implement large adder trees or correlator functions. The shared arithmetic chains can begin in either the first or fifth ALM in a LAB. The Quartus II Compiler automatically links LABs to create shared arithmetic chains longer than 16 (8 ALMs in arithmetic or shared arithmetic mode). For enhanced fitting, a long shared arithmetic chain runs vertically 2–44 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture allowing fast horizontal connections to TriMatrix memory and DSP blocks. A shared arithmetic chain can continue as far as a full column. Similar to the carry chains, the shared arithmetic chains are also top- or bottom-half bypassable. This capability allows the shared arithmetic chain to cascade through half of the ALMs in a LAB while leaving the other half available for narrower fan-in functionality. Every other LAB column is top-half bypassable, while the other LAB columns are bottom-half bypassable. Refer to “MultiTrack Interconnect” on page 2–47 for more information about shared arithmetic chain interconnect. Register Chain In addition to the general routing outputs, the ALMs in a LAB have register chain outputs. The register chain routing allows registers in the same LAB to be cascaded together. The register chain interconnect allows a LAB to use LUTs for a single combinational function and the registers to be used for an unrelated shift register implementation. These resources speed up connections between ALMs while saving local interconnect resources (see Figure 2–31). The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. See “MultiTrack Interconnect” on page 2–47 for more information about register chain interconnect. Altera Corporation 2–45 June 2007 Arria GX Device Handbook, Volume 1 Adaptive Logic Modules Figure 2–31. Register Chain within a LAB Note (1) From Previous ALM Within The LAB reg_chain_in To general or local routing To general or adder0 DQ local routing reg0 Combinational Logic To general or adder1 DQ local routing reg1 To general or local routing To general or local routing To general or adder0 DQ local routing reg0 Combinational Logic To general or adder1 DQ local routing reg1 To general or local routing reg_chain_out To Next ALM within the LAB Note to Figure 2–31: (1) The combinational or adder logic can be utilized to implement an unrelated, un-registered function. 2–46 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Clear and Preset Logic Control LAB-wide signals control the logic for the register’s clear and load/preset signals. The ALM directly supports an asynchronous clear and preset function. The register preset is achieved through the asynchronous load of a logic high. The direct asynchronous preset does not require a NOT gate push-back technique. Arria GX devices support simultaneous asynchronous load/preset, and clear signals. An asynchronous clear signal takes precedence if both signals are asserted simultaneously. Each LAB supports up to two clears and one load/preset signal. In addition to the clear and load/preset ports, Arria GX devices provide a device-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin. This device-wide reset overrides all other control signals. In the Arria GX architecture, the MultiTrack interconnect structure with MultiTrack DirectDrive™ technology provides connections between ALMs, Interconnect TriMatrix memory, DSP blocks, and device I/O pins. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for inter- and intra-design block connectivity. The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance. DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement in the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycles that typically follow design changes and additions. The MultiTrack interconnect consists of row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. Dedicated row interconnects route signals to and from LABs, DSP blocks, and TriMatrix memory in the same row. These row resources include: ■ Direct link interconnects between LABs and adjacent blocks ■ R4 interconnects traversing four blocks to the right or left ■ R24 row interconnects for high-speed access across the length of the device Altera Corporation 2–47 June 2007 Arria GX Device Handbook, Volume 1 MultiTrack Interconnect The direct link interconnect allows a LAB, DSP block, or TriMatrix memory block to drive into the local interconnect of its left and right neighbors and then back into itself, providing fast communication between adjacent LABs and/or blocks without using row interconnect resources. The R4 interconnects span four LABs, three LABs and one M512 RAM block, two LABs and one M4K RAM block, or two LABs and one DSP block to the right or left of a source LAB. These resources are used for fast row connections in a four-LAB region. Every LAB has its own set of R4 interconnects to drive either left or right. Figure 2–32 shows R4 interconnect connections from a LAB. R4 interconnects can drive and be driven by DSP blocks and RAM blocks and row IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4 interconnect. For R4 interconnects that drive to the right, the primary LAB and right neighbor can drive onto the interconnect. For R4 interconnects that drive to the left, the primary LAB and its left neighbor can drive onto the interconnect. R4 interconnects can drive other R4 interconnects to extend the range of LABs they can drive. R4 interconnects can also drive C4 and C16 interconnects for connections from one row to another. Additionally, R4 interconnects can drive R24 interconnects. Figure 2–32. R4 Interconnect Connections Notes (1), (2), (3) Adjacent LAB can C4 and C16 R4 Interconnect Drive onto Another Column Interconnects (1) Driving Right LAB's R4 Interconnect R4 Interconnect Driving Left LAB Primary LAB Neighbor LAB (2) Neighbor Notes to Figure 2–32: (1) C4 and C16 interconnects can drive R4 interconnects. (2) This pattern is repeated for every LAB in the LAB row. (3) The LABs in Figure 2–32 show the 16 possible logical outputs per LAB. 2–48 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture R24 row interconnects span 24 LABs and provide the fastest resource for long row connections between LABs, TriMatrix memory, DSP blocks, and Row IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row interconnects drive to other row or column interconnects at every fourth LAB and do not drive directly to LAB local interconnects. R24 row interconnects drive LAB local interconnects via R4 and C4 interconnects. R24 interconnects can drive R24, R4, C16, and C4 interconnects. The column interconnect operates similarly to the row interconnect and vertically routes signals to and from LABs, TriMatrix memory, DSP blocks, and IOEs. Each column of LABs is served by a dedicated column interconnect. These column resources include: ■ Shared arithmetic chain interconnects in a LAB ■ Carry chain interconnects in a LAB and from LAB to LAB ■ Register chain interconnects in a LAB ■ C4 interconnects traversing a distance of four blocks in up and down direction ■ C16 column interconnects for high-speed vertical routing through the device Arria GX devices include an enhanced interconnect structure in LABs for routing shared arithmetic chains and carry chains for efficient arithmetic functions. The register chain connection allows the register output of one ALM to connect directly to the register input of the next ALM in the LAB for fast shift registers. These ALM to ALM connections bypass the local interconnect. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. Figure 2–33 shows the shared arithmetic chain, carry chain and register chain interconnects. Altera Corporation 2–49 June 2007 Arria GX Device Handbook, Volume 1 MultiTrack Interconnect Figure 2–33. Shared Arithmetic Chain, Carry Chain & Register Chain Interconnects Local Interconnect Routing Among ALMs in the LAB ALM 1 Carry Chain & Shared Register Chain Arithmetic Chain Routing to Adjacent Routing to Adjacent ALM ALM's Register Input ALM 2 Local ALM 3 Interconnect ALM 4 ALM 5 ALM 6 ALM 7 ALM 8 The C4 interconnects span four LABs, M512, or M4K blocks up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. Figure 2–34 shows the C4 interconnect connections from a LAB in a column. The C4 interconnects can drive and be driven by all types of architecture blocks, including DSP blocks, TriMatrix memory blocks, and column and row IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. 2–50 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–34. C4 Interconnect Connections Note (1) C4 Interconnect Drives Local and R4 Interconnects up to Four Rows C4 Interconnect Driving Up LAB Row Interconnect Adjacent LAB can drive onto neighboring LAB's C4 interconnect Local Interconnect C4 Interconnect Driving Down Note to Figure 2–34: (1) Each C4 interconnect can drive either up or down four rows. Altera Corporation 2–51 June 2007 Arria GX Device Handbook, Volume 1 MultiTrack Interconnect C16 column interconnects span a length of 16 LABs and provide the fastest resource for long column connections between LABs, TriMatrix memory blocks, DSP blocks, and IOEs. C16 interconnects can cross M-RAM blocks and also drive to row and column interconnects at every fourth LAB. C16 interconnects drive LAB local interconnects via C4 and R4 interconnects and do not drive LAB local interconnects directly. All embedded blocks communicate with the logic array similar to LAB-to-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks, labclk[5..0]. Table 2–15 shows the Arria GX device’s routing scheme. Table 2–15. Arria GX Device Routing Scheme (Part 1 of 2) Destination Source Shared arithmetic chain v Carry chain v Register chain v Local interconnect vvvvvvv Direct link interconnect v R4 interconnect v vvvv R24 interconnect vvvv C4 interconnect vvv C16 interconnect vvvv ALM vvvvvv v M512 RAM block vvv v M4K RAM block vvv v M-RAM block vvvv DSP blocks vv v 2–52 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Shared Arithmetic Chain Carry Chain Register Chain Local Interconnect Direct Link Interconnect R4 Interconnect R24 Interconnect C4 Interconnect C16 Interconnect ALM M512 RAM Block M4K RAM Block M-RAM Block DSP Blocks Column IOE Row IOE Arria GX Architecture Table 2–15. Arria GX Device Routing Scheme (Part 2 of 2) Destination Source Column IOE vvv Row IOE vvvv TriMatrix memory consists of three types of RAM blocks: M512, M4K, TriMatrix and M-RAM. Although these memory blocks are different, they can all Memory implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and first-in first-out (FIFO) buffers. Table 2–16 shows the size and features of the different RAM blocks. Table 2–16. TriMatrix Memory Features (Part 1 of 2) M512 RAM Block M4K RAM Block M-RAM Block Memory Feature (32 × 18 Bits) (128 × 36 Bits) (4K × 144 Bits) Maximum performance 345 MHz 380 MHz 290 MHz True dual-port memory vv Simple dual-port memory vvv Single-port memory vvv Shift register vv ROM vv FIFO buffer vvv Pack mode vv Byte enable vvv Address clock enable vv Parity bits vvv Mixed clock mode vvv Memory initialization (.mif) vv Altera Corporation 2–53 June 2007 Arria GX Device Handbook, Volume 1 Shared Arithmetic Chain Carry Chain Register Chain Local Interconnect Direct Link Interconnect R4 Interconnect R24 Interconnect C4 Interconnect C16 Interconnect ALM M512 RAM Block M4K RAM Block M-RAM Block DSP Blocks Column IOE Row IOE TriMatrix Memory Table 2–16. TriMatrix Memory Features (Part 2 of 2) M512 RAM Block M4K RAM Block M-RAM Block Memory Feature (32 × 18 Bits) (128 × 36 Bits) (4K × 144 Bits) Simple dual-port memory vvv mixed width support True dual-port memory vv mixed width support Power-up conditions Outputs cleared Outputs cleared Outputs unknown Register clears Output registers Output registers Output registers Mixed-port read-during-write Unknown output/old data Unknown output/old data Unknown output Configurations 512 × 1 4K × 1 64K × 8 256 × 2 2K × 2 64K × 9 128 × 4 1K × 4 32K × 16 64 × 8 512 × 8 32K × 18 64 × 9 512 × 9 16K × 32 32 × 16 256 × 16 16K × 36 32 × 18 256 × 18 8K × 64 128 × 32 8K × 72 128 × 36 4K × 128 4K × 144 TriMatrix memory provides three different memory sizes for efficient application support. The Quartus II software automatically partitions the user-defined memory into the embedded memory blocks using the most efficient size combinations. The designer can also manually assign the memory to a specific block size or a mixture of block sizes. M512 RAM Block The M512 RAM block is a simple dual-port memory block and is useful for implementing small FIFO buffers, DSP, and clock domain transfer applications. Each block contains 576 RAM bits (including parity bits). M512 RAM blocks can be configured in the following modes: ■ Simple dual-port RAM ■ Single-port RAM ■ FIFO ■ ROM ■ Shift register When configured as RAM or ROM, the designer can use an initialization file to pre-load the memory contents. 2–54 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture M512 RAM blocks can have different clocks on its inputs and outputs. The wren, datain, and write address registers are all clocked together from one of the two clocks feeding the block. The read address, rden, and output registers can be clocked by either of the two clocks driving the block, allowing the RAM block to operate in read/write or input/output clock modes. Only the output register can be bypassed. The six labclk signals or local interconnect can drive the inclock, outclock, wren, rden, and outclr signals. Because of the advanced interconnect between the LAB and M512 RAM blocks, ALMs can also control the wren and rden signals and the RAM clock, clock enable, and asynchronous clear signals. Figure 2–35 shows the M512 RAM block control signal generation logic. Figure 2–35. M512 RAM Block Control Signals Dedicated 6 Row LAB Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local inclocken outclocken wren Interconnect Local outclr inclock outclock rden Interconnect The RAM blocks in Arria GX devices have local interconnects to allow ALMs and interconnects to drive into RAM blocks. The M512 RAM block local interconnect is driven by the R4, C4, and direct link interconnects from adjacent LABs. The M512 RAM blocks can communicate with LABs on either the left or right side through these row interconnects or with LAB columns on the left or right side with the column interconnects. The Altera Corporation 2–55 June 2007 Arria GX Device Handbook, Volume 1 TriMatrix Memory M512 RAM block has up to 16 direct link input connections from the left adjacent LABs and another 16 from the right adjacent LAB. M512 RAM outputs can also connect to left and right LABs through direct link interconnect. The M512 RAM block has equal opportunity for access and performance to and from LABs on either its left or right side. Figure 2–36 shows the M512 RAM block to logic array interface. Figure 2–36. M512 RAM Block LAB Row Interface C4 Interconnect R4 Interconnect 16 Direct link Direct link interconnect interconnect 36 to adjacent LAB to adjacent LAB dataout M4K RAM Block Direct link Direct link interconnect interconnect from adjacent LAB from adjacent LAB datain byte control enable signals clocks address 6 M4K RAM Block Local LAB Row Clocks Interconnect Region M4K RAM Blocks The M4K RAM block includes support for true dual-port RAM. The M4K RAM block is used to implement buffers for a wide variety of applications such as storing processor code, implementing lookup schemes, and implementing larger memory applications. Each block contains 4,608 RAM bits (including parity bits). M4K RAM blocks can be configured in the following modes: ■ True dual-port RAM ■ Simple dual-port RAM ■ Single-port RAM 2–56 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture ■ FIFO ■ ROM ■ Shift register When configured as RAM or ROM, the designer can use an initialization file to pre-load the memory contents. The M4K RAM blocks allow for different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M4K RAM block registers (renwe, address, byte enable, datain, and output registers). Only the output register can be bypassed. The six labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K RAM block. ALMs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure 2–37. Figure 2–37. M4K RAM Block Control Signals Dedicated 6 Row LAB Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect clock_b clocken_b renwe_b aclr_b Local Interconnect clock_a clocken_a renwe_a aclr_a Altera Corporation 2–57 June 2007 Arria GX Device Handbook, Volume 1 TriMatrix Memory The R4, C4, and direct link interconnects from adjacent LABs drive the M4K RAM block local interconnect. The M4K RAM blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 16 direct link input connections to the M4K RAM block are possible from the left adjacent LABs and another 16 possible from the right adjacent LAB. M4K RAM block outputs can also connect to left and right LABs through direct link interconnect. Figure 2–38 shows the M4K RAM block to logic array interface. Figure 2–38. M4K RAM Block LAB Row Interface C4 Interconnect R4 Interconnect 16 Direct link Direct link interconnect interconnect 36 to adjacent LAB to adjacent LAB dataout M4K RAM Block Direct link Direct link interconnect interconnect from adjacent LAB from adjacent LAB datain byte control enable signals clocks address 6 M4K RAM Block Local LAB Row Clocks Interconnect Region M-RAM Block The largest TriMatrix memory block, the M-RAM block, is useful for applications where a large volume of data must be stored on-chip. Each block contains 589,824 RAM bits (including parity bits). The M-RAM block can be configured in the following modes: ■ True dual-port RAM ■ Simple dual-port RAM 2–58 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture ■ Single-port RAM ■ FIFO The designer cannot use an initialization file to initialize the contents of a M-RAM block. All M-RAM block contents power up to an undefined value. Only synchronous operation is supported in the M-RAM block, so all inputs are registered. Output registers can be bypassed. Similar to all RAM blocks, M-RAM blocks can have different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M-RAM block registers (renwe, address, byte enable, datain, and output registers). The output register can be bypassed. The six labclk signals or local interconnect can drive the control signals for the A and B ports of the M-RAM block. ALMs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals as shown in Figure 2–39. Figure 2–39. M-RAM Block Control Signals Dedicated 6 Row LAB Clocks Local Local Interconnect Interconnect Local Local Interconnect Interconnect Local Local Interconnect Interconnect Local Local Interconnect Interconnect Local Local Interconnect Interconnect clocken_a renwe_a aclr_b clock_b Local Local Interconnect Interconnect clock_a aclr_a renwe_b clocken_b The R4, R24, C4, and direct link interconnects from adjacent LABs on either the right or left side drive the M-RAM block local interconnect. Up to 16 direct link input connections to the M-RAM block are possible from the left adjacent LABs and another 16 possible from the right adjacent LAB. M-RAM block outputs can also connect to left and right LABs through direct link interconnect. Figure 2–40 shows an example floorplan for the EP1AGX90 device and the location of the M-RAM interfaces. Figures 2–41 and 2–42 show the interface between the M-RAM block and the logic array. Altera Corporation 2–59 June 2007 Arria GX Device Handbook, Volume 1 TriMatrix Memory Figure 2–40. EP1AGX90 Device with M-RAM Interface Locations Note (1) M-RAM blocks interface to LABs on right and left sides for easy access to horizontal I/O pins M-RAM M-RAM Block Block M-RAM M-RAM Block Block M4K M512 DSP LABs DSP Blocks Blocks Blocks Blocks Note to Figure 2–40: (1) The device shown is an EP1AGX90 device. The number and position of M-RAM blocks vary in other devices. 2–60 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–41. M-RAM Block LAB Row Interface Note (1) Row Unit Interface Allows LAB Row Unit Interface Allows LAB Rows to Drive Port A Datain, Rows to Drive Port B Datain, Dataout, Address and Control Dataout, Address and Control Signals to and from M-RAM Block Signals to and from M-RAM Block L0 R0 L1 R1 M-RAM Block L2 R2 Port A Port B L3 R3 L4 R4 L5 R5 LAB Interface Blocks LABs in Row LABs in Row M-RAM Boundary M-RAM Boundary Note to Figure 2–41: (1) Only R24 and C16 interconnects cross the M-RAM block boundaries. Altera Corporation 2–61 June 2007 Arria GX Device Handbook, Volume 1 TriMatrix Memory Figure 2–42. M-RAM Row Unit Interface to Interconnect C4 Interconnect R4 and R24 Interconnects M-RAM Block LAB Up to 16 dataout_a[ ] 16 datain_a[ ] addressa[ ] Up to 28 addr_ena_a Direct Link renwe_a Interconnects byteena [ ] A clocken_a clock_a aclr_a Row Interface Block M-RAM Block to LAB Row Interface Block Interconnect Region 2–62 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Table 2–17 shows the input and output data signal connections along with the address and control signal input connections to the row unit interfaces (L0 to L5 and R0 to R5). Table 2–17. M-RAM Row Interface Unit Signals Unit Interface Block Input Signals Output Signals L0 datain_a[14..0] dataout_a[11..0] byteena_a[1..0] L1 datain_a[29..15] dataout_a[23..12] byteena_a[3..2] L2 datain_a[35..30] dataout_a[35..24] addressa[4..0] addr_ena_a clock_a clocken_a renwe_a aclr_a L3 addressa[15..5] dataout_a[47..36] datain_a[41..36] L4 datain_a[56..42] dataout_a[59..48] byteena_a[5..4] L5 datain_a[71..57] dataout_a[71..60] byteena_a[7..6] R0 datain_b[14..0] dataout_b[11..0] byteena_b[1..0] R1 datain_b[29..15] dataout_b[23..12] byteena_b[3..2] R2 datain_b[35..30] dataout_b[35..24] addressb[4..0] addr_ena_b clock_b clocken_b renwe_b aclr_b R3 addressb[15..5] dataout_b[47..36] datain_b[41..36] R4 datain_b[56..42] dataout_b[59..48] byteena_b[5..4] R5 datain_b[71..57] dataout_b[71..60] byteena_b[7..6] f Refer to the TriMatrix Embedded Memory Blocks in Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook for more information about TriMatrix memory. Altera Corporation 2–63 June 2007 Arria GX Device Handbook, Volume 1 Digital Signal Processing Block The most commonly used DSP functions are finite impulse response (FIR) Digital Signal filters, complex FIR filters, infinite impulse response (IIR) filters, fast Processing Fourier transform (FFT) functions, direct cosine transform (DCT) functions, and correlators. All of these use the multiplier as the Block fundamental building block. Additionally, some applications need specialized operations such as multiply-add and multiply-accumulate operations. Arria GX devices provide DSP blocks to meet the arithmetic requirements of these functions. Each Arria GX device has two to four columns of DSP blocks to efficiently implement DSP functions faster than ALM-based implementations. Each DSP block can be configured to support up to: ■ Eight 9 × 9-bit multipliers ■ Four 18 × 18-bit multipliers ■ One 36 × 36-bit multiplier As indicated, the Arria GX DSP block can support one 36 × 36-bit multiplier in a single DSP block, and is true for any combination of signed, unsigned, or mixed sign multiplications. 2–64 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figures 2–43 shows one of the columns with surrounding LAB rows. Figure 2–43. DSP Blocks Arranged in Columns DSP Block Column DSP Block 4 LAB Rows Altera Corporation 2–65 June 2007 Arria GX Device Handbook, Volume 1 Digital Signal Processing Block Table 2–18 shows the number of DSP blocks in each Arria GX device. DSP block multipliers can optionally feed an adder/subtractor or accumulator in the block depending on the configuration, which makes routing to ALMs easier, saves ALM routing resources, and increases performance because all connections and blocks are in the DSP block. Table 2–18. DSP Blocks in Arria GX Devices Note (1) Total 9 × 9 Total 18 × 18 Total 36 × 36 Device DSP Blocks Multipliers Multipliers Multipliers EP1AGX20 10 80 40 10 EP1AGX35 14 112 56 14 EP1AGX50 26 208 104 26 EP1AGX60 32 256 128 32 EP1AGX90 44 352 176 44 Note to Table 2–18: (1) This list only shows functions that can fit into a single DSP block. Multiple DSP blocks can support larger multiplication functions. Additionally, the DSP block input registers can efficiently implement shift registers for FIR filter applications, and DSP blocks support Q1.15 format rounding and saturation. Figure 2–44 shows the top-level diagram of the DSP block configured for 18 × 18-bit multiplier mode. 2–66 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–44. DSP Block Diagram for 18 × 18-Bit Configuration Optional Serial Shift Register Inputs from Previous DSP Block Multiplier Stage Optional Stage Configurable Output Selection as Accumulator or Dynamic DQ Multiplexer Adder/Subtractor ENA CLRN DQ ENA CLRN DQ ENA CLRN Adder/ Subtractor/ Accumulator 1 DQ ENA CLRN DQ ENA CLRN DQ ENA CLRN Summation DQ ENA CLRN DQ Optional Output Register Stage ENA Summation Stage CLRN for Adding Four DQ Multipliers Together ENA CLRN Adder/ Subtractor/ Accumulator 2 DQ ENA CLRN Optional Serial DQ Shift Register Optional Pipeline Outputs to ENA Register Stage Next DSP Block CLRN DQ in the Column ENA Optional Input Register CLRN Stage with Parallel Input or Shift Register Configuration to MultiTrack Interconnect Altera Corporation 2–67 June 2007 Arria GX Device Handbook, Volume 1 Digital Signal Processing Block Modes of Operation The adder, subtractor, and accumulate functions of a DSP block have four modes of operation: ■ Simple multiplier ■ Multiply-accumulator ■ Two-multipliers adder ■ Four-multipliers adder Table 2–19 shows the different number of multipliers possible in each DSP block mode according to size. These modes allow the DSP blocks to implement numerous applications for DSP including FFTs, complex FIR, FIR, 2D FIR filters, equalizers, IIR, correlators, matrix multiplication, and many other functions. The DSP blocks also support mixed modes and mixed multiplier sizes in the same block. For example, half of one DSP block can implement one 18 × 18-bit multiplier in multiply-accumulator mode, while the other half of the DSP block implements four 9 × 9-bit multipliers in simple multiplier mode. Table 2–19. Multiplier Size and Configurations per DSP Block DSP Block Mode 9 × 9 18 × 18 36 × 36 Multiplier Eight multipliers with Four multipliers with four One multiplier with one eight product outputs product outputs product output Multiply-accumulator - Two 52-bit multiply- - accumulate blocks Two-multipliers adder Four two-multiplier adder Two two-multiplier adder - (two 9 × 9 complex (one 18 × 18 complex multiply) multiply) Four-multipliers adder Two four-multiplier adder One four-multiplier adder - DSP Block Interface The Arria GX device DSP block input registers can generate a shift register that can cascade down in the same DSP block column. Dedicated connections between DSP blocks provide fast connections between the shift register inputs to cascade the shift register chains. The designer can cascade registers within multiple DSP blocks for 9 × 9- or 18 × 18-bit FIR filters larger than four taps, with additional adder stages implemented in ALMs. If the DSP block is configured as 36 × 36 bits, the adder, subtractor, or accumulator stages are implemented in ALMs. Each DSP block can route the shift register chain out of the block to cascade multiple columns of DSP blocks. 2–68 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture The DSP block is divided into four block units that interface with four LAB rows on the left and right. Each block unit can be considered one complete 18 × 18-bit multiplier with 36 inputs and 36 outputs. A local interconnect region is associated with each DSP block. Like a LAB, this interconnect region can be fed with 16 direct link interconnects from the LAB to the left or right of the DSP block in the same row. R4 and C4 routing resources can access the DSP block’s local interconnect region. The outputs also work similarly to LAB outputs as well. Eighteen outputs from the DSP block can drive to the left LAB through direct link interconnects and 18 can drive to the right LAB though direct link interconnects. All 36 outputs can drive to R4 and C4 routing interconnects. Outputs can drive right- or left-column routing. Altera Corporation 2–69 June 2007 Arria GX Device Handbook, Volume 1 Digital Signal Processing Block Figures 2–45 and 2–46 show the DSP block interfaces to LAB rows. Figure 2–45. DSP Block Interconnect Interface DSP Block OA[17..0] R4, C4 & Direct R4, C4 & Direct OB[17..0] Link Interconnects Link Interconnects A1[17..0] B1[17..0] OC[17..0] OD[17..0] A2[17..0] B2[17..0] OE[17..0] OF[17..0] A3[17..0] B3[17..0] OG[17..0] OH[17..0] A4[17..0] B4[17..0] 2–70 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–46. DSP Block Interface to Interconnect Direct Link Interconnect Direct Link Outputs Direct Link Interconnect C4 Interconnect from Adjacent LAB to Adjacent LABs from Adjacent LAB R4 Interconnect 36 DSP Block Row Structure LAB 36 LAB 18 16 16 12 Control 36 36 A[17..0] OA[17..0] B[17..0] OB[17..0] Row Interface Block DSP Block to 36 Inputs per Row 36 Outputs per Row LAB Row Interface Block Interconnect Region A bus of 44 control signals feeds the entire DSP block. These signals include clocks, asynchronous clears, clock enables, signed/unsigned control signals, addition and subtraction control signals, rounding and saturation control signals, and accumulator synchronous loads. The clock signals are routed from LAB row clocks and are generated from specific LAB rows at the DSP block interface. The LAB row source for control signals, data inputs, and outputs is shown in Table 2–20. Altera Corporation 2–71 June 2007 Arria GX Device Handbook, Volume 1 Digital Signal Processing Block f Refer to the DSP Blocks in Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook for more information about DSP blocks. Table 2–20. DSP Block Signal Sources and Destinations LAB Row at Control Signals Generated Data Inputs Data Outputs Interface 0 clock0 A1[17..0] OA[17..0] aclr0 B1[17..0] OB[17..0] ena0 mult01_saturate addnsub1_round/ accum_round addnsub1 signa sourcea sourceb 1 clock1 A2[17..0] OC[17..0] aclr1 B2[17..0] OD[17..0] ena1 accum_saturate mult01_round accum_sload sourcea sourceb mode0 2 clock2 A3[17..0] OE[17..0] aclr2 B3[17..0] OF[17..0] ena2 mult23_saturate addnsub3_round/ accum_round addnsub3 sign_b sourcea sourceb 3 clock3 A4[17..0] OG[17..0] aclr3 B4[17..0] OH[17..0] ena3 accum_saturate mult23_round accum_sload sourcea sourceb mode1 2–72 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Arria GX devices provide a hierarchical clock structure and multiple PLLs and Clock phase-locked loops (PLLs) with advanced features. The large number of Networks clocking resources in combination with the clock synthesis precision provided by enhanced and fast PLLs provides a complete clock management solution. Global and Hierarchical Clocking Arria GX devices provide 16 dedicated global clock networks and 32 regional clock networks (eight per device quadrant). These clocks are organized into a hierarchical clock structure that allows for up to 24 clocks per device region with low skew and delay. This hierarchical clocking scheme provides up to 48 unique clock domains in Arria GX devices. There are 12 dedicated clock pins (CLK[15..12] and CLK[7..0]) to drive either the global or regional clock networks. Four clock pins drive each side of the device except the right side, as shown in Figures 2–47 and 2–48. Internal logic and enhanced and fast PLL outputs can also drive the global and regional clock networks. Each global and regional clock has a clock control block, which controls the selection of the clock source and dynamically enables/disables the clock to reduce power consumption. Table 2–21 shows global and regional clock features. Table 2–21. Global and Regional Clock Features Feature Global Clocks Regional Clocks Number per device 16 32 Number available per 16 8 quadrant Sources Clock pins, PLL outputs, Clock pins, PLL outputs, core routings, core routings, inter-transceiver clocks inter-transceiver clocks Dynamic clock source v selection Dynamic enable/disable vv Global Clock Network These clocks drive throughout the entire device, feeding all device quadrants. The global clock networks can be used as clock sources for all resources in the device IOEs, ALMs, DSP blocks, and all memory blocks. These resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin. The global clock networks can also be driven by internal logic for internally Altera Corporation 2–73 June 2007 Arria GX Device Handbook, Volume 1 PLLs and Clock Networks generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. Figure 2–47 shows the 12 dedicated CLK pins driving global clock networks. Figure 2–47. Global Clocking CLK[15..12] Global Clock [15..0] CLK[3..0] Global Clock [15..0] CLK[7..4] Regional Clock Network There are eight regional clock networks RCLK[7..0] in each quadrant of the Arria GX device that are driven by the dedicated CLK[15..12]and CLK[7..0] input pins, by PLL outputs, or by internal logic. The regional clock networks provide the lowest clock delay and skew for logic contained in a single quadrant. The CLK pins symmetrically drive the RCLK networks in a particular quadrant, as shown in Figure 2–48. 2–74 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–48. Regional Clocks CLK[15..12] 11 5 7 RCLK RCLK [31..28] [27..24] Arria GX Transceiver Block RCLK RCLK [3..0] [23..20] 1 CLK[3..0] 2 RCLK RCLK Arria GX [7..4] [19..16] Transceiver Block RCLK RCLK [11..8] [15..12] 8 12 6 CLK[7..4] Dual-Regional Clock Network A single source (CLK pin or PLL output) can generate a dual-regional clock by driving two regional clock network lines in adjacent quadrants (one from each quadrant), which allows logic that spans multiple quadrants to utilize the same low skew clock. The routing of this clock signal on an entire side has approximately the same speed but slightly higher clock skew when compared with a clock signal that drives a single quadrant. Internal logic-array routing can also drive a dual-regional clock. Clock pins and enhanced PLL outputs on the top and bottom can drive horizontal dual-regional clocks. Clock pins and fast PLL outputs on the left and right can drive vertical dual-regional clocks, as shown in Figure 2–49. Corner PLLs cannot drive dual-regional clocks. Altera Corporation 2–75 June 2007 Arria GX Device Handbook, Volume 1 PLLs and Clock Networks Figure 2–49. Dual-Regional Clocks Clock Pins or PLL Clock Outputs Can Drive Dual-Regional Network Clock Pins or PLL Clock Outputs Can Drive CLK[15..12] CLK[15..12] Dual-Regional Network CLK[3..0] CLK[3..0] PLLs PLLs CLK[7..4] CLK[7..4] Combined Resources Within each quadrant, there are 24 distinct dedicated clocking resources consisting of 16 global clock lines and eight regional clock lines. Multiplexers are used with these clocks to form buses to drive LAB row clocks, column IOE clocks, or row IOE clocks. Another multiplexer is used at the LAB level to select three of the six row clocks to feed the ALM registers in the LAB (see Figure 2–50). 2–76 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–50. Hierarchical Clock Networks Per Quadrant Clocks Available to a Quadrant Column I/O Cell or Half-Quadrant IO_CLK[7..0] Global Clock Network [15..0] Clock [23..0] Lab Row Clock [5..0] Regional Clock Network [7..0] Row I/O Cell IO_CLK[7..0] Designers can use the Quartus II software to control whether a clock input pin drives either a global, regional, or dual-regional clock network. The Quartus II software automatically selects the clocking resources if not specified. Clock Control Block Each global clock, regional clock, and PLL external clock output has its own clock control block. The control block has two functions: ■ Clock source selection (dynamic selection for global clocks) ■ Clock power-down (dynamic clock enable/disable) Figures 2–51 through 2–53 show the clock control block for the global clock, regional clock, and PLL external clock output, respectively. Altera Corporation 2–77 June 2007 Arria GX Device Handbook, Volume 1 PLLs and Clock Networks Figure 2–51. Global Clock Control Blocks CLKp Pins PLL Counter 2 2 Outputs CLKn Internal Pin Logic CLKSELECT[1..0] 2 (1) Static Clock Select (2) This multiplexer supports User-Controllable Dynamic Switching Enable/ Disable Internal Logic GCLK Notes to Figure 2–51: (1) These clock select signals can be dynamically controlled through internal logic when the device is operating in user mode. (2) These clock select signals can only be set through a configuration file (SRAM Object File (.sof) or Programmer Object File (.pof)) and cannot be dynamically controlled during user mode operation. Figure 2–52. Regional Clock Control Blocks CLKp CLKn Pin Pin (2) PLL Counter 2 Internal Outputs Logic Static Clock Select (1) Enable/ Disable Internal Logic RCLK Notes to Figure 2–52: (1) These clock select signals can only be set through a configuration file (SOF or POF) and cannot be dynamically controlled during user mode operation. (2) Only the CLKn pins on the top and bottom of the device feed to regional clock select. 2–78 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–53. External PLL Output Clock Control Blocks PLL Counter Outputs (c[5..0]) 6 Static Clock Select (1) Enable/ Disable Internal Logic IOE (2) Internal Logic Static Clock Select (1) PLL_OUT Pin Notes to Figure 2–53: (1) These clock select signals can only be set through a configuration file (SOF or POF) and cannot be dynamically controlled during user mode operation. (2) The clock control block feeds to a multiplexer within the PLL_OUT pin’s IOE. The PLL_OUT pin is a dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control block. For the global clock control block, the clock source selection can be controlled either statically or dynamically. The designer has the option of statically selecting the clock source by using the Quartus II software to set specific configuration bits in the configuration file (SOF or POF) or the designer can control the selection dynamically by using internal logic to drive the multiplexer select inputs. When selecting statically, the clock source can be set to any of the inputs to the select multiplexer. When selecting the clock source dynamically, the designer can either select between two PLL outputs (such as the C0 or C1 outputs from one PLL), between two PLLs (such as the C0/C1 clock output of one PLL or the C0/C1 c1ock output of the other PLL), between two clock pins (such as CLK0 or CLK1), or between a combination of clock pins or PLL outputs. For the regional and PLL_OUT clock control block, the clock source selection can only be controlled statically using configuration bits. Any of the inputs to the clock select multiplexer can be set as the clock source. Altera Corporation 2–79 June 2007 Arria GX Device Handbook, Volume 1 PLLs and Clock Networks The Arria GX clock networks can be disabled (powered down) by both static and dynamic approaches. When a clock net is powered down, all the logic fed by the clock net is in an off-state thereby reducing the overall power consumption of the device. The global and regional clock networks can be powered down statically through a setting in the configuration file (SOF or POF). Clock networks that are not used are automatically powered down through configuration bit settings in the configuration file generated by the Quartus II software. The dynamic clock enable/disable feature allows the internal logic to control power up/down synchronously on GCLK and RCLK nets and PLL_OUT pins. This function is independent of the PLL and is applied directly on the clock network or PLL_OUT pin, as shown in Figures 2–51 through 2–53. Enhanced and Fast PLLs Arria GX devices provide robust clock management and synthesis using up to four enhanced PLLs and four fast PLLs. These PLLs increase performance and provide advanced clock interfacing and clock frequency synthesis. With features such as clock switchover, spread spectrum clocking, reconfigurable bandwidth, phase control, and reconfigurable phase shifting, the Arria GX device’s enhanced PLLs provide designers with complete control of their clocks and system timing. The fast PLLs provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for high-speed differential I/O support. Enhanced and fast PLLs work together with the Aria GX high-speed I/O and advanced clock architecture to provide significant improvements in system performance and bandwidth. 2–80 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture The Quartus II software enables the PLLs and their features without requiring any external devices. Table 2–22 shows the PLLs available for each Arria GX device and their type. Table 2–22. Arria GX Device PLL Availability Notes (1), (2) Fast PLLs Enhanced PLLs Device 12 3 (3) 4 (3) 78 9 (3) 10 (3) 5 6 11 12 EP1AGX20 vv v v EP1AGX35 vv v v EP1AGX50 (4) vv v v v v v v EP1AGX60(5) vv v v v v v v EP1AGX90 vv v v v v v v Notes to Table 2–22: (1) The global or regional clocks in a fast PLL's transceiver block can drive the fast PLL input. A pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL. (2) EP1AGX20C, EP1AGX35C/D, EP1AGX50C and EP1AGX60C/D devices only have two fast PLLs (PLLs 1 and 2), but the connectivity from these two PLLs to the global and regional clock networks remains the same as shown in this table. (3) PLLs 3, 4, 9, and 10 are not available in Arria GX devices. (4) 4 or 8 PLLs are available depending on C or D device and the package option. (5) 4or 8 PLLs are available depending on C, D, or E device option. Altera Corporation 2–81 June 2007 Arria GX Device Handbook, Volume 1 PLLs and Clock Networks Table 2–23 shows the enhanced PLL and fast PLL features in Arria GX devices. Table 2–23. Arria GX PLL Features Feature Enhanced PLL Fast PLL Clock multiplication and division m/(n × post-scale counter) (1) m/(n × post-scale counter) (2) Phase shift Down to 125-ps increments (3), (4) Down to 125-ps increments (3), (4) Clock switchover vv (5) PLL reconfiguration vv Reconfigurable bandwidth vv Spread spectrum clocking v Programmable duty cycle vv Number of internal clock outputs 6 4 Number of external clock outputs Three differential/six single-ended (6) Number of feedback clock inputs One single-ended or differential (7), (8) Notes to Table 2–23: (1) For enhanced PLLs, m, n range from 1 to 256 and post-scale counters range from 1 to 512 with 50% duty cycle. (2) For fast PLLs, m, and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4. (3) The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8. (4) For degree increments, Arria GX devices can shift all output frequencies in increments of at least 45. Smaller degree increments are possible depending on the frequency and divide parameters. (5) Arria GX fast PLLs only support manual clock switchover. (6) Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data channel to generate txclkout. (7) If the feedback input is used, you will lose one (or two, if f is differential) external clock output pin. BIN (8) Every Arria GX device has at least two enhanced PLLs with one single-ended or differential external feedback input per PLL. 2–82 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–54 shows a top-level diagram of the Arria GX device and PLL floorplan. Figure 2–54. PLL Locations CLK[15..12] 11 5 FPLL7CLK 7 1 CLK[3..0] 2 PLLs FPLL8CLK 8 12 6 CLK[7..4] Figures 2–55 and 2–56 shows the global and regional clocking from the fast PLL outputs and the side clock pins. The connections to the global and regional clocks from the fast PLL outputs, internal drivers, and the CLK pins on the left side of the device are shown in Table 2–24. Altera Corporation 2–83 June 2007 Arria GX Device Handbook, Volume 1 PLLs and Clock Networks Figure 2–55. Global and Regional Clock Connections from Center Clock Pins and Fast PLL Outputs Note (1) C0 CLK0 C1 Fast CLK1 PLL 1 C2 C3 Logic Array Signal Input To Clock Network C0 Fast C1 CLK2 PLL 2 C2 CLK3 C3 RCLK0 RCLK2 RCLK4 RCLK6 GCLK0 GCLK2 RCLK1 RCLK3 RCLK5 RCLK7 GCLK1 GCLK3 Note to Figure 2–55: (1) The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL. 2–84 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–56. Global and Regional Clock Connections from Corner Clock Pins and Fast PLL Outputs Notes (1) RCLK1 RCLK3 RCLK0 RCLK2 C0 C1 Fast PLL 7 C2 C3 C0 C1 Fast PLL 8 C2 C3 RCLK4 RCLK6 GCLK0 GCLK2 RCLK5 RCLK7 GCLK1 GCLK3 Notes to Figure 2–56: (1) The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL. Table 2–24. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part 1 of 3) Left Side Global & Regional Clock Network Connectivity Clock pins CLK0p vv v v CLK1p vvvv CLK2p vv v v CLK3p vvvv Drivers from internal logic GCLKDRV0 vv Altera Corporation 2–85 June 2007 Arria GX Device Handbook, Volume 1 CLK0 CLK1 CLK2 CLK3 RCLK0 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 PLLs and Clock Networks Table 2–24. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part 2 of 3) Left Side Global & Regional Clock Network Connectivity GCLKDRV1 vv GCLKDRV2 vv GCLKDRV3 vv RCLKDRV0 vv RCLKDRV1 vv RCLKDRV2 vv RCLKDRV3 vv RCLKDRV4 vv RCLKDRV5 vv RCLKDRV6 vv RCLKDRV7 vv PLL 1 outputs c0 vv vv vv c1 vv vv vv c2 vvvv vv c3 vv vv vv PLL 2 outputs c0 vv vv vv c1 vv vv vv c2 vv vv vv c3 vvvv vv PLL 7 outputs c0 vv v v c1 vv v v c2 vv v v c3 vv v v PLL 8 outputs c0 vv v v c1 vv v v 2–86 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 CLK0 CLK1 CLK2 CLK3 RCLK0 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 Arria GX Architecture Table 2–24. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part 3 of 3) Left Side Global & Regional Clock Network Connectivity c2 vv v v c3 vv v v Altera Corporation 2–87 June 2007 Arria GX Device Handbook, Volume 1 CLK0 CLK1 CLK2 CLK3 RCLK0 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 PLLs and Clock Networks Figure 2–57 shows the global and regional clocking from enhanced PLL outputs and top and bottom CLK pins. Figure 2–57. Global and Regional Clock Connections from Top and Bottom Clock Pins and Enhanced PLL Outputs Note (1) CLK15 CLK13 CLK12 CLK14 PLL5_FB PLL11_FB PLL 11 PLL 5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 PLL5_OUT[2..0]p PLL11_OUT[2..0]p PLL5_OUT[2..0]n PLL11_OUT[2..0]n RCLK31 RCLK30 RCLK29 RCLK28 RCLK27 Regional RCLK26 Clocks RCLK25 RCLK24 G15 G14 G13 G12 Global Clocks G4 G5 G6 G7 RCLK8 Regional RCLK9 Clocks RCLK10 RCLK11 RCLK12 RCLK13 RCLK14 RCLK15 PLL12_OUT[2..0]p PLL6_OUT[2..0]p PLL12_OUT[2..0]n PLL6_OUT[2..0]n c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 PLL 12 PLL 6 PLL12_FB PLL6_FB CLK4 CLK6 CLK5 CLK7 Note to Figure 2–57: (1) If the design uses the feedback input, you will lose one (or two if FBIN is differential) external clock output pin. 2–88 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture The connections to the global and regional clocks from the top clock pins and enhanced PLL outputs are shown in Table 2–25. The connections to the clocks from the bottom clock pins are shown in Table 2–26. Table 2–25. Global and Regional Clock Connections from Top Clock Pins and Enhanced PLL Outputs (Part 1 of 2) Top Side Global and Regional Clock Network Connectivity Clock pins CLK12p vvv v v CLK13p vvv v v CLK14p vvvv v CLK15p vvv v v CLK12n vv v CLK13n vv v CLK14n vvv CLK15n vv v Drivers from internal logic GCLKDRV0 v GCLKDRV1 v GCLKDRV2 v GCLKDRV3 v RCLKDRV0 vv RCLKDRV1 vv RCLKDRV2 vv RCLKDRV3 vv RCLKDRV4 vv RCLKDRV5 vv RCLKDRV6 vv RCLKDRV7 vv Enhanced PLL5 outputs c0 vvv v v c1 vvv v v Altera Corporation 2–89 June 2007 Arria GX Device Handbook, Volume 1 DLLCLK CLK12 CLK13 CLK14 CLK15 RCLK24 RCLK25 RCLK26 RCLK27 RCLK28 RCLK29 RCLK30 RCLK31 PLLs and Clock Networks Table 2–25. Global and Regional Clock Connections from Top Clock Pins and Enhanced PLL Outputs (Part 2 of 2) Top Side Global and Regional Clock Network Connectivity c2 vvvv v c3 vvv v v c4 v vvv v c5 v v vvv Enhanced PLL 11 outputs c0 vv v v c1 vv v v c2 vv v v c3 vv v v c4 vvv v c5 v vvv Table 2–26. Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL Outputs (Part 1 of 2) Bottom Side Global and Regional Clock Network Connectivity Clock pins CLK4p vv v v v CLK5p vv v v v CLK6p vvvv v CLK7p v vvvv CLK4n vvv CLK5n vv v CLK6n vv v CLK7n vvv Drivers from internal logic GCLKDRV0 v GCLKDRV1 v 2–90 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 DLLCLK DLLCLK CLK4 CLK12 CLK5 CLK13 CLK6 CLK14 CLK7 CLK15 RCLK8 RCLK24 RCLK9 RCLK25 RCLK10 RCLK26 RCLK11 RCLK27 RCLK12 RCLK28 RCLK13 RCLK29 RCLK14 RCLK30 RCLK15 RCLK31 Arria GX Architecture Table 2–26. Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL Outputs (Part 2 of 2) Bottom Side Global and Regional Clock Network Connectivity GCLKDRV2 v GCLKDRV3 v RCLKDRV0 vv RCLKDRV1 vv RCLKDRV2 vv RCLKDRV3 vv RCLKDRV4 vv RCLKDRV5 vv RCLKDRV6 vv RCLKDRV7 vv Enhanced PLL 6 outputs c0 vv v v v c1 vv v v v c2 vvvv v c3 v vvvv c4 vvvvv c5 v vvv v Enhanced PLL 12 outputs c0 vv v v c1 vv v v c2 vv v v c3 vvvv c4 vv vv c5 vvv v Altera Corporation 2–91 June 2007 Arria GX Device Handbook, Volume 1 DLLCLK CLK4 CLK5 CLK6 CLK7 RCLK8 RCLK9 RCLK10 RCLK11 RCLK12 RCLK13 RCLK14 RCLK15 PLLs and Clock Networks Enhanced PLLs Arria GX devices contain up to four enhanced PLLs with advanced clock management features. These features include support for external clock feedback mode, spread-spectrum clocking, and counter cascading. Figure 2–58 shows a diagram of the enhanced PLL. Figure 2–58. Arria GX Enhanced PLL Note (1) From Adjacent PLL VCO Phase Selection Selectable at Each Post-Scale PLL Output Port Counters Clock Switchover Spread /c0 Circuitry Phase Frequency Spectrum Detector INCLK[3..0] /c1 4 4 Global Clocks /n 8 Charge Loop PFD VCO /c2 Pump Filter 6 8 Regional Global or Clocks Regional /c3 Clock 6 I/O Buffers (3) /c4 /m (2) /c5 Lock Detect to I/O or general FBIN & Filter routing VCO Phase Selection Shaded Portions of the Affecting All Outputs PLL are Reconfigurable Notes to Figure 2–58: (1) Each clock source can come from any of the four clock pins that are physically located on the same side of the device as the PLL. (2) If the feedback input is used, you will lose one (or two, if FBIN is differential) external clock output pin. (3) Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs. (4) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL. Fast PLLs Arria GX devices contain up to four fast PLLs with high-speed serial interfacing ability. The fast PLLs offer high-speed outputs to manage the high-speed differential I/O interfaces. Figure 2–59 shows a diagram of the fast PLL. 2–92 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–59. Arria GX Device Fast PLL Post-Scale Counters VCO Phase Selection Selectable at each PLL Clock Output Port Phase Switchover Frequency diffioclk0 (2) Circuitry (4) Global or Detector load_en0 (3) regional clock (1) ÷c0 8 Charge Loop load_en1 (3) ÷n PFD VCO ÷k ÷c1 4 Pump Filter Clock diffioclk1 (2) Input 4 Global clocks ÷c2 4 8 Global or Regional clocks regional clock (1) ÷c3 ÷m 8 to DPA block Shaded Portions of the PLL are Reconfigurable Notes to Figure 2–59: (1) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL. (2) In high-speed differential I/O support mode, this high-speed PLL clock feeds the serializer/deserializer (SERDES) circuitry. Arria GX devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode. (3) This signal is a differential I/O SERDES control signal. (4) Arria GX fast PLLs only support manual clock switchover. f Refer to the PLLs in Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook for more information about enhanced and fast PLLs. Refer to “High-Speed Differential I/O with DPA Support” on page 2–117 for more information on high-speed differential I/O support. The Arria GX IOEs provide many features, including: I/O Structure ■ Dedicated differential and single-ended I/O buffers ■ 3.3-V, 64-bit, 66-MHz PCI compliance ■ 3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance ■ Joint Test Action Group (JTAG) boundary-scan test (BST) support ■ On-chip driver series termination ■ On-chip termination for differential standards ■ Programmable pull-up during configuration ■ Output drive strength control ■ Tri-state buffers ■ Bus-hold circuitry ■ Programmable pull-up resistors ■ Programmable input and output delays ■ Open-drain outputs ■ DQ and DQS I/O pins ■ Double data rate (DDR) registers Altera Corporation 2–93 June 2007 Arria GX Device Handbook, Volume 1 I/O Structure The IOE in Arria GX devices contains a bidirectional I/O buffer, six registers, and a latch for a complete embedded bidirectional single data rate or DDR transfer. Figure 2–60 shows the Arria GX IOE structure. The IOE contains two input registers (plus a latch), two output registers, and two output enable registers. The design can use both input registers and the latch to capture DDR input and both output registers to drive DDR outputs. Additionally, the design can use the output enable (OE) register for fast clock-to-output enable timing. The negative edge-clocked OE register is used for DDR SDRAM interfacing. The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins. 2–94 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–60. Arria GX IOE Structure Logic Array OE Register OE DQ OE Register DQ Output Register Output A DQ CLK Output Register DQ Output B Input Register DQ Input A Input B Input Latch Input Register DQ DQ ENA The IOEs are located in I/O blocks around the periphery of the Arria GX device. There are up to four IOEs per row I/O block and four IOEs per column I/O block. The row I/O blocks drive row, column, or direct link interconnects. The column I/O blocks drive column interconnects. Altera Corporation 2–95 June 2007 Arria GX Device Handbook, Volume 1 I/O Structure Figure 2–61 shows how a row I/O block connects to the logic array. Figure 2–61. Row I/O Block Connection to the Interconnect R4 & R24 C4 Interconnect Interconnects I/O Block Local Interconnect 32 Data & Control Signals from Logic Array (1) 32 LAB Horizontal I/O Block io_dataina[3..0] io_datainb[3..0] Direct Link Direct Link Interconnect Interconnect to Adjacent LAB Horizontal I/O to Adjacent LAB Block Contains io_clk[7:0] up to Four IOEs LAB Local Interconnect Note to Figure 2–61: (1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals io_sclr/spreset[3..0]. 2–96 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–62 shows how a column I/O block connects to the logic array. Figure 2–62. Column I/O Block Connection to the Interconnect 32 Data & Control Signals Vertical I/O from Logic Array (1) Vertical I/O Block Block Contains up to Four IOEs 32 IO_dataina[3..0] io_clk[7..0] IO_datainb[3..0] I/O Block Local Interconnect R4 & R24 Interconnects LAB LAB LAB LAB Local C4 & C16 Interconnect Interconnects Note to Figure 2–62: (1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals io_sclr/spreset[3..0]. Altera Corporation 2–97 June 2007 Arria GX Device Handbook, Volume 1 I/O Structure There are 32 control and data signals that feed each row or column I/O block. These control and data signals are driven from the logic array. The row or column IOE clocks, io_clk[7..0], provide a dedicated routing resource for low-skew, high-speed clocks. I/O clocks are generated from global or regional clocks (refer to “PLLs and Clock Networks” on page 2–73). Figure 2–63 illustrates the signal paths through the I/O block. Figure 2–63. Signal Path Through the I/O Block Row or Column To Other io_clk[7..0] IOEs io_dataina To Logic Array io_datainb oe ce_in io_oe ce_out io_ce_in Control aclr/apreset IOE io_ce_out Signal Selection sclr/spreset io_aclr From Logic clk_in Array io_sclr clk_out io_clk io_dataouta io_dataoutb Each IOE contains its own control signal selection for the following control signals: oe, ce_in, ce_out, aclr/apreset, sclr/spreset, clk_in, and clk_out. Figure 2–64 illustrates the control signal selection. 2–98 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–64. Control Signal Selection per IOE Note (1) Dedicated I/O Clock [7..0] io_oe Local Interconnect io_sclr Local Interconnect io_aclr Local Interconnect io_ce_out Local Interconnect io_ce_in Local Interconnect io_clk clk_out ce_out sclr/spreset Local Interconnect clk_in ce_in aclr/apreset oe Notes to Figure 2–64: (1) Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oe can be global signals even though their control selection multiplexers are not directly fed by the ioe_clk[7..0] signals. The ioe_clk signals can drive the I/O local interconnect, which then drives the control selection multiplexers. In normal bidirectional operation, designers can use the input register for input data requiring fast setup times. The input register can have its own clock input and clock enable separate from the OE and output registers. The output register can be used for data requiring fast clock-to-output performance. Designers can use the OE register for fast clock-to-output enable timing. The OE and output register share the same clock source and the same clock enable source from local interconnect in the associated LAB, dedicated I/O clocks, and the column and row interconnects. Figure 2–65 shows the IOE in bidirectional configuration. Altera Corporation 2–99 June 2007 Arria GX Device Handbook, Volume 1 I/O Structure Figure 2–65. Arria GX IOE in Bidirectional I/O Configuration Note (1) ioe_clk[7..0] Column, Row, or Local Interconnect oe OE Register DQ clkout ENA OE Register CLRN/PRN t Delay CO ce_out V CCIO PCI Clamp (2) V CCIO Programmable aclr/apreset Pull-Up Resistor Chip-Wide Reset On-Chip Output Register Termination Output DQ Pin Delay sclr/spreset Drive Strength Control ENA Open-Drain Output CLRN/PRN Input Pin to Logic Array Delay Bus-Hold Input Pin to Circuit Input Register Delay Input Register clkin DQ ce_in ENA CLRN/PRN Notes to Figure 2–65: (1) All input signals to the IOE can be inverted at the IOE. (2) The optional PCI clamp is only available on column I/O pins. 2–100 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture The Arria GX device IOE includes programmable delays that can be activated to ensure input IOE register-to-logic array register transfers, input pin-to-logic array register transfers, or output IOE register-to-pin transfers. A path in which a pin directly drives a register can require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinational logic may not require the delay. Programmable delays exist for decreasing input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can program these delays to automatically minimize setup time while providing a zero hold time. Programmable delays can increase the register-to-pin delays for output and/or output enable registers. Programmable delays are no longer required to ensure zero hold times for logic array register-to-IOE register transfers. The Quartus II Compiler can create the zero hold time for these transfers. Table 2–27 shows the programmable delays for Arria GX devices. Table 2–27. Arria GX Programmable Delay Chain Programmable Delays Quartus II Logic Option Input pin to logic array delay Input delay from pin to internal cells Input pin to input register delay Input delay from pin to input register Output pin delay Delay from output register to output pin Output enable register t delay Delay to output enable pin CO The IOE registers in Arria GX devices share the same source for clear or preset. The designer can program preset or clear for each individual IOE. The designer can also program the registers to power up high or low after configuration is complete. If programmed to power up low, an asynchronous clear can control the registers. If programmed to power up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of another device’s active-low input upon power-up. If one register in an IOE uses a preset or clear signal then all registers in the IOE must use that same signal if they require preset or clear. Additionally, a synchronous reset signal is available to the designer for the IOE registers. Double Data Rate I/O Pins Arria GX devices have six registers in the IOE, which support DDR interfacing by clocking data on both positive and negative clock edges. The IOEs in Arria GX devices support DDR inputs, DDR outputs, and bidirectional DDR modes. When using the IOE for DDR inputs, the two input registers clock double rate input data on alternating edges. An Altera Corporation 2–101 June 2007 Arria GX Device Handbook, Volume 1 I/O Structure input latch is also used in the IOE for DDR input acquisition. The latch holds the data that is present during the clock high times, allowing both bits of data to be synchronous with the same clock edge (either rising or falling). Figure 2–66 shows an IOE configured for DDR input. Figure 2–67 shows the DDR input timing diagram. Figure 2–66. Arria GX IOE in DDR Input I/O Configuration Note (1) ioe_clk[7..0] VCCIO Column, Row, PCI Clamp (4) or Local To DQS Logic Block (3) Interconnect DQS Local Bus (2) VCCIO Programmable Pull-Up Resistor On-Chip Input Pin to Input RegisterDelay Termination sclr/spreset Input Register DQ clkin ENA CLRN/PRN ce_in Bus-Hold Circuit aclr/apreset Chip-Wide Reset Latch Input Register DQ DQ ENA ENA CLRN/PRN CLRN/PRN Notes to Figure 2–66: (1) All input signals to the IOE can be inverted at the IOE. (2) This signal connection is only allowed on dedicated DQ function pins. (3) This signal is for dedicated DQS function pins only. (4) The optional PCI clamp is only available on column I/O pins. 2–102 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–67. Input Timing Diagram in DDR Mode Data at B0 A0 B1 A1 B2 A2 B3 A3 B4 input pin CLK A0 A1 A2 A3 Input To Logic Array B0 B1 B2 B3 When using the IOE for DDR outputs, the two output registers are configured to clock two data paths from ALMs on rising clock edges. These output registers are multiplexed by the clock to drive the output pin at a ×2 rate. One output register clocks the first bit out on the clock high time, while the other output register clocks the second bit out on the clock low time. Figure 2–68 shows the IOE configured for DDR output. Figure 2–69 shows the DDR output timing diagram. Altera Corporation 2–103 June 2007 Arria GX Device Handbook, Volume 1 I/O Structure Figure 2–68. Arria GX IOE in DDR Output I/O Configuration Notes (1), (2) ioe_clk[7..0] Column, Row, or Local Interconnect oe OE Register DQ clkout ENA CLRN/PRN OE Register ce_out t Delay CO aclr/apreset V CCIO PCI Clamp (3) Chip-Wide Reset OE Register V CCIO DQ Programmable sclr/spreset Pull-Up Used for Resistor ENA DDR, DDR2 CLRN/PRN SDRAM Output Register DQ On-Chip Output Termination Pin Delay ENA clk CLRN/PRN Drive Strength Control Open-Drain Output Output Register DQ Bus-Hold ENA Circuit CLRN/PRN Notes to Figure 2–68: (1) All input signals to the IOE can be inverted at the IOE. (2) The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an inverter at the OE register data port. (3) The optional PCI clamp is only available on column I/O pins. 2–104 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–69. Output Timing Diagram in DDR Mode CLK A1 A2 A3 A4 From Internal Registers B1 B2 B3 B4 DDR output B1 A1 B2 A2 B3 A3 B4 A4 The Arria GX IOE operates in bidirectional DDR mode by combining the DDR input and DDR output configurations. The negative-edge-clocked OE register holds the OE signal inactive until the falling edge of the clock to meet DDR SDRAM timing requirements. External RAM Interfacing In addition to the six I/O registers in each IOE, Arria GX devices also have dedicated phase-shift circuitry for interfacing with external memory interfaces, including DDR and DDR2 SDRAM, and SDR SDRAM. In every Arria GX device, the I/O banks at the top (banks 3 and 4) and bottom (banks 7 and 8) of the device support DQ and DQS signals with DQ bus modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table 2–28 shows the number of DQ and DQS buses that are supported per device. Table 2–28. DQS and DQ Bus Mode Support (Part 1 of 2) Note (1) Number of Number of Number of Number of Device Package ×16/×18 ×32/×36 ×4 Groups ×8/×9 Groups Groups Groups EP1AGX20 484-pin FineLine BGA 2 0 0 0 EP1AGX35 484-pin FineLine BGA 2 0 0 0 780-pin FineLine BGA 18 8 4 0 EP1AGX50/60 484-pin FineLine BGA 2 0 0 0 780-pin FineLine BGA 18 8 4 0 1,152-pin FineLine BGA 36 18 8 4 Altera Corporation 2–105 June 2007 Arria GX Device Handbook, Volume 1 I/O Structure Table 2–28. DQS and DQ Bus Mode Support (Part 2 of 2) Note (1) Number of Number of Number of Number of Device Package ×16/×18 ×32/×36 ×4 Groups ×8/×9 Groups Groups Groups EP1AGX90 1,152-pin FineLine BGA 36 18 8 4 Note to Table 2–28: (1) Numbers are preliminary until devices are available. A compensated delay element on each DQS pin automatically aligns input DQS synchronization signals with the data window of their corresponding DQ data signals. The DQS signals drive a local DQS bus in the top and bottom I/O banks. This DQS bus is an additional resource to the I/O clocks and is used to clock DQ input registers with the DQS signal. The Arria GX device has two phase-shifting reference circuits, one on the top and one on the bottom of the device. The circuit on the top controls the compensated delay elements for all DQS pins on the top. The circuit on the bottom controls the compensated delay elements for all DQS pins on the bottom. Each phase-shifting reference circuit is driven by a system reference clock, which must have the same frequency as the DQS signal. Clock pins CLK[15..12]p feed the phase circuitry on the top of the device and clock pins CLK[7..4]p feed the phase circuitry on the bottom of the device. In addition, PLL clock outputs can also feed the phase-shifting reference circuits. Figure 2–70 shows the phase-shift reference circuit control of each DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device. 2–106 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Figure 2–70. DQS Phase-Shift Circuitry Notes (1), (2) From PLL 5 (4) CLK[15..12]p (3) DQS DQS DQS DQS Pin Pin Pin Pin DQS Δt Δt Phase-Shift Δt Δt Circuitry to IOE to IOE to IOE to IOE Notes to Figure 2–70: (1) There are up to 18 pairs of DQS pins available on the top or the bottom of the Arria GX device. There are up to 10 pairs on the right side and 8 pairs on the left side of the DQS phase-shift circuitry. (2) The “t” module represents the DQS logic block. (3) Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed the phase circuitry on the bottom of the device. Designers can also use a PLL clock output as a reference clock to the phase shift circuitry. (4) Designers can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS phase-shift circuitry on the bottom of the device. These dedicated circuits combined with enhanced PLL clocking and phase-shift ability provide a complete hardware solution for interfacing to high-speed memory. f For more information about external memory interfaces, refer to the External Memory Interfaces in Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook. Programmable Drive Strength The output buffer for each Arria GX device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL, LVCMOS, SSTL, and HSTL standards have several levels of drive strength that the designer can control. The default setting used in the Quartus II software is the maximum current strength setting that is used to achieve maximum I/O performance. For all I/O standards, the minimum setting is the lowest drive strength that guarantees the I /I of the standard. Using OH OL minimum settings provides signal slew rate control to reduce system noise and signal overshoot. Altera Corporation 2–107 June 2007 Arria GX Device Handbook, Volume 1 I/O Structure Table 2–29 shows the possible settings for the I/O standards with drive strength control. Table 2–29. Programmable Drive Strength Note (1) / I Current Strength I / I Current Strength I OH OL OH OL I/O Standard Setting (mA) for Column Setting (mA) for Row I/O I/O Pins Pins 3.3-V LVTTL 24, 20, 16, 12, 8, 4 12, 8, 4 3.3-V LVCMOS 24, 20, 16, 12, 8, 4 8, 4 2.5-V LVTTL/LVCMOS 16, 12, 8, 4 12, 8, 4 1.8-V LVTTL/LVCMOS 12, 10, 8, 6, 4, 2 8, 6, 4, 2 1.5-V LVCMOS 8, 6, 4, 2 4, 2 SSTL-2 Class I 12, 8 12, 8 SSTL-2 Class II 24, 20, 16 16 SSTL-18 Class I 12, 10, 8, 6, 4 10, 8, 6, 4 SSTL-18 Class II 20, 18, 16, 8 - HSTL-18 Class I 12, 10, 8, 6, 4 12, 10, 8, 6, 4 HSTL-18 Class II 20, 18, 16 - HSTL-15 Class I 12, 10, 8, 6, 4 8, 6, 4 HSTL-15 Class II 20, 18, 16 - Note to Table 2–29: (1) The Quartus II software default current setting is the maximum setting for each I/O standard. Open-Drain Output Arria GX devices provide an optional open-drain (equivalent to an open collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (for example, interrupt and write enable signals) that can be asserted by any of several devices. Bus Hold Each Arria GX device I/O pin provides an optional bus-hold feature. The bus-hold circuitry can hold the signal on an I/O pin at its last-driven state. Since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not needed to hold a signal level when the bus is tri-stated. 2–108 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture The bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. The designer can select this feature individually for each I/O pin. The bus-hold output drives no higher than V to prevent CCIO overdriving signals. If the bus-hold feature is enabled, the programmable pull-up option cannot be used. Disable the bus-hold feature when the I/O pin has been configured for differential signals. The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately 7 kΩ to pull the signal level to the last-driven state. This information is provided for each V voltage level. The bus-hold CCIO circuitry is active only after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. f Refer to the DC & Switching Characteristics chapter in volume 1 of the Arria GX Device Handbook for the specific sustaining current driven through this resistor and overdrive current used to identify the next-driven input level. Programmable Pull-Up Resistor Each Arria GX device I/O pin provides an optional programmable pull- up resistor during user mode. If a designer enables this feature for an I/O pin, the pull-up resistor (typically 25 kΩ) holds the output to the V CCIO level of the output pin’s bank. Advanced I/O Standard Support The Arria GX device IOEs support the following I/O standards: ■ 3.3-V LVTTL/LVCMOS ■ 2.5-V LVTTL/LVCMOS ■ 1.8-V LVTTL/LVCMOS ■ 1.5-V LVCMOS ■ 3.3-V PCI ■ 3.3-V PCI-X mode 1 ■ LVDS ■ LVPECL (on input and output clocks only) ■ Differential 1.5-V HSTL class I and II ■ Differential 1.8-V HSTL class I and II ■ Differential SSTL-18 class I and II ■ Differential SSTL-2 class I and II ■ 1.2-V HSTL class I and II ■ 1.5-V HSTL class I and II Altera Corporation 2–109 June 2007 Arria GX Device Handbook, Volume 1 I/O Structure ■ 1.8-V HSTL class I and II ■ SSTL-2 class I and II ■ SSTL-18 class I and II Table 2–30 describes the I/O standards supported by Arria GX devices. Table 2–30. Arria GX Supported I/O Standards Input Reference Output Supply Board Termination I/O Standard Type Voltage (V ) (V) Voltage (V ) (V) Voltage (V ) (V) REF CCIO TT LVTTL Single-ended - 3.3 - LVCMOS Single-ended - 3.3 - 2.5 V Single-ended - 2.5 - 1.8 V Single-ended - 1.8 - 1.5-V LVCMOS Single-ended - 1.5 - 3.3-V PCI Single-ended - 3.3 - 3.3-V PCI-X mode 1 Single-ended - 3.3 - LVDS Differential - 2.5 (3) - LVPECL (1) Differential - 3.3 - HyperTransport technology Differential - 2.5 (3) - Differential 1.5-V HSTL Differential 0.75 1.5 0.75 class I and II (2) Differential 1.8-V HSTL Differential 0.90 1.8 0.90 class I and II (2) Differential SSTL-18 class I Differential 0.90 1.8 0.90 and II (2) Differential SSTL-2 class I Differential 1.25 2.5 1.25 and II (2) 1.2-V HSTL(4) Voltage-referenced 0.6 1.2 0.6 1.5-V HSTL class I and II Voltage-referenced 0.75 1.5 0.75 1.8-V HSTL class I and II Voltage-referenced 0.9 1.8 0.9 SSTL-18 class I and II Voltage-referenced 0.90 1.8 0.90 SSTL-2 class I and II Voltage-referenced 1.25 2.5 1.25 Notes to Table 2–30: (1) This I/O standard is only available on input and output column clock pins. (2) This I/O standard is only available on input clock pins and DQS pins in I/O banks 3, 4, 7, and 8, and output clock pins in I/O banks 9, 10, 11, and 12. (3) V is 3.3 V when using this I/O standard in input and output column clock pins (in I/O banks 3, 4, 7, 8, 9, 10, CCIO 11, and 12). (4) 1.2-V HSTL is only supported in I/O banks 4, 7, and 8. 2–110 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture f For more information about the I/O standards supported by Arria GX I/O banks, refer to the Selectable I/O Standards in Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook. Arria GX devices contain six I/O banks and four enhanced PLL external clock output banks, as shown in Figure 2–71. The two I/O banks on the left of the device contain circuitry to support source-synchronous, high-speed differential I/O for LVDS inputs and outputs. These banks support all Arria GX I/O standards except PCI or PCI-X I/O pins, and SSTL-18 class II and HSTL outputs. The top and bottom I/O banks support all single-ended I/O standards. Additionally, enhanced PLL external clock output banks allow clock output capabilities such as differential support for SSTL and HSTL. Altera Corporation 2–111 June 2007 Arria GX Device Handbook, Volume 1 I/O Structure Figure 2–71. Arria GX I/O Banks Notes (1), (2) DQS ×8 DQS ×8 DQS ×8 DQS ×8 DQS ×8 DQS ×8 DQS ×8 DQS ×8 DQS ×8 PLL11 PLL5 PLL7 VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4 Bank 3 Bank 11 Bank 9 Bank 4 Transmitter: Bank 13 This I/O bank supports LVDS This I/O bank supports LVDS Receiver: Bank 13 and LVPECL standards and LVPECL standards for input clock REFCLK: Bank 13 for input clock operations. Differential HSTL operation. Differential HSTL and and differential SSTL standards differential SSTL standards are are supported for both input supported for both input and output and output operations. (3) operations. (3) I/O Banks 3, 4, 9, and 11 support all single-ended I/O standards for both input and output operations. All differential I/O standards are supported for both input and output operations at I/O banks 9 and 11. I/O banks 1 & 2 support LVTTL, LVCMOS, 2.5 V, 1.8 V, 1.5 V, SSTL-2, SSTL-18 class I, LVDS, pseudo-differential SSTL-2 and pseudo-differential Transmitter: Bank 14 PLL1 SSTL-18 class I standards for both input and output Receiver: Bank 14 operations. HSTL, SSTL-18 class II, REFCLK: Bank 14 pseudo-differential HSTL and pseudo-differential PLL2 SSTL-18 class II standards are only supported for input operations. (4) I/O banks 7, 8, 10 and 12 support all single-ended I/O standards for both input and output operations. All differential I/O standards are supported for both input and output operations at I/O banks 10 and 12. This I/O bank supports LVDS This I/O bank supports LVDS and LVPECL standards for input clock operation. and LVPECL standards for input clock Differential HSTL and differential operation. Differential HSTL and differential Transmitter: Bank 15 SSTL standards are supported SSTL standards are supported Receiver: Bank 15 for both input and output operations. (3) for both input and output operations. (3) REFCLK: Bank 15 Bank 8 Bank 12 Bank 7 Bank 10 VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8 VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7 PLL8 PLL12 PLL6 DQS ×8 DQS ×8 DQS ×8 DQS ×8 DQS ×8 DQS ×8 DQS ×8 DQS ×8 DQS ×8 Notes to Figure 2–71: (1) Figure 2–71 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical representation only. (2) Depending on the size of the device, different device members have different numbers of V groups. Refer to the REF pin list and the Quartus II software for exact locations. (3) Banks 9 through 12 are enhanced PLL external clock output banks. (4) Horizontal I/O banks feature SERDES and DPA circuitry for high speed differential I/O standards. See the High Speed Differential I/O Interfaces in Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook for more information about differential I/O standards. Each I/O bank has its own VCCIO pins. A single device can support 1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different V level independently. Each bank also has dedicated VREF pins to CCIO support the voltage-referenced standards (such as SSTL-2). Each I/O bank can support multiple standards with the same V for CCIO input and output pins. Each bank can support one V voltage level. For REF example, when V is 3.3 V, a bank can support LVTTL, LVCMOS, and CCIO 3.3-V PCI for inputs and outputs. 2–112 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 VREF0B2 VREF2B2 VREF3B2 VREF4B2 VREF0B1 VREF1B1 VREF2B1 VREF3B1 VREF4B1 VREF1B2 Bank 1 Bank 2 Arria GX Architecture On-Chip Termination Arria GX devices provide differential (for the LVDS technology I/O standard) and series on-chip termination to reduce reflections and maintain signal integrity. There is no calibration support for these on-chip termination resistors. On-chip termination simplifies board design by minimizing the number of external termination resistors required. Termination can be placed inside the package, eliminating small stubs that can still lead to reflections. Arria GX devices provide two types of termination: ■ Differential termination (R ) D ■ Series termination (R ) S Table 2–31 shows the Arria GX on-chip termination support per I/O bank. Table 2–31. On-Chip Termination Support by I/O Banks (Part 1 of 2) Top and Bottom Banks On-Chip Termination Support I/O Standard Support Left Bank (1, 2) (3, 4, 7, 8) 3.3-V LVTTL vv 3.3-V LVCMOS vv 2.5-V LVTTL vv 2.5-V LVCMOS vv 1.8-V LVTTL vv 1.8-V LVCMOS vv 1.5-V LVTTL vv 1.5-V LVCMOS Series termination vv SSTL-2 class I and II vv SSTL-18 class I v v SSTL-18 class II v 1.8-V HSTL class I vv 1.8-V HSTL class II v 1.5-V HSTL class I vv 1.2-V HSTL v Altera Corporation 2–113 June 2007 Arria GX Device Handbook, Volume 1 I/O Structure Table 2–31. On-Chip Termination Support by I/O Banks (Part 2 of 2) Top and Bottom Banks On-Chip Termination Support I/O Standard Support Left Bank (1, 2) (3, 4, 7, 8) LVDS v Differential termination (1) HyperTransport technology v Note to Table 2–31: (1) Clock pins CLK1 and CLK3, and pins FPLL[7..8]CLK do not support differential on-chip termination. Clock pins CLK0 and CLK2, do support differential on-chip termination. Clock pins in the top and bottom banks (CLK[4..7, 12..15]) do not support differential on-chip termination. Differential On-Chip Termination Arria GX devices support internal differential termination with a nominal resistance value of 100 Ω for LVDS input receiver buffers. LVPECL input signals (supported on clock pins only) require an external termination resistor. Differential on-chip termination is supported across the full range of supported differential data rates as shown in the High-Speed I/O Specifications section of the DC & Switching Characteristics chapter in volume 1 of the Arria GX Device Handbook. f For more information about differential on-chip termination, refer to the High-Speed Differential I/O Interfaces with DPA in Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook. For more information about tolerance specifications for differential on-chip termination, refer to the DC & Switching Characteristics chapter in volume 1 of the Arria GX Device Handbook. On-Chip Series Termination Arria GX devices support driver impedance matching to provide the I/O driver with controlled output impedance that closely matches the impedance of the transmission line. As a result, reflections can be significantly reduced. Arria GX devices support on-chip series termination for single-ended I/O standards with typical R values of 25 S and 50 Ω . Once matching impedance is selected, current drive strength is no longer selectable. Table 2–31 shows the list of output standards that support on-chip series termination. f For more information about series on-chip termination supported by Arria GX devices, refer to the Selectable I/O Standards in Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook. 2–114 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture f For more information about tolerance specifications for on-chip termination without calibration, refer to the DC & Switching Characteristics chapter in volume 1 of the Arria GX Device Handbook. MultiVolt I/O Interface The Arria GX architecture supports the MultiVolt™ I/O interface feature that allows Arria GX devices in all packages to interface with systems of different supply voltages. The Arria GX VCCINT pins must always be connected to a 1.2-V power supply. With a 1.2-V V level, input pins CCINT are 1.2-, 1.5-, 1.8-, 2.5-, and 3.3-V tolerant. The VCCIO pins can be connected to either a 1.2-, 1.5-, 1.8-, 2.5-, or 3.3-V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as the power supply (for example, when VCCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems). The Arria GX VCCPD power pins must be connected to a 3.3-V power supply. These power pins are used to supply the pre-driver power to the output buffers, which increases the performance of the output pins. The VCCPD pins also power configuration input pins and JTAG input pins. Table 2–32 summarizes Arria GX MultiVolt I/O support. Table 2–32. Arria GX MultiVolt I/O Support Note (1) Input Signal (V) Output Signal (V) V (V) CCIO 1.2 1.5 1.8 2.5 3.3 1.2 1.5 1.8 2.5 3.3 5.0 1.2 (4) v (2) v (2) v (2) v (2) v (4) 1.5 (4) vv v (2) v (2) v (3) v 1.8 (4) v vv (2) v (2) v (3) v (3) v 2.5 (4) vv v (3) v (3) v (3) v 3.3 (4) v vv (3) v (3) v (3) v (3) vv Notes to Table 2–32: (1) To drive inputs higher than V but less than 4.0 V, disable the PCI clamping diode and select CCIO the Allow LVTTL and LVCMOS input levels to overdrive input buffer option in the Quartus II software. (2) The pin current may be slightly higher than the default value. You must verify that the driving device’s V maximum and V minimum voltages do not violate the applicable Arria GX V OL OH IL maximum and V minimum voltage specifications. IH (3) Although V specifies the voltage necessary for the Arria GX device to drive out, a receiving CCIO device powered at a different level can still interface with the Arria GX device if it has inputs that tolerate the V value. CCIO (4) Arria GX devices support 1.2-V HSTL. They do not support 1.2-V LVTTL and 1.2-V LVCMOS. Altera Corporation 2–115 June 2007 Arria GX Device Handbook, Volume 1 I/O Structure The TDO and nCEO pins are powered by V of the bank that they reside. CCIO TDO is in I/O bank 4 and nCEO is in I/O bank 7. Ideally, the V supplies CC for the I/O buffers of any two connected pins are at the same voltage level. This may not always be possible depending on the V level of CCIO TDO and nCEO pins on master devices and the configuration voltage level chosen by V on slave devices. Master and slave devices can be in any CCSEL position in the chain. Master indicates that it is driving out TDO or nCEO to a slave device. For multi-device passive configuration schemes, the nCEO pin of the master device will be driving the nCE pin of the slave device. The VCCSEL pin on the slave device selects which input buffer is used for nCE. When V is logic high, it selects the 1.8-V/1.5-V buffer CCSEL powered by V . When V is logic low it selects the 3.3-V/2.5-V CCIO CCSEL input buffer powered by V . The ideal case is to have the V of the CCPD CCIO nCEO bank in a master device match the V settings for the nCE input CCSEL buffer of the slave device it is connected to, but that may not be possible depending on the application. Table 2–33 contains board design recommendations to ensure that nCEO can successfully drive nCE for all power supply combinations. Table 2–33. Board Design Recommendations for nCEO and nCE Input Buffer Power Arria GX nCEO V Voltage Level in I/O Bank 7 CCIO nCE Input Buffer Power in I/O Bank 3 V = 3.3 V V = 2.5 V V = 1.8 V V = 1.5 V V = 1.2 V CCIO CCIO CCIO CCIO CCIO VCCSEL high v(1), (2) v (3), (4) v (5) vv (V Bank 3 = 1.5 V) CCIO VCCSEL high Level shifter v (1), (2) v (3), (4) vv required (V Bank 3 = 1.8 V) CCIO Level shifter Level shifter VCCSEL low (nCE powered v v (4) v (6) required required by V = 3.3 V) CCPD Notes to Table 2–33: (1) Input buffer is 3.3-V tolerant. (2) The nCEO output buffer meets V (MIN) = 2.4 V. OH (3) Input buffer is 2.5-V tolerant. (4) The nCEO output buffer meets V (MIN) = 2.0 V. OH (5) Input buffer is 1.8-V tolerant. (6) An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal. For JTAG chains, the TDO pin of the first device will be driving the TDI pin of the second device in the chain. The V input on JTAG input I/O CCSEL cells (TCK, TMS, TDI, and TRST) is internally hardwired to GND selecting the 3.3-V/2.5-V input buffer powered by V . The ideal case is to have CCPD the V of the TDO bank from the first device to match the V CCIO CCSEL 2–116 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture settings for TDI on the second device, but that may not be possible depending on the application. Table 2–34 contains board design recommendations to ensure proper JTAG chain operation. Table 2–34. Supported TDO/TDI Voltage Combinations Arria GX TDO V Voltage Level in I/O Bank 4 CCIO TDI Input Device Buffer Power V = 3.3 V V = 2.5 V V = 1.8 V V = 1.5 V V = 1.2 V CCIO CCIO CCIO CCIO CCIO Always v (1) v (2) v (3) Level shifter Level shifter Arria GX V (3.3 V) required required CCPD VCC = 3.3 V Level shifter Level shifter v (1) v (2) v (3) required required VCC = 2.5 V Level shifter Level shifter v (1), (4) v (2) v (3) Non- required required Arria GX VCC = 1.8 V Level shifter Level shifter v (1), (4) v (2), (5) v required required VCC = 1.5 V v (1), (4) v (2), (5) v (6) vv Notes to Table 2–34: (1) The TDO output buffer meets V (MIN) = 2.4 V. OH (2) The TDO output buffer meets V (MIN) = 2.0 V. OH (3) An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal. (4) Input buffer must be 3.3-V tolerant. (5) Input buffer must be 2.5-V tolerant. (6) Input buffer must be 1.8-V tolerant. Arria GX devices contain dedicated circuitry for supporting differential High-Speed standards at speeds up to 840 megabits per second (Mbps). The LVDS Differential I/O differential I/O standards are supported in the Arria GX device. In addition, the LVPECL I/O standard is supported on input and output with DPA clock pins on the top and bottom I/O banks. Support The high-speed differential I/O circuitry supports the following high-speed I/O interconnect standards and applications: ■ SPI-4 Phase 2 (POS-PHY Level 4) ■ SFI-4 ■ Parallel RapidIO™ standard There are two dedicated high-speed PLLs (PLL1 and PLL2) in the EP1AGX20 and EP1AGX35 devices and up to four dedicated high-speed PLLs (PLL1, PLL2, PLL7, and PLL8) in the EP1AGX50, EP1AGX60, and EP1AGX90 devices to multiply reference clocks and drive high-speed differential SERDES channels in I/O banks 1 and 2. Altera Corporation 2–117 June 2007 Arria GX Device Handbook, Volume 1 High-Speed Differential I/O with DPA Support Tables 2–35 through 2–39 show the number of channels that each Fast PLL can clock in each of the Arria GX devices. In Tables 2–35 through 2–39 the first row for each transmitter or receiver provides the maximum number of channels that each fast PLL can drive in its adjacent I/O bank (I/O Bank 1 or I/O Bank 2). The second row shows the maximum number of channels that each fast PLL can drive in both I/O banks (I/O Bank 1 ® and I/O Bank 2). For example, in the 780-pin FineLine BGA EP1AGX20 device, PLL 1 can drive a maximum of 16 transmitter channels in I/O bank 2 or a maximum of 29 transmitter channels in I/O banks 1 and 2. The Quartus II software can also merge receiver and transmitter PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive both the maximum numbers of receiver and transmitter channels. 1 For more details, refer to the “Differential Pin Placement Guidelines” section in the High-Speed Differential I/O Interfaces with DPA in Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook. Table 2–35. EP1AGX20 Device Differential Channels Note (1) Center Fast PLLs Package Transmitter/Receiver Total Channels PLL1 PLL2 Transmitter 29 16 13 13 16 484-pin FineLine BGA Receiver 31 17 14 14 17 Transmitter 29 16 13 13 16 780-pin FineLine GBA Receiver 31 17 14 14 17 Note to Table 2–35: (1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels. 2–118 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Table 2–36. EP1AGX35 Device Differential Channels Note (1) Center Fast PLLs Package Transmitter/Receiver Total Channels PLL1 PLL2 Transmitter 29 16 13 13 16 484-pin FineLine BGA Receiver 31 17 14 14 17 Transmitter 29 16 13 13 16 780-pin FineLine BGA Receiver 31 17 14 14 17 Note to Table 2–36: (1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels. Table 2–37. EP1AGX50 Device Differential Channels Note (1) Center Fast PLLs Corner Fast PLLs Total Package Transmitter/Receiver Channels PLL1 PLL2 PLL7 PLL8 Transmitter 29 16 13 — — 13 16 — — 484-pin FineLine BGA Receiver 31 17 14 — — 14 17 — — Transmitter 29 16 13 — — 13 16 — — 780-pin FineLine BGA Receiver 31 17 14 — — 14 17 — — Transmitter 42 21 21 21 21 21 21 — — 1,152-pin FineLine BGA Receiver 42 21 21 21 21 21 21 — — Note to Table 2–37: (1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels. Altera Corporation 2–119 June 2007 Arria GX Device Handbook, Volume 1 High-Speed Differential I/O with DPA Support Table 2–38. EP1AGX60 Device Differential Channels Note (1) Center Fast PLLs Corner Fast PLLs Total Package Transmitter/Receiver Channels PLL1 PLL2 PLL7 PLL8 Transmitter 29 16 13 — — 13 16 — — 484-pin FineLine BGA Receiver 31 17 14 — — 14 17 — — Transmitter 29 16 13 — — 13 16 — — 780-pin FineLine BGA Receiver 31 17 14 — — 14 17 — — Transmitter 42 212121 21 21 21 — — 1,152-pin FineLine BGA Receiver 42 21 21 21 21 21 21 — — Note to Table 2–38: (1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels. Table 2–39. EP1AGX90 Device Differential Channels Note (1) Center Fast PLLs Corner Fast PLLs Total Package Transmitter/Receiver Channels PLL1 PLL2 PLL7 PLL8 Transmitter 45 232223 22 22 23 — — 1,152-pin FineLine BGA Receiver 47 23 24 23 24 24 23 — — Note to Table 2–39: (1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels. 2–120 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture Dedicated Circuitry with DPA Support Arria GX devices support source-synchronous interfacing with LVDS signaling at up to 840 Mbps. Arria GX devices can transmit or receive serial channels along with a low-speed or high-speed clock. The receiving device PLL multiplies the clock by an integer factor W = 1 through 32. The SERDES factor J determines the parallel data width to deserialize from receivers or to serialize for transmitters. The SERDES factor J can be set to 4, 5, 6, 7, 8, 9, or 10 and does not have to equal the PLL clock-multiplication W value. A design using the dynamic phase aligner also supports all of these J factor values. For a J factor of 1, the Arria GX device bypasses the SERDES block. For a J factor of 2, the Arria GX device bypasses the SERDES block, and the DDR input and output registers are used in the IOE. Figure 2–72 shows the block diagram of the Arria GX transmitter channel. Figure 2–72. Arria GX Transmitter Channel Data from R4, R24, C4, or direct link interconnect + Up to 840 Mbps – 10 10 Dedicated Local Transmitter Interconnect Interface diffioclk refclk Fast load_en PLL Regional or global clock Each Arria GX receiver channel features a DPA block for phase detection and selection, a SERDES, a synchronizer, and a data realigner circuit. You can bypass the dynamic phase aligner without affecting the basic source- synchronous operation of the channel. In addition, you can dynamically switch between using the DPA block or bypassing the block via a control signal from the logic array. Altera Corporation 2–121 June 2007 Arria GX Device Handbook, Volume 1 High-Speed Differential I/O with DPA Support Figure 2–73 shows the block diagram of the Arria GX receiver channel. Figure 2–73. GX Receiver Channel Data to R4, R24, C4, or direct link interconnect + Up to 840 Mbps DQ – Data Realignment Circuitry 10 data retimed_data Dedicated Receiver DPA Synchronizer Interface DPA_clk Eight Phase Clocks 8 diffioclk refclk Fast load_en PLL Regional or global clock An external pin or global or regional clock can drive the fast PLLs, which can output up to three clocks: two multiplied high-speed clocks to drive the SERDES block and/or external pin, and a low-speed clock to drive the logic array. In addition, eight phase-shifted clocks from the VCO can feed to the DPA circuitry. f For more information about fast PLL, see the PLLs in Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook. The eight phase-shifted clocks from the fast PLL feed to the DPA block. The DPA block selects the closest phase to the center of the serial data eye to sample the incoming data. This allows the source-synchronous circuitry to capture incoming data correctly regardless of the channel-to-channel or clock-to-channel skew. The DPA block locks to a phase closest to the serial data phase. The phase-aligned DPA clock is used to write the data into the synchronizer. The synchronizer sits between the DPA block and the data realignment and SERDES circuitry. Since every channel utilizing the DPA block can have a different phase selected to sample the data, the synchronizer is needed to synchronize the data to the high-speed clock domain of the data realignment and the SERDES circuitry. 2–122 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Arria GX Architecture For high-speed source synchronous interfaces such as POS-PHY 4 and the Parallel RapidIO standard, the source synchronous clock rate is not a byte- or SERDES-rate multiple of the data rate. Byte alignment is necessary for these protocols since the source synchronous clock does not provide a byte or word boundary since the clock is one half the data rate, not one eighth. The Arria GX device’s high-speed differential I/O circuitry provides dedicated data realignment circuitry for user-controlled byte boundary shifting. This simplifies designs while saving ALM resources. The designer can use an ALM-based state machine to signal the shift of receiver byte boundaries until a specified pattern is detected to indicate byte alignment. Fast PLL and Channel Layout The receiver and transmitter channels are interleaved such that each I/O bank on the left side of the device has one receiver channel and one transmitter channel per LAB row. Figure 2–74 shows the fast PLL and channel layout in the EP1AGX20C, EP1AGX35C/D, EP1AGX50C/D and EP1AGX60C/D devices. Figure 2–75 shows the fast PLL and channel layout in EP1AGX60E and EP1AGX90E devices. Figure 2–74. Fast PLL and Channel Layout in the EP1AGX20C, EP1AGX35C/D, EP1AGX50C/D, EP1AGX60C/D Devices Note (1) 4 LVDS DPA Clock Clock Quadrant Quadrant 4 2 Fast PLL 1 Fast PLL 2 2 Quadrant Quadrant LVDS DPA Clock Clock 4 Note to Figure 2–74: (1) See Table 2–35 for the number of channels each device supports. Altera Corporation 2–123 June 2007 Arria GX Device Handbook, Volume 1 Document Revision History Figure 2–75. Fast PLL and Channel Layout in the EP1AGX60E and EP1AGX90E Devices Note (1) Fast PLL 7 2 4 LVDS DPA Quadrant Quadrant Clock Clock 4 2 Fast PLL 1 Fast PLL 2 2 LVDS DPA Quadrant Quadrant Clock Clock 4 2 Fast PLL 8 Note to Figure 2–75: (1) See Tables 2–35 through 2–39 for the number of channels each device supports. Table 2–40 shows the revision history for this chapter. Document Revision History Table 2–40. Document Revision History Date and Document Changes Made Summary of Changes Version June 2007, Added GIGE information. — v1.1 May 2007 Initial release. — v1.0 2–124 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 3. Configuration and Testing AGX51003-1.1 TM All Arria GX devices provide Joint Test Action Group (JTAG) IEEE Std. 1149.1 boundary-scan test (BST) circuitry that complies with the IEEE Std. JTAG Boundary- 1149.1. JTAG boundary-scan testing can be performed either before or after, but not during configuration. Arria GX devices can also use the Scan Support ® JTAG port for configuration with the Quartus II software or hardware using either jam files (.jam) or jam byte-code files (.jbc). Arria GX devices support I/O element (IOE) standard setting reconfiguration through the JTAG BST chain. The JTAG chain can update the I/O standard for all input and output pins any time before or during user-mode through the CONFIG_IO instruction. Designers can use this capability for JTAG testing before configuration when some of the Arria GX pins drive or receive from other devices on the board using voltage-referenced standards. Since the Arria GX device may not be configured before JTAG testing, the I/O pins may not be configured for appropriate electrical standards for chip-to-chip communication. Programming these I/O standards via JTAG allows designers to fully test I/O connections to other devices. A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK, and one optional pin, TRST. The TCK pin has an internal weak pull-down resistor, while the TDI, TMS, and TRST pins have weak internal pull-up resistors. The JTAG input pins are powered by the 3.3-V V pins. The TDO output pin is powered by the V power supply in CCPD CCIO I/O bank 4. Arria GX devices also use the JTAG port to monitor the logic operation of ® the device with the SignalTap II embedded logic analyzer. Arria GX devices support the JTAG instructions shown in Table 3–1. ® 1 Arria GX, Stratix , Stratix II, Stratix GX, Stratix II GX, ® Cyclone II, and Cyclone devices must be within the first eight devices in a JTAG chain. All of these devices have the same JTAG controller. If any of these devices appears after the 8th device in the JTAG chain, they will fail configuration. This does not affect SignalTap II embedded logic analysis. Altera Corporation 3–1 June 2007 Configuration and Testing Table 3–1. Arria GX JTAG Instructions (Part 1 of 2) JTAG Instruction Instruction Code Description SAMPLE/PRELOAD 00 0000 0101 Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. Also used by the SignalTap II embedded logic analyzer. EXTEST (1) 00 0000 1111 Allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. BYPASS 11 1111 1111 Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation. 00 0000 0111 USERCODE Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. IDCODE 00 0000 0110 Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. HIGHZ (1) 00 0000 1011 Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins. 00 0000 1010 CLAMP (1) Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding I/O pins to a state defined by the data in the boundary-scan register. ICR instructions — Used when configuring an Arria GX device via the JTAG port with a USB-Blaster™, MasterBlaster™, ByteBlasterMV™, or ByteBlaster II download cable, or when using a .jam or .jbc via TM an embedded processor or JRunner . PULSE_NCONFIG 00 0000 0001 Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected. CONFIG_IO (2) 00 0000 1101 Allows configuration of I/O standards through the JTAG chain for JTAG testing. Can be executed before, during, or after configuration. Stops configuration if executed during configuration. Once issued, the CONFIG_IO instruction will hold nSTATUS low to reset the configuration device. nSTATUS is held low until the IOE configuration register is loaded and the TAP controller state machine transitions to the UPDATE_DR state. 3–2 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 IEEE Std. 1149.1 JTAG Boundary-Scan Support Table 3–1. Arria GX JTAG Instructions (Part 2 of 2) JTAG Instruction Instruction Code Description Notes to Table 3–1: (1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST. (2) For more information about using the CONFIG_IO instruction, refer to the MorphIO: An I/O Reconfiguration Solution for Altera Devices White Paper. The Arria GX device instruction register length is 10 bits and the USERCODE register length is 32 bits. Table 3–2 and Table 3–3 show the boundary-scan register length and device IDCODE information for Arria GX devices. Table 3–2. Arria GX Boundary-Scan Register Length Device Boundary-Scan Register Length EP1AGX20 1320 EP1AGX35 1320 EP1AGX50 1668 EP1AGX60 1668 EP1AGX90 2016 Table 3–3. 2-Bit Arria GX Device IDCODE Device IDCODE (32 Bits) Version (4 Bits) Part Number (16 Bits) Manufacturer LSB (1 Bit) Identity (11 Bits) EP1AGX20 0000 0010 0001 0010 0001 000 0110 1110 1 EP1AGX35 0000 0010 0001 0010 0001 000 0110 1110 1 EP1AGX50 0000 0010 0001 0010 0010 000 0110 1110 1 EP1AGX60 0000 0010 0001 0010 0010 000 0110 1110 1 EP1AGX90 0000 0010 0001 0010 0011 000 0110 1110 1 Altera Corporation 3–3 June 2007 Arria GX Device Handbook, Volume 1 Configuration and Testing Arria GX devices feature the SignalTap II embedded logic analyzer, which SignalTap II monitors design operation over a period of time through the IEEE Std. Embedded Logic 1149.1 (JTAG) circuitry. A designer can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is Analyzer ® particularly important for advanced packages, such as FineLine BGA (FBGA) packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured. The logic, circuitry, and interconnects in the Arria GX architecture are Configuration ® configured with CMOS SRAM elements. Altera FPGAs are reconfigurable and every device is tested with a high coverage production test program so the designer does not have to perform fault testing and can instead focus on simulation and design verification. Arria GX devices are configured at system power-up with data stored in an Altera configuration device or provided by an external controller (for ® example, a MAX II device or microprocessor). Arria GX devices can be configured using the fast passive parallel (FPP), active serial (AS), passive serial (PS), passive parallel asynchronous (PPA), and JTAG configuration schemes. Each Arria GX device has an optimized interface that allows microprocessors to configure it serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat Arria GX devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy. In addition to the number of configuration methods supported, Arria GX devices also offer the decompression, and remote system upgrade features. The decompression feature allows Arria GX FPGAs to receive a compressed configuration bitstream and decompress this data in real-time, reducing storage requirements and configuration time. The remote system upgrade feature allows real-time system upgrades from remote locations of Arria GX designs. For more information, refer to “Configuration Schemes” on page 3–6. Operating Modes The Arria GX architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called configuration. During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. Together, the configuration and initialization processes are called command mode. Normal device operation is called user mode. 3–4 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Configuration SRAM configuration elements allow designers to reconfigure Arria GX devices in-circuit by loading new configuration data into the device. With real-time reconfiguration, the device is forced into command mode with a device pin. The configuration process loads different configuration data, re-initializes the device, and resumes user-mode operation. Designers can perform in-field upgrades by distributing new configuration files either within the system or remotely. PORSEL is a dedicated input pin used to select power-on reset (POR) delay times of 12 ms or 100 ms during power up. When the PORSEL pin is connected to ground, the POR time is 100 ms. When the PORSEL pin is connected to V , the POR time is 12 ms. CC The nIO_PULLUP pin is a dedicated input that chooses whether the internal pull-up resistors on the user I/O pins and dual-purpose configuration I/O pins (nCSO, ASDO, DATA[7..0], nWS, nRS, RDYnBSY, nCS, CS, RUnLU, PGM[2..0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLR) are on or off before and during configuration. A logic high (1.5, 1.8, 2.5, 3.3 V) turns off the weak internal pull-up resistors, while a logic low turns them on. Arria GX devices also offer a new power supply, V , which must be CCPD connected to 3.3 V in order to power the 3.3-V/2.5-V buffer available on the configuration input pins and JTAG pins. V applies to all the JTAG CCPD input pins (TCK, TMS, TDI, and TRST) and the following configuration pins: nCONFIG, DCLK (when used as an input), nIO_PULLUP, DATA[7..0], RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR. The V CCSEL pin allows the V setting (of the banks where the configuration inputs CCIO reside) to be independent of the voltage required by the configuration inputs. Therefore, when selecting the V voltage, designers do not CCIO have to take the VIL and VIH levels driven to the configuration inputs into consideration. The configuration input pins, nCONFIG, DCLK (when used as an input), nIO_PULLUP, RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR, have a dual buffer design: a 3.3-V/2.5-V input buffer and a 1.8-V/1.5-V input buffer. The V input pin selects which input buffer CCSEL is used. The 3.3-V/2.5-V input buffer is powered by V , while the CCPD 1.8-V/1.5-V input buffer is powered by V . CCIO V is sampled during power-up. Therefore, the V setting cannot CCSEL CCSEL change on-the-fly or during a reconfiguration. The V input buffer is CCSEL powered by V and must be hard-wired to V or ground. A logic CCINT CCPD high V connection selects the 1.8-V/1.5-V input buffer, and a logic CCSEL low selects the 3.3-V/2.5-V input buffer. V should be set to comply CCSEL with the logic levels driven out of the configuration device or MAX II microprocessor. Altera Corporation 3–5 June 2007 Arria GX Device Handbook, Volume 1 Configuration and Testing If the design must support configuration input voltages of 3.3 V/2.5 V, set to a logic low. The designer can set the V voltage of the I/O V CCSEL CCIO bank that contains the configuration inputs to any supported voltage. If the design must support configuration input voltages of 1.8 V/1.5 V, set V to a logic high and the V of the bank that contains the CCSEL CCIO configuration inputs to 1.8 V/1.5 V. f For more information about multi-volt support, including information about using TDO and nCEO in multi-volt systems, refer to the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. Configuration Schemes Designers can load the configuration data for an Arria GX device with one of five configuration schemes (refer to Table 3–4), chosen on the basis of the target application. Designers can use a configuration device, intelligent controller, or the JTAG port to configure an Arria GX device. A configuration device can automatically configure an Arria GX device at system power-up. Multiple Arria GX devices can be configured in any of the five configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device. Arria GX FPGAs offer the following: ■ Configuration data decompression to reduce configuration file storage ■ Remote system upgrades for remotely updating Arria GX designs Table 3–4 summarizes which configuration features can be used in each configuration scheme. f Refer to the Configuring Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook for more information about configuration schemes in Arria GX devices. 3–6 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Configuration Table 3–4. Arria GX Configuration Features Configuration Remote System Configuration Method Decompression Scheme Upgrade FPP MAX II device or microprocessor and v(1) v flash device Enhanced configuration device v(2) v AS Serial configuration device vv(3) PS MAX II device or microprocessor and vv flash device Enhanced configuration device vv Download cable (4) v — PPA MAX II device or microprocessor and — v flash device JTAG Download cable (4) —— MAX II device or microprocessor and —— flash device Notes for Table 3–4 (1) In these modes, the host system must send a DCLK that is 4× the data rate. (2) The enhanced configuration device decompression feature is available, while the Arria GX decompression feature is not available. (3) Only remote update mode is supported when using the AS configuration scheme. Local update mode is not supported. (4) The supported download cables include the Altera USB-Blaster universal serial bus (USB) port download cable, MasterBlaster serial/USB communications cable, ByteBlaster II parallel port download cable, and the ByteBlasterMV parallel port download cable. Device Configuration Data Decompression Arria GX FPGAs support decompression of configuration data, which saves configuration memory space and time. This feature allows the designer to store compressed configuration data in configuration devices or other memory, and transmit this compressed bitstream to Arria GX FPGAs. During configuration, the Arria GX FPGA decompresses the bitstream in real time and programs its SRAM cells. Arria GX FPGAs support decompression in the FPP (when using a MAX II device or microprocessor and flash memory), AS, and PS configuration schemes. Decompression is not supported in the PPA configuration scheme nor in JTAG-based configuration. Altera Corporation 3–7 June 2007 Arria GX Device Handbook, Volume 1 Configuration and Testing Remote System Upgrades Shortened design cycles, evolving standards, and system deployments in remote locations are difficult challenges faced by system designers. Arria GX devices can help effectively deal with these challenges with their inherent re programmability and dedicated circuitry to perform remote system updates. Remote system updates help deliver feature enhancements and bug fixes without costly recalls, reduce time to market, and extend product life. Arria GX FPGAs feature dedicated remote system upgrade circuitry to ® facilitate remote system updates. Soft logic (Nios processor or user logic) implemented in the Arria GX device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides error status information. This dedicated remote system upgrade circuitry avoids system downtime and is the critical component for successful remote system upgrades. Remote system configuration is supported in the following Arria GX configuration schemes: FPP, AS, PS, and PPA. Remote system configuration can also be implemented in conjunction with Arria GX features such as real-time decompression of configuration data for efficient field upgrades. f Refer to the Remote System Upgrades with Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook for more information about remote configuration in Arria GX devices. Configuring Arria GX FPGAs with JRunner The JRunner software driver configures Altera FPGAs, including Arria GX FPGAs, through the ByteBlaster II or ByteBlasterMV cables in JTAG mode. The programming input file supported is in Raw Binary File (.rbf) format. JRunner also requires a Chain Description File (.cdf) generated by the Quartus II software. JRunner is targeted for embedded JTAG configuration. The source code is developed for the Windows NT operating system (OS), but can be customized to run on other platforms. f For more information about the JRunner software driver, refer to the JRunner Software Driver: An Embedded Solution for PLD JTAG Configuration White Paper and the source files on the Altera web site (www.altera.com). 3–8 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Configuration Programming Serial Configuration Devices with SRunner A serial configuration device can be programmed in-system by an TM external microprocessor using SRunner . SRunner is a software driver developed for embedded serial configuration device programming that can be easily customized to fit into different embedded systems. SRunner reads a raw programming data file (.rpd) and writes to serial configuration devices. The serial configuration device programming time using SRunner is comparable to the programming time when using the Quartus II software. f For more information about SRunner, refer to the SRunner: An Embedded Solution for Serial Configuration Device Programming White Paper and the source code on the Altera web site. f For more information on programming serial configuration devices, refer to the Serial Configuration Devices (EPCS1, EPCS4, and EPCS64) Data Sheet in the Configuration Handbook. Configuring Arria GX FPGAs with the MicroBlaster Driver The MicroBlaster™ software driver supports a raw binary file (RBF) programming input file and is ideal for embedded FPP or PS configuration. The source code is developed for the Windows NT operating system, although it can be customized to run on other operating systems. f For more information about the MicroBlaster software driver, refer to the Configuring the MicroBlaster Fast Passive Parallel Software Driver White Paper or the Configuring the MicroBlaster Passive Serial Software Driver White Paper on the Altera web site. PLL Reconfiguration The phase-locked loops (PLLs) in the Arria GX device family support reconfiguration of their multiply, divide, VCO-phase selection, and bandwidth selection settings without reconfiguring the entire device. Designers can use either serial data from the logic array or regular I/O pins to program the PLL's counter settings in a serial chain. This option provides considerable flexibility for frequency synthesis, allowing real-time variation of the PLL frequency and delay. The rest of the device is functional while reconfiguring the PLL. f Refer to the PLLs in Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook for more information about Arria GX PLLs. Altera Corporation 3–9 June 2007 Arria GX Device Handbook, Volume 1 Configuration and Testing Arria GX devices include a diode-connected transistor for use as a Temperature temperature sensor in power management. This diode is used with an Sensing Diode external digital thermometer device such as a MAX1617A or MAX1619 from MAXIM Integrated Products. These devices steer bias current through the Arria GX diode, measuring forward voltage and converting this reading to temperature in the form of an eight-bit signed number (seven bits plus one sign bit). The external device's output represents the junction temperature of the Arria GX device and can be used for intelligent power management. The diode requires two pins (tempdiodep and tempdioden) on the Arria GX device to connect to the external temperature-sensing device, as shown in Figure 3–1. The temperature sensing diode is a passive element and therefore can be used before the Arria GX device is powered. Figure 3–1. External Temperature-Sensing Diode Arria GX Device Temperature-Sensing Device tempdiodep tempdioden Table 3–5 shows the specifications for bias voltage and current of the Arria GX temperature sensing diode. Table 3–5. Temperature-Sensing Diode Electrical Characteristics Parameter Minimum Typical Maximum Unit IBIAS high 80 100 120 μA IBIAS low 8 10 12 μA VBP - VBN 0.3 — 0.9 V VBN — 0.7 — V Series resistance — — 3 Ω 3–10 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 Automated Single Event Upset (SEU) Detection The temperature-sensing diode works for the entire operating range, as shown in Figure 3–2. Figure 3–2. Temperature vs. Temperature-Sensing Diode Voltage 0.95 0.90 100 μA Bias Current 0.85 10 μA Bias Current 0.80 0.75 0.70 Voltage (Across Diode) 0.65 0.60 0.55 0.50 0.45 0.40 –55 –30 –5 20 45 70 95 120 Temperature (˚C) Arria GX devices offer on-chip circuitry for automated checking of single Automated event upset (SEU) detection. Some applications that require the device to Single Event operate error free at high elevations or in close proximity to Earth's North or South Pole will require periodic checks to ensure continued data Upset (SEU) integrity. The error detection cyclic redundancy check (CRC) feature Detection controlled by the Device and Pin Options dialog box in the Quartus II software uses a 32-bit CRC circuit to ensure data reliability and is one of the best options for mitigating SEU. Designers can implement the error detection CRC feature with existing circuitry in Arria GX devices, eliminating the need for external logic. Arria GX devices compute CRC during configuration. The Arria GX device checks the computed-CRC against an automatically computed CRC during normal operation. The CRC_ERROR pin reports a soft error when configuration SRAM data is corrupted, triggering device reconfiguration. Altera Corporation 3–11 June 2007 Arria GX Device Handbook, Volume 1 Configuration and Testing Custom-Built Circuitry Dedicated circuitry is built into Arria GX devices to automatically perform error detection. This circuitry constantly checks for errors in the configuration SRAM cells while the device is in user mode. Designers can monitor one external pin for the error and use it to trigger a reconfiguration cycle. The designer can select the desired time between checks by adjusting a built-in clock divider. Software Interface Beginning with version 7.1 of the Quartus II software, designers can turn on the automated error detection CRC feature in the Device and Pin Options dialog box. This dialog box allows the designer to enable the feature and set the internal frequency of the CRC between 400 kHz to 50 MHz. This controls the rate that the CRC circuitry verifies the internal configuration SRAM bits in the Arria GX FPGA. f For more information on CRC, refer to AN 357: Error Detection Using CRC in Altera FPGAs. Table 3–6 shows the revision history for this chapter. Document Revision History Table 3–6. Document Revision History Date and Document Changes Made Summary of Changes Version June 2007, v1.1 Deleted Signal Tap II information from — Table 3–1. May 2007, v1.0 Initial Release — 3–12 Altera Corporation Arria GX Device Handbook, Volume 1 June 2007 4. DC & Switching Characteristics AGX51004-1.1 Arria™ GX devices are offered in both commercial and industrial grades. Operating Both commercial and industrial devices are offered in -6 speed grade only. Conditions Tables 4–1 through 4–37 provide information on absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for Arria GX devices. Absolute Maximum Ratings Table 4–1 contains the absolute maximum ratings for the Arria GX device family. Table 4–1. Arria GX Device Absolute Maximum Ratings Notes (1), (2), (3) Symbol Parameter Conditions Minimum Maximum Unit V Supply voltage With respect to ground –0.5 1.8 V CCINT V Supply voltage With respect to ground –0.5 4.6 V CCIO V Supply voltage With respect to ground –0.5 4.6 V CCPD V –0.5 4.6 V DC input voltage (4) I I DC output current, per pin –25 40 mA OUT T Storage temperature No bias –65 150 C STG T Junction temperature BGA packages under bias –55 125 C J Notes to Table 4–1: (1) See the Operating Requirements for Altera Devices Data Sheet for more information. (2) Conditions beyond those listed in Table 4–1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply. (4) During transitions, the inputs may overshoot to the voltage shown in Table 4–2 based upon the input duty cycle. The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. Altera Corporation 4–1 June 2007 Operating Conditions Table 4–2. Maximum Duty Cycles in Voltage Transitions Note (1) Maximum Duty Cycles Symbol Parameter Condition (%) V Maximum duty cycles V = 4.0 V 100 I I in voltage transitions V = 4.1 V 90 I V = 4.2 V 50 I V = 4.3 V 30 I V = 4.4 V 17 I V = 4.5 V 10 I Note to Table 4–2: (1) During transition, the inputs may overshoot to the voltages shown based on the input duty cycle. The duty cycle case is equivalent to 100% duty cycle. Recommended Operating Conditions Table 4–3 contains the Arria GX device family recommended operating conditions. Table 4–3. Arria GX Device Recommended Operating Conditions (Part 1 of 2) Note (1) Symbol Parameter Conditions Minimum Maximum Unit V Supply voltage for internal logic Rise time ≤ 100 ms (3) 1.15 1.25 V CCINT and input buffers V Supply voltage for output Rise time ≤ 100 ms (3), (6) 3.135 3.465 V CCIO buffers, 3.3-V operation (3.00) (3.60) Supply voltage for output Rise time ≤ 100 ms (3) 2.375 2.625 V buffers, 2.5-V operation Supply voltage for output Rise time ≤ 100 ms (3) 1.71 1.89 V buffers, 1.8-V operation Supply voltage for output Rise time ≤ 100 ms (3) 1.425 1.575 V buffers, 1.5-V operation Supply voltage for output Rise time ≤ 100 ms (3) 1.15 1.25 V buffers, 1.2-V operation V Supply voltage for pre-drivers as 100 μs ≤ rise time ≤ 100 ms (4) 3.135 3.465 V CCPD well as configuration and JTAG I/O buffers. V Input voltage (see Table 4–2) (2), (5) –0.5 4.0 V I V Output voltage 0 V V O CCIO 4–2 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–3. Arria GX Device Recommended Operating Conditions (Part 2 of 2) Note (1) Symbol Parameter Conditions Minimum Maximum Unit T Operating junction temperature For commercial use 0 85 C J For industrial use –40 100 C Notes to Table 4–3: (1) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply. (2) During transitions, the inputs may overshoot to the voltage shown in Table 4–2 based upon the input duty cycle. The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. (3) Maximum V rise time is 100 ms, and V must rise monotonically from ground to V . CC CC CC (4) V must ramp-up from 0 V to 3.3 V within 100 μs to 100 ms. If V is not ramped up within this specified CCPD CCPD time, the Arria GX device will not configure successfully. If the system does not allow for a V ramp-up time of CCPD 100 ms or less, hold nCONFIG low until all power supplies are reliable. (5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V , V , and V CCINT CCPD CCIO are powered. (6) V maximum and minimum conditions for PCI and PCI-X are shown in parentheses. CCIO Transceiver Block Characteristics Tables 4–4 through 4–6 contain transceiver block specifications. Table 4–4. Arria GX Transceiver Block Absolute Maximum Ratings Note (1) Symbol Parameter Conditions Minimum Maximum Units V Transceiver block supply Commercial and –0.5 4.6 V CCA voltage industrial V Transceiver block supply Commercial and –0.5 1.8 V CCP voltage industrial V Transceiver block supply Commercial and –0.5 1.8 V CCR Voltage industrial V Transceiver block supply Commercial and –0.5 1.8 V CCT_B voltage industrial V Transceiver block supply Commercial and –0.5 1.8 V CCL_B voltage industrial V Transceiver block supply Commercial and –0.5 2.4 V CCH_B voltage industrial Note to Tables 4–4: (1) The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is not violated. Altera Corporation 4–3 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Operating Conditions Table 4–5. Arria GX Transceiver Block Operating Conditions Symbol Parameter Conditions Minimum Typical Maximum Units V Transceiver block supply Commercial 3.135 3.3 3.465 V CCA voltage and industrial V Transceiver block supply Commercial 1.15 1.2 1.25 V CCP voltage and industrial V Transceiver block supply Commercial 1.15 1.2 1.25 V CCR voltage and industrial V Transceiver block supply Commercial 1.15 1.2 1.25 V CCT_B voltage and industrial V Transceiver block supply Commercial 1.15 1.2 1.25 V CCL_B voltage and industrial V (2) Transceiver block supply Commercial 1.15 1.2 1.25 V CCH_B voltage and industrial 1.425 1.5 1.575 V RREFB (1) Reference resistor Commercial 2K –1% 2K 2K +1% Ω and industrial Notes to Table 4–5: (1) The DC signal on this pin must be as clean as possible. Ensure that no noise is coupled to this pin. (2) V = 1.2 V for PCI Express (PIPE) mode. V = 1.5 V for Gigabit Ethernet (GIGE) and Serial RapidIO mode CCH_B CCH_B Table 4–6. Arria GX Transceiver Block AC Specification (Part 1 of 4) -6 Speed Grade Commercial and Industrial Symbol / Description Conditions Unit Min Typ Max Reference clock Input reference clock PCI Express (PIPE) 100 MHz frequency GIGE 62.5, 125 MHz Serial RapidIO (1.25 Gbps) 62.5, 78.125, 125, 156.25 MHz Serial RapidIO (2.5 Gbps) 125, 156.25, 250, 312.5 MHz Input reference clock —— 3.3 V frequency Absolute Vmax for a -0.3 — — V REFCLK Pin Rise/Fall time — 0.2 — UI Duty cycle 45 — 55 % Peak to peak differential 200 — 2000 mV input voltage Vid (diff p- p) 4–4 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–6. Arria GX Transceiver Block AC Specification (Part 2 of 4) -6 Speed Grade Commercial and Industrial Symbol / Description Conditions Unit Min Typ Max Spread spectrum 0 to -0.5% 30 — 33 kHz clocking (1) On-chip termination 115 ± 20% Ω resistors Vicm (AC coupled) 1200 ± 5% mV Vicm (DC coupled) (2) PCI Express (PIPE) mode 0.25 — 0.55 V RREFB 2000 +/-1% Ω Transceiver Clocks Calibration block clock 10 - 125 MHz frequency Calibration block 30 - - ns minimum power-down pulse width fixedclk clock 125 ±10% MHz frequency (3) Transceiver block 100 - - ns minimum power-down pulse width Receiver Absolute V for a -- 2.0 V MAX receiver pin (4) Absolute V for a -0.4 - - V MIN receiver pin Maximum peak-to-peak Vicm = 0.85V - - 3.3 V differential input voltage V (diff p-p) ID Minimum peak-to-peak DC Gain = 3 dB 160 - - mV differential input voltage V (diff p-p) ID On-chip termination 100±15% Ω resistors Bandwidth at 2.5 Gbps BW = Med - 35 - MHz Return loss differential 50 MHz to 1.25 GHz (PCI -10 dB mode Express) Altera Corporation 4–5 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Operating Conditions Table 4–6. Arria GX Transceiver Block AC Specification (Part 3 of 4) -6 Speed Grade Commercial and Industrial Symbol / Description Conditions Unit Min Typ Max Return loss common 50 MHz to 1.25 GHz (PCI -6 dB mode Express) Programmable PPM ±62.5, 100, 125, 200, 250, 300, PPM detector (5) 500, 1000 Run length (6) 80 UI Signal detect/loss 65 - 175 mV threshold (7) CDR LTR TIme (8), (9) - - 75 us CDR Minimum T1b (9), 15 - - us (10) LTD lock time (9), (11) 0 100 4000 ns Data lock time from -- 4 us rx_freqlocked (9), (12) Programmable DC gain 0, 3, 6 dB Transmitter Buffer Output Common Mode 580 ± 10% mV voltage (Vocm) On-chip termination 108±10% Ω resistors Typical peak to peak PCI Express (PIPE) 820 mV differential output GIGE, Serial RapidIO 830 mV voltage Vod (diff p-p) Return loss differential 50 MHz to 1.25 GHz (PCI -10 dB mode Express) Return loss common 50 MHz to 1.25 GHz (PCI -6 dB mode Express) Rise time 35 - 65 ps Fall time 35 - 65 ps Intra differential pair V = 800 mV - - 15 ps OD skew Intra-transceiver block - - 100 ps skew (x4) (13) Transmitter PLL Bandwidth at 2.5 Gbps BW = High - 8 - MHz 4–6 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–6. Arria GX Transceiver Block AC Specification (Part 4 of 4) -6 Speed Grade Commercial and Industrial Symbol / Description Conditions Unit Min Typ Max TX PLL lock time from - - 100 us gxb_powerdown deassertion (9), (14) PCS Interface speed per PCI Express (PIPE) 125 MHz mode GIGE 125 MHz Serial RapidIO (2.5 Gbps) 125 MHz Serial RapidIO (1.25 Gbps) 62.5 MHz Digital Reset Pulse Minimum is 2 parallel clock cycles Width Note to Table 4–6: (1) Spread spectrum clocking is allowed only in PCI Express (PIPE) mode if the upstream transmitter and the receiver share the same clock source. (2) The reference clock DC coupling option is only available in PCI Express (PIPE) mode for the HCSL I/O standard. (3) The fixedclk is used in PIPE mode receiver detect circuitry. (4) The device cannot tolerate prolonged operation at this absolute maximum. (5) The rate matcher supports only up to ± 300 PPM for PIPE mode and ± 100 PPM for GIGE mode. (6) This parameter is measured by embedding the run length data in a PRBS sequence. (7) Signal detect threshold detector circuitry is available only in PCI Express (PIPE mode). (8) Time taken for rx_pll_locked to go high from rx_analogreset deassertion. Refer to Figure 4–1. (9) Please refer to protocol characterization documents for lock times specific to the protocols. (10) Time for which the CDR needs to stay in LTR mode after rx_pll_locked is asserted and before rx_locktodata is asserted in manual mode. Refer to Figure 4–1. (11) Time taken to recover valid data from GXB after the rx_locktodata signal is asserted in manual mode. Measurement results are based on PRBS31, for native data rates only. Refer to Figure 4–1. (12) Time taken to recover valid data from GXB after the rx_freqlocked signal goes high in automatic mode. Measurement results are based on PRBS31, for native data rates only. Refer to Figure 4–2. (13) This is applicable only to PCI Express (PIPE) ×4 mode. (14) Time taken to lock TX PLL from gxb_powerdown deassertion. Figure 4–1 shows the lock time parameters in manual mode. Figure 4–2 shows the lock time parameters in automatic mode. 1 LTD = Lock to data LTR = Lock to reference clock Altera Corporation 4–7 June 2007 Preliminary Arria GX Device Handbook, Volume 1 r x_pll_locked Operating Conditions Figure 4–1. Lock Time Parameters for Manual Mode r x_analogreset CDR status LTR LTD r x_locktodata Invalid Data Valid data r x_dataout CDR LTR Time LTD lock time CDR Minimum T1b Figure 4–2. Lock Time Parameters for Automatic Mode LTR LTD CDR status r x_freqlocked Valid data Invalid data r x_dataout Data lock time from rx_freqlocked 4–8 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Figure 4–3 and Figure 4–4 show differential receiver input and transmitter output waveforms, respectively. Figure 4–3. Receiver Input Waveform Single-Ended Waveform Positive Channel (p) V ID Negative Channel (n) V CM Ground Differential Waveform V (diff peak-peak) = 2 x V (single-ended) ID ID V ID p − n = 0 V V ID Figure 4–4. Transmitter Output Waveform Single-Ended Waveform Positive Channel (p) V OD Negative Channel (n) V CM Ground Differential Waveform V (diff peak-peak) = 2 x V (single-ended) OD OD V OD p − n = 0 V V OD Altera Corporation 4–9 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Operating Conditions Table 4–7 shows the Arria GX transceiver block AC specification. Table 4–7. Arria GX Transceiver Block AC Specification -6 Speed Grade Description Condition Unit Commercial & Industrial PCI Express (PIPE) Transmitter Jitter Generation Total Transmitter Jitter Generation Compliance Pattern; < 0.25 UI p-p V = 800 mV; OD Pre-emphasis = 49% PCI Express (PIPE) Receiver Jitter Tolerance Total Receiver Jitter Tolerance Compliance Pattern; > 0.6 UI p-p DC Gain = 3 db Gigabit Ethernet (GIGE) Transmitter Jitter Generation Total Transmitter Jitter Generation CRPAT: V = 800 mV; < 0.279 UI p-p OD (TJ) Pre-emphasis = 0% Deterministic Transmitter Jitter CRPAT; V = 800 mV; < 0.279 UI p-p OD Generation (DJ) Pre-emphasis = 0% Gigabit Ethernet (GIE) Receiver Jitter Tolerance Total Jitter Tolerance CJPAT Compliance Pattern; > 0.66 UI p-p DC Gain = 0 dB Deterministic Jitter Tolerance CJPAT Compliance Pattern; > 0.4 UI p-p DC Gain = 0 dB Serial RapidIO (1.25 Gbps and 2.5 Gbps) Transmitter Jitter Generation Total Transmitter Jitter Generation CJPAT Compliance Pattern; < 0.35 UI p-p (TJ) V = 800 mV; OD Pre-emphasis = 0% Deterministic Transmitter Jitter CJPAT Compliance Pattern; < 0.17 UI p-p Generation (DJ) V = 800 mV; OD Pre-emphasis = 0% Serial RapidIO (1.25 Gbps and 2.5 Gbps) Receiver Jitter Tolerance Total Jitter Tolerance CJPAT Compliance Pattern; > 0.65 UI p-p DC Gain = 0 dB Combined Deterministic and CJPAT Compliance Pattern; > 0.55 UI p-p Random Jitter Tolerance (J ) DC Gain = 0 dB DR Deterministic Jitter Tolerance (J ) CJPAT Compliance Pattern; > 0.37 UI p-p D DC Gain = 0 dB Sinusoidal Jitter Tolerance Jitter Frequency = 22.1 KHz > 8.5 UI p-p Jitter Frequency = 200 KHz > 1.0 UI p-p Jitter Frequency = 1.875 MHz > 0.1 UI p-p Jitter Frequency = 20 MHz > 0.1 UI p-p 4–10 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–8 shows the PCS latency information for each mode. Table 4–8. Arria GX PCS Latency Protocol PCS Block PCI Express GIGE Serial RapidIO (PIPE) TX PIPE 1 0 0 TX Phase Comp FIFO 3-4 2-3 2-3 Transmitter PCS (1) Byte Serializer 1 1 1 8B/10B Encoder 0.5 1 0.5 Sum (3) 6-7 4-5 4-5 Word Aligner 2-2.5 4-5 2-2.5 Rate Matcher (2) 5.5-6.5 11-13 0 8B/10B Decoder 0.5 1 0.5 Receiver PCS (1) Byte Deserializer 2 2 2 RX Phase Comp FIFO 2-3 1-2 1-2 RX PIPE 1 0 0 Sum (3) 13-16 19-23 6-7 Notes to Table 4–8: (1) The latency numbers are with respect to the PLD-transceiver interface clock cycles. (2) The rate matcher latency shown is the steady state latency. Actual latency may vary depending on the skip ordered set gap allowed by the protocol, actual PPM difference between the reference clocks, and so forth. (3) The total latency number is rounded off in the Sum column. DC Electrical Characteristics Table 4–9 shows the Arria GX device family DC electrical characteristics. Table 4–9. Arria GX Device DC Operating Conditions (Part 1 of 2) Note (1) Symbol Parameter Conditions Device Minimum Typical Maximum Unit I Input pin leakage V = V to All –10 10 μA I I CCIOmax current 0V (2) I Tri-stated I/O pin V = V to All –10 10 μA OZ O CCIOmax leakage current 0V (2) I V supply current V = ground, no EP1AGX20/35 0.30 (3) A CCINT0 CCINT I (standby) load, no toggling EP1AGX50/60 0.50 (3) A inputs EP1AGX90 0.62 (3) A T = 25 °C J Altera Corporation 4–11 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Operating Conditions Table 4–9. Arria GX Device DC Operating Conditions (Part 2 of 2) Note (1) Symbol Parameter Conditions Device Minimum Typical Maximum Unit I V supply current V = ground, no EP1AGX20/35 2.7 (3) mA CCPD0 CCPD I (standby) load, no toggling EP1AGX50/60 3.6 (3) mA inputs EP1AGX90 4.3 (3) mA T = 25 °C, J V = 3.3V CCPD I V supply current V = ground, no EP1AGX20/35 4.0 (3) mA CCI00 CCIO I (standby) load, no toggling EP1AGX50/60 4.0 (3) mA inputs EP1AGX90 4.0 (3) mA T = 25 °C J R Value of I/O pin pull-up Vi = 0, V = 10 25 50 kΩ CONF CCIO resistor before and (4) 3.3 V during configuration Vi = 0, V = 15 35 70 kΩ CCIO 2.5 V Vi = 0, V = 30 50 100 kΩ CCIO 1.8 V Vi = 0, V = 40 75 150 kΩ CCIO 1.5 V Vi = 0, V = 50 90 170 kΩ CCIO 1.2 V Recommended value 12 kΩ of I/O pin external pull-down resistor before and during configuration Notes to Table 4–9: (1) Typical values are for T = 25 °C, V = 1.2 V, and V = 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V. A CCINT CCIO (2) This value is specified for normal device operation. The value may vary during power-up. This applies for all V CCIO settings (3.3, 2.5, 1.8, 1.5 V, and 1.2 V). (3) Maximum values depend on the actual TJ and design utilization. See the Excel-based PowerPlay early power ® estimator (available at www.altera.com) or the Quartus II PowerPlay power analyzer feature for maximum values. See the section “Power Consumption” on page 4–27 for more information. (4) Pin pull-up resistance values will lower if an external source drives the pin higher than V . CCIO 4–12 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics I/O Standard Specifications Tables 4–10 through 4–33 show the Arria GX device family I/O standard specifications. Table 4–10. LVTTL Specifications Symbol Parameter Conditions Minimum Maximum Unit V (1) Output supply voltage 3.135 3.465 V CCIO V High-level input voltage 1.7 4.0 V IH V Low-level input voltage –0.3 0.8 V IL V High-level output voltage I = –4 mA (2) 2.4 V OH OH V Low-level output voltage I = 4 mA (2) 0.45 V OL OL Notes to Table 4–10: (1) Arria GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B. (2) This specification is supported across all the programmable drive strength settings available for this I/O standard as shown in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. Table 4–11. LVCMOS Specifications Symbol Parameter Conditions Minimum Maximum Unit V (1) Output supply voltage 3.135 3.465 V CCIO V High-level input voltage 1.7 4.0 V IH V Low-level input voltage –0.3 0.8 V IL V High-level output voltage V = 3.0, I = –0.1 mA (2) V – 0.2 V OH CCIO OH CCIO V Low-level output voltage V = 3.0, I = 0.1 mA (2) 0.2 V OL CCIO OL Notes to Table 4–11: (1) Arria GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B. (2) This specification is supported across all the programmable drive strength available for this I/O standard as shown in Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. Altera Corporation 4–13 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Operating Conditions Table 4–12. 2.5-V I/O Specifications Symbol Parameter Conditions Minimum Maximum Unit V (1) Output supply voltage 2.375 2.625 V CCIO V High-level input voltage 1.7 4.0 V IH V Low-level input voltage –0.3 0.7 V IL V High-level output voltage I = –1 mA (2) 2.0 V OH OH V Low-level output voltage I = 1 mA (2) 0.4 V OL OL Notes to Table 4–12: (1) The Arria GX device V voltage level support of 2.5 to 5% is narrower than defined in the Normal Range of the CCIO EIA/JEDEC standard. (2) This specification is supported across all the programmable drive settings available for this I/O standard as shown in Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. Table 4–13. 1.8-V I/O Specifications Symbol Parameter Conditions Minimum Maximum Unit V (1) Output supply voltage 1.71 1.89 V CCIO V High-level input voltage 0.65 × V 2.25 V IH CCIO V Low-level input voltage –0.3 0.35 × V V IL CCIO V High-level output voltage I = –2 mA (2) V – 0.45 V OH OH CCIO V Low-level output voltage I = 2 mA (2) 0.45 V OL OL Notes to Table 4–13: (1) The Arria GX device V voltage level support of 1.8 to 5% is narrower than defined in the Normal Range of the CCIO EIA/JEDEC standard. (2) This specification is supported across all the programmable drive settings available for this I/O standard as shown in Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. 4–14 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–14. 1.5-V I/O Specifications Symbol Parameter Conditions Minimum Maximum Unit V (1) Output supply voltage 1.425 1.575 V CCIO V High-level input voltage 0.65 V V + 0.3 V IH CCIO CCIO V Low-level input voltage –0.3 0.35 V V IL CCIO V High-level output voltage I = –2 mA (2) 0.75 V V OH OH CCIO V Low-level output voltage I = 2 mA (2) 0.25 V V OL OL CCIO Notes to Table 4–14: (1) The Arria GX device V voltage level support of 1.5 to 5% is narrower than defined in the Normal Range of the CCIO EIA/JEDEC standard. (2) This specification is supported across all the programmable drive settings available for this I/O standard as shown in Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. Figures 4–5 and 4–6 show receiver input and transmitter output waveforms, respectively, for all differential I/O standards (LVDS and LVPECL). Figure 4–5. Receiver Input Waveforms for Differential I/O Standards Single-Ended Waveform Positive Channel (p) = V IH V ID Negative Channel (n) = V IL V CM Ground Differential Waveform V ID p − n = 0 V V V ID ID (Peak-to-Peak) Altera Corporation 4–15 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Operating Conditions Figure 4–6. Transmitter Output Waveforms for Differential I/O Standards Single-Ended Waveform Positive Channel (p) = V OH V OD Negative Channel (n) = V OL V CM Ground Differential Waveform V OD p − n = 0 V V OD Table 4–15. 2.5-V LVDS I/O Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V I/O supply voltage for left and 2.375 2.5 2.625 V CCIO right I/O banks (1, 2, 5, and 6) V Input differential voltage 100 350 900 mV ID swing (single-ended) V Input common mode voltage 200 1,250 1,800 mV ICM V Output differential voltage R = 100 Ω 250 450 mV OD L (single-ended) V Output common mode R = 100 Ω 1.125 1.375 V OCM L voltage R Receiver differential input 90 100 110 Ω L discrete resistor (external to Arria GX devices) Table 4–16. 3.3-V LVDS I/O Specifications (Part 1 of 2) Symbol Parameter Conditions Minimum Typical Maximum Unit V (1) I/O supply voltage for top and 3.135 3.3 3.465 V CCIO bottom PLL banks (9, 10, 11, and 12) V Input differential voltage 100 350 900 mV ID swing (single-ended) 4–16 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–16. 3.3-V LVDS I/O Specifications (Part 2 of 2) Symbol Parameter Conditions Minimum Typical Maximum Unit V Input common mode voltage 200 1,250 1,800 mV ICM V Output differential voltage R = 100 Ω 250 710 mV OD L (single-ended) V Output common mode R = 100 Ω 840 1,570 mV OCM L voltage R Receiver differential input 90 100 110 Ω L discrete resistor (external to Arria GX devices) Note to Table 4–16: (1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V , not V . CCINT CCIO The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, connect VCC_PLL_OUT to 3.3 V. Table 4–17. 3.3-V PCML Specifications Symbol Parameter Conditions Minimum Typical Maximum Units V I/O supply voltage 3.135 3.3 3.465 V CCIO V Input differential voltage 300 600 mV ID swing (single-ended) V Input common mode 1.5 3.465 V ICM voltage V Output differential voltage 300 370 500 mV OD (single-ended) ΔV Change in V between 50 mV OD OD high and low V Output common mode 2.5 2.85 3.3 V OCM voltage ΔV Change in V between 50 mV OCM OCM high and low V Output termination voltage V V T CCIO R Output external pull-up 45 50 55 Ω 1 resistors R Output external pull-up 45 50 55 Ω 2 resistors Altera Corporation 4–17 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Operating Conditions Table 4–18. LVPECL Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V (1) I/O supply voltage 3.135 3.3 3.465 V CCIO V Input differential voltage 300 600 1,000 mV ID swing (single-ended) V Input common mode voltage 1.0 2.5 V ICM V Output differential voltage R = 100 Ω 525 970 mV OD L (single-ended) V Output common mode R = 100 Ω 1,650 2,250 mV OCM L voltage R Receiver differential input 90 100 110 Ω L resistor Note to Table 4–18: (1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V , not V . CCINT CCIO The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, connect VCC_PLL_OUT to 3.3 V. Table 4–19. 3.3-V PCI Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 3.0 3.3 3.6 V CCIO V High-level input voltage 0.5 V V + 0.5 V IH CCIO CCIO V Low-level input voltage –0.3 0.3 V V IL CCIO V High-level output voltage I = –500 μA 0.9 V V OH OUT CCIO V Low-level output voltage I = 1,500 μA 0.1 V V OL OUT CCIO Table 4–20. PCI-X Mode 1 Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 3.0 3.6 V CCIO V High-level input voltage 0.5 V V + 0.5 V IH CCIO CCIO V Low-level input voltage –0.3 0.35 V V IL CCIO V Input pull-up voltage 0.7 V V IPU CCIO V High-level output voltage I = –500 μA 0.9 V V OH OUT CCIO V Low-level output voltage I = 1,500 μA 0.1 V V OL OUT CCIO 4–18 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–21. SSTL-18 Class I Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 1.71 1.8 1.89 V CCIO V Reference voltage 0.855 0.9 0.945 V REF V Termination voltage V – 0.04 V V + 0.04 V TT REF REF REF V (DC) High-level DC input voltage V + 0.125 V IH REF V (DC) Low-level DC input voltage V – 0.125 V IL REF V (AC) High-level AC input voltage V + 0.25 V IH REF V (AC) Low-level AC input voltage V – 0.25 V IL REF V High-level output voltage I = –6.7 mA (1) V + 0.475 V OH OH TT V Low-level output voltage I = 6.7 mA (1) V – 0.475 V OL OL TT Note to Table 4–21: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. Table 4–22. SSTL-18 Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 1.71 1.8 1.89 V CCIO V Reference voltage 0.855 0.9 0.945 V REF V Termination voltage V – 0.04 V V + 0.04 V TT REF REF REF V (DC) High-level DC input voltage V + 0.125 V IH REF V (DC) Low-level DC input voltage V – 0.125 V IL REF V (AC) High-level AC input voltage V + 0.25 V IH REF V (AC) Low-level AC input voltage V – 0.25 V IL REF V High-level output voltage I = –13.4 mA (1) V – 0.28 V OH OH CCIO V Low-level output voltage I = 13.4 mA (1) 0.28 V OL OL Note to Table 4–22: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. Altera Corporation 4–19 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Operating Conditions Table 4–23. SSTL-18 Class I & II Differential Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 1.71 1.8 1.89 V CCIO V DC differential input voltage 0.25 V SWING (DC) V (AC) AC differential input cross (V /2) – 0.175 (V /2) + 0.175 V X CCIO CCIO point voltage V AC differential input voltage 0.5 V SWING (AC) V Input clock signal offset 0.5 V V ISO CCIO voltage ΔV Input clock signal offset 200 mV ISO voltage variation V (AC) AC differential cross point (V /2) – 0.125 (V /2) + 0.125 V OX CCIO CCIO voltage Table 4–24. SSTL-2 Class I Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 2.375 2.5 2.625 V CCIO V Termination voltage V – 0.04 V V + 0.04 V TT REF REF REF V Reference voltage 1.188 1.25 1.313 V REF V (DC) High-level DC input voltage V + 0.18 3.0 V IH REF V (DC) Low-level DC input voltage –0.3 V – 0.18 V IL REF V (AC) High-level AC input voltage V + 0.35 V IH REF V (AC) Low-level AC input voltage V – 0.35 V IL REF V High-level output voltage I = –8.1 mA (1) V + 0.57 V OH OH TT V Low-level output voltage I = 8.1 mA (1) V – 0.57 V OL OL TT Note to Table 4–24: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. Table 4–25. SSTL-2 Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 2.375 2.5 2.625 V CCIO V Termination voltage V – 0.04 V V + 0.04 V TT REF REF REF V Reference voltage 1.188 1.25 1.313 V REF 4–20 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–25. SSTL-2 Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V (DC) High-level DC input voltage V + 0.18 V + 0.3 V IH REF CCIO V (DC) Low-level DC input voltage –0.3 V – 0.18 V IL REF V (AC) High-level AC input voltage V + 0.35 V IH REF V (AC) Low-level AC input voltage V – 0.35 V IL REF V High-level output voltage I = –16.4 mA (1) V + 0.76 V OH OH TT V Low-level output voltage I = 16.4 mA (1) V – 0.76 V OL OL TT Note to Table 4–25: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. Table 4–26. SSTL-2 Class I & II Differential Specifications Note (1) Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 2.375 2.5 2.625 V CCIO V (DC) DC differential input voltage 0.36 V SWING V (AC) AC differential input cross (V /2) – 0.2 (V /2) + 0.2 V X CCIO CCIO point voltage V (AC) AC differential input voltage 0.7 V SWING V Input clock signal offset 0.5 V V ISO CCIO voltage ΔV Input clock signal offset 200 mV ISO voltage variation V (AC) AC differential output cross (V /2) – 0.2 (V /2) + 0.2 V OX CCIO CCIO point voltage Note to Table 4–26: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. Table 4–27. 1.2-V HSTL Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 1.14 1.2 1.26 V CCIO V Reference voltage 0.48 V 0.5 V 0.52 V V REF CCIO CCIO CCIO V (DC) High-level DC input voltage V + 0.08 V + 0.15 V IH REF CCIO V (DC) Low-level DC input voltage –0.15 V – 0.08 V IL REF V (AC) High-level AC input voltage V + 0.15 V + 0.24 V IH REF CCIO Altera Corporation 4–21 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Operating Conditions Table 4–27. 1.2-V HSTL Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V (AC) Low-level AC input voltage –0.24 V – 0.15 V IL REF V High-level output voltage I = 8 mA V + 0.15 V + 0.15 V OH OH REF CCIO V Low-level output voltage I = –8 mA –0.15 V – 0.15 V OL OH REF Table 4–28. 1.5-V HSTL Class I Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 1.425 1.5 1.575 V CCIO V Input reference voltage 0.713 0.75 0.788 V REF V Termination voltage 0.713 0.75 0.788 V TT V (DC) DC high-level input voltage V + 0.1 V IH REF V (DC) DC low-level input voltage –0.3 V – 0.1 V IL REF V (AC) AC high-level input voltage V + 0.2 V IH REF V (AC) AC low-level input voltage V – 0.2 V IL REF V High-level output voltage I = 8 mA (1) V – 0.4 V OH OH CCIO V Low-level output voltage I = –8 mA (1) 0.4 V OL OH Note to Table 4–28: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. Table 4–29. 1.5-V HSTL Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 1.425 1.50 1.575 V CCIO V Input reference voltage 0.713 0.75 0.788 V REF V Termination voltage 0.713 0.75 0.788 V TT V (DC) DC high-level input voltage V + 0.1 V IH REF V (DC) DC low-level input voltage –0.3 V – 0.1 V IL REF V (AC) AC high-level input voltage V + 0.2 V IH REF V (AC) AC low-level input voltage V – 0.2 V IL REF V High-level output voltage I = 16 mA (1) V – 0.4 V OH OH CCIO 4–22 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–29. 1.5-V HSTL Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Low-level output voltage I = –16 mA (1) 0.4 V OL OH Note to Table 4–29: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. Table 4–30. 1.5-V HSTL Class I & II Differential Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V I/O supply voltage 1.425 1.5 1.575 V CCIO V (DC) DC input differential voltage 0.2 V DIF V (DC) DC common mode input 0.68 0.9 V CM voltage V (AC) AC differential input voltage 0.4 V DIF V (AC) AC differential cross point 0.68 0.9 V OX voltage Table 4–31. 1.8-V HSTL Class I Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 1.71 1.80 1.89 V CCIO V Input reference voltage 0.85 0.90 0.95 V REF V Termination voltage 0.85 0.90 0.95 V TT V (DC) DC high-level input voltage V + 0.1 V IH REF V (DC) DC low-level input voltage –0.3 V – 0.1 V IL REF V (AC) AC high-level input voltage V + 0.2 V IH REF V (AC) AC low-level input voltage V – 0.2 V IL REF V High-level output voltage I = 8 mA (1) V – 0.4 V OH OH CCIO V Low-level output voltage I = –8 mA (1) 0.4 V OL OH Note to Table 4–31: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. Altera Corporation 4–23 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Operating Conditions Table 4–32. 1.8-V HSTL Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V Output supply voltage 1.71 1.80 1.89 V CCIO V Input reference voltage 0.85 0.90 0.95 V REF V Termination voltage 0.85 0.90 0.95 V TT V (DC) DC high-level input voltage V + 0.1 V IH REF V (DC) DC low-level input voltage –0.3 V – 0.1 V IL REF V (AC) AC high-level input voltage V + 0.2 V IH REF V (AC) AC low-level input voltage V – 0.2 V IL REF V High-level output voltage I = 16 mA (1) V – 0.4 V OH OH CCIO V Low-level output voltage I = –16 mA (1) 0.4 V OL OH Note to Table 4–32: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. Table 4–33. 1.8-V HSTL Class I & II Differential Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit V I/O supply voltage 1.71 1.80 1.89 V CCIO V (DC) DC input differential voltage 0.2 V DIF V (DC) DC common mode input 0.78 1.12 V CM voltage V (AC) AC differential input voltage 0.4 V DIF V (AC) AC differential cross point 0.68 0.9 V OX voltage 4–24 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Bus Hold Specifications Table 4–34 shows the Arria GX device family bus hold specifications. Table 4–34. Bus Hold Parameters V Level CCIO Parameter Conditions 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V Unit Min Max Min Max Min Max Min Max Min Max Low V > V 22.5 25 30 50 70 μA IN IL sustaining (maximum) current High V < V –22.5 –25 –30 –50 –70 μA IN IH sustaining (minimum) current Low 0 V < V < 120 160 200 300 500 μA IN overdrive V CCIO current High 0 V < V < –120 –160 –200 –300 –500 μA IN overdrive V CCIO current Bus-hold 0.45 0.95 0.5 1.0 0.68 1.07 0.7 1.7 0.8 2.0 V trip point On-Chip Termination Specifications Tables 4–35 and 4–36 define the specification for internal termination resistance tolerance when using series or differential on-chip termination. Table 4–35. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 1 of 2) Resistance Tolerance Symbol Description Conditions Commercial Industrial Unit Max Max 25-Ω R Internal series termination without V = 3.3/2.5V ±30 ±30 % S CCIO calibration (25-Ω setting) 3.3/2.5 50-Ω R Internal series termination without V = 3.3/2.5V ±30 ± 30 % S CCIO 3.3/2.5 calibration (50-Ω setting) 25-Ω R Internal series termination without V = 1.8V ±30 ±30 % S CCIO calibration (25-Ω setting) 1.8 50-Ω R Internal series termination without V = 1.8V ±30 ±30 % S CCIO calibration (50-Ω setting) 1.8 Altera Corporation 4–25 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Operating Conditions Table 4–35. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 2 of 2) Resistance Tolerance Symbol Description Conditions Commercial Industrial Unit Max Max 50-Ω R Internal series termination without V = 1.5V ±36 ±36 % S CCIO calibration (50-Ω setting) 1.5 50-Ω R Internal series termination without V = 1.2V ±50 ±50 % S CCIO 1.2 calibration (50-Ω setting) Table 4–36. Series On-Chip Termination Specification for Left I/O Banks Resistance Tolerance Symbol Description Conditions Commercial Industrial Unit Max Max 25-Ω R Internal series termination without V = 3.3/2.5V ±30 ±30 % S CCIO calibration (25-Ω setting) 3.3/2.5 50-Ω R Internal series termination without V = 3.3/2.5/1.8V ±30 ±30 % S CCIO calibration (50-Ω setting) 3.3/2.5/1.8 50-Ω R 1.5 Internal series termination without V = 1.5V ±36 ±36 % S CCIO calibration (50-Ω setting) R Internal differential termination for V = 3.3 V ±20 ±25 % D CCIO LVDS (100-Ω setting) Pin Capacitance Table 4–37 shows the Arria GX device family pin capacitance. Table 4–37. Arria GX Device Capacitance Note (1) Symbol Parameter Typical Unit C Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8. 5.0 pF IOTB C Input capacitance on I/O pins in I/O banks 1 and 2, including high-speed 6.1 pF IOL differential receiver and transmitter pins. C Input capacitance on top/bottom clock input pins: CLK[4..7] and 6.0 pF CLKTB CLK[12..15]. C Input capacitance on left clock inputs: CLK0 and CLK2. 6.1 pF CLKL C Input capacitance on left clock inputs: CLK1 and CLK3. 3.3 pF CLKL+ 4–26 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–37. Arria GX Device Capacitance Note (1) Symbol Parameter Typical Unit C Input capacitance on dual-purpose clock output/feedback pins in PLL 6.7 pF OUTFB banks 11 and 12. Note to Table 4–37: (1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within ±0.5 pF. Altera offers two ways to calculate power for a design: the Excel-based Power PowerPlay early power estimator power calculator and the Quartus II Consumption PowerPlay power analyzer feature. The interactive Excel-based PowerPlay early power estimator is typically used prior to designing the FPGA in order to get an estimate of device power. The Quartus II PowerPlay power analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. The power analyzer can apply a combination of user-entered, simulation-derived and estimated signal activities which, combined with detailed circuit models, can yield very accurate power estimates. In both cases, these calculations should only be used as an estimation of power, not as a specification. f For more information on PowerPlay tools, refer to the PowerPlay Early Power Estimator User Guide and the PowerPlay Early Power Estimator and PowerPlay Power Analyzer chapters in volume 3 of the Quartus II Handbook. The PowerPlay early power estimator is available on the Altera web site at www.altera. com. See Table 4–9 on page 11 for typical I standby CC specifications. The DirectDrive™ technology and MultiTrack™ interconnect ensures I/O Timing predictable performance, accurate simulation, and accurate timing Model analysis across all Arria GX device densities and speed grades. This section describes and specifies the performance of I/Os. All specifications are representative of worst-case supply voltage and junction temperature conditions. 1 The timing numbers listed in the tables of this section are extracted from the Quartus II software, version 7.1. Altera Corporation 4–27 June 2007 Preliminary Arria GX Device Handbook, Volume 1 I/O Timing Model Preliminary, Correlated, and Final Timing Timing models can have either preliminary, correlated, or final status. The Quartus II software issues an informational message during design compilation if the timing models are preliminary. Table 4–38 shows the status of the Arria GX device timing models. ■ Preliminary status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible. ■ Correlated numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under worst-case voltage and junction temperature conditions. ■ Final timing numbers are based on complete correlation to actual devices and addressing any minor deviations from the correlated timing model. When the timing models are final, all or most of the Arria GX family devices have been completely characterized and no further changes to the timing model are expected. Table 4–38. Arria GX Device Timing Model Status Device Preliminary Correlated Final EP1AGX20 v EP1AGX35 v EP1AGX50 v EP1AGX60 v EP1AGX90 v I/O Timing Measurement Methodology Different I/O standards require different baseline loading techniques for reporting timing delays. Altera characterizes timing delays with the required termination for each I/O standard and with 0 pF (except for PCI and PCI-X which use 10 pF) loading and the timing is specified up to the output pin of the FPGA device. The Quartus II software calculates the I/O timing for each I/O standard with a default baseline loading as specified by the I/O standards. The following measurements are made during device characterization. Altera measures clock-to-output delays (t ) at worst-case process, CO minimum voltage, and maximum temperature (PVT) for default loading conditions shown in Table 4–39. Use the following equations to calculate clock pin to output pin timing for Arria GX devices. 4–28 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics t from clock pin to I/O pin = delay from clock pad to I/O output CO register + IOE output register clock-to-output delay + delay from output register to output pin + I/O output delay t /t from clock pin to I/O pin = delay from clock pad to I/O xz zx output register + IOE output register clock-to-output delay + delay from output register to output pin + I/O output delay + output enable pin delay Simulation using IBIS models is required to determine the delays on the PCB traces in addition to the output pin delay timing reported by the Quartus II software and the timing model in the device handbook. 1. Simulate the output driver of choice into the generalized test setup, using values from Table 4–39. 2. Record the time to V . MEAS 3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load. 4. Record the time to V . MEAS 5. Compare the results of steps 2 and 4. The increase or decrease in delay should be added to or subtracted from the I/O Standard Output Adder delays to yield the actual worst-case propagation delay (clock-to-output) of the PCB trace. The Quartus II software reports the timing with the conditions shown in Table 4–39 using the above equation. Figure 4–7 shows the model of the circuit that is represented by the output timing of the Quartus II software. Altera Corporation 4–29 June 2007 Preliminary Arria GX Device Handbook, Volume 1 I/O Timing Model Figure 4–7. Output Delay Timing Reporting Setup Modeled by Quartus II V TT V CCIO Output R p T R S Output Output R D Buffer V Output MEAS n C L GND GND Notes to Figure 4–7: (1) Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay need to be accounted for with IBIS model simulations. (2) V is 3.085 V unless otherwise specified. CCPD (3) V is 1.12 V unless otherwise specified. CCINT Table 4–39. Output Timing Measurement Methodology for Output Pins (Part 1 of 2) Notes (1), (2), (3), (4) Measurement Loading & Termination Point I/O Standard R (Ω) S R (Ω)R (Ω)V (V) V (V) C (pF) V (V) D T CCIO TT L MEAS LVTTL (5) 3.135 0 1.5675 LVCMOS (5) 3.135 0 1.5675 2.5 V (5) 2.375 0 1.1875 1.8 V (5) 1.710 0 0.855 1.5 V (5) 1.425 0 0.7125 PCI (6) 2.970 10 1.485 PCI-X (6) 2.970 10 1.485 SSTL-2 Class I 25 50 2.325 1.123 0 1.1625 SSTL-2 Class II 25 25 2.325 1.123 0 1.1625 SSTL-18 Class I 25 50 1.660 0.790 0 0.83 SSTL-18 Class II 25 25 1.660 0.790 0 0.83 1.8-V HSTL Class I 50 1.660 0.790 0 0.83 1.8-V HSTL Class II 25 1.660 0.790 0 0.83 1.5-V HSTL Class I 50 1.375 0.648 0 0.6875 1.5-V HSTL Class II 25 1.375 0.648 0 0.6875 1.2-V HSTL with OCT 1.140 0 0.570 Differential SSTL-2 Class I 25 50 2.325 1.123 0 1.1625 4–30 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–39. Output Timing Measurement Methodology for Output Pins (Part 2 of 2) Notes (1), (2), (3), (4) Measurement Loading & Termination Point I/O Standard R (Ω) S R (Ω)R (Ω)V (V) V (V) C (pF) V (V) D T CCIO TT L MEAS Differential SSTL-2 Class II 25 25 2.325 1.123 0 1.1625 Differential SSTL-18 Class I 50 50 1.660 0.790 0 0.83 Differential SSTL-18 Class II 25 25 1.660 0.790 0 0.83 1.5-V differential HSTL Class I 50 1.375 0.648 0 0.6875 1.5-V differential HSTL Class II 25 1.375 0.648 0 0.6875 1.8-V differential HSTL Class I 50 1.660 0.790 0 0.83 1.8-V differential HSTL Class II 25 1.660 0.790 0 0.83 LVDS 1002.32501.1625 LVPECL 100 3.135 0 1.5675 Notes to Table 4–39: (1) Input measurement point at internal node is 0.5 V . CCINT (2) Output measuring point for V at buffer output is 0.5 V . MEAS CCIO (3) Input stimulus edge rate is 0 to V in 0.2 ns (internal signal) from the driver preceding the I/O buffer. CC (4) The data in this table is preliminary. Altera will provide a report upon completion of characterization of the Arria GX devices. Conditions for testing the silicon have not been determined. (5) Less than 50-mV ripple on V and V , V = 1.15 V with less than 30-mV ripple. CCIO CCPD CCINT (6) V = 2.97 V, less than 50-mV ripple on V and V , V = 1.15 V. CCPD CCIO CCPD CCINT Altera Corporation 4–31 June 2007 Preliminary Arria GX Device Handbook, Volume 1 I/O Timing Model Figures 4–8 and 4–9 show the measurement setup for output disable and output enable timing. Figure 4–8. Measurement Setup for t Note (1) xz t , Driving High to Tristate XZ Enable Disable OE OE Dout ½ V CCINT “1” Din Din 100 Ω 100 mv Dout GND t hz t , Driving Low to Tristate XZ Enable Disable OE ½ V CCINT 100 Ω OE Dout Din “0” Din t lz V CCIO Dout 100 mv Note to Figure 4–8: (1) V is 1.12 V for this measurement. CCINT 4–32 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Figure 4–9. Measurement Setup for t zx t , Tristate to Driving High ZX Disable Enable ½ V CCINT OE OE Dout “1” Din Din 1 MΩ t Dout zh ½ V CCIO t , Tristate to Driving Low ZX Disable Enable ½ V CCINT OE 1 MΩ OE Dout Din “0” Din ½ V t CCIO zl Dout Table 4–40 specifies the input timing measurement setup. Table 4–40. Timing Measurement Methodology for Input Pins (Part 1 of 2) Notes (1), (2), (3), (4), (5) Measurement Conditions Measurement Point I/O Standard V (V) V (V) Edge Rate (ns) VMEAS (V) CCIO REF LVTTL (6) 3.135 3.135 1.5675 LVCMOS (6) 3.135 3.135 1.5675 2.5 V (6) 2.375 2.375 1.1875 1.8 V (6) 1.710 1.710 0.855 1.5 V (6) 1.425 1.425 0.7125 PCI (7) 2.970 2.970 1.485 PCI-X (7) 2.970 2.970 1.485 SSTL-2 Class I 2.325 1.163 2.325 1.1625 SSTL-2 Class II 2.325 1.163 2.325 1.1625 SSTL-18 Class I 1.660 0.830 1.660 0.83 SSTL-18 Class II 1.660 0.830 1.660 0.83 1.8-V HSTL Class I 1.660 0.830 1.660 0.83 Altera Corporation 4–33 June 2007 Preliminary Arria GX Device Handbook, Volume 1 I/O Timing Model Table 4–40. Timing Measurement Methodology for Input Pins (Part 2 of 2) Notes (1), (2), (3), (4), (5) Measurement Conditions Measurement Point I/O Standard V (V) V (V) Edge Rate (ns) VMEAS (V) CCIO REF 1.8-V HSTL Class II 1.660 0.830 1.660 0.83 1.5-V HSTL Class I 1.375 0.688 1.375 0.6875 1.5-V HSTL Class II 1.375 0.688 1.375 0.6875 1.2-V HSTL with OCT 1.140 0.570 1.140 0.570 Differential SSTL-2 Class I 2.325 1.163 2.325 1.1625 Differential SSTL-2 Class II 2.325 1.163 2.325 1.1625 Differential SSTL-18 Class I 1.660 0.830 1.660 0.83 Differential SSTL-18 Class II 1.660 0.830 1.660 0.83 1.5-V differential HSTL Class I 1.375 0.688 1.375 0.6875 1.5-V differential HSTL Class II 1.375 0.688 1.375 0.6875 1.8-V differential HSTL Class I 1.660 0.830 1.660 0.83 1.8-V differential HSTL Class II 1.660 0.830 1.660 0.83 LVDS 2.325 0.1001.1625 LVPECL 3.135 0.100 1.5675 Notes to Table 4–40: (1) Input buffer sees no load at buffer input. (2) Input measuring point at buffer input is 0.5 V . CCIO (3) Output measuring point is 0.5 V at internal node. CC (4) Input edge rate is 1 V/ns. (5) The data in this table is preliminary. Altera will provide a report upon completion of characterization of the Arria GX devices. Conditions for testing the silicon have not been determined. (6) Less than 50-mV ripple on V and V , V = 1.15 V with less than 30-mV ripple. CCIO CCPD CCINT (7) V = 2.97 V, less than 50-mV ripple on V and V , V = 1.15 V. CCPD CCIO CCPD CCINT Clock Network Skew Adders The Quartus II software models skew within dedicated clock networks such as global and regional clocks. Therefore, the intra-clock network skew adder is not specified. Table 4–41 specifies the clock skew between any two clock networks driving registers in the I/O element (IOE). Table 4–41. Clock Network Specifications (Part 1 of 2) Name Description Min Typ Max Unit Clock skew adder Inter-clock network, same side ± 50 ps EP1AGX20/35 (1) Inter-clock network, entire chip ± 100 ps 4–34 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–41. Clock Network Specifications (Part 2 of 2) Name Description Min Typ Max Unit Clock skew adder Inter-clock network, same side ± 50 ps EP1AGX50/60 (1) Inter-clock network, entire chip ± 100 ps Clock skew adder Inter-clock network, same side ± 55 ps EP1AGX90 (1) Inter-clock network, entire chip ± 110 ps Notes to Table 4–41: (1) This is in addition to intra-clock network skew, which is modeled in the Quartus II software. Default Capacitive Loading of Different I/O Standards See Table 4–42 for default capacitive loading of different I/O standards. Table 4–42. Default Loading of Different I/O Standards for Arria GX Devices (Part 1 of 2) Note (1) I/O Standard Capacitive Load Unit LVTTL 0 pF LVCMOS 0 pF 2.5 V 0 pF 1.8 V 0 pF 1.5 V 0 pF PCI 10 pF PCI-X 10 pF SSTL-2 Class I 0 pF SSTL-2 Class II 0 pF SSTL-18 Class I 0 pF SSTL-18 Class II 0 pF 1.5-V HSTL Class I 0 pF 1.5-V HSTL Class II 0 pF 1.8-V HSTL Class I 0 pF 1.8-V HSTL Class II 0 pF Differential SSTL-2 Class I 0 pF Differential SSTL-2 Class II 0 pF Differential SSTL-18 Class I 0 pF Differential SSTL-18 Class II 0 pF 1.5-V differential HSTL Class I 0 pF Altera Corporation 4–35 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–42. Default Loading of Different I/O Standards for Arria GX Devices (Part 2 of 2) Note (1) I/O Standard Capacitive Load Unit 1.5-V differential HSTL Class II 0 pF 1.8-V differential HSTL Class I 0 pF 1.8-V differential HSTL Class II 0 pF LVDS 0pF Note to Table 4–42: (1) The data in this table is preliminary. Altera will provide a report upon completion of characterization of the Arria GX devices. Conditions for testing the silicon have not been determined. The following section describes the typical design performance for the Typical Design Arria GX device family. Performance User I/O Pin Timing Tables 4–43 to 4–72 show user I/O pin timing for Arria GX devices. I/O buffer t , t , and t are reported for the cases when I/O clock is driven SU H CO by a non-PLL global clock (GCLK) and a PLL driven global clock (GCLK-PLL). For t , t and t using regional clock, add the value from SU H CO the adder tables listed for each device to the GCLK/GCLK-PLL values for the device. EP1AGX20 I/O Timing Parameters Tables 4–43 through 4–46 show the maximum I/O timing parameters for EP1AGX20 devices for I/O standards which support general purpose I/O pins. Table 4–43 describes the row pin delay adders when using the regional clock in Arria GX devices. Table 4–43. EP1AGX20 Row Pin Delay Adders for Regional Clock (Part 1 Fast Corner -6 Speed Parameter Units Grade Industrial Commercial RCLK input 0.117 0.117 0.273 ns adder RCLK PLL 0.011 0.011 0.019 ns input adder 4–36 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–43. EP1AGX20 Row Pin Delay Adders for Regional Clock (Part 2 Fast Corner -6 Speed Parameter Units Grade Industrial Commercial -0.117 -0.117 -0.273 ns RCLK output adder RCLK PLL -0.011 -0.011 -0.019 ns output adder Table 4–44 describes I/O timing specifications. Table 4–44. EP1AGX20 Column Pins Input Timing Parameters (Part 1 of 3) Fast Corner -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial 3.3-V LVTTL GCLK t 1.251 1.251 2.915 ns SU t -1.146 -1.146 -2.638 ns H t 2.693 2.693 6.021 ns GCLK PLL SU t -2.588 -2.588 -5.744 ns H 3.3-V GCLK t 1.251 1.251 2.915 ns SU LVCMOS t -1.146 -1.146 -2.638 ns H GCLK PLL t 2.693 2.693 6.021 ns SU t -2.588 -2.588 -5.744 ns H 2.5 V t 1.261 1.261 2.897 ns GCLK SU t -1.156 -1.156 -2.620 ns H GCLK PLL t 2.703 2.703 6.003 ns SU t -2.598 -2.598 -5.726 ns H 1.8 V t 1.327 1.327 3.107 ns GCLK SU t -1.222 -1.222 -2.830 ns H GCLK PLL t 2.769 2.769 6.213 ns SU t -2.664 -2.664 -5.936 ns H 1.5 V GCLK t 1.330 1.330 3.200 ns SU t -1.225 -1.225 -2.923 ns H t 2.772 2.772 6.306 ns GCLK PLL SU t -2.667 -2.667 -6.029 ns H Altera Corporation 4–37 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–44. EP1AGX20 Column Pins Input Timing Parameters (Part 2 of 3) Fast Corner -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial SSTL-2 GCLK t 1.075 1.075 2.372 ns SU CLASS I t -0.970 -0.970 -2.095 ns H t 2.517 2.517 5.480 ns GCLK PLL SU t -2.412 -2.412 -5.203 ns H SSTL-2 GCLK t 1.075 1.075 2.372 ns SU CLASS II t -0.970 -0.970 -2.095 ns H GCLK PLL t 2.517 2.517 5.480 ns SU t -2.412 -2.412 -5.203 ns H SSTL-18 t 1.113 1.113 2.479 ns GCLK SU CLASS I t -1.008 -1.008 -2.202 ns H GCLK PLL t 2.555 2.555 5.585 ns SU t -2.450 -2.450 -5.308 ns H SSTL-18 t 1.114 1.114 2.479 ns GCLK SU CLASS II t -1.009 -1.009 -2.202 ns H GCLK PLL t 2.556 2.556 5.587 ns SU t -2.451 -2.451 -5.310 ns H 1.8-V HSTL GCLK t 1.113 1.113 2.479 ns SU CLASS I t -1.008 -1.008 -2.202 ns H t 2.555 2.555 5.585 ns GCLK PLL SU t -2.450 -2.450 -5.308 ns H 1.8-V HSTL GCLK t 1.114 1.114 2.479 ns SU CLASS II t -1.009 -1.009 -2.202 ns H t 2.556 2.556 5.587 ns GCLK PLL SU t -2.451 -2.451 -5.310 ns H 1.5-V HSTL GCLK t 1.131 1.131 2.607 ns SU CLASS I t -1.026 -1.026 -2.330 ns H GCLK PLL t 2.573 2.573 5.713 ns SU t -2.468 -2.468 -5.436 ns H 4–38 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–44. EP1AGX20 Column Pins Input Timing Parameters (Part 3 of 3) Fast Corner -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial 1.5-V HSTL GCLK t 1.132 1.132 2.607 ns SU CLASS II t -1.027 -1.027 -2.330 ns H t 2.574 2.574 5.715 ns GCLK PLL SU t -2.469 -2.469 -5.438 ns H 3.3-V PCI GCLK t 1.256 1.256 2.903 ns SU t -1.151 -1.151 -2.626 ns H GCLK PLL t 2.698 2.698 6.009 ns SU t -2.593 -2.593 -5.732 ns H 3.3-V PCI-X t 1.256 1.256 2.903 ns GCLK SU t -1.151 -1.151 -2.626 ns H GCLK PLL t 2.698 2.698 6.009 ns SU t -2.593 -2.593 -5.732 ns H LVDS t 1.106 1.106 2.489 ns GCLK SU t -1.001 -1.001 -2.212 ns H GCLK PLL t 2.530 2.530 5.564 ns SU t -2.425 -2.425 -5.287 ns H Table 4–45 describes I/O timing specifications. Table 4–45. EP1AGX20 Row Pins output Timing Parameters (Part 1 of 3) Fast Model I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 3.3-V 4mA GCLK t 2.904 2.904 6.699 ns CO LVTTL t 1.485 1.485 3.627 ns GCLK PLL CO 3.3-V 8mA t 2.776 2.776 6.059 ns GCLK CO LVTTL GCLK PLL t 1.357 1.357 2.987 ns CO 3.3-V 12 mA GCLK t 2.720 2.720 6.022 ns CO LVTTL GCLK PLL t 1.301 1.301 2.950 ns CO 3.3-V 4mA t 2.776 2.776 6.059 ns GCLK CO LVCMOS t 1.357 1.357 2.987 ns GCLK PLL CO Altera Corporation 4–39 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–45. EP1AGX20 Row Pins output Timing Parameters (Part 2 of 3) Fast Model I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 3.3-V 8mA GCLK t 2.670 2.670 5.753 ns CO LVCMOS GCLK PLL t 1.251 1.251 2.681 ns CO 2.5 V 4 mA t 2.759 2.759 6.033 ns GCLK CO t 1.340 1.340 2.961 ns GCLK PLL CO 2.5 V 8 mA GCLK t 2.656 2.656 5.775 ns CO GCLK PLL t 1.237 1.237 2.703 ns CO 2.5 V 12 mA GCLK t 2.637 2.637 5.661 ns CO t 1.218 1.218 2.589 ns GCLK PLL CO 1.8 V 2 mA t 2.829 2.829 7.052 ns GCLK CO GCLK PLL t 1.410 1.410 3.980 ns CO 1.8 V 4 mA GCLK t 2.818 2.818 6.273 ns CO GCLK PLL t 1.399 1.399 3.201 ns CO 1.8 V 6 mA t 2.707 2.707 5.972 ns GCLK CO t 1.288 1.288 2.900 ns GCLK PLL CO 1.8 V 8 mA GCLK t 2.676 2.676 5.858 ns CO GCLK PLL t 1.257 1.257 2.786 ns CO 1.5 V 2 mA GCLK t 2.789 2.789 6.551 ns CO t 1.370 1.370 3.479 ns GCLK PLL CO 1.5 V 4 mA t 2.682 2.682 5.950 ns GCLK CO GCLK PLL t 1.263 1.263 2.878 ns CO SSTL-2 8 mA GCLK t 2.626 2.626 5.614 ns CO CLASS I GCLK PLL t 1.207 1.207 2.542 ns CO SSTL-2 12 mA t 2.602 2.602 5.538 ns GCLK CO CLASS I t 1.183 1.183 2.466 ns GCLK PLL CO SSTL-2 16 mA GCLK t 2.568 2.568 5.407 ns CO CLASS II GCLK PLL t 1.149 1.149 2.335 ns CO SSTL-18 4mA GCLK t 2.614 2.614 5.556 ns CO CLASS I t 1.195 1.195 2.484 ns GCLK PLL CO SSTL-18 6mA t 2.618 2.618 5.485 ns GCLK CO CLASS I GCLK PLL t 1.199 1.199 2.413 ns CO 4–40 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–45. EP1AGX20 Row Pins output Timing Parameters (Part 3 of 3) Fast Model I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial SSTL-18 8mA GCLK t 2.594 2.594 5.468 ns CO CLASS I GCLK PLL t 1.175 1.175 2.396 ns CO SSTL-18 10 mA t 2.597 2.597 5.447 ns GCLK CO CLASS I t 1.178 1.178 2.375 ns GCLK PLL CO 1.8-V HSTL 4mA GCLK t 2.595 2.595 5.466 ns CO CLASS I GCLK PLL t 1.176 1.176 2.394 ns CO 1.8-V HSTL 6mA GCLK t 2.598 2.598 5.430 ns CO CLASS I t 1.179 1.179 2.358 ns GCLK PLL CO 1.8-V HSTL 8mA t 2.580 2.580 5.426 ns GCLK CO CLASS I GCLK PLL t 1.161 1.161 2.354 ns CO 1.8-V HSTL 10 mA GCLK t 2.584 2.584 5.415 ns CO CLASS I GCLK PLL t 1.165 1.165 2.343 ns CO 1.8-V HSTL 12 mA t 2.575 2.575 5.414 ns GCLK CO CLASS I t 1.156 1.156 2.342 ns GCLK PLL CO 1.5-V HSTL 4mA GCLK t 2.594 2.594 5.443 ns CO CLASS I GCLK PLL t 1.175 1.175 2.371 ns CO 1.5-V HSTL 6 mA GCLK t 2.597 2.597 5.429 ns CO CLASS I t 1.178 1.178 2.357 ns GCLK PLL CO 1.5-V HSTL 8mA t 2.582 2.582 5.421 ns GCLK CO CLASS I GCLK PLL t 1.163 1.163 2.349 ns CO LVDS - GCLK t 2.654 2.654 5.613 ns CO GCLK PLL t 1.226 1.226 2.530 ns CO Table 4–46 describes I/O timing specifications. Table 4–46. EP1AGX20 Column Pins Output Timing Parameters (Part 1 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 3.3-V 4mA t 2.909 2.909 6.541 ns GCLK CO LVTTL t 1.467 1.467 3.435 ns GCLK PLL CO Altera Corporation 4–41 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–46. EP1AGX20 Column Pins Output Timing Parameters (Part 2 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 3.3-V 8mA GCLK t 2.764 2.764 6.169 ns CO LVTTL GCLK PLL t 1.322 1.322 3.063 ns CO 3.3-V 12 mA t 2.697 2.697 6.169 ns GCLK CO LVTTL t 1.255 1.255 3.063 ns GCLK PLL CO 3.3-V 16 mA GCLK t 2.671 2.671 6.000 ns CO LVTTL GCLK PLL t 1.229 1.229 2.894 ns CO 3.3-V 20 mA GCLK t 2.649 2.649 5.875 ns CO LVTTL t 1.207 1.207 2.769 ns GCLK PLL CO 3.3-V 24 mA t 2.642 2.642 5.877 ns GCLK CO LVTTL GCLK PLL t 1.200 1.200 2.771 ns CO 3.3-V 4mA GCLK t 2.764 2.764 6.169 ns CO LVCMOS GCLK PLL t 1.322 1.322 3.063 ns CO 3.3-V 8mA t 2.672 2.672 5.874 ns GCLK CO LVCMOS t 1.230 1.230 2.768 ns GCLK PLL CO 3.3-V 12 mA GCLK t 2.644 2.644 5.796 ns CO LVCMOS GCLK PLL t 1.202 1.202 2.690 ns CO 3.3-V 16 mA GCLK t 2.651 2.651 5.764 ns CO LVCMOS t 1.209 1.209 2.658 ns GCLK PLL CO 3.3-V 20 mA t 2.638 2.638 5.746 ns GCLK CO LVCMOS GCLK PLL t 1.196 1.196 2.640 ns CO 3.3-V 24 mA GCLK t 2.627 2.627 5.724 ns CO LVCMOS GCLK PLL t 1.185 1.185 2.618 ns CO 2.5 V 4 mA t 2.726 2.726 6.201 ns GCLK CO t 1.284 1.284 3.095 ns GCLK PLL CO 2.5 V 8 mA GCLK t 2.674 2.674 5.939 ns CO GCLK PLL t 1.232 1.232 2.833 ns CO 2.5 V 12 mA GCLK t 2.653 2.653 5.822 ns CO t 1.211 1.211 2.716 ns GCLK PLL CO 2.5 V 16 mA t 2.635 2.635 5.748 ns GCLK CO GCLK PLL t 1.193 1.193 2.642 ns CO 4–42 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–46. EP1AGX20 Column Pins Output Timing Parameters (Part 3 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.8 V 2 mA GCLK t 2.766 2.766 7.193 ns CO GCLK PLL t 1.324 1.324 4.087 ns CO 1.8 V 4 mA t 2.771 2.771 6.419 ns GCLK CO t 1.329 1.329 3.313 ns GCLK PLL CO 1.8 V 6 mA GCLK t 2.695 2.695 6.155 ns CO GCLK PLL t 1.253 1.253 3.049 ns CO 1.8 V 8 mA GCLK t 2.697 2.697 6.064 ns CO t 1.255 1.255 2.958 ns GCLK PLL CO 1.8 V 10 mA t 2.651 2.651 5.987 ns GCLK CO GCLK PLL t 1.209 1.209 2.881 ns CO 1.8 V 12 mA GCLK t 2.652 2.652 5.930 ns CO GCLK PLL t 1.210 1.210 2.824 ns CO 1.5 V 2 mA t 2.746 2.746 6.723 ns GCLK CO t 1.304 1.304 3.617 ns GCLK PLL CO 1.5 V 4 mA GCLK t 2.682 2.682 6.154 ns CO GCLK PLL t 1.240 1.240 3.048 ns CO 1.5 V 6 mA GCLK t 2.685 2.685 6.036 ns CO t 1.243 1.243 2.930 ns GCLK PLL CO 1.5 V 8 mA t 2.644 2.644 5.983 ns GCLK CO GCLK PLL t 1.202 1.202 2.877 ns CO SSTL-2 8mA GCLK t 2.629 2.629 5.762 ns CO CLASS I GCLK PLL t 1.184 1.184 2.650 ns CO SSTL-2 12 mA t 2.612 2.612 5.712 ns GCLK CO CLASS I t 1.167 1.167 2.600 ns GCLK PLL CO SSTL-2 16 mA GCLK t 2.590 2.590 5.639 ns CO CLASS II GCLK PLL t 1.145 1.145 2.527 ns CO SSTL-2 20 mA GCLK t 2.591 2.591 5.626 ns CO CLASS II t 1.146 1.146 2.514 ns GCLK PLL CO SSTL-2 24 mA t 2.587 2.587 5.624 ns GCLK CO CLASS II GCLK PLL t 1.142 1.142 2.512 ns CO Altera Corporation 4–43 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–46. EP1AGX20 Column Pins Output Timing Parameters (Part 4 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial SSTL-18 4mA GCLK t 2.626 2.626 5.733 ns CO CLASS I GCLK PLL t 1.184 1.184 2.627 ns CO SSTL-18 6mA t 2.630 2.630 5.694 ns GCLK CO CLASS I t 1.185 1.185 2.582 ns GCLK PLL CO SSTL-18 8mA GCLK t 2.609 2.609 5.675 ns CO CLASS I GCLK PLL t 1.164 1.164 2.563 ns CO SSTL-18 10 mA GCLK t 2.614 2.614 5.673 ns CO CLASS I t 1.169 1.169 2.561 ns GCLK PLL CO SSTL-18 12 mA t 2.608 2.608 5.659 ns GCLK CO CLASS I GCLK PLL t 1.163 1.163 2.547 ns CO SSTL-18 8mA GCLK t 2.597 2.597 5.625 ns CO CLASS II GCLK PLL t 1.152 1.152 2.513 ns CO SSTL-18 16 mA t 2.609 2.609 5.603 ns GCLK CO CLASS II t 1.164 1.164 2.491 ns GCLK PLL CO SSTL-18 18 mA GCLK t 2.605 2.605 5.611 ns CO CLASS II GCLK PLL t 1.160 1.160 2.499 ns CO SSTL-18 20 mA GCLK t 2.605 2.605 5.609 ns CO CLASS II t 1.160 1.160 2.497 ns GCLK PLL CO 1.8-V HSTL 4mA t 2.629 2.629 5.664 ns GCLK CO CLASS I GCLK PLL t 1.187 1.187 2.558 ns CO 1.8-V HSTL 6mA GCLK t 2.634 2.634 5.649 ns CO CLASS I GCLK PLL t 1.189 1.189 2.537 ns CO 1.8-V HSTL 8mA t 2.612 2.612 5.638 ns GCLK CO CLASS I t 1.167 1.167 2.526 ns GCLK PLL CO 1.8-V HSTL 10 mA GCLK t 2.616 2.616 5.644 ns CO CLASS I GCLK PLL t 1.171 1.171 2.532 ns CO 1.8-V HSTL 12 mA GCLK t 2.608 2.608 5.637 ns CO CLASS I t 1.163 1.163 2.525 ns GCLK PLL CO 1.8-V HSTL 16 mA t 2.591 2.591 5.401 ns GCLK CO CLASS II GCLK PLL t 1.146 1.146 2.289 ns CO 4–44 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–46. EP1AGX20 Column Pins Output Timing Parameters (Part 5 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.8-V HSTL 18 mA GCLK t 2.593 2.593 5.412 ns CO CLASS II GCLK PLL t 1.148 1.148 2.300 ns CO 1.8-V HSTL 20 mA t 2.593 2.593 5.421 ns GCLK CO CLASS II t 1.148 1.148 2.309 ns GCLK PLL CO 1.5-V HSTL 4mA GCLK t 2.629 2.629 5.663 ns CO CLASS I GCLK PLL t 1.187 1.187 2.557 ns CO 1.5-V HSTL 6mA GCLK t 2.633 2.633 5.641 ns CO CLASS I t 1.188 1.188 2.529 ns GCLK PLL CO 1.5-V HSTL 8mA t 2.615 2.615 5.643 ns GCLK CO CLASS I GCLK PLL t 1.170 1.170 2.531 ns CO 1.5-V HSTL 10 mA GCLK t 2.615 2.615 5.645 ns CO CLASS I GCLK PLL t 1.170 1.170 2.533 ns CO 1.5-V HSTL 12 mA t 2.609 2.609 5.643 ns GCLK CO CLASS I t 1.164 1.164 2.531 ns GCLK PLL CO 1.5-V HSTL 16 mA GCLK t 2.596 2.596 5.455 ns CO CLASS II GCLK PLL t 1.151 1.151 2.343 ns CO 1.5-V HSTL 18 mA GCLK t 2.599 2.599 5.465 ns CO CLASS II t 1.154 1.154 2.353 ns GCLK PLL CO 1.5-V HSTL 20 mA t 2.601 2.601 5.478 ns GCLK CO CLASS II GCLK PLL t 1.156 1.156 2.366 ns CO 3.3-V PCI - GCLK t 2.755 2.755 5.791 ns CO GCLK PLL t 1.313 1.313 2.685 ns CO 3.3-V PCI-X - t 2.755 2.755 5.791 ns GCLK CO t 1.313 1.313 2.685 ns GCLK PLL CO LVDS - GCLK t 3.621 3.621 6.969 ns CO GCLK PLL t 2.190 2.190 3.880 ns CO Tables 4–47 through 4–48 shows EP1AGX20 regional clock (RCLK) adder values that should be added to GCLK values. These adder values are used to determine I/O timing when the I/O pin is driven using the regional clock. This applies for all I/O standards supported by Arria GX with general purpose I/O pins. Altera Corporation 4–45 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–47 describes row pin delay adders when using the regional clock in Arria GX devices. Table 4–47. EP1AGX20 Row Pin Delay Adders for Regional Clock Fast Corner -6 Speed Parameter Units Grade Industrial Commercial 0.117 0.117 0.273 ns RCLK input adder RCLK PLL 0.011 0.011 0.019 ns input adder RCLK output -0.117 -0.117 -0.273 ns adder -0.011 -0.011 -0.019 ns RCLK PLL output adder Table 4–48 describes column pin delay adders when using the regional clock in Arria GX devices. Table 4–48. EP1AGX20 Column Pin Delay Adders for Regional Clock Fast Corner -6 Speed Parameter Units Grade Industrial Commercial 0.081 0.081 0.223 ns RCLK input adder RCLK PLL -0.012 -0.012 -0.008 ns input adder RCLK output -0.081 -0.081 -0.224 ns adder 1.11 1.11 2.658 ns RCLK PLL output adder EP1AGX35 I/O Timing Parameters Tables 4–49 through 4–52 show the maximum I/O timing parameters for EP1AGX35 devices for I/O standards which support general purpose I/O pins. 4–46 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–49 describes I/O timing specifications. Table 4–49. EP1AGX20 Row Pins Input Timing Parameters (Part 1 of 2) Fast Model -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial 3.3-V LVTTL GCLK t 1.561 1.561 3.556 ns SU t -1.456 -1.456 -3.279 ns H t 2.980 2.980 6.628 ns GCLK PLL SU t -2.875 -2.875 -6.351 ns H 3.3-V GCLK t 1.561 1.561 3.556 ns SU LVCMOS t -1.456 -1.456 -3.279 ns H GCLK PLL t 2.980 2.980 6.628 ns SU t -2.875 -2.875 -6.351 ns H 2.5 V t 1.573 1.573 3.537 ns GCLK SU t -1.468 -1.468 -3.260 ns H GCLK PLL t 2.992 2.992 6.609 ns SU t -2.887 -2.887 -6.332 ns H 1.8 V t 1.639 1.639 3.744 ns GCLK SU t -1.534 -1.534 -3.467 ns H GCLK PLL t 3.058 3.058 6.816 ns SU t -2.953 -2.953 -6.539 ns H 1.5 V GCLK t 1.642 1.642 3.839 ns SU t -1.537 -1.537 -3.562 ns H t 3.061 3.061 6.911 ns GCLK PLL SU t -2.956 -2.956 -6.634 ns H SSTL-2 GCLK t 1.385 1.385 3.009 ns SU CLASS I t -1.280 -1.280 -2.732 ns H t 2.804 2.804 6.081 ns GCLK PLL SU t -2.699 -2.699 -5.804 ns H SSTL-2 GCLK t 1.385 1.385 3.009 ns SU CLASS II t -1.280 -1.280 -2.732 ns H GCLK PLL t 2.804 2.804 6.081 ns SU t -2.699 -2.699 -5.804 ns H Altera Corporation 4–47 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–49. EP1AGX20 Row Pins Input Timing Parameters (Part 2 of 2) Fast Model -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial SSTL-18 GCLK t 1.417 1.417 3.118 ns SU CLASS I t -1.312 -1.312 -2.841 ns H t 2.836 2.836 6.190 ns GCLK PLL SU t -2.731 -2.731 -5.913 ns H SSTL-18 GCLK t 1.417 1.417 3.118 ns SU CLASS II t -1.312 -1.312 -2.841 ns H GCLK PLL t 2.836 2.836 6.190 ns SU t -2.731 -2.731 -5.913 ns H 1.8-V HSTL t 1.417 1.417 3.118 ns GCLK SU CLASS I t -1.312 -1.312 -2.841 ns H GCLK PLL t 2.836 2.836 6.190 ns SU t -2.731 -2.731 -5.913 ns H 1.8-V HSTL t 1.417 1.417 3.118 ns GCLK SU CLASS II t -1.312 -1.312 -2.841 ns H GCLK PLL t 2.836 2.836 6.190 ns SU t -2.731 -2.731 -5.913 ns H 1.5-V HSTL GCLK t 1.443 1.443 3.246 ns SU CLASS I t -1.338 -1.338 -2.969 ns H t 2.862 2.862 6.318 ns GCLK PLL SU t -2.757 -2.757 -6.041 ns H 1.5-V HSTL GCLK t 1.443 1.443 3.246 ns SU CLASS II t -1.338 -1.338 -2.969 ns H t 2.862 2.862 6.318 ns GCLK PLL SU t -2.757 -2.757 -6.041 ns H LVDS GCLK t 1.341 1.341 3.088 ns SU t -1.236 -1.236 -2.811 ns H GCLK PLL t 2.769 2.769 6.171 ns SU t -2.664 -2.664 -5.894 ns H 4–48 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–50 describes I/O timing specifications. Table 4–50. EP1AGX20 Column Pins Input Timing Parameters (Part 1 of 3) Fast Corner -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial 3.3-V LVTTL GCLK t 1.251 1.251 2.915 ns SU t -1.146 -1.146 -2.638 ns H t 2.693 2.693 6.021 ns GCLK PLL SU t -2.588 -2.588 -5.744 ns H 3.3-V GCLK t 1.251 1.251 2.915 ns SU LVCMOS t -1.146 -1.146 -2.638 ns H GCLK PLL t 2.693 2.693 6.021 ns SU t -2.588 -2.588 -5.744 ns H 2.5 V t 1.261 1.261 2.897 ns GCLK SU t -1.156 -1.156 -2.620 ns H GCLK PLL t 2.703 2.703 6.003 ns SU t -2.598 -2.598 -5.726 ns H 1.8 V t 1.327 1.327 3.107 ns GCLK SU t -1.222 -1.222 -2.830 ns H GCLK PLL t 2.769 2.769 6.213 ns SU t -2.664 -2.664 -5.936 ns H 1.5 V GCLK t 1.330 1.330 3.200 ns SU t -1.225 -1.225 -2.923 ns H t 2.772 2.772 6.306 ns GCLK PLL SU t -2.667 -2.667 -6.029 ns H SSTL-2 GCLK t 1.075 1.075 2.372 ns SU CLASS I t -0.970 -0.970 -2.095 ns H t 2.517 2.517 5.480 ns GCLK PLL SU t -2.412 -2.412 -5.203 ns H SSTL-2 GCLK t 1.075 1.075 2.372 ns SU CLASS II t -0.970 -0.970 -2.095 ns H GCLK PLL t 2.517 2.517 5.480 ns SU t -2.412 -2.412 -5.203 ns H Altera Corporation 4–49 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–50. EP1AGX20 Column Pins Input Timing Parameters (Part 2 of 3) Fast Corner -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial SSTL-18 GCLK t 1.113 1.113 2.479 ns SU CLASS I t -1.008 -1.008 -2.202 ns H t 2.555 2.555 5.585 ns GCLK PLL SU t -2.450 -2.450 -5.308 ns H SSTL-18 GCLK t 1.114 1.114 2.479 ns SU CLASS II t -1.009 -1.009 -2.202 ns H GCLK PLL t 2.556 2.556 5.587 ns SU t -2.451 -2.451 -5.310 ns H 1.8-V HSTL t 1.113 1.113 2.479 ns GCLK SU CLASS I t -1.008 -1.008 -2.202 ns H GCLK PLL t 2.555 2.555 5.585 ns SU t -2.450 -2.450 -5.308 ns H 1.8-V HSTL t 1.114 1.114 2.479 ns GCLK SU CLASS II t -1.009 -1.009 -2.202 ns H GCLK PLL t 2.556 2.556 5.587 ns SU t -2.451 -2.451 -5.310 ns H 1.5-V HSTL GCLK t 1.131 1.131 2.607 ns SU CLASS I t -1.026 -1.026 -2.330 ns H t 2.573 2.573 5.713 ns GCLK PLL SU t -2.468 -2.468 -5.436 ns H 1.5-V HSTL GCLK t 1.132 1.132 2.607 ns SU CLASS II t -1.027 -1.027 -2.330 ns H t 2.574 2.574 5.715 ns GCLK PLL SU t -2.469 -2.469 -5.438 ns H 3.3-V PCI GCLK t 1.256 1.256 2.903 ns SU t -1.151 -1.151 -2.626 ns H GCLK PLL t 2.698 2.698 6.009 ns SU t -2.593 -2.593 -5.732 ns H 4–50 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–50. EP1AGX20 Column Pins Input Timing Parameters (Part 3 of 3) Fast Corner -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial 3.3-V PCI-X GCLK t 1.256 1.256 2.903 ns SU t -1.151 -1.151 -2.626 ns H t 2.698 2.698 6.009 ns GCLK PLL SU t -2.593 -2.593 -5.732 ns H LVDS GCLK t 1.106 1.106 2.489 ns SU t -1.001 -1.001 -2.212 ns H GCLK PLL t 2.530 2.530 5.564 ns SU t -2.425 -2.425 -5.287 ns H Table 4–51 describes I/O timing specifications. Table 4–51. EP1AGX20 Row Pins Output Timing Parameters (Part 1 of 3) Fast Model I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 3.3-V 4mA t 2.904 2.904 6.699 ns GCLK CO LVTTL GCLK PLL t 1.485 1.485 3.627 ns CO 3.3-V 8mA GCLK t 2.776 2.776 6.059 ns CO LVTTL GCLK PLL t 1.357 1.357 2.987 ns CO 3.3-V 12 mA t 2.720 2.720 6.022 ns GCLK CO LVTTL t 1.301 1.301 2.950 ns GCLK PLL CO 3.3-V 4mA GCLK t 2.776 2.776 6.059 ns CO LVCMOS GCLK PLL t 1.357 1.357 2.987 ns CO 3.3-V 8mA GCLK t 2.670 2.670 5.753 ns CO LVCMOS t 1.251 1.251 2.681 ns GCLK PLL CO 2.5 V 4 mA t 2.759 2.759 6.033 ns GCLK CO GCLK PLL t 1.340 1.340 2.961 ns CO 2.5 V 8 mA GCLK t 2.656 2.656 5.775 ns CO GCLK PLL t 1.237 1.237 2.703 ns CO 2.5 V 12 mA t 2.637 2.637 5.661 ns GCLK CO t 1.218 1.218 2.589 ns GCLK PLL CO Altera Corporation 4–51 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–51. EP1AGX20 Row Pins Output Timing Parameters (Part 2 of 3) Fast Model I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.8 V 2 mA GCLK t 2.829 2.829 7.052 ns CO GCLK PLL t 1.410 1.410 3.980 ns CO 1.8 V 4 mA t 2.818 2.818 6.273 ns GCLK CO t 1.399 1.399 3.201 ns GCLK PLL CO 1.8 V 6 mA GCLK t 2.707 2.707 5.972 ns CO GCLK PLL t 1.288 1.288 2.900 ns CO 1.8 V 8 mA GCLK t 2.676 2.676 5.858 ns CO t 1.257 1.257 2.786 ns GCLK PLL CO 1.5 V 2 mA t 2.789 2.789 6.551 ns GCLK CO GCLK PLL t 1.370 1.370 3.479 ns CO 1.5 V 4 mA GCLK t 2.682 2.682 5.950 ns CO GCLK PLL t 1.263 1.263 2.878 ns CO SSTL-2 8mA t 2.626 2.626 5.614 ns GCLK CO CLASS I t 1.207 1.207 2.542 ns GCLK PLL CO SSTL-2 12 mA GCLK t 2.602 2.602 5.538 ns CO CLASS I GCLK PLL t 1.183 1.183 2.466 ns CO SSTL-2 16 mA GCLK t 2.568 2.568 5.407 ns CO CLASS II t 1.149 1.149 2.335 ns GCLK PLL CO SSTL-18 4mA t 2.614 2.614 5.556 ns GCLK CO CLASS I GCLK PLL t 1.195 1.195 2.484 ns CO SSTL-18 6mA GCLK t 2.618 2.618 5.485 ns CO CLASS I GCLK PLL t 1.199 1.199 2.413 ns CO SSTL-18 8mA t 2.594 2.594 5.468 ns GCLK CO CLASS I t 1.175 1.175 2.396 ns GCLK PLL CO SSTL-18 10 mA GCLK t 2.597 2.597 5.447 ns CO CLASS I GCLK PLL t 1.178 1.178 2.375 ns CO 1.8-V HSTL 4mA GCLK t 2.595 2.595 5.466 ns CO CLASS I t 1.176 1.176 2.394 ns GCLK PLL CO 1.8-V HSTL 6mA t 2.598 2.598 5.430 ns GCLK CO CLASS I GCLK PLL t 1.179 1.179 2.358 ns CO 4–52 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–51. EP1AGX20 Row Pins Output Timing Parameters (Part 3 of 3) Fast Model I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.8-V HSTL 8mA GCLK t 2.580 2.580 5.426 ns CO CLASS I GCLK PLL t 1.161 1.161 2.354 ns CO 1.8-V HSTL 10 mA t 2.584 2.584 5.415 ns GCLK CO CLASS I t 1.165 1.165 2.343 ns GCLK PLL CO 1.8-V HSTL 12 mA GCLK t 2.575 2.575 5.414 ns CO CLASS I GCLK PLL t 1.156 1.156 2.342 ns CO 1.5-V HSTL 4mA GCLK t 2.594 2.594 5.443 ns CO CLASS I t 1.175 1.175 2.371 ns GCLK PLL CO 1.5-V HSTL 6mA t 2.597 2.597 5.429 ns GCLK CO CLASS I GCLK PLL t 1.178 1.178 2.357 ns CO 1.5-V HSTL 8mA GCLK t 2.582 2.582 5.421 ns CO CLASS I GCLK PLL t 1.163 1.163 2.349 ns CO LVDS - t 2.654 2.654 5.613 ns GCLK CO t 1.226 1.226 2.530 ns GCLK PLL CO Table 4–52 describes I/O timing specifications. Table 4–52. EP1AGX20 Column Pins Output Timing Parameters (Part 1 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 3.3-V 4mA GCLK t 2.909 2.909 6.541 ns CO LVTTL GCLK PLL t 1.467 1.467 3.435 ns CO 3.3-V 8 mA GCLK t 2.764 2.764 6.169 ns CO LVTTL t 1.322 1.322 3.063 ns GCLK PLL CO 3.3-V 12 mA t 2.697 2.697 6.169 ns GCLK CO LVTTL GCLK PLL t 1.255 1.255 3.063 ns CO 3.3-V 16 mA GCLK t 2.671 2.671 6.000 ns CO LVTTL GCLK PLL t 1.229 1.229 2.894 ns CO 3.3-V 20 mA t 2.649 2.649 5.875 ns GCLK CO LVTTL t 1.207 1.207 2.769 ns GCLK PLL CO Altera Corporation 4–53 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–52. EP1AGX20 Column Pins Output Timing Parameters (Part 2 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 3.3-V 24 mA GCLK t 2.642 2.642 5.877 ns CO LVTTL GCLK PLL t 1.200 1.200 2.771 ns CO 3.3-V 4mA t 2.764 2.764 6.169 ns GCLK CO LVCMOS t 1.322 1.322 3.063 ns GCLK PLL CO 3.3-V 8mA GCLK t 2.672 2.672 5.874 ns CO LVCMOS GCLK PLL t 1.230 1.230 2.768 ns CO 3.3-V 12 mA GCLK t 2.644 2.644 5.796 ns CO LVCMOS t 1.202 1.202 2.690 ns GCLK PLL CO 3.3-V 16 mA t 2.651 2.651 5.764 ns GCLK CO LVCMOS GCLK PLL t 1.209 1.209 2.658 ns CO 3.3-V 20 mA GCLK t 2.638 2.638 5.746 ns CO LVCMOS GCLK PLL t 1.196 1.196 2.640 ns CO 3.3-V 24 mA t 2.627 2.627 5.724 ns GCLK CO LVCMOS t 1.185 1.185 2.618 ns GCLK PLL CO 2.5 V 4 mA GCLK t 2.726 2.726 6.201 ns CO GCLK PLL t 1.284 1.284 3.095 ns CO 2.5 V 8 mA GCLK t 2.674 2.674 5.939 ns CO t 1.232 1.232 2.833 ns GCLK PLL CO 2.5 V 12 mA t 2.653 2.653 5.822 ns GCLK CO GCLK PLL t 1.211 1.211 2.716 ns CO 2.5 V 16 mA GCLK t 2.635 2.635 5.748 ns CO GCLK PLL t 1.193 1.193 2.642 ns CO 1.8 V 2 mA t 2.766 2.766 7.193 ns GCLK CO t 1.324 1.324 4.087 ns GCLK PLL CO 1.8 V 4 mA GCLK t 2.771 2.771 6.419 ns CO GCLK PLL t 1.329 1.329 3.313 ns CO 1.8 V 6 mA GCLK t 2.695 2.695 6.155 ns CO t 1.253 1.253 3.049 ns GCLK PLL CO 1.8 V 8 mA t 2.697 2.697 6.064 ns GCLK CO GCLK PLL t 1.255 1.255 2.958 ns CO 4–54 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–52. EP1AGX20 Column Pins Output Timing Parameters (Part 3 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.8 V 10 mA GCLK t 2.651 2.651 5.987 ns CO GCLK PLL t 1.209 1.209 2.881 ns CO 1.8 V 12 mA t 2.652 2.652 5.930 ns GCLK CO t 1.210 1.210 2.824 ns GCLK PLL CO 1.5 V 2 mA GCLK t 2.746 2.746 6.723 ns CO GCLK PLL t 1.304 1.304 3.617 ns CO 1.5 V 4 mA GCLK t 2.682 2.682 6.154 ns CO t 1.240 1.240 3.048 ns GCLK PLL CO 1.5 V 6 mA t 2.685 2.685 6.036 ns GCLK CO GCLK PLL t 1.243 1.243 2.930 ns CO 1.5 V 8 mA GCLK t 2.644 2.644 5.983 ns CO GCLK PLL t 1.202 1.202 2.877 ns CO SSTL-2 8mA t 2.629 2.629 5.762 ns GCLK CO CLASS I t 1.184 1.184 2.650 ns GCLK PLL CO SSTL-2 12 mA GCLK t 2.612 2.612 5.712 ns CO CLASS I GCLK PLL t 1.167 1.167 2.600 ns CO SSTL-2 16 mA GCLK t 2.590 2.590 5.639 ns CO CLASS II t 1.145 1.145 2.527 ns GCLK PLL CO SSTL-2 20 mA t 2.591 2.591 5.626 ns GCLK CO CLASS II GCLK PLL t 1.146 1.146 2.514 ns CO SSTL-2 24 mA GCLK t 2.587 2.587 5.624 ns CO CLASS II GCLK PLL t 1.142 1.142 2.512 ns CO SSTL-18 4mA t 2.626 2.626 5.733 ns GCLK CO CLASS I t 1.184 1.184 2.627 ns GCLK PLL CO SSTL-18 6mA GCLK t 2.630 2.630 5.694 ns CO CLASS I GCLK PLL t 1.185 1.185 2.582 ns CO SSTL-18 8mA GCLK t 2.609 2.609 5.675 ns CO CLASS I t 1.164 1.164 2.563 ns GCLK PLL CO SSTL-18 10 mA t 2.614 2.614 5.673 ns GCLK CO CLASS I GCLK PLL t 1.169 1.169 2.561 ns CO Altera Corporation 4–55 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–52. EP1AGX20 Column Pins Output Timing Parameters (Part 4 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial SSTL-18 12 mA GCLK t 2.608 2.608 5.659 ns CO CLASS I GCLK PLL t 1.163 1.163 2.547 ns CO SSTL-18 8mA t 2.597 2.597 5.625 ns GCLK CO CLASS II t 1.152 1.152 2.513 ns GCLK PLL CO SSTL-18 16 mA GCLK t 2.609 2.609 5.603 ns CO CLASS II GCLK PLL t 1.164 1.164 2.491 ns CO SSTL-18 18 mA GCLK t 2.605 2.605 5.611 ns CO CLASS II t 1.160 1.160 2.499 ns GCLK PLL CO SSTL-18 20 mA t 2.605 2.605 5.609 ns GCLK CO CLASS II GCLK PLL t 1.160 1.160 2.497 ns CO 1.8-V HSTL 4mA GCLK t 2.629 2.629 5.664 ns CO CLASS I GCLK PLL t 1.187 1.187 2.558 ns CO 1.8-V HSTL 6mA t 2.634 2.634 5.649 ns GCLK CO CLASS I t 1.189 1.189 2.537 ns GCLK PLL CO 1.8-V HSTL 8mA GCLK t 2.612 2.612 5.638 ns CO CLASS I GCLK PLL t 1.167 1.167 2.526 ns CO 1.8-V HSTL 10 mA GCLK t 2.616 2.616 5.644 ns CO CLASS I t 1.171 1.171 2.532 ns GCLK PLL CO 1.8-V HSTL 12 mA t 2.608 2.608 5.637 ns GCLK CO CLASS I GCLK PLL t 1.163 1.163 2.525 ns CO 1.8-V HSTL 16 mA GCLK t 2.591 2.591 5.401 ns CO CLASS II GCLK PLL t 1.146 1.146 2.289 ns CO 1.8-V HSTL 18 mA t 2.593 2.593 5.412 ns GCLK CO CLASS II t 1.148 1.148 2.300 ns GCLK PLL CO 1.8-V HSTL 20 mA GCLK t 2.593 2.593 5.421 ns CO CLASS II GCLK PLL t 1.148 1.148 2.309 ns CO 1.5-V HSTL 4mA GCLK t 2.629 2.629 5.663 ns CO CLASS I t 1.187 1.187 2.557 ns GCLK PLL CO 1.5-V HSTL 6mA t 2.633 2.633 5.641 ns GCLK CO CLASS I GCLK PLL t 1.188 1.188 2.529 ns CO 4–56 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–52. EP1AGX20 Column Pins Output Timing Parameters (Part 5 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.5-V HSTL 8mA GCLK t 2.615 2.615 5.643 ns CO CLASS I GCLK PLL t 1.170 1.170 2.531 ns CO 1.5-V HSTL 10 mA t 2.615 2.615 5.645 ns GCLK CO CLASS I t 1.170 1.170 2.533 ns GCLK PLL CO 1.5-V HSTL 12 mA GCLK t 2.609 2.609 5.643 ns CO CLASS I GCLK PLL t 1.164 1.164 2.531 ns CO 1.5-V HSTL 16 mA GCLK t 2.596 2.596 5.455 ns CO CLASS II t 1.151 1.151 2.343 ns GCLK PLL CO 1.5-V HSTL 18 mA t 2.599 2.599 5.465 ns GCLK CO CLASS II GCLK PLL t 1.154 1.154 2.353 ns CO 1.5-V HSTL 20 mA GCLK t 2.601 2.601 5.478 ns CO CLASS II GCLK PLL t 1.156 1.156 2.366 ns CO 3.3-V PCI - t 2.755 2.755 5.791 ns GCLK CO t 1.313 1.313 2.685 ns GCLK PLL CO 3.3-V PCI-X - GCLK t 2.755 2.755 5.791 ns CO GCLK PLL t 1.313 1.313 2.685 ns CO LVDS - GCLK t 3.621 3.621 6.969 ns CO t 2.190 2.190 3.880 ns GCLK PLL CO Tables 4–53 through 4–54 shows EP1AGX35 regional clock (RCLK) adder values that should be added to GCLK values. These adder values are used to determine I/O timing when the I/O pin is driven using the regional clock. This applies for all I/O standards supported by Arria GX with general purpose I/O pins. Altera Corporation 4–57 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–53 describes row pin delay adders when using the regional clock in Arria GX devices. Table 4–53. EP1AGX35 Row Pin Delay Adders for Regional Clock Fast Corner -6 Speed Parameter Units Grade Industrial Commercial input 0.126 0.126 0.281 ns RCLK adder 0.011 0.011 0.018 ns RCLK PLL input adder RCLK output -0.126 -0.126 -0.281 ns adder RCLK PLL -0.011 -0.011 -0.018 ns output adder Table 4–54 describes column pin delay adders when using the regional clock in Arria GX devices. Table 4–54. EP1AGX35 Column Pin Delay Adders for Regional Clock Fast Corner -6 Speed Parameter Units Grade Industrial Commercial input 0.099 0.099 0.254 ns RCLK adder -0.012 -0.012 -0.01 ns RCLK PLL input adder RCLK output -0.086 -0.086 -0.244 ns adder RCLK PLL 1.253 1.253 3.133 ns output adder EP1AGX50I/O Timing Parameters Tables 4–55 through 4–58 show the maximum I/O timing parameters for EP1AGX50 devices for I/O standards which support general purpose I/O pins. 4–58 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–55 describes I/O timing specifications. Table 4–55. EP1AGX35 Row Pins Input Timing Parameters (Part 1 of 2) Fast Model -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial 3.3-V LVTTL GCLK t 1.550 1.550 3.542 ns SU t -1.445 -1.445 -3.265 ns H t 2.978 2.978 6.626 ns GCLK PLL SU t -2.873 -2.873 -6.349 ns H 3.3-V GCLK t 1.550 1.550 3.542 ns SU LVCMOS t -1.445 -1.445 -3.265 ns H GCLK PLL t 2.978 2.978 6.626 ns SU t -2.873 -2.873 -6.349 ns H 2.5 V t 1.562 1.562 3.523 ns GCLK SU t -1.457 -1.457 -3.246 ns H GCLK PLL t 2.990 2.990 6.607 ns SU t -2.885 -2.885 -6.330 ns H 1.8 V t 1.628 1.628 3.730 ns GCLK SU t -1.523 -1.523 -3.453 ns H GCLK PLL t 3.056 3.056 6.814 ns SU t -2.951 -2.951 -6.537 ns H 1.5 V GCLK t 1.631 1.631 3.825 ns SU t -1.526 -1.526 -3.548 ns H t 3.059 3.059 6.909 ns GCLK PLL SU t -2.954 -2.954 -6.632 ns H SSTL-2 GCLK t 1.375 1.375 2.997 ns SU CLASS I t -1.270 -1.270 -2.720 ns H t 2.802 2.802 6.079 ns GCLK PLL SU t -2.697 -2.697 -5.802 ns H SSTL-2 GCLK t 1.375 1.375 2.997 ns SU CLASS II t -1.270 -1.270 -2.720 ns H GCLK PLL t 2.802 2.802 6.079 ns SU t -2.697 -2.697 -5.802 ns H Altera Corporation 4–59 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–55. EP1AGX35 Row Pins Input Timing Parameters (Part 2 of 2) Fast Model -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial SSTL-18 GCLK t 1.406 1.406 3.104 ns SU CLASS I t -1.301 -1.301 -2.827 ns H t 2.834 2.834 6.188 ns GCLK PLL SU t -2.729 -2.729 -5.911 ns H SSTL-18 GCLK t 1.407 1.407 3.106 ns SU CLASS II t -1.302 -1.302 -2.829 ns H GCLK PLL t 2.834 2.834 6.188 ns SU t -2.729 -2.729 -5.911 ns H 1.8-V HSTL t 1.406 1.406 3.104 ns GCLK SU CLASS I t -1.301 -1.301 -2.827 ns H GCLK PLL t 2.834 2.834 6.188 ns SU t -2.729 -2.729 -5.911 ns H 1.8-V HSTL t 1.407 1.407 3.106 ns GCLK SU CLASS II t -1.302 -1.302 -2.829 ns H GCLK PLL t 2.834 2.834 6.188 ns SU t -2.729 -2.729 -5.911 ns H 1.5-V HSTL GCLK t 1.432 1.432 3.232 ns SU CLASS I t -1.327 -1.327 -2.955 ns H t 2.860 2.860 6.316 ns GCLK PLL SU t -2.755 -2.755 -6.039 ns H 1.5-V HSTL GCLK t 1.433 1.433 3.234 ns SU CLASS II t -1.328 -1.328 -2.957 ns H t 2.860 2.860 6.316 ns GCLK PLL SU t -2.755 -2.755 -6.039 ns H LVDS GCLK t 1.341 1.341 3.088 ns SU t -1.236 -1.236 -2.811 ns H GCLK PLL t 2.769 2.769 6.171 ns SU t -2.664 -2.664 -5.894 ns H 4–60 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–56 describes I/O timing specifications. Table 4–56. EP1AGX35 Column Pins Input Timing Parameters (Part 1 of 3) Fast Corner -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial 3.3-V LVTTL GCLK t 1.242 1.242 2.902 ns SU t -1.137 -1.137 -2.625 ns H t 2.684 2.684 6.009 ns GCLK PLL SU t -2.579 -2.579 -5.732 ns H 3.3-V GCLK t 1.242 1.242 2.902 ns SU LVCMOS t -1.137 -1.137 -2.625 ns H GCLK PLL t 2.684 2.684 6.009 ns SU t -2.579 -2.579 -5.732 ns H 2.5 V t 1.252 1.252 2.884 ns GCLK SU t -1.147 -1.147 -2.607 ns H GCLK PLL t 2.694 2.694 5.991 ns SU t -2.589 -2.589 -5.714 ns H 1.8 V t 1.318 1.318 3.094 ns GCLK SU t -1.213 -1.213 -2.817 ns H GCLK PLL t 2.760 2.760 6.201 ns SU t -2.655 -2.655 -5.924 ns H 1.5 V GCLK t 1.321 1.321 3.187 ns SU t -1.216 -1.216 -2.910 ns H t 2.763 2.763 6.294 ns GCLK PLL SU t -2.658 -2.658 -6.017 ns H SSTL-2 GCLK t 1.034 1.034 2.314 ns SU CLASS I t -0.929 -0.929 -2.037 ns H t 2.500 2.500 5.457 ns GCLK PLL SU t -2.395 -2.395 -5.180 ns H SSTL-2 GCLK t 1.034 1.034 2.314 ns SU CLASS II t -0.929 -0.929 -2.037 ns H GCLK PLL t 2.500 2.500 5.457 ns SU t -2.395 -2.395 -5.180 ns H Altera Corporation 4–61 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–56. EP1AGX35 Column Pins Input Timing Parameters (Part 2 of 3) Fast Corner -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial SSTL-18 GCLK t 1.104 1.104 2.466 ns SU CLASS I t -0.999 -0.999 -2.189 ns H t 2.546 2.546 5.573 ns GCLK PLL SU t -2.441 -2.441 -5.296 ns H SSTL-18 GCLK t 1.074 1.074 2.424 ns SU CLASS II t -0.969 -0.969 -2.147 ns H GCLK PLL t 2.539 2.539 5.564 ns SU t -2.434 -2.434 -5.287 ns H 1.8-V HSTL t 1.104 1.104 2.466 ns GCLK SU CLASS I t -0.999 -0.999 -2.189 ns H GCLK PLL t 2.546 2.546 5.573 ns SU t -2.441 -2.441 -5.296 ns H 1.8-V HSTL t 1.074 1.074 2.424 ns GCLK SU CLASS II t -0.969 -0.969 -2.147 ns H GCLK PLL t 2.539 2.539 5.564 ns SU t -2.434 -2.434 -5.287 ns H 1.5-V HSTL GCLK t 1.122 1.122 2.594 ns SU CLASS I t -1.017 -1.017 -2.317 ns H t 2.564 2.564 5.701 ns GCLK PLL SU t -2.459 -2.459 -5.424 ns H 1.5-V HSTL GCLK t 1.094 1.094 2.557 ns SU CLASS II t -0.989 -0.989 -2.280 ns H t 2.557 2.557 5.692 ns GCLK PLL SU t -2.452 -2.452 -5.415 ns H 3.3-V PCI GCLK t 1.247 1.247 2.890 ns SU t -1.142 -1.142 -2.613 ns H GCLK PLL t 2.689 2.689 5.997 ns SU t -2.584 -2.584 -5.720 ns H 4–62 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–56. EP1AGX35 Column Pins Input Timing Parameters (Part 3 of 3) Fast Corner -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial 3.3-V PCI-X GCLK t 1.247 1.247 2.890 ns SU t -1.142 -1.142 -2.613 ns H t 2.689 2.689 5.997 ns GCLK PLL SU t -2.584 -2.584 -5.720 ns H LVDS GCLK t 1.106 1.106 2.489 ns SU t -1.001 -1.001 -2.212 ns H GCLK PLL t 2.530 2.530 5.564 ns SU t -2.425 -2.425 -5.287 ns H Table 4–57 describes I/O timing specifications. Table 4–57. EP1AGX35 Row Pins Output Timing Parameters (Part 1 of 3) Fast Model I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 3.3-V 4mA t 2.915 2.915 6.713 ns GCLK CO LVTTL GCLK PLL t 1.487 1.487 3.629 ns CO 3.3-V 8mA GCLK t 2.787 2.787 6.073 ns CO LVTTL GCLK PLL t 1.359 1.359 2.989 ns CO 3.3-V 12 mA t 2.731 2.731 6.036 ns GCLK CO LVTTL t 1.303 1.303 2.952 ns GCLK PLL CO 3.3-V 4mA GCLK t 2.787 2.787 6.073 ns CO LVCMOS GCLK PLL t 1.359 1.359 2.989 ns CO 3.3-V 8mA GCLK t 2.681 2.681 5.767 ns CO LVCMOS t 1.253 1.253 2.683 ns GCLK PLL CO 2.5 V 4 mA t 2.770 2.770 6.047 ns GCLK CO GCLK PLL t 1.342 1.342 2.963 ns CO 2.5 V 8 mA GCLK t 2.667 2.667 5.789 ns CO GCLK PLL t 1.239 1.239 2.705 ns CO 2.5 V 12 mA t 2.648 2.648 5.675 ns GCLK CO t 1.220 1.220 2.591 ns GCLK PLL CO Altera Corporation 4–63 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–57. EP1AGX35 Row Pins Output Timing Parameters (Part 2 of 3) Fast Model I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.8 V 2 mA GCLK t 2.840 2.840 7.066 ns CO GCLK PLL t 1.412 1.412 3.982 ns CO 1.8 V 4 mA t 2.829 2.829 6.287 ns GCLK CO t 1.401 1.401 3.203 ns GCLK PLL CO 1.8 V 6 mA GCLK t 2.718 2.718 5.986 ns CO GCLK PLL t 1.290 1.290 2.902 ns CO 1.8 V 8 mA GCLK t 2.687 2.687 5.872 ns CO t 1.259 1.259 2.788 ns GCLK PLL CO 1.5 V 2 mA t 2.800 2.800 6.565 ns GCLK CO GCLK PLL t 1.372 1.372 3.481 ns CO 1.5 V 4 mA GCLK t 2.693 2.693 5.964 ns CO GCLK PLL t 1.265 1.265 2.880 ns CO SSTL-2 8mA t 2.636 2.636 5.626 ns GCLK CO CLASS I t 1.209 1.209 2.544 ns GCLK PLL CO SSTL-2 12 mA GCLK t 2.612 2.612 5.550 ns CO CLASS I GCLK PLL t 1.185 1.185 2.468 ns CO SSTL-2 16 mA GCLK t 2.578 2.578 5.419 ns CO CLASS II t 1.151 1.151 2.337 ns GCLK PLL CO SSTL-18 4mA t 2.625 2.625 5.570 ns GCLK CO CLASS I GCLK PLL t 1.197 1.197 2.486 ns CO SSTL-18 6mA GCLK t 2.628 2.628 5.497 ns CO CLASS I GCLK PLL t 1.201 1.201 2.415 ns CO SSTL-18 8mA t 2.604 2.604 5.480 ns GCLK CO CLASS I t 1.177 1.177 2.398 ns GCLK PLL CO SSTL-18 10 mA GCLK t 2.607 2.607 5.459 ns CO CLASS I GCLK PLL t 1.180 1.180 2.377 ns CO 1.8-V HSTL 4mA GCLK t 2.606 2.606 5.480 ns CO CLASS I t 1.178 1.178 2.396 ns GCLK PLL CO 1.8-V HSTL 6mA t 2.608 2.608 5.442 ns GCLK CO CLASS I GCLK PLL t 1.181 1.181 2.360 ns CO 4–64 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–57. EP1AGX35 Row Pins Output Timing Parameters (Part 3 of 3) Fast Model I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.8-V HSTL 8mA GCLK t 2.590 2.590 5.438 ns CO CLASS I GCLK PLL t 1.163 1.163 2.356 ns CO 1.8-V HSTL 10 mA t 2.594 2.594 5.427 ns GCLK CO CLASS I t 1.167 1.167 2.345 ns GCLK PLL CO 1.8-V HSTL 12 mA GCLK t 2.585 2.585 5.426 ns CO CLASS I GCLK PLL t 1.158 1.158 2.344 ns CO 1.5-V HSTL 4mA GCLK t 2.605 2.605 5.457 ns CO CLASS I t 1.177 1.177 2.373 ns GCLK PLL CO 1.5-V HSTL 6mA t 2.607 2.607 5.441 ns GCLK CO CLASS I GCLK PLL t 1.180 1.180 2.359 ns CO 1.5-V HSTL 8mA GCLK t 2.592 2.592 5.433 ns CO CLASS I GCLK PLL t 1.165 1.165 2.351 ns CO LVDS - t 2.654 2.654 5.613 ns GCLK CO t 1.226 1.226 2.530 ns GCLK PLL CO Table 4–58 describes I/O timing specifications. Table 4–58. EP1AGX35 Column Pins Output Timing Parameters (Part 1 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 3.3-V 4mA GCLK t 2.948 2.948 6.608 ns CO LVTTL GCLK PLL t 1.476 1.476 3.447 ns CO 3.3-V 8mA GCLK t 2.797 2.797 6.203 ns CO LVTTL t 1.331 1.331 3.075 ns GCLK PLL CO 3.3-V 12 mA t 2.722 2.722 6.204 ns GCLK CO LVTTL GCLK PLL t 1.264 1.264 3.075 ns CO 3.3-V 16 mA GCLK t 2.694 2.694 6.024 ns CO LVTTL GCLK PLL t 1.238 1.238 2.906 ns CO 3.3-V 20 mA t 2.670 2.670 5.896 ns GCLK CO LVTTL t 1.216 1.216 2.781 ns GCLK PLL CO Altera Corporation 4–65 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–58. EP1AGX35 Column Pins Output Timing Parameters (Part 2 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 3.3-V 24 mA GCLK t 2.660 2.660 5.895 ns CO LVTTL GCLK PLL t 1.209 1.209 2.783 ns CO 3.3-V 4mA t 2.797 2.797 6.203 ns GCLK CO LVCMOS t 1.331 1.331 3.075 ns GCLK PLL CO 3.3-V 8mA GCLK t 2.695 2.695 5.893 ns CO LVCMOS GCLK PLL t 1.239 1.239 2.780 ns CO 3.3-V 12 mA GCLK t 2.663 2.663 5.809 ns CO LVCMOS t 1.211 1.211 2.702 ns GCLK PLL CO 3.3-V 16 mA t 2.666 2.666 5.776 ns GCLK CO LVCMOS GCLK PLL t 1.218 1.218 2.670 ns CO 3.3-V 20 mA GCLK t 2.651 2.651 5.758 ns CO LVCMOS GCLK PLL t 1.205 1.205 2.652 ns CO 3.3-V 24 mA t 2.638 2.638 5.736 ns GCLK CO LVCMOS t 1.194 1.194 2.630 ns GCLK PLL CO 2.5 V 4 mA GCLK t 2.754 2.754 6.240 ns CO GCLK PLL t 1.293 1.293 3.107 ns CO 2.5 V 8 mA GCLK t 2.697 2.697 5.963 ns CO t 1.241 1.241 2.845 ns GCLK PLL CO 2.5 V 12 mA t 2.672 2.672 5.837 ns GCLK CO GCLK PLL t 1.220 1.220 2.728 ns CO 2.5 V 16 mA GCLK t 2.654 2.654 5.760 ns CO GCLK PLL t 1.202 1.202 2.654 ns CO 1.8 V 2 mA t 2.804 2.804 7.295 ns GCLK CO t 1.333 1.333 4.099 ns GCLK PLL CO 1.8 V 4 mA GCLK t 2.808 2.808 6.479 ns CO GCLK PLL t 1.338 1.338 3.325 ns CO 1.8 V 6 mA GCLK t 2.717 2.717 6.195 ns CO t 1.262 1.262 3.061 ns GCLK PLL CO 1.8 V 8 mA t 2.719 2.719 6.098 ns GCLK CO GCLK PLL t 1.264 1.264 2.970 ns CO 4–66 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–58. EP1AGX35 Column Pins Output Timing Parameters (Part 3 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.8 V 10 mA GCLK t 2.671 2.671 6.012 ns CO GCLK PLL t 1.218 1.218 2.893 ns CO 1.8 V 12 mA t 2.671 2.671 5.953 ns GCLK CO t 1.219 1.219 2.836 ns GCLK PLL CO 1.5 V 2 mA GCLK t 2.779 2.779 6.815 ns CO GCLK PLL t 1.313 1.313 3.629 ns CO 1.5 V 4 mA GCLK t 2.703 2.703 6.210 ns CO t 1.249 1.249 3.060 ns GCLK PLL CO 1.5 V 6 mA t 2.705 2.705 6.118 ns GCLK CO GCLK PLL t 1.252 1.252 2.942 ns CO 1.5 V 8 mA GCLK t 2.660 2.660 6.014 ns CO GCLK PLL t 1.211 1.211 2.889 ns CO SSTL-2 8mA t 2.648 2.648 5.777 ns GCLK CO CLASS I t 1.202 1.202 2.675 ns GCLK PLL CO SSTL-2 12 mA GCLK t 2.628 2.628 5.722 ns CO CLASS I GCLK PLL t 1.185 1.185 2.625 ns CO SSTL-2 16 mA GCLK t 2.606 2.606 5.649 ns CO CLASS II t 1.163 1.163 2.552 ns GCLK PLL CO SSTL-2 20 mA t 2.606 2.606 5.636 ns GCLK CO CLASS II GCLK PLL t 1.164 1.164 2.539 ns CO SSTL-2 24 mA GCLK t 2.601 2.601 5.634 ns CO CLASS II GCLK PLL t 1.160 1.160 2.537 ns CO SSTL-18 4mA t 2.643 2.643 5.749 ns GCLK CO CLASS I t 1.193 1.193 2.639 ns GCLK PLL CO SSTL-18 6mA GCLK t 2.649 2.649 5.708 ns CO CLASS I GCLK PLL t 1.203 1.203 2.607 ns CO SSTL-18 8mA GCLK t 2.626 2.626 5.686 ns CO CLASS I t 1.182 1.182 2.588 ns GCLK PLL CO SSTL-18 10 mA t 2.630 2.630 5.685 ns GCLK CO CLASS I GCLK PLL t 1.187 1.187 2.586 ns CO Altera Corporation 4–67 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–58. EP1AGX35 Column Pins Output Timing Parameters (Part 4 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial SSTL-18 12 mA GCLK t 2.625 2.625 5.669 ns CO CLASS I GCLK PLL t 1.181 1.181 2.572 ns CO SSTL-18 8mA t 2.614 2.614 5.635 ns GCLK CO CLASS II t 1.170 1.170 2.538 ns GCLK PLL CO SSTL-18 16 mA GCLK t 2.623 2.623 5.613 ns CO CLASS II GCLK PLL t 1.182 1.182 2.516 ns CO SSTL-18 18 mA GCLK t 2.616 2.616 5.621 ns CO CLASS II t 1.178 1.178 2.524 ns GCLK PLL CO SSTL-18 20 mA t 2.616 2.616 5.619 ns GCLK CO CLASS II GCLK PLL t 1.178 1.178 2.522 ns CO 1.8-V HSTL 4mA GCLK t 2.637 2.637 5.676 ns CO CLASS I GCLK PLL t 1.196 1.196 2.570 ns CO 1.8-V HSTL 6mA t 2.645 2.645 5.659 ns GCLK CO CLASS I t 1.207 1.207 2.562 ns GCLK PLL CO 1.8-V HSTL 8mA GCLK t 2.623 2.623 5.648 ns CO CLASS I GCLK PLL t 1.185 1.185 2.551 ns CO 1.8-V HSTL 10 mA GCLK t 2.627 2.627 5.654 ns CO CLASS I t 1.189 1.189 2.557 ns GCLK PLL CO 1.8-V HSTL 12 mA t 2.619 2.619 5.647 ns GCLK CO CLASS I GCLK PLL t 1.181 1.181 2.550 ns CO 1.8-V HSTL 16 mA GCLK t 2.602 2.602 5.574 ns CO CLASS II GCLK PLL t 1.164 1.164 2.314 ns CO 1.8-V HSTL 18 mA t 2.604 2.604 5.578 ns GCLK CO CLASS II t 1.166 1.166 2.325 ns GCLK PLL CO 1.8-V HSTL 20 mA GCLK t 2.604 2.604 5.577 ns CO CLASS II GCLK PLL t 1.166 1.166 2.334 ns CO 1.5-V HSTL 4mA GCLK t 2.637 2.637 5.675 ns CO CLASS I t 1.196 1.196 2.569 ns GCLK PLL CO 1.5-V HSTL 6mA t 2.644 2.644 5.651 ns GCLK CO CLASS I GCLK PLL t 1.206 1.206 2.554 ns CO 4–68 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–58. EP1AGX35 Column Pins Output Timing Parameters (Part 5 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.5-V HSTL 8mA GCLK t 2.626 2.626 5.653 ns CO CLASS I GCLK PLL t 1.188 1.188 2.556 ns CO 1.5-V HSTL 10 mA t 2.626 2.626 5.655 ns GCLK CO CLASS I t 1.188 1.188 2.558 ns GCLK PLL CO 1.5-V HSTL 12 mA GCLK t 2.620 2.620 5.653 ns CO CLASS I GCLK PLL t 1.182 1.182 2.556 ns CO 1.5-V HSTL 16 mA GCLK t 2.607 2.607 5.573 ns CO CLASS II t 1.169 1.169 2.368 ns GCLK PLL CO 1.5-V HSTL 18 mA t 2.610 2.610 5.571 ns GCLK CO CLASS II GCLK PLL t 1.172 1.172 2.378 ns CO 1.5-V HSTL 20 mA GCLK t 2.612 2.612 5.581 ns CO CLASS II GCLK PLL t 1.174 1.174 2.391 ns CO 3.3-V PCI - t 2.786 2.786 5.803 ns GCLK CO t 1.322 1.322 2.697 ns GCLK PLL CO 3.3-V PCI-X - GCLK t 2.786 2.786 5.803 ns CO GCLK PLL t 1.322 1.322 2.697 ns CO LVDS - GCLK t 3.621 3.621 6.969 ns CO t 2.190 2.190 3.880 ns GCLK PLL CO Tables 4–59 through 4–60 shows EP1AGX50 regional clock (RCLK) adder values that should be added to the GCLK values. These adder values are used to determine I/O timing when the I/O pin is driven using the regional clock. This applies for all I/O standards supported by Arria GX with general purpose I/O pins. Altera Corporation 4–69 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–59 describes row pin delay adders when using the regional clock in Arria GX devices. Table 4–59. EP1AGX50 Row Pin Delay Adders for Regional Clock Fast Corner -6 Speed Parameter Units Grade Industrial Commercial 0.151 0.151 0.329 ns RCLK input adder RCLK PLL 0.011 0.011 0.016 ns input adder RCLK output -0.151 -0.151 -0.329 ns adder -0.011 -0.011 -0.016 ns RCLK PLL output adder Table 4–60 describes column pin delay adders when using the regional clock in Arria GX devices. Table 4–60. EP1AGX50 Column Pin Delay Adders for Regional Clock Fast Corner -6 Speed Parameter Units Grade Industrial Commercial 0.146 0.146 0.334 ns RCLK input adder RCLK PLL -1.713 -1.713 -3.645 ns input adder RCLK output -0.146 -0.146 -0.336 ns adder 1.716 1.716 4.488 ns RCLK PLL output adder EP1AGX60I/O Timing Parameters Tables 4–61 through 4–64 show the maximum I/O timing parameters for EP1AGX60 devices for I/O standards which support general purpose I/O pins. 4–70 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–61 describes I/O timing specifications. Table 4–61. EP1AGX60 Row Pins Input Timing Parameters (Part 1 of 2) Fast Model -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial 3.3-V LVTTL GCLK t 1.413 1.413 3.113 ns SU t -1.308 -1.308 -2.836 ns H t 2.975 2.975 6.536 ns GCLK PLL SU t -2.870 -2.870 -6.259 ns H 3.3-V GCLK t 1.413 1.413 3.113 ns SU LVCMOS t -1.308 -1.308 -2.836 ns H GCLK PLL t 2.975 2.975 6.536 ns SU t -2.870 -2.870 -6.259 ns H 2.5 V t 1.425 1.425 3.094 ns GCLK SU t -1.320 -1.320 -2.817 ns H GCLK PLL t 2.987 2.987 6.517 ns SU t -2.882 -2.882 -6.240 ns H 1.8 V t 1.477 1.477 3.275 ns GCLK SU t -1.372 -1.372 -2.998 ns H GCLK PLL t 3.049 3.049 6.718 ns SU t -2.944 -2.944 -6.441 ns H 1.5 V GCLK t 1.480 1.480 3.370 ns SU t -1.375 -1.375 -3.093 ns H t 3.052 3.052 6.813 ns GCLK PLL SU t -2.947 -2.947 -6.536 ns H SSTL-2 GCLK t 1.237 1.237 2.566 ns SU CLASS I t -1.132 -1.132 -2.289 ns H tsu 2.800 2.800 5.990 ns GCLK PLL t -2.695 -2.695 -5.713 ns H SSTL-2 t 1.237 1.237 2.566 ns GCLK SU CLASS II t -1.132 -1.132 -2.289 ns H GCLK PLL t 2.800 2.800 5.990 ns SU t -2.695 -2.695 -5.713 ns H Altera Corporation 4–71 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–61. EP1AGX60 Row Pins Input Timing Parameters (Part 2 of 2) Fast Model -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial SSTL-18 GCLK t 1.255 1.255 2.649 ns SU CLASS I t -1.150 -1.150 -2.372 ns H t 2.827 2.827 6.092 ns GCLK PLL SU t -2.722 -2.722 -5.815 ns H SSTL-18 GCLK t 1.255 1.255 2.649 ns SU CLASS II t -1.150 -1.150 -2.372 ns H GCLK PLL t 2.827 2.827 6.092 ns SU t -2.722 -2.722 -5.815 ns H 1.8-V HSTL t 1.255 1.255 2.649 ns GCLK SU CLASS I t -1.150 -1.150 -2.372 ns H GCLK PLL t 2.827 2.827 6.092 ns SU t -2.722 -2.722 -5.815 ns H 1.8-V HSTL t 1.255 1.255 2.649 ns GCLK SU CLASS II t -1.150 -1.150 -2.372 ns H GCLK PLL t 2.827 2.827 6.092 ns SU t -2.722 -2.722 -5.815 ns H 1.5-V HSTL GCLK t 1.281 1.281 2.777 ns SU CLASS I t -1.176 -1.176 -2.500 ns H t 2.853 2.853 6.220 ns GCLK PLL SU t -2.748 -2.748 -5.943 ns H 1.5-V HSTL GCLK t 1.281 1.281 2.777 ns SU CLASS II t -1.176 -1.176 -2.500 ns H t 2.853 2.853 6.220 ns GCLK PLL SU t -2.748 -2.748 -5.943 ns H LVDS GCLK t 1.208 1.208 2.664 ns SU t -1.103 -1.103 -2.387 ns H GCLK PLL t 2.767 2.767 6.083 ns SU t -2.662 -2.662 -5.806 ns H 4–72 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–62 describes I/O timing specifications. Table 4–62. EP1AGX60 Column Pins Input Timing Parameters (Part 1 of 3) Fast Corner -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial 3.3-V LVTTL GCLK t 1.124 1.124 2.493 ns SU t -1.019 -1.019 -2.216 ns H t 2.694 2.694 5.928 ns GCLK PLL SU t -2.589 -2.589 -5.651 ns H 3.3-V GCLK t 1.124 1.124 2.493 ns SU LVCMOS t -1.019 -1.019 -2.216 ns H GCLK PLL t 2.694 2.694 5.928 ns SU t -2.589 -2.589 -5.651 ns H 2.5 V t 1.134 1.134 2.475 ns GCLK SU t -1.029 -1.029 -2.198 ns H GCLK PLL t 2.704 2.704 5.910 ns SU t -2.599 -2.599 -5.633 ns H 1.8 V t 1.200 1.200 2.685 ns GCLK SU t -1.095 -1.095 -2.408 ns H GCLK PLL t 2.770 2.770 6.120 ns SU t -2.665 -2.665 -5.843 ns H 1.5 V GCLK t 1.203 1.203 2.778 ns SU t -1.098 -1.098 -2.501 ns H t 2.773 2.773 6.213 ns GCLK PLL SU t -2.668 -2.668 -5.936 ns H SSTL-2 GCLK t 0.948 0.948 1.951 ns SU CLASS I t -0.843 -0.843 -1.674 ns H t 2.519 2.519 5.388 ns GCLK PLL SU t -2.414 -2.414 -5.111 ns H SSTL-2 GCLK t 0.948 0.948 1.951 ns SU CLASS II t -0.843 -0.843 -1.674 ns H GCLK PLL t 2.519 2.519 5.388 ns SU t -2.414 -2.414 -5.111 ns H Altera Corporation 4–73 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–62. EP1AGX60 Column Pins Input Timing Parameters (Part 2 of 3) Fast Corner -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial SSTL-18 GCLK t 0.986 0.986 2.057 ns SU CLASS I t -0.881 -0.881 -1.780 ns H t 2.556 2.556 5.492 ns GCLK PLL SU t -2.451 -2.451 -5.215 ns H SSTL-18 GCLK t 0.987 0.987 2.058 ns SU CLASS II t -0.882 -0.882 -1.781 ns H GCLK PLL t 2.558 2.558 5.495 ns SU t -2.453 -2.453 -5.218 ns H 1.8-V HSTL t 0.986 0.986 2.057 ns GCLK SU CLASS I t -0.881 -0.881 -1.780 ns H GCLK PLL t 2.556 2.556 5.492 ns SU t -2.451 -2.451 -5.215 ns H 1.8-V HSTL t 0.987 0.987 2.058 ns GCLK SU CLASS II t -0.882 -0.882 -1.781 ns H GCLK PLL t 2.558 2.558 5.495 ns SU t -2.453 -2.453 -5.218 ns H 1.5-V HSTL GCLK t 1.004 1.004 2.185 ns SU CLASS I t -0.899 -0.899 -1.908 ns H t 2.574 2.574 5.620 ns GCLK PLL SU t -2.469 -2.469 -5.343 ns H 1.5-V HSTL GCLK t 1.005 1.005 2.186 ns SU CLASS II t -0.900 -0.900 -1.909 ns H t 2.576 2.576 5.623 ns GCLK PLL SU t -2.471 -2.471 -5.346 ns H 3.3-V PCI GCLK t 1.129 1.129 2.481 ns SU t -1.024 -1.024 -2.204 ns H GCLK PLL t 2.699 2.699 5.916 ns SU t -2.594 -2.594 -5.639 ns H 4–74 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–62. EP1AGX60 Column Pins Input Timing Parameters (Part 3 of 3) Fast Corner -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial 3.3-V PCI-X GCLK t 1.129 1.129 2.481 ns SU t -1.024 -1.024 -2.204 ns H t 2.699 2.699 5.916 ns GCLK PLL SU t -2.594 -2.594 -5.639 ns H LVDS GCLK t 0.980 0.980 2.062 ns SU t -0.875 -0.875 -1.785 ns H GCLK PLL t 2.557 2.557 5.512 ns SU t -2.452 -2.452 -5.235 ns H Table 4–63 describes I/O timing specifications. Table 4–63. EP1AGX60 Row Pins Output Timing Parameters (Part 1 of 3) Fast Model I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 3.3-V 4mA t 3.052 3.052 7.142 ns GCLK CO LVTTL GCLK PLL t 1.490 1.490 3.719 ns CO 3.3-V 8mA GCLK t 2.924 2.924 6.502 ns CO LVTTL GCLK PLL t 1.362 1.362 3.079 ns CO 3.3-V 12 mA t 2.868 2.868 6.465 ns GCLK CO LVTTL t 1.306 1.306 3.042 ns GCLK PLL CO 3.3-V 4mA GCLK t 2.924 2.924 6.502 ns CO LVCMOS GCLK PLL t 1.362 1.362 3.079 ns CO 3.3-V 8mA GCLK t 2.818 2.818 6.196 ns CO LVCMOS t 1.256 1.256 2.773 ns GCLK PLL CO 2.5 V 4 mA t 2.907 2.907 6.476 ns GCLK CO GCLK PLL t 1.345 1.345 3.053 ns CO 2.5 V 8 mA GCLK t 2.804 2.804 6.218 ns CO GCLK PLL t 1.242 1.242 2.795 ns CO 2.5 V 12 mA t 2.785 2.785 6.104 ns GCLK CO t 1.223 1.223 2.681 ns GCLK PLL CO Altera Corporation 4–75 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–63. EP1AGX60 Row Pins Output Timing Parameters (Part 2 of 3) Fast Model I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.8 V 2 mA GCLK t 2.991 2.991 7.521 ns CO GCLK PLL t 1.419 1.419 4.078 ns CO 1.8 V 4 mA t 2.980 2.980 6.742 ns GCLK CO t 1.408 1.408 3.299 ns GCLK PLL CO 1.8 V 6 mA GCLK t 2.869 2.869 6.441 ns CO GCLK PLL t 1.297 1.297 2.998 ns CO 1.8 V 8 mA GCLK t 2.838 2.838 6.327 ns CO t 1.266 1.266 2.884 ns GCLK PLL CO 1.5 V 2 mA t 2.951 2.951 7.020 ns GCLK CO GCLK PLL t 1.379 1.379 3.577 ns CO 1.5 V 4 mA GCLK t 2.844 2.844 6.419 ns CO GCLK PLL t 1.272 1.272 2.976 ns CO SSTL-2 8mA t 2.774 2.774 6.057 ns GCLK CO CLASS I t 1.211 1.211 2.633 ns GCLK PLL CO SSTL-2 12 mA GCLK t 2.750 2.750 5.981 ns CO CLASS I GCLK PLL t 1.187 1.187 2.557 ns CO SSTL-2 16 mA GCLK t 2.716 2.716 5.850 ns CO CLASS II t 1.153 1.153 2.426 ns GCLK PLL CO SSTL-18 4mA t 2.776 2.776 6.025 ns GCLK CO CLASS I GCLK PLL t 1.204 1.204 2.582 ns CO SSTL-18 6mA GCLK t 2.780 2.780 5.954 ns CO CLASS I GCLK PLL t 1.208 1.208 2.511 ns CO SSTL-18 8mA t 2.756 2.756 5.937 ns GCLK CO CLASS I t 1.184 1.184 2.494 ns GCLK PLL CO SSTL-18 10 mA GCLK t 2.759 2.759 5.916 ns CO CLASS I GCLK PLL t 1.187 1.187 2.473 ns CO 1.8-V HSTL 4mA GCLK t 2.757 2.757 5.935 ns CO CLASS I t 1.185 1.185 2.492 ns GCLK PLL CO 1.8-V HSTL 6mA t 2.760 2.760 5.899 ns GCLK CO CLASS I GCLK PLL t 1.188 1.188 2.456 ns CO 4–76 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–63. EP1AGX60 Row Pins Output Timing Parameters (Part 3 of 3) Fast Model I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.8-V HSTL 8mA GCLK t 2.742 2.742 5.895 ns CO CLASS I GCLK PLL t 1.170 1.170 2.452 ns CO 1.8-V HSTL 10 mA t 2.746 2.746 5.884 ns GCLK CO CLASS I t 1.174 1.174 2.441 ns GCLK PLL CO 1.8-V HSTL 12 mA GCLK t 2.737 2.737 5.883 ns CO CLASS I GCLK PLL t 1.165 1.165 2.440 ns CO 1.5-V HSTL 4mA GCLK t 2.756 2.756 5.912 ns CO CLASS I t 1.184 1.184 2.469 ns GCLK PLL CO 1.5-V HSTL 6mA t 2.759 2.759 5.898 ns GCLK CO CLASS I GCLK PLL t 1.187 1.187 2.455 ns CO 1.5-V HSTL 8mA GCLK t 2.744 2.744 5.890 ns CO CLASS I GCLK PLL t 1.172 1.172 2.447 ns CO LVDS - t 2.787 2.787 6.037 ns GCLK CO t 1.228 1.228 2.618 ns GCLK PLL CO Table 4–64 describes I/O timing specifications. Table 4–64. EP1AGX60 Column Pins Output Timing Parameters (Part 1 of 5) Fast Corner Drive -6 Speed IO Standard Clock Parameter Units Strength Grade Industrial Commercial 3.3-V 4mA GCLK t 3.036 3.036 6.963 ns CO LVTTL GCLK PLL t 1.466 1.466 3.528 ns CO 3.3-V 8mA GCLK t 2.891 2.891 6.591 ns CO LVTTL t 1.321 1.321 3.156 ns GCLK PLL CO 3.3-V 12 mA t 2.824 2.824 6.591 ns GCLK CO LVTTL GCLK PLL t 1.254 1.254 3.156 ns CO 3.3-V 16 mA GCLK t 2.798 2.798 6.422 ns CO LVTTL GCLK PLL t 1.228 1.228 2.987 ns CO 3.3-V 20 mA t 2.776 2.776 6.297 ns GCLK CO LVTTL t 1.206 1.206 2.862 ns GCLK PLL CO Altera Corporation 4–77 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–64. EP1AGX60 Column Pins Output Timing Parameters (Part 2 of 5) Fast Corner Drive -6 Speed IO Standard Clock Parameter Units Strength Grade Industrial Commercial 3.3-V 24 mA GCLK t 2.769 2.769 6.299 ns CO LVTTL GCLK PLL t 1.199 1.199 2.864 ns CO 3.3-V 4mA t 2.891 2.891 6.591 ns GCLK CO LVCMOS t 1.321 1.321 3.156 ns GCLK PLL CO 3.3-V 8mA GCLK t 2.799 2.799 6.296 ns CO LVCMOS GCLK PLL t 1.229 1.229 2.861 ns CO 3.3-V 12 mA GCLK t 2.771 2.771 6.218 ns CO LVCMOS t 1.201 1.201 2.783 ns GCLK PLL CO 3.3-V 16 mA t 2.778 2.778 6.186 ns GCLK CO LVCMOS GCLK PLL t 1.208 1.208 2.751 ns CO 3.3-V 20 mA GCLK t 2.765 2.765 6.168 ns CO LVCMOS GCLK PLL t 1.195 1.195 2.733 ns CO 3.3-V 24 mA t 2.754 2.754 6.146 ns GCLK CO LVCMOS t 1.184 1.184 2.711 ns GCLK PLL CO 2.5 V 4 mA GCLK t 2.853 2.853 6.623 ns CO GCLK PLL t 1.283 1.283 3.188 ns CO 2.5 V 8 mA GCLK t 2.801 2.801 6.361 ns CO t 1.231 1.231 2.926 ns GCLK PLL CO 2.5 V 12 mA t 2.780 2.780 6.244 ns GCLK CO GCLK PLL t 1.210 1.210 2.809 ns CO 2.5 V 16 mA GCLK t 2.762 2.762 6.170 ns CO GCLK PLL t 1.192 1.192 2.735 ns CO 1.8 V 2 mA t 2.893 2.893 7.615 ns GCLK CO t 1.323 1.323 4.180 ns GCLK PLL CO 1.8 V 4 mA GCLK t 2.898 2.898 6.841 ns CO GCLK PLL t 1.328 1.328 3.406 ns CO 1.8 V 6 mA GCLK t 2.822 2.822 6.577 ns CO t 1.252 1.252 3.142 ns GCLK PLL CO 1.8 V 8 mA t 2.824 2.824 6.486 ns GCLK CO GCLK PLL t 1.254 1.254 3.051 ns CO 4–78 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–64. EP1AGX60 Column Pins Output Timing Parameters (Part 3 of 5) Fast Corner Drive -6 Speed IO Standard Clock Parameter Units Strength Grade Industrial Commercial 1.8 V 10 mA GCLK t 2.778 2.778 6.409 ns CO GCLK PLL t 1.208 1.208 2.974 ns CO 1.8 V 12 mA t 2.779 2.779 6.352 ns GCLK CO t 1.209 1.209 2.917 ns GCLK PLL CO 1.5 V 2 mA GCLK t 2.873 2.873 7.145 ns CO GCLK PLL t 1.303 1.303 3.710 ns CO 1.5 V 4 mA GCLK t 2.809 2.809 6.576 ns CO t 1.239 1.239 3.141 ns GCLK PLL CO 1.5 V 6 mA t 2.812 2.812 6.458 ns GCLK CO GCLK PLL t 1.242 1.242 3.023 ns CO 1.5 V 8 mA GCLK t 2.771 2.771 6.405 ns CO GCLK PLL t 1.201 1.201 2.970 ns CO SSTL-2 8mA t 2.757 2.757 6.184 ns GCLK CO CLASS I t 1.184 1.184 2.744 ns GCLK PLL CO SSTL-2 12 mA GCLK t 2.740 2.740 6.134 ns CO CLASS I GCLK PLL t 1.167 1.167 2.694 ns CO SSTL-2 16 mA GCLK t 2.718 2.718 6.061 ns CO CLASS II t 1.145 1.145 2.621 ns GCLK PLL CO SSTL-2 20 mA t 2.719 2.719 6.048 ns GCLK CO CLASS II GCLK PLL t 1.146 1.146 2.608 ns CO SSTL-2 24 mA GCLK t 2.715 2.715 6.046 ns CO CLASS II GCLK PLL t 1.142 1.142 2.606 ns CO SSTL-18 4mA t 2.753 2.753 6.155 ns GCLK CO CLASS I t 1.183 1.183 2.720 ns GCLK PLL CO SSTL-18 6mA GCLK t 2.758 2.758 6.116 ns CO CLASS I GCLK PLL t 1.185 1.185 2.676 ns CO SSTL-18 8mA GCLK t 2.737 2.737 6.097 ns CO CLASS I t 1.164 1.164 2.657 ns GCLK PLL CO SSTL-18 10 mA t 2.742 2.742 6.095 ns GCLK CO CLASS I GCLK PLL t 1.169 1.169 2.655 ns CO Altera Corporation 4–79 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–64. EP1AGX60 Column Pins Output Timing Parameters (Part 4 of 5) Fast Corner Drive -6 Speed IO Standard Clock Parameter Units Strength Grade Industrial Commercial SSTL-18 12 mA GCLK t 2.736 2.736 6.081 ns CO CLASS I GCLK PLL t 1.163 1.163 2.641 ns CO SSTL-18 8mA t 2.725 2.725 6.047 ns GCLK CO CLASS II t 1.152 1.152 2.607 ns GCLK PLL CO SSTL-18 16 mA GCLK t 2.737 2.737 6.025 ns CO CLASS II GCLK PLL t 1.164 1.164 2.585 ns CO SSTL-18 18 mA GCLK t 2.733 2.733 6.033 ns CO CLASS II t 1.160 1.160 2.593 ns GCLK PLL CO SSTL-18 20 mA t 2.733 2.733 6.031 ns GCLK CO CLASS II GCLK PLL t 1.160 1.160 2.591 ns CO 1.8-V HSTL 4mA GCLK t 2.756 2.756 6.086 ns CO CLASS I GCLK PLL t 1.186 1.186 2.651 ns CO 1.8-V HSTL 6mA t 2.762 2.762 6.071 ns GCLK CO CLASS I t 1.189 1.189 2.631 ns GCLK PLL CO 1.8-V HSTL 8mA GCLK t 2.740 2.740 6.060 ns CO CLASS I GCLK PLL t 1.167 1.167 2.620 ns CO 1.8-V HSTL 10 mA GCLK t 2.744 2.744 6.066 ns CO CLASS I t 1.171 1.171 2.626 ns GCLK PLL CO 1.8-V HSTL 12 mA t 2.736 2.736 6.059 ns GCLK CO CLASS I GCLK PLL t 1.163 1.163 2.619 ns CO 1.8-V HSTL 16 mA GCLK t 2.719 2.719 5.823 ns CO CLASS II GCLK PLL t 1.146 1.146 2.383 ns CO 1.8-V HSTL 18 mA t 2.721 2.721 5.834 ns GCLK CO CLASS II t 1.148 1.148 2.394 ns GCLK PLL CO 1.8-V HSTL 20 mA GCLK t 2.721 2.721 5.843 ns CO CLASS II GCLK PLL t 1.148 1.148 2.403 ns CO 1.5-V HSTL 4mA GCLK t 2.756 2.756 6.085 ns CO CLASS I t 1.186 1.186 2.650 ns GCLK PLL CO 1.5-V HSTL 6mA t 2.761 2.761 6.063 ns GCLK CO CLASS I GCLK PLL t 1.188 1.188 2.623 ns CO 4–80 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–64. EP1AGX60 Column Pins Output Timing Parameters (Part 5 of 5) Fast Corner Drive -6 Speed IO Standard Clock Parameter Units Strength Grade Industrial Commercial 1.5-V HSTL 8mA GCLK t 2.743 2.743 6.065 ns CO CLASS I GCLK PLL t 1.170 1.170 2.625 ns CO 1.5-V HSTL 10 mA t 2.743 2.743 6.067 ns GCLK CO CLASS I t 1.170 1.170 2.627 ns GCLK PLL CO 1.5-V HSTL 12 mA GCLK t 2.737 2.737 6.065 ns CO CLASS I GCLK PLL t 1.164 1.164 2.625 ns CO 1.5-V HSTL 16 mA GCLK t 2.724 2.724 5.877 ns CO CLASS II t 1.151 1.151 2.437 ns GCLK PLL CO 1.5-V HSTL 18 mA t 2.727 2.727 5.887 ns GCLK CO CLASS II GCLK PLL t 1.154 1.154 2.447 ns CO 1.5-V HSTL 20 mA GCLK t 2.729 2.729 5.900 ns CO CLASS II GCLK PLL t 1.156 1.156 2.460 ns CO 3.3-V PCI - t 2.882 2.882 6.213 ns GCLK CO t 1.312 1.312 2.778 ns GCLK PLL CO 3.3-V PCI-X - GCLK t 2.882 2.882 6.213 ns CO GCLK PLL t 1.312 1.312 2.778 ns CO LVDS - GCLK t 3.746 3.746 7.396 ns CO t 2.185 2.185 3.973 ns GCLK PLL CO Tables 4–65 through 4–66 show EP1AGX60 regional clock (RCLK) adder values that should be added to the GCLK values. These adder values are used to determine I/O timing when the I/O pin is driven using the regional clock. This applies for all I/O standards supported by Arria GX with general purpose I/O pins. Altera Corporation 4–81 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–65 describes row pin delay adders when using the regional clock in Arria GX devices. Table 4–65. EP1AGX60 Row Pin Delay Adders for Regional Clock Fast Corner -6 Speed Parameter Units Grade Industrial Commercial 0.138 0.138 0.311 ns RCLK input adder RCLK PLL -0.003 -0.003 -0.006 ns input adder RCLK output -0.138 -0.138 -0.311 ns adder 0.003 0.003 0.006 ns RCLK PLL output adder Table 4–66 describes column pin delay adders when using the regional clock in Arria GX devices. Table 4–66. EP1AGX60 Column Pin Delay Adders for Regional Clock Fast Corner -6 Speed Parameter Units Grade Industrial Commercial 0.153 0.153 0.344 ns RCLK input adder RCLK PLL -1.066 -1.066 -2.338 ns input adder RCLK output -0.153 -0.153 -0.343 ns adder RCLK PLL 1.721 1.721 4.486 ns output adder EP1AGX90I/O Timing Parameters Tables 4–67 through 4–70 show the maximum I/O timing parameters for EP1AGX90 devices for I/O standards which support general purpose I/O pins. 4–82 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–67 describes I/O timing specifications. Table 4–67. EP1AGX90 Row Pins Input Timing Parameters (Part 1 of 2) Fast Model -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial 3.3-V LVTTL GCLK t 1.295 1.295 2.873 ns SU t -1.190 -1.190 -2.596 ns H t 3.366 3.366 7.017 ns GCLK PLL SU t -3.261 -3.261 -6.740 ns H 3.3-V GCLK t 1.295 1.295 2.873 ns SU LVCMOS t -1.190 -1.190 -2.596 ns H GCLK PLL t 3.366 3.366 7.017 ns SU t -3.261 -3.261 -6.740 ns H 2.5 V t 1.307 1.307 2.854 ns GCLK SU t -1.202 -1.202 -2.577 ns H GCLK PLL t 3.378 3.378 6.998 ns SU t -3.273 -3.273 -6.721 ns H 1.8 V t 1.381 1.381 3.073 ns GCLK SU t -1.276 -1.276 -2.796 ns H GCLK PLL t 3.434 3.434 7.191 ns SU t -3.329 -3.329 -6.914 ns H 1.5 V GCLK t 1.384 1.384 3.168 ns SU t -1.279 -1.279 -2.891 ns H t 3.437 3.437 7.286 ns GCLK PLL SU t -3.332 -3.332 -7.009 ns H SSTL-2 GCLK t 1.121 1.121 2.329 ns SU CLASS I t -1.016 -1.016 -2.052 ns H t 3.187 3.187 6.466 ns GCLK PLL SU t -3.082 -3.082 -6.189 ns H SSTL-2 GCLK t 1.121 1.121 2.329 ns SU CLASS II t -1.016 -1.016 -2.052 ns H GCLK PLL t 3.187 3.187 6.466 ns SU t -3.082 -3.082 -6.189 ns H Altera Corporation 4–83 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–67. EP1AGX90 Row Pins Input Timing Parameters (Part 2 of 2) Fast Model -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial SSTL-18 GCLK t 1.159 1.159 2.447 ns SU CLASS I t -1.054 -1.054 -2.170 ns H t 3.212 3.212 6.565 ns GCLK PLL SU t -3.107 -3.107 -6.288 ns H SSTL-18 GCLK t 1.157 1.157 2.441 ns SU CLASS II t -1.052 -1.052 -2.164 ns H GCLK PLL t 3.235 3.235 6.597 ns SU t -3.130 -3.130 -6.320 ns H 1.8-V HSTL t 1.159 1.159 2.447 ns GCLK SU CLASS I t -1.054 -1.054 -2.170 ns H GCLK PLL t 3.212 3.212 6.565 ns SU t -3.107 -3.107 -6.288 ns H 1.8-V HSTL t 1.157 1.157 2.441 ns GCLK SU CLASS II t -1.052 -1.052 -2.164 ns H GCLK PLL t 3.235 3.235 6.597 ns SU t -3.130 -3.130 -6.320 ns H 1.5-V HSTL GCLK t 1.185 1.185 2.575 ns SU CLASS I t -1.080 -1.080 -2.298 ns H t 3.238 3.238 6.693 ns GCLK PLL SU t -3.133 -3.133 -6.416 ns H 1.5-V HSTL GCLK t 1.183 1.183 2.569 ns SU CLASS II t -1.078 -1.078 -2.292 ns H t 3.261 3.261 6.725 ns GCLK PLL SU t -3.156 -3.156 -6.448 ns H LVDS GCLK t 1.098 1.098 2.439 ns SU t -0.993 -0.993 -2.162 ns H GCLK PLL t 3.160 3.160 6.566 ns SU t -3.055 -3.055 -6.289 ns H 4–84 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–68 describes I/O timing specifications. Table 4–68. EP1AGX90 Column Pins Input Timing Parameters (Part 1 of 3) Fast Corner -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial 3.3-V LVTTL GCLK t 1.018 1.018 2.290 ns SU t -0.913 -0.913 -2.013 ns H t 3.082 3.082 6.425 ns GCLK PLL SU t -2.977 -2.977 -6.148 ns H 3.3-V GCLK t 1.018 1.018 2.290 ns SU LVCMOS t -0.913 -0.913 -2.013 ns H GCLK PLL t 3.082 3.082 6.425 ns SU t -2.977 -2.977 -6.148 ns H 2.5 V t 1.028 1.028 2.272 ns GCLK SU t -0.923 -0.923 -1.995 ns H GCLK PLL t 3.092 3.092 6.407 ns SU t -2.987 -2.987 -6.130 ns H 1.8 V t 1.094 1.094 2.482 ns GCLK SU t -0.989 -0.989 -2.205 ns H GCLK PLL t 3.158 3.158 6.617 ns SU t -3.053 -3.053 -6.340 ns H 1.5 V GCLK t 1.097 1.097 2.575 ns SU t -0.992 -0.992 -2.298 ns H t 3.161 3.161 6.710 ns GCLK PLL SU t -3.056 -3.056 -6.433 ns H SSTL-2 GCLK t 0.844 0.844 1.751 ns SU CLASS I t -0.739 -0.739 -1.474 ns H t 2.908 2.908 5.886 ns GCLK PLL SU t -2.803 -2.803 -5.609 ns H SSTL-2 GCLK t 0.844 0.844 1.751 ns SU CLASS II t -0.739 -0.739 -1.474 ns H GCLK PLL t 2.908 2.908 5.886 ns SU t -2.803 -2.803 -5.609 ns H Altera Corporation 4–85 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–68. EP1AGX90 Column Pins Input Timing Parameters (Part 2 of 3) Fast Corner -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial SSTL-18 GCLK t 0.880 0.880 1.854 ns SU CLASS I t -0.775 -0.775 -1.577 ns H t 2.944 2.944 5.989 ns GCLK PLL SU t -2.839 -2.839 -5.712 ns H SSTL-18 GCLK t 0.883 0.883 1.858 ns SU CLASS II t -0.778 -0.778 -1.581 ns H GCLK PLL t 2.947 2.947 5.993 ns SU t -2.842 -2.842 -5.716 ns H 1.8-V HSTL t 0.880 0.880 1.854 ns GCLK SU CLASS I t -0.775 -0.775 -1.577 ns H GCLK PLL t 2.944 2.944 5.989 ns SU t -2.839 -2.839 -5.712 ns H 1.8-V HSTL t 0.883 0.883 1.858 ns GCLK SU CLASS II t -0.778 -0.778 -1.581 ns H GCLK PLL t 2.947 2.947 5.993 ns SU t -2.842 -2.842 -5.716 ns H 1.5-V HSTL GCLK t 0.898 0.898 1.982 ns SU CLASS I t -0.793 -0.793 -1.705 ns H t 2.962 2.962 6.117 ns GCLK PLL SU t -2.857 -2.857 -5.840 ns H 1.5-V HSTL GCLK t 0.901 0.901 1.986 ns SU CLASS II t -0.796 -0.796 -1.709 ns H t 2.965 2.965 6.121 ns GCLK PLL SU t -2.860 -2.860 -5.844 ns H 3.3-V PCI GCLK t 1.023 1.023 2.278 ns SU t -0.918 -0.918 -2.001 ns H GCLK PLL t 3.087 3.087 6.413 ns SU t -2.982 -2.982 -6.136 ns H 4–86 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–68. EP1AGX90 Column Pins Input Timing Parameters (Part 3 of 3) Fast Corner -6 Speed I/O Standard Clock Parameter Units Grade Industrial Commercial 3.3-V PCI-X GCLK t 1.023 1.023 2.278 ns SU t -0.918 -0.918 -2.001 ns H t 3.087 3.087 6.413 ns GCLK PLL SU t -2.982 -2.982 -6.136 ns H LVDS GCLK t 0.891 0.891 1.920 ns SU t -0.786 -0.786 -1.643 ns H GCLK PLL t 2.963 2.963 6.066 ns SU t -2.858 -2.858 -5.789 ns H Table 4–69 describes I/O timing specifications. Table 4–69. EP1AGX90 Row Pins Output Timing Parameters (Part 1 of 3) Fast Model I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 3.3-V 4mA t 3.170 3.170 7.382 ns GCLK CO LVTTL GCLK PLL t 1.099 1.099 3.238 ns CO 3.3-V 8mA GCLK t 3.042 3.042 6.742 ns CO LVTTL GCLK PLL t 0.971 0.971 2.598 ns CO 3.3-V 12 mA t 2.986 2.986 6.705 ns GCLK CO LVTTL t 0.915 0.915 2.561 ns GCLK PLL CO 3.3-V 4mA GCLK t 3.042 3.042 6.742 ns CO LVCMOS GCLK PLL t 0.971 0.971 2.598 ns CO 3.3-V 8mA GCLK t 2.936 2.936 6.436 ns CO LVCMOS t 0.865 0.865 2.292 ns GCLK PLL CO 2.5 V 4 mA t 3.025 3.025 6.716 ns GCLK CO GCLK PLL t 0.954 0.954 2.572 ns CO 2.5 V 8 mA GCLK t 2.922 2.922 6.458 ns CO GCLK PLL t 0.851 0.851 2.314 ns CO 2.5 V 12 mA t 2.903 2.903 6.344 ns GCLK CO t 0.832 0.832 2.200 ns GCLK PLL CO Altera Corporation 4–87 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–69. EP1AGX90 Row Pins Output Timing Parameters (Part 2 of 3) Fast Model I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.8 V 2 mA GCLK t 3.087 3.087 7.723 ns CO GCLK PLL t 1.034 1.034 3.605 ns CO 1.8 V 4 mA t 3.076 3.076 6.944 ns GCLK CO t 1.023 1.023 2.826 ns GCLK PLL CO 1.8 V 6 mA GCLK t 2.965 2.965 6.643 ns CO GCLK PLL t 0.912 0.912 2.525 ns CO 1.8 V 8 mA GCLK t 2.934 2.934 6.529 ns CO t 0.881 0.881 2.411 ns GCLK PLL CO 1.5 V 2 mA t 3.047 3.047 7.222 ns GCLK CO GCLK PLL t 0.994 0.994 3.104 ns CO 1.5 V 4 mA GCLK t 2.940 2.940 6.621 ns CO GCLK PLL t 0.887 0.887 2.503 ns CO SSTL-2 8mA t 2.890 2.890 6.294 ns GCLK CO CLASS I t 0.824 0.824 2.157 ns GCLK PLL CO SSTL-2 12 mA GCLK t 2.866 2.866 6.218 ns CO CLASS I GCLK PLL t 0.800 0.800 2.081 ns CO SSTL-2 16 mA GCLK t 2.832 2.832 6.087 ns CO CLASS II t 0.766 0.766 1.950 ns GCLK PLL CO SSTL-18 4mA t 2.872 2.872 6.227 ns GCLK CO CLASS I GCLK PLL t 0.819 0.819 2.109 ns CO SSTL-18 6mA GCLK t 2.878 2.878 6.162 ns CO CLASS I GCLK PLL t 0.800 0.800 2.006 ns CO SSTL-18 8mA t 2.854 2.854 6.145 ns GCLK CO CLASS I t 0.776 0.776 1.989 ns GCLK PLL CO SSTL-18 10 mA GCLK t 2.857 2.857 6.124 ns CO CLASS I GCLK PLL t 0.779 0.779 1.968 ns CO 1.8-V HSTL 4mA GCLK t 2.853 2.853 6.137 ns CO CLASS I t 0.800 0.800 2.019 ns GCLK PLL CO 1.8-V HSTL 6mA t 2.858 2.858 6.107 ns GCLK CO CLASS I GCLK PLL t 0.780 0.780 1.951 ns CO 4–88 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–69. EP1AGX90 Row Pins Output Timing Parameters (Part 3 of 3) Fast Model I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.8-V HSTL 8mA GCLK t 2.840 2.840 6.103 ns CO CLASS I GCLK PLL t 0.762 0.762 1.947 ns CO 1.8-V HSTL 10 mA t 2.844 2.844 6.092 ns GCLK CO CLASS I t 0.766 0.766 1.936 ns GCLK PLL CO 1.8-V HSTL 12 mA GCLK t 2.835 2.835 6.091 ns CO CLASS I GCLK PLL t 0.757 0.757 1.935 ns CO 1.5-V HSTL 4mA GCLK t 2.852 2.852 6.114 ns CO CLASS I t 0.799 0.799 1.996 ns GCLK PLL CO 1.5-V HSTL 6mA t 2.857 2.857 6.106 ns GCLK CO CLASS I GCLK PLL t 0.779 0.779 1.950 ns CO 1.5-V HSTL 8mA GCLK t 2.842 2.842 6.098 ns CO CLASS I GCLK PLL t 0.764 0.764 1.942 ns CO LVDS - t 2.898 2.898 6.265 ns GCLK CO t 0.831 0.831 2.129 ns GCLK PLL CO Table 4–70 describes I/O timing specifications. Table 4–70. EP1AGX90 Column Pins Output Timing Parameters (Part 1 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 3.3-V 4mA GCLK t 3.141 3.141 7.164 ns CO LVTTL GCLK PLL t 1.077 1.077 3.029 ns CO 3.3-V 8mA GCLK t 2.996 2.996 6.792 ns CO LVTTL t 0.932 0.932 2.657 ns GCLK PLL CO 3.3-V 12 mA t 2.929 2.929 6.792 ns GCLK CO LVTTL GCLK PLL t 0.865 0.865 2.657 ns CO 3.3-V 16 mA GCLK t 2.903 2.903 6.623 ns CO LVTTL GCLK PLL t 0.839 0.839 2.488 ns CO 3.3-V 20 mA t 2.881 2.881 6.498 ns GCLK CO LVTTL t 0.817 0.817 2.363 ns GCLK PLL CO Altera Corporation 4–89 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–70. EP1AGX90 Column Pins Output Timing Parameters (Part 2 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 3.3-V 24 mA GCLK t 2.874 2.874 6.500 ns CO LVTTL GCLK PLL t 0.810 0.810 2.365 ns CO 3.3-V 4mA t 2.996 2.996 6.792 ns GCLK CO LVCMOS t 0.932 0.932 2.657 ns GCLK PLL CO 3.3-V 8mA GCLK t 2.904 2.904 6.497 ns CO LVCMOS GCLK PLL t 0.840 0.840 2.362 ns CO 3.3-V 12 mA GCLK t 2.876 2.876 6.419 ns CO LVCMOS t 0.812 0.812 2.284 ns GCLK PLL CO 3.3-V 16 mA t 2.883 2.883 6.387 ns GCLK CO LVCMOS GCLK PLL t 0.819 0.819 2.252 ns CO 3.3-V 20 mA GCLK t 2.870 2.870 6.369 ns CO LVCMOS GCLK PLL t 0.806 0.806 2.234 ns CO 3.3-V 24 mA t 2.859 2.859 6.347 ns GCLK CO LVCMOS t 0.795 0.795 2.212 ns GCLK PLL CO 2.5 V 4 mA GCLK t 2.958 2.958 6.824 ns CO GCLK PLL t 0.894 0.894 2.689 ns CO 2.5 V 8 mA GCLK t 2.906 2.906 6.562 ns CO t 0.842 0.842 2.427 ns GCLK PLL CO 2.5 V 12 mA t 2.885 2.885 6.445 ns GCLK CO GCLK PLL t 0.821 0.821 2.310 ns CO 2.5 V 16 mA GCLK t 2.867 2.867 6.371 ns CO GCLK PLL t 0.803 0.803 2.236 ns CO 1.8 V 2 mA t 2.998 2.998 7.816 ns GCLK CO t 0.934 0.934 3.681 ns GCLK PLL CO 1.8 V 4 mA GCLK t 3.003 3.003 7.042 ns CO GCLK PLL t 0.939 0.939 2.907 ns CO 1.8 V 6 mA GCLK t 2.927 2.927 6.778 ns CO t 0.863 0.863 2.643 ns GCLK PLL CO 1.8 V 8 mA t 2.929 2.929 6.687 ns GCLK CO GCLK PLL t 0.865 0.865 2.552 ns CO 4–90 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–70. EP1AGX90 Column Pins Output Timing Parameters (Part 3 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.8 V 10 mA GCLK t 2.883 2.883 6.610 ns CO GCLK PLL t 0.819 0.819 2.475 ns CO 1.8 V 12 mA t 2.884 2.884 6.553 ns GCLK CO t 0.820 0.820 2.418 ns GCLK PLL CO 1.5 V 2 mA GCLK t 2.978 2.978 7.346 ns CO GCLK PLL t 0.914 0.914 3.211 ns CO 1.5 V 4 mA GCLK t 2.914 2.914 6.777 ns CO t 0.850 0.850 2.642 ns GCLK PLL CO 1.5 V 6 mA t 2.917 2.917 6.659 ns GCLK CO GCLK PLL t 0.853 0.853 2.524 ns CO 1.5 V 8 mA GCLK t 2.876 2.876 6.606 ns CO GCLK PLL t 0.812 0.812 2.471 ns CO SSTL-2 8mA t 2.859 2.859 6.381 ns GCLK CO CLASS I t 0.797 0.797 2.250 ns GCLK PLL CO SSTL-2 12 mA GCLK t 2.842 2.842 6.331 ns CO CLASS I GCLK PLL t 0.780 0.780 2.200 ns CO SSTL-2 16 mA GCLK t 2.820 2.820 6.258 ns CO CLASS II t 0.758 0.758 2.127 ns GCLK PLL CO SSTL-2 20 mA t 2.821 2.821 6.245 ns GCLK CO CLASS II GCLK PLL t 0.759 0.759 2.114 ns CO SSTL-2 24 mA GCLK t 2.817 2.817 6.243 ns CO CLASS II GCLK PLL t 0.755 0.755 2.112 ns CO SSTL-18 4mA t 2.858 2.858 6.356 ns GCLK CO CLASS I t 0.794 0.794 2.221 ns GCLK PLL CO SSTL-18 6mA GCLK t 2.860 2.860 6.313 ns CO CLASS I GCLK PLL t 0.798 0.798 2.182 ns CO SSTL-18 8mA GCLK t 2.839 2.839 6.294 ns CO CLASS I t 0.777 0.777 2.163 ns GCLK PLL CO SSTL-18 10 mA t 2.844 2.844 6.292 ns GCLK CO CLASS I GCLK PLL t 0.782 0.782 2.161 ns CO Altera Corporation 4–91 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–70. EP1AGX90 Column Pins Output Timing Parameters (Part 4 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial SSTL-18 12 mA GCLK t 2.838 2.838 6.278 ns CO CLASS I GCLK PLL t 0.776 0.776 2.147 ns CO SSTL-18 8mA t 2.827 2.827 6.244 ns GCLK CO CLASS II t 0.765 0.765 2.113 ns GCLK PLL CO SSTL-18 16 mA GCLK t 2.839 2.839 6.222 ns CO CLASS II GCLK PLL t 0.777 0.777 2.091 ns CO SSTL-18 18 mA GCLK t 2.835 2.835 6.230 ns CO CLASS II t 0.773 0.773 2.099 ns GCLK PLL CO SSTL-18 20 mA t 2.835 2.835 6.228 ns GCLK CO CLASS II GCLK PLL t 0.773 0.773 2.097 ns CO 1.8-V HSTL 4mA GCLK t 2.861 2.861 6.287 ns CO CLASS I GCLK PLL t 0.797 0.797 2.152 ns CO 1.8-V HSTL 6mA t 2.864 2.864 6.268 ns GCLK CO CLASS I t 0.802 0.802 2.137 ns GCLK PLL CO 1.8-V HSTL 8mA GCLK t 2.842 2.842 6.257 ns CO CLASS I GCLK PLL t 0.780 0.780 2.126 ns CO 1.8-V HSTL 10 mA GCLK t 2.846 2.846 6.263 ns CO CLASS I t 0.784 0.784 2.132 ns GCLK PLL CO 1.8-V HSTL 12 mA t 2.838 2.838 6.256 ns GCLK CO CLASS I GCLK PLL t 0.776 0.776 2.125 ns CO 1.8-V HSTL 16 mA GCLK t 2.821 2.821 6.020 ns CO CLASS II GCLK PLL t 0.759 0.759 1.889 ns CO 1.8-V HSTL 18 mA t 2.823 2.823 6.031 ns GCLK CO CLASS II t 0.761 0.761 1.900 ns GCLK PLL CO 1.8-V HSTL 20 mA GCLK t 2.823 2.823 6.040 ns CO CLASS II GCLK PLL t 0.761 0.761 1.909 ns CO 1.5-V HSTL 4mA GCLK t 2.861 2.861 6.286 ns CO CLASS I t 0.797 0.797 2.151 ns GCLK PLL CO 1.5-V HSTL 6mA t 2.863 2.863 6.260 ns GCLK CO CLASS I GCLK PLL t 0.801 0.801 2.129 ns CO 4–92 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–70. EP1AGX90 Column Pins Output Timing Parameters (Part 5 of 5) Fast Corner I/O Drive -6 Speed Clock Parameter Units Standard Strength Grade Industrial Commercial 1.5-V HSTL 8mA GCLK t 2.845 2.845 6.262 ns CO CLASS I GCLK PLL t 0.783 0.783 2.131 ns CO 1.5-V HSTL 10 mA t 2.845 2.845 6.264 ns GCLK CO CLASS I t 0.783 0.783 2.133 ns GCLK PLL CO 1.5-V HSTL 12 mA GCLK t 2.839 2.839 6.262 ns CO CLASS I GCLK PLL t 0.777 0.777 2.131 ns CO 1.5-V HSTL 16 mA GCLK t 2.826 2.826 6.074 ns CO CLASS II t 0.764 0.764 1.943 ns GCLK PLL CO 1.5-V HSTL 18 mA t 2.829 2.829 6.084 ns GCLK CO CLASS II GCLK PLL t 0.767 0.767 1.953 ns CO 1.5-V HSTL 20 mA GCLK t 2.831 2.831 6.097 ns CO CLASS II GCLK PLL t 0.769 0.769 1.966 ns CO 3.3-V PCI - t 2.987 2.987 6.414 ns GCLK CO t 0.923 0.923 2.279 ns GCLK PLL CO 3.3-V PCI-X - GCLK t 2.987 2.987 6.414 ns CO GCLK PLL t 0.923 0.923 2.279 ns CO LVDS - GCLK t 3.835 3.835 7.541 ns CO t 1.769 1.769 3.404 ns GCLK PLL CO Tables 4–71 through 4–72 show the EP1AGX90 regional clock (RCLK) adder values that should be added to the GCLK values. These adder values are used to determine I/O timing when the I/O pin is driven using the regional clock. This applies for all I/O standards supported by Arria GX with general purpose I/O pins. Altera Corporation 4–93 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–71 describes row pin delay adders when using the regional clock in Arria GX devices. Table 4–71. EP1AGX90 Row Pin Delay Adders for Regional Clock Fast Corner -6 Speed Parameter Units Grade Industrial Commercial 0.175 0.175 0.418 ns RCLK input adder RCLK PLL 0.007 0.007 0.015 ns input adder RCLK output -0.175 -0.175 -0.418 ns adder -0.007 -0.007 -0.015 ns RCLK PLL output adder Table 4–72 describes column pin delay adders when using the regional clock in Arria GX devices. Table 4–72. EP1AGX90 Column Pin Delay Adders for Regional Clock Fast Corner -6 Speed Parameter Units Grade Industrial Commercial 0.138 0.138 0.354 ns RCLK input adder RCLK PLL -1.697 -1.697 -3.607 ns input adder RCLK output -0.138 -0.138 -0.353 ns adder 1.966 1.966 5.188 ns RCLK PLL output adder Dedicated Clock Pin Timing Tables 4–74 to 4–93 show clock pin timing for Arria GX devices when the clock is driven by the global clock, regional clock, periphery clock, and a PLL. 4–94 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Tables 4–73 describes Arria GX clock timing parameters. Table 4–73. Arria GX Clock Timing Parameters Symbol Parameter t Delay from clock pad to I/O input register CIN t Delay from clock pad to I/O output register COUT t Delay from PLL inclk pad to I/O input register PLLCIN t Delay from PLL inclk pad to I/O output register PLLCOUT EP1AGX20 Clock Timing Parameters Tables 4–74 through 4–75 show the GCLK clock timing parameters for EP1AGX20 devices. Table 4–74 describes clock timing specifications. Table 4–74. EP1AGX20 Row Pins Global Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.394 1.394 3.161 ns tcout 1.399 1.399 3.155 ns tpllcin -0.027 -0.027 0.091 ns tpllcout -0.022 -0.022 0.085 ns Table 4–75 describes clock timing specifications. Table 4–75. EP1AGX20 Row Pins Global Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.655 1.655 3.726 ns tcout 1.655 1.655 3.726 ns tpllcin 0.236 0.236 0.655 ns tpllcout 0.236 0.236 0.655 ns Altera Corporation 4–95 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Tables 4–76 through 4–77 show the RCLK clock timing parameters for EP1AGX20 devices. Table 4–76 describes clock timing specifications. Table 4–76. EP1AGX20 Row Pins Regional Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.283 1.283 2.901 ns 1.288 1.288 2.895 ns tcout tpllcin -0.034 -0.034 0.077 ns -0.029 -0.029 0.071 ns tpllcout Table 4–77 describes clock timing specifications. Table 4–77. EP1AGX20 Row Pins Regional Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.569 1.569 3.487 ns 1.569 1.569 3.487 ns tcout tpllcin 0.278 0.278 0.706 ns 0.278 0.278 0.706 ns tpllcout EP1AGX35 Clock Timing Parameters Tables 4–78 through 4–79 show the GCLK clock timing parameters for EP1AGX35 devices. Table 4–78 describes clock timing specifications. Table 4–78. EP1AGX35 Row Pins Global Clock Timing Parameters (Part 1 of 2) Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.394 1.394 3.161 ns 1.399 1.399 3.155 ns tcout 4–96 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–78. EP1AGX35 Row Pins Global Clock Timing Parameters (Part 2 of 2) Fast Model -6 Speed Parameter Units Grade Industrial Commercial tpllcin -0.027 -0.027 0.091 ns -0.022 -0.022 0.085 ns tpllcout Table 4–79 describes clock timing specifications. Table 4–79. EP1AGX35 Row Pins Global Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.655 1.655 3.726 ns 1.655 1.655 3.726 ns tcout tpllcin 0.236 0.236 0.655 ns 0.236 0.236 0.655 ns tpllcout Tables 4–80 through 4–81 show the RCLK clock timing parameters for EP1AGX35 devices. Table 4–80 describes clock timing specifications. Table 4–80. EP1AGX35 Row Pins Regional Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.283 1.283 2.901 ns 1.288 1.288 2.895 ns tcout tpllcin -0.034 -0.034 0.077 ns -0.029 -0.029 0.071 ns tpllcout Altera Corporation 4–97 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–81 describes clock timing specifications. Table 4–81. EP1AGX35 Row Pins Regional Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.569 1.569 3.487 ns 1.569 1.569 3.487 ns tcout tpllcin 0.278 0.278 0.706 ns 0.278 0.278 0.706 ns tpllcout EP1AGX50 Clock Timing Parameters Tables 4–82 through 4–83 show the GCLK clock timing parameters for EP1AGX50 devices. Table 4–82 describes clock timing specifications. Table 4–82. EP1AGX50 Row Pins Global Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.529 1.529 3.587 ns 1.534 1.534 3.581 ns tcout tpllcin -0.024 -0.024 0.181 ns -0.019 -0.019 0.175 ns tpllcout Table 4–83 describes clock timing specifications. Table 4–83. EP1AGX50 Row Pins Global Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.793 1.793 4.165 ns 1.793 1.793 4.165 ns tcout tpllcin 0.238 0.238 0.758 ns 0.238 0.238 0.758 ns tpllcout 4–98 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Tables 4–84 through 4–85 show the RCLK clock timing parameters for EP1AGX50 devices. Table 4–84 describes clock timing specifications. Table 4–84. EP1AGX50 Row Pins Regional Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.396 1.396 3.287 ns 1.401 1.401 3.281 ns tcout tpllcin -0.017 -0.017 0.195 ns -0.012 -0.012 0.189 ns tpllcout Table 4–85 describes clock timing specifications. Table 4–85. EP1AGX50 Row Pins Regional Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.653 1.653 3.841 ns 1.651 1.651 3.839 ns tcout tpllcin 0.245 0.245 0.755 ns 0.245 0.245 0.755 ns tpllcout EP1AGX60 Clock Timing Parameters Tables 4–86 through 4–87 show the GCLK clock timing parameters for EP1AGX60 devices. Table 4–86 describes clock timing specifications. Table 4–86. EP1AGX60 Row Pins Global Clock Timing Parameters (Part 1 of 2) Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.531 1.531 3.593 ns 1.536 1.536 3.587 ns tcout Altera Corporation 4–99 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Typical Design Performance Table 4–86. EP1AGX60 Row Pins Global Clock Timing Parameters (Part 2 of 2) Fast Model -6 Speed Parameter Units Grade Industrial Commercial tpllcin -0.023 -0.023 0.188 ns -0.018 -0.018 0.182 ns tpllcout Table 4–87 describes clock timing specifications. Table 4–87. EP1AGX60 Row Pins Global Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.792 1.792 4.165 ns 1.792 1.792 4.165 ns tcout tpllcin 0.238 0.238 0.758 ns 0.238 0.238 0.758 ns tpllcout Tables 4–88 through 4–89 show the RCLK clock timing parameters for EP1AGX60 devices. Table 4–88 describes clock timing specifications. Table 4–88. EP1AGX60 Row Pins Regional Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.382 1.382 3.268 ns 1.387 1.387 3.262 ns tcout tpllcin -0.031 -0.031 0.174 ns -0.026 -0.026 0.168 ns tpllcout 4–100 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–89 describes clock timing specifications. Table 4–89. EP1AGX60 Row Pins Regional Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.649 1.649 3.835 ns 1.651 1.651 3.839 ns tcout tpllcin 0.245 0.245 0.755 ns 0.245 0.245 0.755 ns tpllcout EP1AGX90 Clock Timing Parameters Tables 4–90 through 4–91 show the GCLK clock timing parameters for EP1AGX90 devices. Table 4–90 describes clock timing specifications. Table 4–90. EP1AGX90 Row Pins Global Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.630 1.630 3.799 ns 1.635 1.635 3.793 ns tcout tpllcin -0.422 -0.422 -0.310 ns -0.417 -0.417 -0.316 ns tpllcout Table 4–91 describes clock timing specifications. Table 4–91. EP1AGX90 Row Pins Global Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.904 1.904 4.376 ns 1.904 1.904 4.376 ns tcout tpllcin -0.153 -0.153 0.254 ns -0.153 -0.153 0.254 ns tpllcout Altera Corporation 4–101 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Block Performance Tables 4–92 through 4–93 show the RCLK clock timing parameters for EP1AGX90 devices. Table 4–92 describes clock timing specifications. Table 4–92. EP1AGX90 Row Pins Regional Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.462 1.462 3.407 ns 1.467 1.467 3.401 ns tcout tpllcin -0.430 -0.430 -0.322 ns -0.425 -0.425 -0.328 ns tpllcout Table 4–93 describes clock timing specifications. Table 4–93. EP1AGX90 Row Pins Regional Clock Timing Parameters Fast Model -6 Speed Parameter Units Grade Industrial Commercial tcin 1.760 1.760 4.011 ns 1.760 1.760 4.011 ns tcout tpllcin -0.118 -0.118 0.303 ns -0.118 -0.118 0.303 ns tpllcout Table 4–94 shows the Arria GX performance for some common designs. Block All performance values were obtained with the Quartus II software Performance compilation of library of parameterized modules (LPM) or MegaCore functions for finite impulse response (FIR) and fast Fourier transform (FFT) designs. 4–102 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–94 describes performance notes. Table 4–94. Arria GX Performance Notes (Part 1 of 2) Resources Used Performance Applications TriMatrix ALUTs DSP Blocks -6 Speed Grade Memory Blocks LE 16-to-1 5 0 0 168.41 multiplexer 32-to-1 11 0 0 334.11 multiplexer 16-bit counter 16 0 0 374.0 64-bit counter 64 0 0 168.41 TriMatrix Simple dual-port 0 1 0 348.0 Memory M512 RAM 32 x 18 bit block FIFO 32 x 18 bit 0 1 0 333.22 TriMatrix Simple dual-port 0 1 0 344.71 Memory M4K RAM 128 x 36 bit block True dual-port 0 1 0 348.0 RAM 128 x 18 bit TriMatrix Single port RAM 0 2 0 244.0 Memory 4K x 144 bit MegaRAM block Simple dual-port 0 1 0 292.0 RAM 4K x 144 bit True dual-port 0 2 0 244.0 RAM 4K x 144 bit Single port RAM 0 1 0 247.0 8K x 72 bit Simple dual-port 0 1 0 292.0 RAM 8K x 72 bit Single port RAM 0 1 0 254.0 16K x 36 bit Simple dual-port 0 1 0 292.0 RAM 16K x 36 bit True dual-port 0 1 0 251.0 RAM 16K x 36 bit Single port RAM 0 1 0 317.36 32K x 18 bit Altera Corporation 4–103 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Block Performance Table 4–94. Arria GX Performance Notes (Part 2 of 2) Resources Used Performance Applications TriMatrix ALUTs DSP Blocks -6 Speed Grade Memory Blocks Simple dual-port 0 1 0 292.0 RAM 32K x 18 bit True dual-port 0 1 0 251.0 RAM 32K x 18 bit Single port RAM 0 1 0 254.0 64K x 9 bit Simple dual-port 0 1 0 292.0 RAM 64K x 9 bit True dual-port 0 1 0 251.0 RAM 64K x 9 bit DSP block 9 x 9-bit 0 0 1 335.35 multiplier 18 x 18-bit 0 0 2 285.0 multiplier 18 x 18-bit 0 0 4 335.35 multiplier 36 x 36-bit 0 0 8 174.4 multiplier 36 x 36-bit 0 0 8 285.0 multiplier 18-bit 4-tap FIR 0 0 8 163.0 filter Larger Designs 8-bit 16-tap 0 0 4 163.0 parallel FIR filter 4–104 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Refer to Tables 4–95 to 4–96 for IOE programmable delay. IOE Programmable Table 4–95 describes IOE programmable delays. Delay Table 4–95. Arria GX IOE Programmable Delay on Row Pins Fast Model -6 Speed Grade Paths Available Industrial Commercial Parameter Units Affected Settings Min Max Min Max Min Max Offset Offset Offset Offset Offset Offset Input delay from Pad to I/O 8 0 1.782 0 1.782 0 4.124 ns pin to internal dataout to cells core Input delay from Pad to I/O 64 0 2.054 0 2.054 0 4.689 ns pin to input input register register Delay from I/O output 2 0 0.332 0 0.332 0 0.717 ns output register register to to output pin pad Output enable txz/tzx 2 0 0.32 0 0.32 0 0.693 ns pin delay Table 4–96 describes IOE programmable delays. Table 4–96. Arria GX IOE Programmable Delay on Column Pins (Part 1 of 2) Fast Model -6 Speed Grade Paths Available Industrial Commercial Parameter Units Affected Settings Min Max Min Max Min Max Offset Offset Offset Offset Offset Offset Input delay Pad to I/O 8 0 1.781 0 1.781 0 4.132 ns from pin to dataout to internal cells core Input delay Pad to I/O 64 0 2.053 0 2.053 0 4.697 ns from pin to input input register register Altera Corporation 4–105 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Maximum Input and Output Clock Toggle Rate Table 4–96. Arria GX IOE Programmable Delay on Column Pins (Part 2 of 2) Fast Model -6 Speed Grade Paths Available Industrial Commercial Parameter Units Affected Settings Min Max Min Max Min Max Offset Offset Offset Offset Offset Offset Delay from I/O output 2 0 0.332 0 0.332 0 0.717 ns output register register to to output pin pad Output enable txz/tzx 2 0 0.32 0 0.32 0 0.693 ns pin delay Maximum clock toggle rate is defined as the maximum frequency Maximum Input achievable for a clock type signal at an I/O pin. The I/O pin can be a and Output Clock regular I/O pin or a dedicated clock I/O pin. Toggle Rate The maximum clock toggle rate is different from the maximum data bit rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz, the maximum data bit rate for dual data rate (DDR) could be potentially as high as 600 Mbps on the same I/O pin. Table 4–73 specifies the maximum input clock toggle rates. To calculate the output toggle rate for a non 0 pF load, use this formula: The toggle rate for a non 0 pF load = 1,000 / (1,000/ toggle rate at 0 pF load + derating factor × load value in pF /1,000) For example, the output toggle rate at 0 pF load for SSTL-18 Class II 20 mA I/O standard is 550 MHz on a -3 device clock output pin. The derating factor is 94 ps/pF. For a 10 pF load the toggle rate is calculated as: 1,000 / (1,000/550 + 94 × 10 /1,000) = 363 (MHz) Table 4–97 shows the maximum input clock toggle rates for Arria GX device column I/O pins. 4–106 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–97 describes maximum input toggle rate for column I/O pins. Table 4–97. Arria GX Maximum Input Toggle Rate for Column I/O Pins I/O Standards -6 Speed Grade Units 3.3-V LVTTL 420 MHz 3.3-V LVCMOS 420 MHz 2.5 V 420 MHz 1.8 V 420 MHz 1.5 V 420 MHz SSTL-2 CLASS I 467 MHz SSTL-2 CLASS II 467 MHz SSTL-18 CLASS I 467 MHz SSTL-18 CLASS II 467 MHz 1.8-V HSTL CLASS I 467 MHz 1.8-V HSTL CLASS II 467 MHz 1.5-V HSTL CLASS I 467 MHz 1.5-V HSTL CLASS II 467 MHz 3.3-V PCI 420 MHz 3.3-V PCI-X 420 MHz Table 4–98 shows the maximum input clock toggle rates for Arria GX device row I/O pins. Table 4–98 describes maximum input toggle rate for row I/O pins. Table 4–98. Arria GX Maximum Input Toggle Rate for Row I/O Pins (Part 1 of 2) I/O Standards -6 Speed Grade Units 3.3-V LVTTL 420 MHz 3.3-V LVCMOS 420 MHz 2.5 V 420 MHz 1.8 V 420 MHz 1.5 V 420 MHz SSTL-2 CLASS I 467 MHz SSTL-2 CLASS II 467 MHz SSTL-18 CLASS I 467 MHz Altera Corporation 4–107 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Maximum Input and Output Clock Toggle Rate Table 4–98. Arria GX Maximum Input Toggle Rate for Row I/O Pins (Part 2 of 2) I/O Standards -6 Speed Grade Units SSTL-18 CLASS II 467 MHz 1.8-V HSTL CLASS I 467 MHz 1.8-V HSTL CLASS II 467 MHz 1.5-V HSTL CLASS I 467 MHz 1.5-V HSTL CLASS II 467 MHz LVDS 392 MHz Table 4–99 shows the maximum input clock toggle rates for Arria GX device dedicated clock pins. Table 4–99 describes maximum input clock rate for dedicated clock pins. Table 4–99. Arria GX Maximum Input Clock Rate for Dedicated Clock Pins (Part 1 of 2) I/O Standards -6 Speed Grade Units 3.3-V LVTTL 373 MHz 3.3-V LVCMOS 373 MHz 2.5 V 373 MHz 1.8 V 373 MHz 1.5 V 373 MHz SSTL-2 CLASS I 467 MHz SSTL-2 CLASS II 467 MHz 3.3-V PCI 373 MHz 3.3-V PCI-X 373 MHz SSTL-18 CLASS I 467 MHz SSTL-18 CLASS II 467 MHz 1.8-V HSTL CLASS I 467 MHz 1.8-V HSTL CLASS II 467 MHz 1.5-V HSTL CLASS I 467 MHz 1.5-V HSTL CLASS II 467 MHz 1.2-V HSTL 233 MHz DIFFERENTAL SSTL-2 467 MHz DIFFERENTIAL 2.5-V 467 MHz SSTL CLASS II 4–108 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–99. Arria GX Maximum Input Clock Rate for Dedicated Clock Pins (Part 2 of 2) I/O Standards -6 Speed Grade Units DIFFERENTIAL 1.8-V 467 MHz SSTL CLASS I DIFFERENTIAL 1.8-V 467 MHz SSTL CLASS II DIFFERENTIAL 1.8-V 467 MHz HSTL CLASS I DIFFERENTIAL 1.8-V 467 MHz HSTL CLASS II DIFFERENTIAL 1.5-V 467 MHz HSTL CLASS I DIFFERENTIAL 1.5-V 467 MHz HSTL CLASS II DIFFERENTIAL 1.2-V 233 MHz HSTL LVDS 598 MHz LVDS (1) 373 MHz Note to Table 4–99: (1) This set of numbers refers to the VIO dedicated input clock pins. Table 4–100 shows the maximum output clock toggle rates for Arria GX device column I/O pins. Table 4–100 describes maximum output toggle rate for column I/O pins. Table 4–100. Arria GX Maximum Output Toggle Rate for Column I/O Pins (Part 1 of 3) I/O Standards Drive Strength -6 Speed Grade Units 3.3-V LVTTL 4 mA 196 MHz 8mA 303 MHz 12 mA 393 MHz 16 mA 486 MHz 20 mA 570 MHz 24 mA 626 MHz Altera Corporation 4–109 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Maximum Input and Output Clock Toggle Rate Table 4–100. Arria GX Maximum Output Toggle Rate for Column I/O Pins (Part 2 of 3) I/O Standards Drive Strength -6 Speed Grade Units 3.3-V LVCMOS 4 mA 215 MHz 8mA 411 MHz 12 mA 626 MHz 16 mA 819 MHz 20 mA 874 MHz 24 mA 934 MHz 2.5 V 4 mA 168 MHz 8mA 355 MHz 12 mA 514 MHz 16 mA 766 MHz 1.8 V 2 mA 97 MHz 4mA 215 MHz 6mA 336 MHz 8mA 486 MHz 10 mA 706 MHz 12 mA 925 MHz 1.5 V 2 mA 168 MHz 4mA 303 MHz 6mA 350 MHz 8mA 392 MHz SSTL-2 CLASS I 8 mA 280 MHz 12 mA 327 MHz SSTL-2 CLASS II 16 mA 280 MHz 20 mA 327 MHz 24 mA 327 MHz SSTL-18 CLASS I 4 mA 140 MHz 6mA 186 MHz 8mA 280 MHz 10 mA 373 MHz 12 mA 373 MHz 4–110 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–100. Arria GX Maximum Output Toggle Rate for Column I/O Pins (Part 3 of 3) I/O Standards Drive Strength -6 Speed Grade Units SSTL-18 CLASS II 8 mA 140 MHz 16 mA 327 MHz 18 mA 373 MHz 20 mA 420 MHz 1.8-V HSTL CLASS I 4 mA 280 MHz 6mA 420 MHz 8mA 561 MHz 10 mA 561 MHz 12 mA 607 MHz 1.8-V HSTL CLASS II 16 mA 420 MHz 18 mA 467 MHz 20 mA 514 MHz 1.5-V HSTL CLASS I 4 mA 280 MHz 6mA 420 MHz 8mA 561 MHz 10 mA 607 MHz 12 mA 654 MHz 1.5-V HSTL CLASS II 16 mA 514 MHz 18 mA 561 MHz 20 mA 561 MHz 3.3-V PCI mA 626 MHz 3.3-V PCI-X mA 626 MHz Table 4–101 shows the maximum output clock toggle rates for Arria GX device row I/O pins. Table 4–101 describes maximum output toggle rate for row I/O pins. Table 4–101. Arria GX Maximum Output Toggle Rate for Row I/O Pins (Part 1 of 2) I/O Standards Drive Strength -6 Speed Grade Units 3.3-V LVTTL 4 mA 196 MHz 8mA 303 MHz 12 mA 393 MHz Altera Corporation 4–111 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Maximum Input and Output Clock Toggle Rate Table 4–101. Arria GX Maximum Output Toggle Rate for Row I/O Pins (Part 2 of 2) I/O Standards Drive Strength -6 Speed Grade Units 3.3-V LVCMOS 4 mA 215 MHz 8mA 411 MHz 2.5 V 4 mA 168 MHz 8mA 355 MHz 12 mA 514 MHz 1.8 V 2 mA 97 MHz 4mA 215 MHz 6mA 336 MHz 8mA 486 MHz 1.5 V 2 mA 168 MHz 4mA 303 MHz SSTL-2 CLASS I 8 mA 280 MHz 12 mA 327 MHz SSTL-2 CLASS II 16 mA 280 MHz SSTL-18 CLASS I 4 mA 140 MHz 6mA 186 MHz 8mA 280 MHz 10 mA 373 MHz 1.8-V HSTL CLASS I 4 mA 280 MHz 6mA 420 MHz 8mA 561 MHz 10 mA 561 MHz 12 mA 607 MHz 1.5-V HSTL CLASS I 4 mA 280 MHz 6mA 420 MHz 8mA 561 MHz LVDS mA 598 MHz Table 4–102 shows the maximum output clock toggle rates for Arria GX device dedicated clock pins. 4–112 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–102 describes maximum output clock rate for dedicated clock pins. Table 4–102. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 1 of 4) -6 Speed I/O Standards Drive Strength Units Grade 3.3-V LVTTL 4 mA 196 MHz 8mA 303 MHz 12 mA 393 MHz 16 mA 486 MHz 20 mA 570 MHz 24 mA 626 MHz 3.3-V LVCMOS 4 mA 215 MHz 8mA 411 MHz 12 mA 626 MHz 16 mA 819 MHz 20 mA 874 MHz 24 mA 934 MHz 2.5 V 4 mA 168 MHz 8mA 355 MHz 12 mA 514 MHz 16 mA 766 MHz 1.8 V 2 mA 97 MHz 4mA 215 MHz 6mA 336 MHz 8mA 486 MHz 10 mA 706 MHz 12 mA 925 MHz 1.5 V 2 mA 168 MHz 4mA 303 MHz 6mA 350 MHz 8mA 392 MHz SSTL-2 CLASS I 8 mA 280 MHz 12 mA 327 MHz Altera Corporation 4–113 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Maximum Input and Output Clock Toggle Rate Table 4–102. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 2 of 4) -6 Speed I/O Standards Drive Strength Units Grade SSTL-2 CLASS II 16 mA 280 MHz 20 mA 327 MHz 24 mA 327 MHz SSTL-18 CLASS I 4 mA 140 MHz 6mA 186 MHz 8mA 280 MHz 10 mA 373 MHz 12 mA 373 MHz SSTL-18 CLASS II 8 mA 140 MHz 16 mA 327 MHz 18 mA 373 MHz 20 mA 420 MHz 1.8-V HSTL CLASS I 4 mA 280 MHz 6mA 420 MHz 8mA 561 MHz 10 mA 561 MHz 12 mA 607 MHz 1.8-V HSTL CLASS II 16 mA 420 MHz 18 mA 467 MHz 20 mA 514 MHz 1.5-V HSTL CLASS I 4 mA 280 MHz 6mA 420 MHz 8mA 561 MHz 10mA 607 MHz 12 mA 654 MHz 1.5-V HSTL CLASS II 16 mA 514 MHz 18 mA 561 MHz 20 mA 561 MHz 24 mA 278 MHz DIFFERENTIAL SSTL-2 8 mA 280 MHz 12 mA 327 MHz 4–114 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–102. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 3 of 4) -6 Speed I/O Standards Drive Strength Units Grade DIFFERENTIAL 2.5-V 16 mA 280 MHz SSTL CLASS II 20 mA 327 MHz 24 mA 327 MHz DIFFERENTIAL 1.8-V 4mA 140 MHz SSTL CLASS I 6mA 186 MHz 8mA 280 MHz 10 mA 373 MHz 12 mA 373 MHz DIFFERENTIAL 1.8-V 8mA 140 MHz SSTL CLASS II 16 mA 327 MHz 18 mA 373 MHz 20 mA 420 MHz DIFFERENTIAL 1.8-V 4mA 280 MHz HSTL CLASS I 6mA 420 MHz 8mA 561 MHz 10 mA 561 MHz 12 mA 607 MHz DIFFERENTIAL 1.8-V 16 mA 420 MHz HSTL CLASS II 18 mA 467 MHz 20 mA 514 MHz DIFFERENTIAL 1.5-V 4mA 280 MHz HSTL CLASS I 6mA 420 MHz 8mA 561 MHz 10 mA 607 MHz 12 mA 654 MHz DIFFERENTIAL 1.5-V 16 mA 514 MHz HSTL CLASS II 18 mA 561 MHz 20 mA 561 MHz 24 mA 278 MHz 3.3-V PCI - 626 MHz 3.3-V PCI-X - 626 MHz LVDS - 280 MHz HYPERTRANSPORT - 116 MHz Altera Corporation 4–115 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Maximum Input and Output Clock Toggle Rate Table 4–102. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 4 of 4) -6 Speed I/O Standards Drive Strength Units Grade LVPECL - 280 MHz 3.3-V LVTTL SERIES_25_OHMS 327 MHz SERIES_50_OHMS 327 MHz 3.3-V LVCMOS SERIES_25_OHMS 280 MHz SERIES_50_OHMS 280 MHz 2.5 V SERIES_25_OHMS 280 MHz SERIES_50_OHMS 280 MHz 1.8 V SERIES_25_OHMS 420 MHz SERIES_50_OHMS 420 MHz 1.5 V SERIES_50_OHMS 373 MHz SSTL-2 CLASS I SERIES_50_OHMS 467 MHz SSTL-2 CLASS II SERIES_25_OHMS 467 MHz SSTL-18 CLASS I SERIES_50_OHMS 327 MHz SSTL-18 CLASS II SERIES_25_OHMS 420 MHz 1.8-V HSTL CLASS I SERIES_50_OHMS 561 MHz 1.8-V HSTL CLASS II SERIES_25_OHMS 420 MHz 1.5-V HSTL CLASS I SERIES_50_OHMS 467 MHz 1.2-V HSTL SERIES_50_OHMS 233 MHz DIFFERENTIAL SSTL-2 SERIES_50_OHMS 467 MHz DIFFERENTIAL 2.5-V SERIES_25_OHMS 467 MHz SSTL CLASS II DIFFERENTIAL 1.8-V SERIES_50_OHMS 327 MHz SSTL CLASS I DIFFERENTIAL 1.8-V SERIES_25_OHMS 420 MHz SSTL CLASS II DIFFERENTIAL 1.8-V SERIES_50_OHMS 561 MHz HSTL CLASS I DIFFERENTIAL 1.8-V SERIES_25_OHMS 420 MHz HSTL CLASS II DIFFERENTIAL 1.5-V SERIES_50_OHMS 467 MHz HSTL CLASS I DIFFERENTIAL 1.2-V SERIES_50_OHMS 233 MHz HSTL 4–116 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Duty cycle distortion (DCD) describes how much the falling edge of a Duty Cycle clock is off from its ideal position. The ideal position is when both the Distortion clock high time (CLKH) and the clock low time (CLKL) equal half of the clock period (T), as shown in Figure 4–10. DCD is the deviation of the non-ideal falling edge from the ideal falling edge, such as D1 for the falling edge A and D2 for the falling edge B (see Figure 4–10). The maximum DCD for a clock is the larger value of D1 and D2. Figure 4–10. Duty Cycle Distortion Ideal Falling Edge CLKH = T/2 CLKL = T/2 D1 D2 Falling Edge A Falling Edge B Clock Period (T) DCD expressed in absolution derivation, for example, D1 or D2 in Figure 4–10, is clock-period independent. DCD can also be expressed as a percentage, and the percentage number is clock-period dependent. DCD as a percentage is defined as: (T/2 – D1) / T (the low percentage boundary) (T/2 + D2) / T (the high percentage boundary) DCD Measurement Techniques DCD is measured at an FPGA output pin driven by registers inside the corresponding I/O element (IOE) block. When the output is a single data rate signal (non-DDIO), only one edge of the register input clock (positive or negative) triggers output transitions (Figure 4–11). Therefore, any DCD present on the input clock signal or caused by the clock input buffer or different input I/O standard does not transfer to the output signal. Altera Corporation 4–117 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Duty Cycle Distortion Figure 4–11. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs However, when the output is a double data rate input/output (DDIO) signal, both edges of the input clock signal (positive and negative) trigger output transitions (Figure 4–12). Therefore, any distortion on the input clock and the input clock buffer affect the output DCD. Figure 4–12. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs When an FPGA PLL generates the internal clock, the PLL output clocks the IOE block. As the PLL only monitors the positive edge of the reference clock input and internally re-creates the output clock signal, any DCD present on the reference clock is filtered out. Therefore, the DCD for a DDIO output with PLL in the clock path is better than the DCD for a DDIO output without PLL in the clock path. 4–118 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Tables 4–103 through 4–108 show the maximum DCD in absolution derivation for different I/O standards on Arria GX devices. Examples are also provided that show how to calculate DCD as a percentage. Table 4–103. Maximum DCD for Non-DDIO Output on Row I/O Pins Maximum DCD (ps) for Non-DDIO Output Row I/O Output Standard -6 Speed Grade Unit 3.3-V LVTTTL 275 ps 3.3-V LVCMOS 155 ps 2.5 V 135 ps 1.8 V 180 ps 1.5-V LVCMOS 195 ps SSTL-2 Class I 145 ps SSTL-2 Class II 125 ps SSTL-18 Class I 85 ps 1.8-V HSTL Class I 100 ps 1.5-V HSTL Class I 115 ps LVDS 80 ps Here is an example for calculating the DCD as a percentage for a non-DDIO output on a row I/O: If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum DCD is 125 ps (see Table 4–104). If the clock frequency is 267 MHz, the clock period T is: T = 1/ f = 1 / 267 MHz = 3.745 ns = 3,745 ps To calculate the DCD as a percentage: (T/2 – DCD) / T = (3,745 ps/2 – 125 ps) / 3,745 ps = 46.66% (for low boundary) (T/2 + DCD) / T = (3,745 ps/2 + 125 ps) / 3,745 ps = 53.33% (for high boundary) Therefore, the DCD percentage for the output clock at 267 MHz is from 46.66% to 53.33%. Altera Corporation 4–119 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Duty Cycle Distortion Table 4–104. Maximum DCD for Non-DDIO Output on Column I/O Pins Maximum DCD (ps) for Non-DDIO Column I/O Output Output Unit Standard I/O Standard -6 Speed Grade 3.3-V LVTTL 220 ps 3.3-V LVCMOS 175 ps 2.5 V 155 ps 1.8 V 110 ps 1.5-V LVCMOS 215 ps SSTL-2 Class I 135 ps SSTL-2 Class II 130 ps SSTL-18 Class I 115 ps SSTL-18 Class II 100 ps 1.8-V HSTL Class I 110 ps 1.8-V HSTL Class II 110 ps 1.5-V HSTL Class I 115 ps 1.5-V HSTL Class II 80 ps 1.2-V HSTL-12 200 ps LVPECL 80 ps Table 4–105. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path Note (1) Input I/O Standard (No PLL in the Clock Path) Maximum DCD (ps) for Row DDIO Output I/O TTL/CMOS SSTL-2 SSTL/HSTL LVDS Unit Standard 3.3/2.5V 1.8/1.5V 2.5V 1.8/1.5V 3.3V 3.3-V LVTTL 440 495 170 160 105 ps 3.3-V LVCMOS 390 450 120 110 75 ps 2.5 V 375 430 105 95 90 ps 1.8 V 325 385 90 100 135 ps 1.5-V LVCMOS 430 490 160 155 100 ps SSTL-2 Class I 355 410 85 75 85 ps SSTL-2 Class II 350 405 80 70 90 ps 4–120 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–105. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path Note (1) Input I/O Standard (No PLL in the Clock Path) Maximum DCD (ps) for Row DDIO Output I/O TTL/CMOS SSTL-2 SSTL/HSTL LVDS Unit Standard 3.3/2.5V 1.8/1.5V 2.5V 1.8/1.5V 3.3V SSTL-18 Class I 335 390 65 65 105 ps 1.8-V HSTL Class I 330 385 60 70 110 ps 1.5-V HSTL Class I 330 390 60 70 105 ps LVDS 180 180 180 180 180 ps Note to Table 4–105: (1) Table 4–105 assumes the input clock has zero DCD. Table 4–106. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path Note (1) Input IO Standard (No PLL in the Clock Path) Maximum DCD (ps) for DDIO Column Output I/O TTL/CMOS SSTL-2 SSTL/HSTL Unit Standard 3.3/2.5V 1.8/1.5V 2.5V 1.8/1.5V 3.3-V LVTTL 440 495 170 160 ps 3.3-V LVCMOS 390 450 120 110 ps 2.5 V 375 430 105 95 ps 1.8 V 325 385 90 100 ps 1.5-V LVCMOS 430 490 160 155 ps SSTL-2 Class I 355 410 85 75 ps SSTL-2 Class II 350 405 80 70 ps SSTL-18 Class I 335 390 65 65 ps SSTL-18 Class II 320 375 70 80 ps 1.8-V HSTL Class I 330 385 60 70 ps 1.8-V HSTL Class II 330 385 60 70 ps 1.5-V HSTL Class I 330 390 60 70 ps 1.5-V HSTL Class II 330 360 90 100 ps LVPECL 180 180 180 180 ps Note to Table 4–106: (1) Table 4–106 assumes the input clock has zero DCD. Altera Corporation 4–121 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Duty Cycle Distortion Table 4–107. Maximum DCD for DDIO Output on Row I/O Pins With PLL in the Clock Path Arria GX Devices (PLL Output Maximum DCD (ps) for Row DDIO Feeding DDIO) Unit Output I/O Standard -6 Speed Grade 3.3-V LVTTL 105 ps 3.3-V LVCMOS 75 ps 2.5V 90 ps 1.8V 100 ps 1.5-V LVCMOS 100 ps SSTL-2 Class I 75 ps SSTL-2 Class II 70 ps SSTL-18 Class I 65 ps 1.8-V HSTL Class I 70 ps 1.5-V HSTL Class I 70 ps LVDS 180 ps Table 4–108. Maximum DCD for DDIO Output on Column I/O Pins With PLL in the Clock Path (Part 1 of 2) Arria GX Devices (PLL Output Maximum DCD (ps) for Column Feeding DDIO) Unit DDIO Output I/O Standard -6 Speed Grade 3.3-V LVTTL 160 ps 3.3-V LVCMOS 110 ps 2.5V 95 ps 1.8V 100 ps 1.5-V LVCMOS 155 ps SSTL-2 Class I 75 ps SSTL-2 Class II 70 ps SSTL-18 Class I 65 ps SSTL-18 Class II 80 ps 1.8-V HSTL Class I 70 ps 1.8-V HSTL Class II 70 ps 1.5-V HSTL Class I 70 ps 1.5-V HSTL Class II 100 ps 4–122 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–108. Maximum DCD for DDIO Output on Column I/O Pins With PLL in the Clock Path (Part 2 of 2) Arria GX Devices (PLL Output Maximum DCD (ps) for Column Feeding DDIO) Unit DDIO Output I/O Standard -6 Speed Grade 1.2-V HSTL 155 ps LVPECL 180 ps Table 4–109 provides high-speed timing specifications definitions. High-Speed I/O Specifications Table 4–109. High-Speed Timing Specifications & Definitions High-Speed Timing Specifications Definitions t High-speed receiver/transmitter input and output clock period. C f High-speed receiver/transmitter input and output clock frequency. HSCLK J Deserialization factor (width of parallel data bus). W PLL multiplication factor. t Low-to-high transmission time. RISE t High-to-low transmission time. FALL Timing unit interval (TUI) The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency × Multiplication Factor) = t /w). C f Maximum/minimum LVDS data transfer rate (f = 1/TUI), non-DPA. HSDR HSDR f Maximum/minimum LVDS data transfer rate (f = 1/TUI), DPA. HSDRDPA HSDRDPA Channel-to-channel skew (TCCS) The timing difference between the fastest and slowest output edges, including t variation and clock skew. The clock is included in the TCCS CO measurement. Sampling window (SW) The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window. Input jitter Peak-to-peak input jitter on high-speed PLLs. Output jitter Peak-to-peak output jitter on high-speed PLLs. t Duty cycle on high-speed transmitter output clock. DUTY t Lock time for high-speed transmitter and receiver PLLs. LOCK Altera Corporation 4–123 June 2007 Preliminary Arria GX Device Handbook, Volume 1 High-Speed I/O Specifications Table 4–110 shows the high-speed I/O timing specifications. Table 4–110. High-Speed I/O Specifications Notes (1), (2) -6 Speed Grade Symbol Conditions Unit Min Typ Max f (clock frequency) W = 2 to 32 (LVDS, HyperTransport technology) 16 420 MHz HSCLK (3) f = f / W HSCLK HSDR W = 1 (SERDES bypass, LVDS only) 16 500 MHz W = 1 (SERDES used, LVDS only) 150 640 MHz f (data rate) J = 4 to 10 (LVDS, HyperTransport technology) 150 840 Mbps HSDR J = 2 (LVDS, HyperTransport technology) (4) 700 Mbps J = 1 (LVDS only) (4) 500 Mbps f (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology) 150 840 Mbps HSDRDPA TCCS All differential I/O standards - 200 ps SW All differential I/O standards 440 - ps Output jitter 190 ps Output t All differential I/O standards 290 ps RISE Output t All differential I/O standards 290 ps FALL t 45 50 55 % DUTY DPA run length 6,400 UI DPA jitter tolerance Data channel peak-to-peak jitter 0.44 UI DPA lock time Standard Training Transition Number of Pattern Density repetitions SPI-4 0000000000 10% 256 1111111111 Parallel Rapid I/O 00001111 25% 256 10010000 50% 256 Miscellaneous 10101010 100% 256 01010101 256 Notes to Table 4–110: (1) When J = 4 to 10, the SERDES block is used. (2) When J = 1 or 2, the SERDES block is bypassed. (3) The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock frequency × W ≤ 1,040. (4) The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not have a minimum toggle rate. 4–124 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Tables 4–111 and 4–112 describe the Arria GX PLL specifications when PLL Timing operating in both the commercial junction temperature range (0 to 85 C) Specifications and the industrial junction temperature range (–40 to 100 C), except for the clock switchover and phase-shift stepping features. These two features are only supported from the 0 to 100 C junction temperature range. Table 4–111. Enhanced PLL Specifications (Part 1 of 2) Name Description Min Typ Max Unit f Input clock frequency 2 500 MHz IN f Input frequency to the PFD 2 420 MHz INPFD f Input clock duty cycle 40 60 % INDUTY f External feedback input clock duty cycle 40 60 % ENDUTY t Input or external feedback clock input jitter 0.5 ns (peak- INJITTER tolerance in terms of period jitter. to-peak) Bandwidth ≤ 0.85 MHz Input or external feedback clock input jitter 1.0 ns (peak- tolerance in terms of period jitter. to-peak) Bandwidth > 0.85 MHz t Dedicated clock output period jitter 50 100 250 ps (p-p) OUTJITTER t External feedback compensation time 10 ns FCOMP f Output frequency for internal global or 1.5 (2) 550 MHz OUT regional clock f Scanclk frequency 100 MHz SCANCLK t Time required to reconfigure scan chains 174/f ns CONFIGEPLL SCANCLK for EPLLs f PLL external clock output frequency 1.5 (2) (1) MHz OUT_EXT t Time required for the PLL to lock from the 0.03 1 ms LOCK time it is enabled or the end of device configuration t Time required for the PLL to lock 1ms DLOCK dynamically after automatic clock switchover between two identical clock frequencies f Frequency range where the clock 1.5 1 500 MHz SWITCHOVER switchover performs properly f PLL closed-loop bandwidth 0.13 1.2 16.9 MHz CLBW f PLL VCO operating range 300 840 MHz VCO f Spread-spectrum modulation frequency 100 500 kHz SS % spread Percent down spread for a given clock 0.4 0.5 0.6 % frequency Altera Corporation 4–125 June 2007 Preliminary Arria GX Device Handbook, Volume 1 PLL Timing Specifications Table 4–111. Enhanced PLL Specifications (Part 2 of 2) Name Description Min Typ Max Unit t Accuracy of PLL phase shift ±30 ps PLL_PSERR t Minimum pulse width on areset signal. 10 ns ARESET t 500 ns Minimum pulse width on the areset ARESET_RECONFIG signal when using PLL reconfiguration. Reset the PLL after scandone goes high. t The time required for the wait after the 2us RECONFIGWAIT reconfiguration is done and the areset is applied. Notes to Table 4–111: (1) This is limited by the I/O f . MAX (2) If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency. Table 4–112. Fast PLL Specifications (Part 1 of 2) Name Description Min Typ Max Unit f Input clock frequency 16.08 640 MHz IN f Input frequency to the PFD 16.08 500 MHz INPFD f Input clock duty cycle 40 60 % INDUTY t Input clock jitter tolerance in terms of period 0.5 ns (p-p) INJITTER jitter. Bandwidth ≤ 2MHz Input clock jitter tolerance in terms of period 1.0 ns (p-p) jitter. Bandwidth > 0.2 MHz f Upper VCO frequency range 300 840 MHz VCO Lower VCO frequency range 150 420 MHz f 4.6875 550 MHz PLL output frequency to GCLK or RCLK OUT PLL output frequency to LVDS or DPA clock 150 840 MHz f PLL clock output frequency to regular I/O 4.6875 (1) MHz OUT_EXT f Duty cycle for external clock output 45 50 55 % OUTDUTY t Time required to reconfigure scan chains for 75/f ns CONFIGPLL SCANCLK fast PLLs f PLL closed-loop bandwidth 1.16 5 28 MHz CLBW t Time required for the PLL to lock from the 0.03 1 ms LOCK time it is enabled or the end of the device configuration t Accuracy of PLL phase shift ±30 ps PLL_PSERR t Minimum pulse width on areset signal. 10 ns ARESET 4–126 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Table 4–112. Fast PLL Specifications (Part 2 of 2) Name Description Min Typ Max Unit t Minimum pulse width on the areset signal 500 ns ARESET_RECONFIG when using PLL reconfiguration. Reset the PLL after scandone goes high. Note to Table 4–112: (1) This is limited by the I/O f . MAX Tables 4–113 through 4–117 contain Arria GX device specifications for the External dedicated circuitry used for interfacing with external memory devices. Memory Interface Table 4–113. DLL Frequency Range Specifications Specifications Frequency Mode Frequency Range (MHz) 0 100 to 175 1 150 to 230 2 200 to 310 Table 4–114. DQS Jitter Specifications for DLL-Delayed Clock (t _ ), DQS JITTER Note (1) Number of DQS Delay Buffer Stages Commercial (ps) Industrial (ps) (2) 1 80 110 2 110 130 3 130 180 4 160 210 Notes to Table 4–114: (1) Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on two delay stages under commercial conditions is 200 ps peak-to-peak or 100 ps. (2) Delay stages used for requested DQS phase shift are reported in a project’s Compilation Report in the Quartus II software. Table 4–115. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (t _ ) (Part 1 of 2) DQS PSERR Number of DQS Delay Buffer Stages –6 Speed Grade (ps) 135 270 Altera Corporation 4–127 June 2007 Preliminary Arria GX Device Handbook, Volume 1 External Memory Interface Specifications Table 4–115. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (t _ ) (Part 2 of 2) DQS PSERR Number of DQS Delay Buffer Stages –6 Speed Grade (ps) 3105 4140 Table 4–116. DQS Bus Clock Skew Adder Specifications (t _CLOCK_SKEW_ADDER) DQS Mode DQS Clock Skew Adder (ps) 4 DQ per DQS 40 9 DQ per DQS 70 18 DQ per DQS 75 36 DQ per DQS 95 Table 4–117. DQS Phase Offset Delay Per Stage (ps) Notes (1), (2), and (3) Positive Offset Negative Offset Speed Grade Min Max Min Max -6 10 16 8 12 Notes to Table 4–117: (1) The delay settings are linear. (2) The valid settings for phase offset are -32 to +31. (3) The typical value equals the average of the minimum and maximum values. 4–128 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Figure 4–13 shows the timing requirements for the JTAG signals JTAG Timing Specifications Figure 4–13. Arria GX JTAG Waveforms. TMS TDI t JCP t t t t JCH JCL JPSU JPH TCK t t t JPZX JPXZ JPCO TDO t t JSSU JSH Signal to be Captured t t t JSCO JSXZ JSZX Signal to be Driven Altera Corporation 4–129 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Document Revision History Table 4–118 shows the JTAG timing parameters and values for Arria GX devices. Table 4–118. Arria GX JTAG Timing Parameters & Values Symbol Parameter Min Max Unit t TCK clock period 30 ns JCP t TCK clock high time 12 ns JCH t TCK clock low time 12 ns JCL t JTAG port setup time 4 ns JPSU t JTAG port hold time 5 ns JPH t JTAG port clock to output 9 ns JPCO t JTAG port high impedance to valid output 9 ns JPZX t JTAG port valid output to high impedance 9 ns JPXZ t Capture register setup time 4 ns JSSU t Capture register hold time 5 ns JSH t Update register clock to output 12 ns JSCO t Update register high impedance to valid output 12 ns JSZX t Update register valid output to high impedance 12 ns JSXZ Table 4–119 shows the revision history for this chapter. Document Revision History Table 4–119. Document Revision History Date and Document Changes Made Summary of Changes Version June 2007, v1.1 Updated Table 4–94. Added GIGE information. — May 2007 Initial release. — v1.0 4–130 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 DC & Switching Characteristics Altera Corporation 4–131 June 2007 Preliminary Arria GX Device Handbook, Volume 1 Document Revision History 4–132 Altera Corporation Arria GX Device Handbook, Volume 1 Preliminary June 2007 5. Reference and Ordering Information AGX51005-1.0 TM ® ® Arria GX devices are supported by the Altera Quartus II design Software software, which provides a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software includes HDL and schematic design entry, compilation and logic ® synthesis, full simulation and advanced timing analysis, SignalTap II logic analyzer, and device configuration. f Refer to the Quartus II Development Software Handbook for more information on the Quartus II software features. The Quartus II software supports the Windows XP/2000/NT, Sun Solaris 8/9, Linux Red Hat v7.3, Linux Red Hat Enterprise 3, and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the NativeLink interface. Device Pin-Outs f Arria GX device pin-outs are available on the Altera web site at www.altera.com. Altera Corporation 5–1 May 2007 Reference and Ordering Information Figure 5–1 describes the ordering codes for Arria GX devices. Ordering Information f For more information on a specific package, refer to the Package Information for Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook. Figure 5–1. Arria GX Device Packaging Ordering Information EP1AGX 20 CFN 484 C 6 Family Signature Optional Suffix EP1AGX : Arria GX Indicates specific device options or shipment method. N: Lead-free devices Device Type 20 35 Speed Grade 50 60 6 90 Operating Temperature Number of C: Commercial temperature (T = 0˚ C to 85˚ C) J Transceiver I: Industrial temperature (T = -40˚ C to 100˚ C) J Channels Pin Count C: 4 D: 8 484 E: 12 780 Package Type 1152 F: FineLine BGA (FBGA) Table 5–1 shows the revision history for this chapter. Document Revision History Table 5–1. Document Revision History Date and Document Changes Made Summary of Changes Version May 2007, v1.0 Initial Release. — 5–2 Altera Corporation Arria GX Device Handbook, Volume 1 May 2007