Classic EPLD Family ® May 1999, ver. 5 Data Sheet nComplete device family with logic densities of 300 to 900 usable gates Features (see Table 1) nDevice erasure and reprogramming with non-volatile EPROM configuration elements nFast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz n24 to 68 pins available in dual in-line package (DIP), plastic J-lead chip carrier (PLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages nProgrammable security bit for protection of proprietary designs n100% generically tested to provide 100% programming yield nProgrammable registers providing D, T, JK, and SR flipflops with individual clear and clock controls ® ® nSoftware design support featuring the Altera MAX+PLUS II development system on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000 workstations, and third-party development systems nProgramming support with Altera’s Master Programming Unit (MPU); programming hardware from Data I/O, BP Microsystems, and other third-party programming vendors nAdditional design entry and simulation support provided by EDIF, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Table 1. Classic Device Features Feature EP610 EP910 EP1810 EP610I EP910I Usable gates 300 450 900 Macrocells 16 24 48 Maximum user I/O pins 22 38 64 t (ns) 10 12 20 PD f (MHz) 100 76.9 50 CNT Altera Corporation 745 A-DS-CLASSIC-05 Classic EPLD Family Data Sheet TM The Altera Classic device family offers a solution to high-speed, low- General power logic integration. Fabricated on advanced CMOS technology, Description Classic devices also have a Turbo-only version, which is described in this data sheet. Classic devices support 100% TTL emulation and can easily integrate multiple PAL- and GAL-type devices with densities ranging from 300 to 900 usable gates. The Classic family provides pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz. Classic devices are available in a wide range of packages, including ceramic dual in-line package (CerDIP), plastic dual in-line package (PDIP), plastic J-lead chip carrier (PLCC), ceramic J-lead chip carrier (JLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages. EPROM-based Classic devices can reduce active power consumption without sacrificing performance. This reduced power consumption makes the Classic family well suited for a wide range of low-power applications. Classic devices are 100% generically tested devices in windowed packages and can be erased with ultra-violet (UV) light, allowing design changes to be implemented quickly. Classic devices use sum-of-products logic and a programmable register. The sum-of-products logic provides a programmable-AND/fixed-OR structure that can implement logic with up to eight product terms. The programmable register can be individually programmed for D, T, SR, or JK flipflop operation or can be bypassed for combinatorial operation. In addition, macrocell registers can be individually clocked either by a global clock or by any input or feedback path to the AND array. Altera’s proprietary programmable I/O architecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. These features make it possible to implement a variety of logic functions simultaneously. Classic devices are supported by Altera’s MAX+PLUS II development system, a single, integrated package that offers schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and workstation- based EDA tools. The MAX+PLUS II software runs on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. These devices also contain on-board logic test circuitry to allow verification of function and AC specifications during standard production flow. 746 Altera Corporation Classic EPLD Family Data Sheet For more information, see the MAX+PLUS II Programmable Logic f Development System & Software Data Sheet. The Classic architecture includes the following elements: Functional DescriptionnMacrocells nProgrammable registers nOutput enable/clock select nFeedback select Macrocells Classic macrocells, shown in Figure 1, can be individually configured for both sequential and combinatorial logic operation. Eight product terms form a programmable-AND array that feeds an OR gate for combinatorial logic implementation. An additional product term is used for asynchronous clear control of the internal register; another product term implements either an output enable or a logic-array-generated clock. Inputs to the programmable-AND array come from both the true and complement signals of the dedicated inputs, feedbacks from I/O pins that are configured as inputs, and feedbacks from macrocell outputs. Signals from dedicated inputs are globally routed and can feed the inputs of all device macrocells. The feedback multiplexer controls the routing of feedback signals from macrocells and from I/O pins. For additional information on feedback select configurations, see Figure 3 on page 749. Figure 1. Classic Device Macrocell VCC Logic Array Output Enable/Clock Select Global Clock OE CLK Q CLR Programmable Register Feedback To Logic Array Input, I/O, and Select Macrocell Feedbacks Asynchronous Clear Altera Corporation 747 Classic EPLD Family Data Sheet The eight product terms of the programmable-AND array feed the 8-input OR gate, which then feeds one input to an XOR gate. The other input to the XOR gate is connected to a programmable bit that allows the array output to be inverted. Altera’s MAX+PLUS II software uses the XOR gate to implement either active-high or active-low logic, or De Morgan’s inversion to reduce the number of product terms needed to implement a function. Programmable Registers To implement registered functions, each macrocell register can be individually programmed for D, T, JK, or SR operation. If necessary, the register can be bypassed for combinatorial operation. During design compilation, the MAX+PLUS II software selects the most efficient register operation for each registered function to minimize the logic resources needed by the design. Registers have an individual asynchronous clear function that is controlled by a dedicated product term. These registers are cleared automatically during power-up. In addition, macrocell registers can be individually clocked by either a global clock or any input or feedback path to the AND array. Altera’s proprietary programmable I/O architecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. These features make it possible to simultaneously implement a variety of logic functions. Output Enable/Clock Select Figure 2 shows the two operating modes (Modes 0 and 1) provided by the output enable/clock (OE/CLK) select. The OE/CLK select, which is controlled by a single programmable bit, can be individually configured for each macrocell. In Mode 0, the tri-state output buffer is controlled by a single product term. If the output enable is high, the output buffer is enabled. If the output enable is low, the output has a high-impedance value. In Mode 0, the macrocell flipflop is clocked by its global clock input signal. In Mode 1, the output enable buffer is always enabled, and the macrocell register can be triggered by an array clock signal generated by a product term. This mode allows registers to be individually clocked by any signal on the AND array. With both true and complement signals in the AND array, the register can be configured to trigger on a rising or falling edge. This product-term-controlled clock configuration also supports gated clock structures. 748 Altera Corporation Classic EPLD Family Data Sheet Figure 2. Classic Output Enable/Clock Select Mode 0 Output Enable/Clock VCC Global Select Clock In Mode 0, the register OE AND is clocked by the global Array clock signal. The CLK output is enabled by the logic from the product term. Data Q OE = Product Term CLK = Global Macrocell CLR Output Buffer Mode 1 Output Enable/Clock Global VCC Select Clock In Mode 1, the output OE AND is permanently enabled Array and the register is CLK clocked by the product term, which allows gated clocks to be Data Q generated. OE = Enabled CLK = Product Term Macrocell CLR Output Buffer Feedback Select Each macrocell in a Classic device provides feedback selection that is controlled by the feedback multiplexer. This feedback selection allows the designer to feed either the macrocell output or the I/O pin input associated with the macrocell back into the AND array. The macrocell output can be either the Q output of the programmable register or the combinatorial output of the macrocell. Different devices have different feedback multiplexer configurations. See Figure 3. Figure 3. Classic Feedback Multiplexer Configurations Global Feedback Multiplexer Quadrant Feedback Multiplexer Dual Feedback Multiplexer Quadrant Q Q Q Global Quadrant I/O I/O I/O Global EP610 EP1810 EP1810 EP610I EP910 EP910I Altera Corporation 749 Classic EPLD Family Data Sheet EP610, EP610I, EP910, and EP910I devices have a global feedback configuration; either the macrocell output (Q) or the I/O pin input (I/O) can feed back to the AND array so that it is accessible to all other macrocells. EP1810 macrocells can have either of two feedback configurations: quadrant or dual. Most macrocells in EP1810 devices have a quadrant feedback configuration; either the macrocell output or I/O pin input can feed back to other macrocells in the same quadrant. Selected macrocells in EP1810 devices have a dual feedback configuration: the output of the macrocell feeds back to other macrocells in the same quadrant, and the I/O pin input feeds back to all macrocells in the device. If the associated I/O pin is not used, the macrocell output can optionally feed all macrocells in the device. In this case, the output of the macrocell passes through the tri-state buffer and uses the feedback path between the buffer and the I/O pin. Classic devices contain a programmable security bit that controls access to Design Security the data programmed into the device. When this bit is programmed, a proprietary design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security because data within configuration elements is invisible. The security bit that controls this function and other program data is reset only when the device is erased. Device timing can be analyzed with the MAX+PLUS II software, with a Timing Model variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure 4. Devices have fixed internal delays that allow the user to determine the worst-case timing for any design. The MAX+PLUS II software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for system- level performance evaluation. Figure 4. Classic Timing Model Global Clock Delay t ICS Input Register Output Delay Array Clock t SU Delay t t IN Delay H t OD t IC t XZ t ZX Logic Array Delay t LAD t CLR I/O Feedback Delay Delay t IO t FD 750 Altera Corporation Classic EPLD Family Data Sheet Timing information can be derived from the timing model and parameters for a particular device. External timing parameters represent pin-to-pin timing delays, and can be calculated from the sum of internal parameters. Figure 5 shows the internal timing relationship for internal and external delay parameters. For more information on device timing, refer to Application Note 78 f (Understanding MAX 5000 & Classic Timing) in this data book. Altera Corporation 751 Classic EPLD Family Data Sheet Figure 5. Classic Switching Waveforms Input Mode t t t t t and t < 3 ns. PD1 = IN + LAD + OD R F t t = t + t + t + t IO PD2 IO IN LAD OD Inputs are driven at 3 V I/O Pin for a logic high and t 0 V for a logic low. IN All timing characteristics Input Pin are measured at 1.5 V. t LAD Logic Array Input t CLR Logic Array Output t OD Output Pin Global Clock Mode t t t t R CH CL F Global Clock Pin t t IN ICS Global Clock at Register t t SU H Data from Logic Array Array Clock Mode t t t t R ACH ACL F Clock Pin t IN Clock into Logic Array t IC Clock from Logic Array t t ASU AH Data from Logic Array t FD Register Output to Logic Array Output Mode Clock from Logic Array t OD Data from Logic Array t t XZ ZX Output Pin High-Impedance Tri-State 752 Altera Corporation Classic EPLD Family Data Sheet TM Many Classic devices contain a programmable Turbo Bit option to Turbo Bit control the automatic power-down feature that enables the low-standby- Option power mode. When the Turbo Bit option is turned on, the low-standby- power mode is disabled. All AC values are tested with the Turbo Bit option turned on. When the device is operating with the Turbo Bit option turned off (non-Turbo mode), a non-Turbo adder must be added to the appropriate AC parameter to determine worst-case timing. The non- Turbo adder is specified in the “AC Operating Conditions” tables for each Classic device that supports the Turbo mode. Classic devices are fully functionally tested. Complete testing of each Generic Testing programmable EPROM configuration element and all internal logic elements before and after packaging ensures 100% programming yield. See Figure 6 for AC test measurement conditions. These devices also contain on-board logic test circuitry to allow verification of function and AC specifications during standard production flow. Figure 6. AC Test Conditions Power-supply transients can affect AC VCC measurements. Simultaneous transitions of R1 multiple outputs should be avoided for 885 Ω accurate measurement. Threshold tests To T est Device must not be performed under AC System Output conditions. Large-amplitude, fast ground- current transients normally occur as the device outputs discharge the load R2 capacitances. When these transients flow 340 Ω C1 (includes through the parasitic inductance between JIG capacitance) the device ground pin and the test system ground, significant reductions in observable noise immunity can result. Classic devices can be programmed on 486- and Pentium-based PCs with Device the MAX+PLUS II Programmer, an Altera Logic Programmer card, the Programming MPU, and the appropriate device adapter. The MPU performs continuity checking to ensure adequate electrical contact between the adapter and the device. Data I/O, BP Microsystems, and other programming hardware manufacturers also offer programming support for Altera devices. See Programming Hardware Manufacturers for more information. Altera Corporation 753 Notes: EP610 EP610 EP610 EPLD nHigh-performance, 16-macrocell Classic EPLD Features – Combinatorial speeds with t as fast as 10 ns PD – Counter frequencies of up to 100 MHz – Pipelined data rates of up to 125 MHz nProgrammable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins nEP610 and EP610I devices are pin-, function-, and programming file-compatible nProgrammable clock option for independent clocking of all registers nMacrocells individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation nAvailable in the following packages (see Figure 7): – 24-pin small-outline integrated circuit (plastic SOIC only) – 24-pin ceramic and plastic dual in-line package (CerDIP and PDIP) – 28-pin plastic J-lead chip carrier (PLCC) Figure 7. EP610 Package Pin-Out Diagrams Package outlines not drawn to scale. Windows in ceramic packages only. CLK1 1 24 VCC INPUT 2 23 INPUT I/O 3 22 I/O 1 24 VCC CLK1 4 3 2 1 28 27 26 2 23 INPUT 4 21 INPUT I/O I/O 5 25 I/O I/O 3 22 I/O I/O I/O 5 20 I/O I/O 6 24 I/O 4 21 I/O I/O I/O 6 19 I/O 5 20 I/O I/O I/O 7 23 I/O 7 18 I/O I/O 6 19 I/O I/O I/O 8 22 I/O I/O 8 17 7 18 I/O I/O I/O 8 17 I/O I/O 9 EP610 21 I/O I/O 9 16 I/O I/O 9 16 I/O I/O I/O 10 15 I/O I/O 10 20 I/O 10 15 I/O I/O INPUT 11 14 INPUT NC 11 19 NC 11 14 INPUT INPUT GND 12 13 CLK2 12 13 14 15 16 17 18 12 13 CLK2 GND 24-Pin SOIC 24-Pin DIP 28-Pin PLCC EP610 EP610 EP610 EP610I EP610I Altera Corporation 755 I/O I/O INPUT INPUT GND CLK1 GND VCC CLK2 VCC INPUT INPUT I/O I/O Classic EPLD Family Data Sheet EP610 devices have 16 macrocells, 4 dedicated input pins, 16 I/O pins, General and 2 global clock pins (see Figure 8). Each macrocell can access signals Description from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of either the output of the macrocell or the I/O input. The CLK1 signal is a dedicated global clock input for the registers in macrocells 9 through 16. The CLK2 signal is a dedicated global clock input for registers in macrocells 1 through 8. Figure 8. EP610 Block Diagram Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages. 2 (3) INPUT INPUT (27) 23 1 (2) CLK1 CLK2 (16) 13 3 (4) Macrocell 9 Macrocell 1 (26) 22 4 (5) Macrocell 10 Macrocell 2 (25) 21 5 (6) Macrocell 11 (24) 20 Macrocell 3 Global 6 (7) Macrocell 12 (23) 19 Bus Macrocell 4 7 (8) (22) 18 Macrocell 13 Macrocell 5 8 (9) Macrocell 14 Macrocell 6 (21) 17 9 (10) Macrocell 15 Macrocell 7 (20) 16 10 (12) Macrocell 16 Macrocell 8 (18) 15 INPUT (17) 14 11 (13) INPUT Figure 9 shows the typical supply current (I ) versus frequency of EP610 CC devices. Figure 9. I vs. Frequency of EP610 Devices CC 100 Turbo 10 Typical I CC Active (mA) V = 5.0 V CC T = 25° C A 1.0 Non-Turbo 0.1 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 80 MHz Frequency 756 Altera Corporation Classic EPLD Family Data Sheet Figure 10 shows the typical output drive characteristics of EP610 devices. Figure 10. Output Drive Characteristics of EP610 Devices Drive characteristics may exceed shown curves. EP610-15 & EP610-20 EPLDs EP610-25, EP610-30 & EP610-35 EPLDs 200 80 I OL I 150 OL 60 Typical I Typical I CC CC V = 5.0 V V = 5.0 V CC CC Output Output T = 25° C T = 25° C 100 A 40 A Current (mA) Current (mA) I OH 50 20 I OH 0.45 1 2 3 4 5 0.45 1 2 3 4 5 V Output Voltage (V) V Output Voltage (V) O O EP610I EPLDs 100 80 I OL 60 Typical I CC V = 5.0 V CC Output T = 25° C A Current (mA) 40 I 20 OH 1 2 3 4 5 V Output Voltage (V) O Altera Corporation 757 Classic EPLD Family Data Sheet Tables 2 through 7 provide information on absolute maximum ratings, Operating recommended operating conditions, operating conditions, and Conditions capacitance for EP610 and EP610I devices. Table 2. EP610 & EP610I Device Absolute Maximum Ratings Notes (1), (2) Symbol Parameter Conditions EP610 EP610I Unit Min Max Min Max V Supply voltage With respect to ground (3) –2.0 7.0 –2.0 7.0 V CC V DC input voltage –2.0 7.0 –0.5 V + 0.5 V I CC I DC V or ground current –175 175 mA MAX CC I DC output current, per pin –25 25 mA OUT T Storage temperature No bias –65 150 –65 150 ° C STG T Ambient temperature Under bias –65 135 –65 135 ° C AMB T Junction temperature Ceramic packages, under 150 150 ° C J bias Plastic packages, under bias 135 135 ° C Table 3. EP610 & EP610I Device Recommended Operating Conditions Note (2) Symbol Parameter Conditions EP610 EP610I Unit Min Max Min Max V Supply voltage (4) 4.75 (4.5) 5.25 (5.5) 4.75 5.25 V CC V Input voltage –0.3 V + 0.3 –0.3 V + 0.3 V I CC CC V Output voltage 0 V 0 V V O CC CC T Operating temperature For commercial use 0 70 0 70 ° C A For industrial use –40 85 –40 85 ° C t Input rise time (5) 100 (50) 500 ns R t Input fall time (5) 100 (50) 500 ns F Table 4. EP610 & EP610I Device DC Operating Conditions Note (6) Symbol Parameter Conditions Min Max Unit V High-level input voltage 2.0 V + 0.3 V IH CC V Low-level input voltage –0.3 0.8 V IL V High-level TTL output voltage I = –4 mA DC (7) 2.4 V OH OH High-level CMOS output voltage I = –0.6 mA DC (7), (8) 3.84 V OH V Low-level output voltage I = 4 mA DC (7) 0.45 V OL OL I I/O pin leakage current of dedicated input V = V or ground –10 10 μA I I CC pins I Tri-state output leakage current V = V or ground –10 10 μA OZ O CC 758 Altera Corporation Classic EPLD Family Data Sheet Table 5. EP610 & EP610I Device Capacitance Note (9) Symbol Parameter Conditions EP610-15 EP610-25 EP610I Unit EP610-20 EP610-30 EP610-35 Min Max Min Max Min Max C Input pin capacitance V = 0 V, f = 1.0 MHz 10 20 8 pF IN IN C I/O pin capacitance V = 0 V, f = 1.0 MHz 12 20 8 pF I/O OUT C CLK1 pin capacitance V = 0 V, f = 1.0 MHz 20 20 10 pF CLK1 IN C CLK2 pin capacitance V = 0 V, f = 1.0 MHz 20 50 12 pF CLK2 IN Table 6. EP610 Device I Supply Current Notes (2), (10) CC Symbol Parameter Conditions Speed EP610 Unit Grade Min Typ Max I V supply current V = V or ground, no load 20 150 μA CC1 CC I CC (non-Turbo, standby) (11), (12) I V supply current V = V or ground, no load, 5 10 (15) mA CC2 CC I CC (non-Turbo, active) f = 1.0 MHz (11), (12) I V supply current V = V or ground, no load, -15, -20 60 90 (115) mA CC3 CC I CC (Turbo, active) f = 1.0 MHz (12) -25, -30, 45 60 (75) mA -35 Table 7. EP610I Device I Supply Current Note (10) CC Symbol Parameter Conditions EP610I Unit Min Typ Max I V supply current V = V or ground, no load, 20 150 μA CC1 CC I CC (non-Turbo, standby) (11), (12) I V supply current V = V or ground, no load, 3 8 mA CC2 CC I CC (non-Turbo, active) f = 1.0 MHz (11), (12) I V supply current V = V or ground, no load, 65 105 mA CC3 CC I CC (Turbo, active) f = 1.0 MHz (12) Altera Corporation 759 Classic EPLD Family Data Sheet Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet in this data book. (2) Numbers in parentheses are for industrial-temperature-range devices. (3) The minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V (EP610) or –0.5 V (EP610I) or overshoot to 7.0 V (EP610) or V + 0.5 V (EP610I) for input currents less than 100 mA and periods CC less than 20 ns. (4) For EP610 devices, maximum V rise time is 50 ms. For EP610I devices, maximum V rise time is unlimited with CC CC monotonic rise. (5) For EP610-15 and EP610-20 devices: t and t = 40 ns. R F For EP610-15 and EP610-20 clocks: t and t = 20 ns. R F (6) These values are specified in Table 3 on page 758. (7) The I parameter refers to high-level TTL or CMOS output current; the I parameter refers to low-level TTL OH OL output current. (8) This parameter does not apply to EP610I devices. (9) The device capacitance is measured at 25° C and is sample-tested only. (10) Typical values are for T = 25° C and V = 5 V. A CC (11) When the Turbo Bit option is not set (non-Turbo mode), EP610 devices enter standby mode if no logic transitions occur for 100 ns after the last transition. When the Turbo Bit option is not set, EP610I devices enter standby mode if no logic transitions occur for 75 ns after the last transition. (12) Measured with a device programmed as a 16-bit counter. 760 Altera Corporation Classic EPLD Family Data Sheet Tables 8 and 9 show the timing parameters for EP610-15 and EP610-20 devices. Table 8. EP610-15 & EP610-20 External Timing Parameters Notes (1), (2) Symbol Parameter Conditions EP610-15 EP610-20 Non-Turbo Unit Adder (3) Min Max Min Max t Input to non-registered output C1 = 35 pF 15.0 20.0 20.0 ns PD1 t I/O input to non-registered output C1 = 35 pF 17.0 22.0 20.0 ns PD2 t Input to output enable C1 = 35 pF 15.0 20.0 20.0 ns PZX t Input to output disable C1 = 5 pF (4) 15.0 20.0 20.0 ns PXZ t Asynchronous output clear time C1 = 35 pF 15.0 20.0 20.0 ns CLR f Maximum clock frequency (5) 83.3 62.5 0.0 MHz MAX t Global clock input setup time 9.0 11.0 20.0 ns SU t Global clock input hold time 0.0 0.0 0.0 ns H t Global clock high time 6.0 8.0 0.0 ns CH t Global clock low time 6.0 8.0 0.0 ns CL t Global clock to output delay 11.0 13.0 0.0 ns CO1 t Global clock minimum period 12.0 16.0 0.0 ns CNT f Maximum internal global clock (6) 83.3 62.5 0.0 MHz CNT frequency t Array clock input setup time 6.0 8.0 20.0 ns ASU t Array clock input hold time 6.0 8.0 0.0 ns AH t Array clock high time 7.0 9.0 0.0 ns ACH t Array clock low time 7.0 9.0 0.0 ns ACL t Output data hold time after clock C1 = 35 pF (7) 1.0 1.0 1.0 ns ODH t Array clock to output delay 15.0 20.0 20.0 ns ACO1 t Array clock minimum period 14.0 18.0 0.0 ns ACNT f Array clock internal maximum (6) 71.4 55.6 0.0 MHz ACNT frequency Table 9. EP610-15 & EP610-20 Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions EP610-15 EP610-20 Unit Min Max Min Max t Input pad and buffer delay 4.0 4.0 ns IN t I/O input pad and buffer delay 2.0 2.0 ns IO t Logic array delay 6.0 11.0 ns LAD t Output buffer and pad delay C1 = 35 pF 5.0 5.0 ns OD t Output buffer enable delay C1 = 35 pF 5.0 5.0 ns ZX t Output buffer disable delay C1 = 5 pF 5.0 5.0 ns XZ Altera Corporation 761 Classic EPLD Family Data Sheet Table 9. EP610-15 & EP610-20 Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions EP610-15 EP610-20 Unit Min Max Min Max t Register setup time 5.0 4.0 ns SU t Register hold time 4.0 7.0 ns H t Array clock delay 6.0 11.0 ns IC t Global clock delay 2.0 4.0 ns ICS t Feedback delay 1.0 1.0 ns FD t Register clear time 6.0 11.0 ns CLR Tables 10 and 11 show the timing parameters for EP610-25, EP610-30 and EP610-35 devices. Table 10. EP610-25, EP610-30 & EP610-35 External Timing Parameters Notes (1), (2) Symbol Parameter Conditions EP610-25 EP610-30 EP610-35 Non-Turbo Unit Adder Min Max Min Max Min Max (3) t Input to non-registered output C1 = 35 pF 25.0 30.0 35.0 30.0 ns PD1 t I/O input to non-registered output 27.0 32.0 37.0 30.0 ns PD2 t Input to output enable 25.0 30.0 35.0 30.0 ns PZX t Input to output disable C1 = 5 pF (4) 25.0 30.0 35.0 30.0 ns PXZ t Asynchronous output clear time C1 = 35 pF 27.0 32.0 37.0 30.0 ns CLR f Maximum frequency (5) 47.6 41.7 37.0 0.0 MHz MAX t Global clock input setup time 21.0 24.0 27.0 30.0 ns SU t Global clock input hold time 0.0 0.0 0.0 0.0 ns H t Global clock high time 10.0 11.0 12.0 0.0 ns CH t Global clock low time 10.0 11.0 12.0 0.0 ns CL t Global clock to output delay 15.0 17.0 20.0 0.0 ns CO1 t Global clock minimum period 25.0 30.0 35.0 0.0 ns CNT f Maximum internal global clock (6) 40.0 33.3 28.6 0.0 MHz CNT frequency t Array clock input setup time 8.0 8.0 8.0 30.0 ns ASU t Array clock input hold time 12.0 12.0 12.0 0.0 ns AH t Array clock high time 10.0 11.0 12.0 0.0 ns ACH t Array clock low time 10.0 11.0 12.0 0.0 ns ACL t Output data hold time after clock C1 = 35 pF (7) 1.0 1.0 1.0 ns ODH t Array clock to output delay 27.0 32.0 37.0 30.0 ns ACO1 t Array clock minimum period 25.0 30.0 35.0 0.0 ns ACNT f Maximum internal global clock (6) 40.0 33.3 28.6 0.0 MHz ACNT frequency 762 Altera Corporation Classic EPLD Family Data Sheet Table 11. EP610-25, EP610-30 & EP610-35 Internal Timing Parameters Unit Symbol Parameter Condition EP610-25 EP610-30 EP610-35 Min Max Min Max Min Max t Input pad and buffer delay 8.0 9.0 11.0 ns IN t I/O input pad and buffer delay 2.0 2.0 2.0 ns IO t Logic array delay 11.0 14.0 15.0 ns LAD t Output buffer and pad delay C1 = 35 pF 6.0 7.0 9.0 ns OD t Output buffer enable delay C1 = 35 pF 6.0 7.0 9.0 ns ZX t Output buffer disable delay C1 = 5 pF 6.0 7.0 9.0 ns XZ t Register setup time 11.0 11.0 12.0 ns SU t Register hold time 10.0 10.0 10.0 ns H t Array clock delay 13.0 16.0 17.0 ns IC t Global clock delay 1.0 1.0 0.0 ns ICS t Feedback delay 3.0 5.0 8.0 ns FD t Register clear time 13.0 16.0 17.0 ns CLR Notes to tables: (1) These values are specified in Table 3 on page 758. (2) See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for information on internal timing parameters. (3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (5) The f values represent the highest frequency for pipelined data. MAX (6) Measured with a device programmed as a 16-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter applies for both global and array clocking. Altera Corporation 763 Classic EPLD Family Data Sheet Tables 12 and 13 show the timing parameters for EP610I devices. Table 12. EP610I External Timing Parameters Notes (1), (2) Symbol Parameter Conditions EP610I-10 EP610I-12 EP610I-15 Non-Turbo Unit Adder Min Max Min Max Min Max (3) t Input to non-registered output C1 = 35 pF 10.0 12.0 15.0 25.0 ns PD1 t I/O input to non-registered output 10.0 12.0 15.0 25.0 ns PD2 t Input to output enable 15.0 15.0 18.0 25.0 ns PZX t Input to output disable C1 = 5 pF (4) 13.0 15.0 18.0 25.0 ns PXZ t Asynchronous output clear time C1 = 35 pF 13.0 15.0 18.0 25.0 ns CLR f Maximum frequency (5) 125.0 100. 83.3 0.0 MHz MAX 0 t Global clock input setup time 7.0 9.0 12.0 25 ns SU t Global clock input hold time 0.0 0.0 0.0 0.0 ns H t Global clock high time 5.0 5.0 5.0 0.0 ns CH t Global clock low time 5.0 5.0 5.0 0.0 ns CL t Global clock to output delay 6.5 8.0 8.0 0.0 ns CO1 t Global clock minimum period 10.0 12.0 15.0 25.0 ns CNT f Maximum internal global clock (6) 100.0 83.3 66.0 0.0 MHz CNT frequency t Array clock input setup time 1.5 3.0 4.0 25.0 ns ASU t Array clock input hold time 5.5 6.0 6.0 0.0 ns AH t Array clock high time 5.0 5.0 6.0 0.0 ns ACH t Array clock low time 5.0 5.0 6.0 0.0 ns ACL t Output data hold time after clock C1 = 35 pF 1.0 1.0 1.0 ns ODH (7) t Array clock to output delay 12.0 14.0 16.0 25.0 ns ACO1 t Array clock minimum period 10.0 12.0 15.0 25.0 ns ACNT f Maximum internal array clock (6) 100.0 83.3 66.0 0.0 MHz ACNT frequency 764 Altera Corporation Classic EPLD Family Data Sheet Table 13. EP610 Internal Timing Parameters Symbol Parameter Conditions EP610I-10 EP610I-12 EP610I-15 Unit Min Max Min Max Min Max t Input pad and buffer delay 1.5 4.0 4.0 ns IN t I/O input pad and buffer delay 0.0 0.0 0.0 ns IO t Logic array delay 5.5 6.0 9.0 ns LAD t Output buffer and pad delay C1 = 35 pF 3.0 2.0 2.0 ns OD t Output buffer enable delay C1 = 35 pF 8.0 5.0 6.0 ns ZX t Output buffer disable delay C1 = 5 pF 6.0 5.0 6.0 ns XZ t Register setup time 3.5 5.0 5.0 ns SU t Register hold time 3.5 4.0 7.0 ns H t Array clock delay 7.5 8.0 10.0 ns IC t Global clock delay 2.0 2.0 2.0 ns ICS t Feedback delay 1.0 1.0 1.0 ns FD t Register clear time 8.5 9.0 12.0 ns CLR Notes to tables: (1) These values are specified in Table 3 on page 758. (2) See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for more information on Classic timing parameters. (3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (5) The f values represent the highest frequency for pipelined data. MAX (6) Measured with a device programmed as a 16-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter applies for both global and array clocking. Altera Corporation 765 Notes: EP910 EPLD nHigh-performance, 24-macrocell Classic EPLD Features – Combinatorial speeds with t as fast as 12 ns PD – Counter frequencies of up to 76.9 MHz – Pipelined data rates of up to 125 MHz nProgrammable I/O architecture with up to 36 inputs or 24 outputs nEP910 and EP910I devices are pin-, function-, and programming file- compatible nProgrammable clock option for independent clocking of all registers nMacrocells individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation nAvailable in the following packages (see Figure 11) – 44-pin plastic J-lead chip carrier (PLCC) – 40-pin ceramic and plastic dual in-line packages (CerDIP and PDIP) Figure 11. EP910 Package Pin-Out Diagrams Package outlines are not drawn to scale. Windows in ceramic packages only. 1 40 VCC CLK1 2 39 INPUT INPUT 3 38 INPUT INPUT 4 37 INPUT INPUT 5 36 I/O I/O 6 I/O 35 I/O 6 5 4 3 2 1 44 43 42 41 40 7 34 I/O I/O 8 33 I/O 7 39 I/O I/O NC 9 32 I/O 8 38 I/O I/O I/O 10 31 I/O 9 37 I/O I/O I/O 11 30 I/O 10 36 I/O I/O I/O 12 29 I/O 11 35 I/O I/O I/O 13 I/O 28 I/O I/O 12 34 I/O 14 27 I/O 13 33 I/O I/O I/O 15 26 I/O 14 32 I/O I/O I/O 16 I/O 25 I/O 15 31 I/O I/O 17 24 INPUT 16 30 INPUT I/O I/O 18 23 INPUT 17 29 INPUT NC I/O 19 22 INPUT INPUT 20 21 CLK2 18 19 20 21 22 23 24 25 26 27 28 GND 40-Pin DIP 44-Pin PLCC EP910 EP910 EP910I EP910I Altera Corporation 767 I/O I/O INPUT INPUT INPUT INPUT INPUT INPUT GND CLK1 GND VCC CLK2 VCC INPUT INPUT INPUT INPUT INPUT INPUT I/O I/O Classic EPLD Family Data Sheet Altera EP910 devices can implement up to 450 usable gates of SSI and MSI General logic functions. EP910 devices have 24 macrocells, 12 dedicated input Description pins, 24 I/O pins, and 2 global clock pins (see Figure 12). Each macrocell can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of either the output of the macrocell or the I/O input. The CLK1 and CLK2 signals are the dedicated clock inputs for the registers in macrocells 13 through 24 and 1 through 12, respectively. Figure 12. EP910 Block Diagram Numbers without parentheses are for DIP packages. Numbers in parentheses are for J-lead packages. 2 (3) INPUT INPUT (43) 39 3 (4) INPUT INPUT (42) 38 4 (5) INPUT INPUT (41) 37 1 (2) CLK1 CLK2 (24) 21 5 (6) (40) 36 Macrocell 13 Macrocell 1 6 (7) (38) 35 Macrocell 14 Macrocell 2 7 (8) (37) 34 Macrocell 3 Macrocell 15 8 (9) (36) 33 Macrocell 16 Macrocell 4 9 (10) (35) 32 Macrocell 17 Macrocell 5 Global 10 (11) 31 Macrocell 18 Bus Macrocell 6 (34) 11 (12) 30 Macrocell 19 Macrocell 7 (33) 12 (13) 29 Macrocell 20 Macrocell 8 (32) 13 (14) 28 Macrocell 21 Macrocell 9 (31) 14 (15) 27 Macrocell 22 Macrocell 10 (30) 15 (16) 26 Macrocell 23 Macrocell 11 (29) 16 (18) 25 Macrocell 24 Macrocell 12 (28) (27) 17 (19) INPUT INPUT 24 18 (20) INPUT INPUT (26) 23 19 (21) INPUT INPUT (25) 22 768 Altera Corporation Classic EPLD Family Data Sheet Figure 13 shows the typical supply current (I ) versus frequency of CC EP910 devices. Figure 13. I vs. Frequency of EP910 Devices CC 100 Turbo 10 Typical I V = 5.0 V CC CC Active (mA) T = 25° C A 1.0 Non-Turbo 0.1 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 40 MHz Frequency Figure 14 shows the typical output drive characteristics of EP910 devices. Figure 14. Output Drive Characteristics of EP910 Devices Drive characteristics may exceed shown curves. EP910I EPLDs EP910 EPLDs 60 120 50 100 I OL 40 80 I OL Typical I Typical I O O Output Output V = 5.0 V CC 60 30 Current (mA) Current (mA) T = 25° C A V = 5.0 V CC T = 25° C A 40 20 I OH 20 10 I OH 0 0.45 1 2 3 4 5 0.45 1 2 3 4 5 V Output Voltage (V) V Output Voltage (V) O O Altera Corporation 769 Classic EPLD Family Data Sheet Tables 14 through 18 provide information on absolute maximum ratings, Operating recommended operating conditions, operating conditions, and Conditions capacitance for EP910 and EP910I devices. Table 14. EP910 & EP910I Device Absolute Maximum Ratings Notes (1), (2) Symbol Parameter Conditions EP910 EP910I Unit Min Max Min Max V Supply voltage With respect to ground (3) –2.0 7.0 –2.0 7.0 V CC V DC input voltage –2.0 7.0 –0.5 V + 0.5 V I CC I DC V or ground current –250 250 mA MAX CC I DC output current, per pin –25 25 mA OUT T Storage temperature No bias –65 150 –65 150 ° C STG T Ambient temperature Under bias –65 135 –65 135 ° C AMB T Junction temperature Ceramic packages, under 150 150 ° C J bias Plastic packages, under 135 135 ° C bias Table 15. EP910 & EP910I Device Recommended Operating Conditions Note (2) Symbol Parameter Conditions EP910 EP910I Unit Min Max Min Max V Supply voltage (4) 4.75 (4.5) 5.25 (5.5) 4.75 5.25 V CC V Input voltage –0.3 V + 0.3 –0.3 V + 0.3 V I CC CC V Output voltage 0 V 0 V V O CC CC T Operating temperature For commercial use 0 70 0 70 ° C A For industrial use –40 85 ° C t Input rise time (5) 100 (50) 500 ns R t Input fall time (5) 100 (50) 500 ns F Table 16. EP910 & EP910I Device DC Operating Conditions Notes (6), (7) Symbol Parameter Conditions Min Max Unit V High-level input voltage 2.0 V + 0.3 V IH CC V Low-level input voltage –0.3 0.8 V IL V High-level TTL output voltage I = –4 mA DC (8) 2.4 V OH OH High-level CMOS output voltage I = –0.6 mA DC (8), (9) 3.84 V OH V Low-level output voltage I = 4 mA DC (8) 0.45 V OL OL I I/O leakage current of dedicated input pins V = V or ground –10 10 μA I I CC I Tri-state output leakage current V = V or ground –10 10 μA OZ O CC 770 Altera Corporation Classic EPLD Family Data Sheet Table 17. EP910 & EP910I Device Capacitance Note (6) Symbol Parameter Conditions EP910 EP910I Unit Min Max Min Max C Input pin capacitance V = 0 V, f = 1.0 MHz 20 8 pF IN IN C I/O pin capacitance V = 0 V, f = 1.0 MHz 20 8 pF I/O OUT C CLK1 pin capacitance V = 0 V, f = 1.0 MHz 20 10 pF CLK1 IN C CLK2 pin capacitance V = 0 V, f = 1.0 MHz 60 12 pF CLK2 IN Table 18. EP910 & EP910I Device I Supply Current Notes (2), (6), (7) CC Symbol Parameter Conditions EP910 EP910I Unit Min Typ Max Min Typ Max I V supply current V = V or ground, no load 20 150 60 150 μA CC1 CC I CC (non-Turbo, standby) (10), (11) I V supply current V = V or ground, no load, 6 20 4 12 mA CC2 CC I CC (non-Turbo, active) f = 1.0 MHz (10), (11) I V supply current V = V or ground, no load, 45 80 120 150 mA CC3 CC I CC (Turbo, active) f = 1.0 MHz (11) (100) Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet in this data book. (2) Numbers in parentheses are for industrial-temperature-range devices. (3) The minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V (EP910) or –0.5 V (EP910I) or overshoot to 7.0 V (EP910) or V + 0.5 V (EP910I) for input currents less than 100 mA and periods CC less than 20 ns. (4) Maximum V rise time for EP910 devices = 50 ms; for EP910I devices, maximum V rise time is unlimited with CC CC monotonic rise. (5) For all clocks: t and t = 100 ns (50 ns for the industrial-temperature-range version). R F (6) These values are specified in Table 15 on page 770. (7) The device capacitance is measured at 25° C and is sample-tested only. (8) The I parameter refers to high-level TTL or CMOS output current; the I parameter refers to low-level TTL OH OL output current. (9) This parameter does not apply to EP910I devices. (10) When the Turbo Bit option is not set (non-Turbo mode), an EP910 device will enter standby mode if no logic transitions occur for 100 ns after the last transition, and an EP910I device will enter standby mode if no logic transitions occur for 75 ns after the last transition. (11) Measured with a device programmed as a 24-bit counter. Altera Corporation 771 Classic EPLD Family Data Sheet Tables 19 and 20 show the timing parameters for EP910 devices. Table 19. EP910 External Timing Parameters Notes (1), (2) Symbol Parameter Conditions EP910-30 EP910-35 EP910-40 Non- Unit Turbo Min Max Min Max Min Max Adder (3) t Input to non-registered output C1 = 35 pF 30.0 35.0 40.0 30.0 ns PD1 t I/O input to non-registered output C1 = 35 pF 33.0 38.0 43.0 30.0 ns PD2 t Input to output enable C1 = 35 pF 30.0 35.0 40.0 30.0 ns PZX t Input to output disable C1 = 5 pF (4) 30.0 35.0 40.0 30.0 ns PXZ t Asynchronous output clear time C1 = 35 pF 33.0 38.0 43.0 30.0 ns CLR f Maximum frequency (5) 41.7 37.0 32.3 0.0 MHz MAX t Global clock input setup time 24.0 27.0 31.0 30.0 ns SU t Global clock input hold time 0.0 0.0 0.0 0.0 ns H t Global clock high time 12.0 13.0 15.0 0.0 ns CH t Global clock low time 12.0 13.0 15.0 0.0 ns CL t Global clock to output delay C1 = 35 pF 18 21.0 24.0 0.0 ns CO1 t Global clock minimum clock period (6) 30.0 35.0 40.0 0.0 ns CNT f Maximum internal global clock (6) 33.3 28.6 25.0 0.0 MHz CNT frequency t Array clock input setup time 10.0 10.0 10.0 30.0 ns ASU t Array clock input hold time 15.0 15.0 15.0 0.0 ns AH t Array clock high time 15.0 16.0 17.0 0.0 ns ACH t Array clock low time 15.0 16.0 17.0 0.0 ns ACL t Output data hold time after clock C1 = 35 pF (7) 1.0 1.0 1.0 ns ODH t Array clock to output delay C1 = 35 pF 33.0 38.0 43.0 30.0 ns ACO1 t Array clock minimum clock period 30.0 35.0 40.0 0.0 ns ACNT f Maximum internal array clock (6) 33.3 28.6 25.0 0.0 MHz ACNT frequency 772 Altera Corporation Classic EPLD Family Data Sheet Table 20. EP910 Internal Timing Parameters EP910-30 EP910-35 EP910-40 Unit Symbol Parameter Condition Min Max Min Max Min Max t Input pad and buffer delay 9.0 10.0 13.0 ns IN t I/O input pad and buffer delay 3.0 3.0 3.0 ns IO t Logic array delay 14.0 16.0 17.0 ns LAD t Output buffer and pad delay C1 = 35 pF 7.0 9.0 10.0 ns OD t Output buffer enable delay C1 = 35 pF 7.0 9.0 10.0 ns ZX t Output buffer disable delay C1 = 5 pF 7.0 9.0 10.0 ns XZ t Register setup time 12.0 13.0 15.0 ns SU t Register hold time 12.0 12.0 12.0 ns H t Array clock delay 17.0 19.0 20.0 ns IC t Global clock delay 2.0 2.0 1.0 ns ICS t Feedback delay 4.0 6.0 8.0 ns FD t Register clear time 17.0 19.0 20.0 ns CLR Notes to tables: (1) These values are specified in Table 15 on page 770. (2) See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for more information on Classic timing parameters. (3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (5) The f values represent the highest frequency for pipelined data. MAX (6) Measured with a device programmed as a 24-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both global and array clocking. Altera Corporation 773 Classic EPLD Family Data Sheet Tables 21 and 22 show the timing parameters for EP910I devices. Table 21. EP910I External Timing Parameters Notes (1), (2) Symbol Parameter Conditions EP910I-12 EP910I-15 EP910I-25 Non-Turbo Unit Adder (3) Min Max Min Max Min Max t Input to non-registered output C1 = 35 pF 12.0 15.0 25.0 40.0 ns PD1 t I/O input to non-registered output C1 = 35 pF 12.0 15.0 25.0 40.0 ns PD2 t Input to output enable C1 = 35 pF 15.0 18.0 28.0 40.0 ns PZX t Input to output disable C1 = 35 pF 15.0 18.0 28.0 40.0 ns PXZ (4) t Asynchronous output clear time C1 = 35 pF 15.0 18.0 28.0 40.0 ns CLR f Global clock maximum frequency (5) 125.0 100.0 62.5 0.0 MHz MAX t Global clock input setup time 8.0 11.0 16.0 40.0 ns SU t Global clock input hold time 0.0 0.0 0.0 0.0 ns H t Global clock high time 5.0 6.0 10.0 0.0 ns CH t Global clock low time 5.0 6.0 10.0 0.0 ns CL t Global clock to output delay 8.0 9.0 14.0 0.0 ns CO1 t Global clock minimum clock period C1 = 35 pF 13.0 15.0 25.0 40.0 ns CNT f Maximum internal global clock (6) 76.9 66.6 40.0 0.0 MHz CNT frequency t Array clock input setup time 3.0 4.0 8.0 40.0 ns ASU t Array clock input hold time 6.0 7.0 8.0 ns AH t Array clock high time 6.0 7.5 12.5 ns ACH t Array clock low time 6.0 7.5 12.5 ns ACL t Output data hold time after clock C1 = 35 pF 1.0 1.0 1.0 ns ODH (7) t Array clock to output delay C1 = 35 pF 16.0 18.0 22.0 40.0 ns ACO1 t Array clock minimum clock period 13.0 15.0 25.0 40.0 ns ACNT f Maximum internal array clock (6) 76.9 66.6 40.0 MHz ACNT frequency 774 Altera Corporation Classic EPLD Family Data Sheet Table 22. EP910I Internal Timing Parameters Symbol Parameter Condition EP910I-12 EP910I-15 EP910I-25 Unit Min Max Min Max Min Max t Input pad and buffer delay 2.0 3.0 2.0 ns IN t I/O input pad and buffer delay 0.0 0.0 0.0 ns IO t Logic array delay 8.0 9.0 17.0 ns LAD t Output buffer and pad delay C1 = 35 pF 2.0 3.0 6.0 ns OD t Output buffer enable delay C1 = 35 pF 5.0 6.0 9.0 ns ZX t Output buffer disable delay C1 = 5 pF 5.0 6.0 9.0 ns XZ t Register setup time 4.0 5.0 5.0 ns SU t Register hold time 4.0 6.0 11.0 ns H t Array clock delay 12.0 12.0 14.0 ns IC t Global clock delay 4.0 3.0 6.0 ns ICS t Feedback delay 1.0 1.0 3.0 ns FD t Register clear time 11.0 12.0 20.0 ns CLR Notes to tables: (1) These values are specified in Table 15 on page 770. (2) See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for information on internal timing parameters. (3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (5) The f values represent the highest frequency for pipelined data. MAX (6) Measured with the device programmed as a 24-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both global and array clocking. Altera Corporation 775 Notes: EP1810 EPLD nHigh-performance, 48-macrocell Classic EPLD Features – Combinatorial speeds with t as fast as 20 ns PD – Counter frequencies of up to 50 MHz – Pipelined data rates of up to 62.5 MHz nProgrammable I/O architecture with up to 64 inputs or 48 outputs nProgrammable clock option for independent clocking of all registers nMacrocells individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation nAvailable in the following packages (see Figure 15) – 68-pin ceramic pin-grid array (PGA) – 68-pin plastic J-lead chip carrier (PLCC) Figure 15. EP1810 Package Pin-Out Diagrams Package outlines not drawn to scale. See Table 32 on page 785 of this data sheet for PGA package pin-out information. Windows in ceramic packages only. L I/O 10 60 I/O K I/O 11 59 I/O 12 58 I/O I/O J I/O 13 57 I/O 14 56 INPUT INPUT H INPUT 15 55 INPUT INPUT 16 54 INPUT G Bottom 17 53 CLK1/INPUT CLK4/INPUT VCC 18 52 VCC F View 19 51 CLK2/INPUT CLK3/INPUT E INPUT 20 50 INPUT 21 49 INPUT INPUT D INPUT 22 48 INPUT 23 47 INPUT I/O C 24 46 INPUT I/O INPUT 25 45 I/O B 26 44 I/O I/O A 1 2 3 4 5 6 7 8 9 10 11 68-Pin PGA 68-Pin PLCC EP1810 EP1810 Altera Corporation 777 9 I/O I/O 27 8 I/O 28 I/O I/O 7 29 I/O 6 I/O 30 I/O 5 I/O 31 I/O 4 I/O I/O 32 3 I/O 33 I/O 2 I/O 34 I/O 1 GND 35 GND 68 I/O 36 I/O 67 I/O 37 I/O 66 I/O 38 I/O 65 I/O 39 I/O 64 I/O 40 I/O 63 I/O 41 I/O 62 I/O 42 I/O 61 I/O 43 I/O Classic EPLD Family Data Sheet Altera EP1810 devices offer LSI density, TTL-equivalent speed, and low- General power consumption. EP1810 devices have 48 macrocells, 16 dedicated Description input pins, and 48 I/O pins (see Figure 16). EP1810 devices are divided into four quadrants, each containing 12 macrocells. Of the 12 macrocells in each quadrant, 8 have quadrant feedback and are “local” macrocells (see “Feedback Select” on page 749 of this data sheet for more information). The remaining 4 macrocells in the quadrant are “global” macrocells. Both local and global macrocells can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of the feedbacks from the global macrocells. EP1810 devices also have four dedicated inputs (one in each quadrant) that can be used as quadrant clock inputs. If the dedicated input is used as a clock pin, the input feeds the clock input of all registers in that particular quadrant. 778 Altera Corporation Classic EPLD Family Data Sheet Figure 16. EP1810 Block Diagram Pin numbers are for J-lead packages. Pin numbers in parentheses are for PGA packages. Quadrant A Quadrant D (F1) (E1) 68 2 Macrocell 48 Macrocell 1 (G2) (E2) 67 3 Macrocell 47 Macrocell 2 (D1) 66 4 (G1) Macrocell 46 Macrocell 3 5 (H2) (D2) 65 Macrocell 4 Macrocell 45 6 (H1) (C1) 64 Macrocell 5 Macrocell 44 (J2) (C2) 63 7 Macrocell 6 Macrocell 43 (B1) 62 8 (J1) Macrocell 42 Macrocell 7 (B2) 61 9 (K1) Macrocell 41 Macrocell 8 10 (K2) Macrocell 40 (A2) 60 Macrocell 9 11 (L2) Macrocell 39 (A3) 59 Macrocell 10 12 (K3) Macrocell 38 (B3) 58 Macrocell 11 Macrocell 37 13 (L3) Macrocell 12 (A4) 57 14 (K4) INPUT (B4) 56 INPUT 15 (L4) INPUT (A5) 55 INPUT 16 INPUT (K5) (B5) 54 INPUT 17 (L5) INPUT/CLK1 Global INPUT/CLK4 (A6) 53 Bus 19 (L6) INPUT/CLK2 (A7) 51 INPUT/CLK3 20 (K7) INPUT (B7) 50 INPUT 21 (L7) INPUT (A8) 49 INPUT 22 (K8) INPUT (B8) 48 INPUT Quadrant B Quadrant C 23 (L8) Macrocell 13 Macrocell 36 (A9) 47 24 (K9) Macrocell 35 (B9) 46 Macrocell 14 25 (L9) Macrocell 34 (A10) 45 Macrocell 15 26(L10) (B10) 44 Macrocell 16 Macrocell 33 27(K10) (B11) 43 Macrocell 17 Macrocell 32 28 (K1 1) (C11) 42 Macrocell 18 Macrocell 31 29 (J10) Macrocell 19 Macrocell 30 (C10) 41 30 (J1 1) Macrocell 20 Macrocell 29 (D11) 40 31(H10) Macrocell 21 Macrocell 28 (D10) 39 32(H1 1) Macrocell 22 Macrocell 27 (E11) 38 33(G10) Macrocell 23 Macrocell 26 (E10) 37 34(G1 1) Macrocell 25 (F11) 36 Macrocell 24 Global Macrocells Local Macrocells Altera Corporation 779 Local Bus—Quadrant B Local Bus—Quadrant A Local Bus—Quadrant C Local Bus—Quadrant D Classic EPLD Family Data Sheet Figure 17 shows the typical supply current (I ) versus frequency for CC EP1810 EPLDs. Figure 17. I vs. Frequency of EP1810 Devices CC EP1810 100 10 Typical I CC V = 5.0 V CC Active (mA) T = 25° C A 1.0 0.1 10 kHz 100 kHz 1 MHz 10 MHz 60 MHz Frequency Figure 18 shows the output drive characteristics of EP1810 devices. Figure 18. Output Drive Characteristics of EP1810 Devices Drive characteristics may exceed shown curves. EP1810-20 & EP1810-25 EPLDs EP1810-35 & EP1810-45 EPLDs 200 80 I OL 150 60 I OL Typical I Typical I O O V = 5.0 V V = 5.0 V CC CC Output Output 100 40 T = 25° C T = 25° C A A Current (mA) Current (mA) I OH 50 20 I OH 1 2 3 4 5 1 2 3 4 5 V Output Voltage (V) V Output Voltage (V) O O 780 Altera Corporation Classic EPLD Family Data Sheet Tables 23 through 27 provide information on absolute maximum ratings, Operating recommended operating conditions, operating conditions, and Conditions capacitance for EP1810 devices. Table 23. EP1810 Device Absolute Maximum Ratings Notes (1), (2) Symbol Parameter Conditions Min Max Unit V Supply voltage With respect to ground (3) –2.0 (–0.5) 7.0 V CC V DC input voltage With respect to ground (3) –2.0 (–0.5) 7.0 V I I DC V or ground current –300 (–400) 300 (400) mA MAX CC I DC output current, per pin –25 25 mA OUT T Storage temperature No bias –65 150 ° C STG T Ambient temperature Under bias –65 135 ° C AMB T Junction temperature Ceramic packages, under bias 150 ° C J Plastic packages, under bias 135 ° C Table 24. EP1810 Device Recommended Operating Conditions Note (2) Symbol Parameter Conditions Min Max Unit V Supply voltage (4) 4.75 (4.5) 5.25 (5.5) V CC V Input voltage –0.3 V + 0.3 V I CC V Output voltage 0 V V O CC T Operating temperature For commercial use 0 70 ° C A For industrial use –40 85 ° C t Input rise time (5) 50 ns R t Input fall time (5) 50 ns F Table 25. EP1810 Device DC Operating Conditions Notes (6), (7) Symbol Parameter Conditions Min Max Unit V High-level input voltage 2.0 V + 0.3 V IH CC V Low-level input voltage –0.3 0.8 V IL V High-level TTL output voltage I = –4 mA DC (8) 2.4 V OH OH High-level CMOS output voltage I = –0.6 mA DC (8) 3.84 V OH V Low-level output voltage I = 4 mA DC (8) 0.45 V OL OL I I/O pin leakage current of dedicated V = V or ground –10 10 μA I I CC input pins I Tri-state output leakage current V = V or ground –10 10 μA OZ O CC Altera Corporation 781 Classic EPLD Family Data Sheet Table 26. EP1810 Device Capacitance Note (9) Symbol Parameter Conditions Min Max Unit C Input pin capacitance V = 0 V, f = 1.0 MHz 20 pF IN IN C I/O pin capacitance V = 0 V, f = 1.0 MHz 20 pF IO OUT C C pin capacitance V = 0 V, f = 1.0 MHz 25 pF CLK1 CLK1 IN C C pin capacitance V = 0 V, f = 1.0 MHz 160 pF CLK2 CLK2 IN Table 27. EP1810 Device I Supply Current Notes (2), (6), (7) CC Symbol Parameter Conditions Speed Min Typ Max Unit Grade I V supply current V = V or ground, no load, -20, -25 50 150 μA CC1 CC I CC (10) (non-Turbo, standby) -35, -45 35 150 μA I V supply current V = V or ground, no load, -20, -25 20 40 mA CC2 CC I CC f = 1.0 MHz (10) (non-Turbo, active) -35, -45 10 30 (40) mA I V supply current (Turbo, active) V = V or ground, no load -20, -25 180 225 (250) mA CC3 CC I CC f = 1.0 MHz (10) -35, -45 100 180 (240) mA Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet in this data book. (2) Numbers in parentheses are for industrial-temperature-range devices. (3) The minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods less than 20 ns. (4) Maximum V rise time is 50 ms. CC (5) For EP1810 clocks: t and t = 100 ns (50 ns for industrial-temperature-range versions). R F (6) Typical values are for T = 25° C and V = 5 V. A CC (7) These values are specified in Table 24 on page 781. (8) The I parameter refers to high-level TTL or CMOS output current; the I parameter refers to low-level TTL OH OL output current. (9) The device capacitance is measured at 25° C and is sample-tested only. (10) Measured with a device programmed as four 12-bit counters. 782 Altera Corporation Classic EPLD Family Data Sheet Tables 28 through 31 show the timing parameters for EP1810-20, EP1810-25, EP1810-35, and EP1810-45 devices. Table 28. EP1810-20 & EP1810-25 External Timing Parameters Note (1) Symbol Parameter Conditions EP1810-20 EP1810-25 Non-Turbo Unit Adder (2) Min Max Min Max t Input to non-registered output C1 = 35 pF 20.0 25.0 25.0 ns PD1 t I/O input to non-registered output C1 = 35 pF 22.0 28.0 25.0 ns PD2 t Global clock setup time 13.0 17.0 25.0 ns SU t Global clock hold time 0.0 0.0 0.0 ns H t Global clock high time 8.0 10.0 0.0 ns CH t Global clock low time 8.0 10.0 0.0 ns CL t Global clock to output delay C1 = 35 pF 15.0 18.0 0.0 ns CO1 t Minimum global clock period (3) 20.0 25.0 0.0 ns CNT f Maximum internal frequency (3) 50.0 40.0 0.0 MHz CNT t Array clock setup time 8.0 10.0 25.0 ns ASU t Array clock hold time 8.0 10.0 0.0 ns AH t Array clock to output delay C1 = 35 pF 20.0 25.0 25.0 ns ACO1 t Output data hold time after clock C1 = 35 pF (4) 1.0 1.0 0.0 ns ODH t Array clock maximum clock period (3) 20.0 25.0 0.0 ns ACNT f Maximum internal array clock (3) 50.0 40.0 0.0 ns ACNT frequency f Maximum clock frequency (5) 62.5 50.0 0.0 MHz MAX Table 29. EP1810-20 and EP1810-25 Internal Timing Parameters Symbol Parameter Conditions EP1810-20 EP1810-25 Non-Turbo Unit Adder (2) Min Max Min Max t Input pad and buffer delay 5.0 7.0 0.0 ns IN t I/O input pad and buffer delay 2.0 3.0 0.0 ns IO t Logic array delay 9.0 12.0 25.0 ns LAD t Output buffer and pad delay C1 = 35 pF 6.0 6.0 0.0 ns OD t Output buffer enable delay C1 = 35 pF 6.0 6.0 0.0 ns ZX t Output buffer disable delay C1 = 5 pF (6) 6.0 6.0 0.0 ns XZ t Register setup time 8.0 10.0 0.0 ns SU t Register hold time 5.0 10.0 0.0 ns H t Array clock delay 9.0 12.0 25.0 ns IC t Global clock delay 4.0 5.0 0.0 ns ICS t Feedback delay 3.0 3.0 –25.0 ns FD t Register clear time 9.0 12.0 25.0 ns CLR Altera Corporation 783 Classic EPLD Family Data Sheet Table 30. EP1810-35 & EP1810-45 External Timing Parameters Note (1) Symbol Parameter Conditions EP1810-35 EP1810-45 Non-Turbo Unit Adder Min Max Min Max (2) t Input to non-registered output C1 = 35 pF 35.0 45.0 30.0 ns PD1 t I/O input to non-registered output C1 = 35 pF 40.0 50.0 30.0 ns PD2 t Global clock setup time 25.0 30.0 30.0 ns SU t Global clock hold time 0.0 0.0 0.0 ns H t Global clock high time 12.0 15.0 0.0 ns CH t Global clock low time 12.0 15.0 0.0 ns CL t Global clock to output delay C1 = 35 pF 20.0 25.0 0.0 ns CO1 t Minimum global clock period (3) 35.0 45.0 0.0 ns CNT f Maximum internal frequency (3) 28.6 22.2 0.0 MHz CNT t Array clock setup time 10.0 11.0 30.0 ns ASU t Array clock hold time 15.0 18.0 0.0 ns AH t Array clock to output delay C1 = 35 pF 35.0 45.0 30.0 ns ACO1 t Output data hold time after clock C1 = 35 pF (4) 1.0 1.0 ns ODH t Array clock maximum clock period (3) 35.0 45.0 0.0 ns ACNT f Maximum internal array clock (3) 28.6 22.2 0.0 ns ACNT frequency f Maximum clock frequency (5) 40 33.3 0.0 MHz MAX Table 31. EP1810-35 & EP1810-45 Internal Timing Parameters Non-Turbo Symbol Parameter Conditions EP1810-35 EP1810-45 Unit Adder (2) Min Max Min Max t Input pad and buffer delay 7.0 6.0 0.0 ns IN t I/O input pad and buffer delay 5.0 5.0 0.0 ns IO t Logic array delay 19.0 28.0 30.0 ns LAD t Output buffer and pad delay C1 = 35 pF 9.0 11.0 0.0 ns OD t Output buffer enable delay C1 = 35 pF 9.0 11.0 0.0 ns ZX t Output buffer disable delay C1 = 5 pF (6) 9.0 11.0 0.0 ns XZ t Register setup time 10.0 10.0 0.0 ns SU t Register hold time 15.0 18.0 0.0 ns H t Array clock delay 19.0 28.0 30.0 ns IC t Global clock delay 4.0 8.0 0.0 ns ICS t Feedback delay 6.0 7.0 –30.0 ns FD t Register clear time 24.0 32.0 30.0 ns CLR 784 Altera Corporation Classic EPLD Family Data Sheet Notes to tables: (1) These values are specified in Table 24 on page 781. (2) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (3) Measured with a device programmed as four 12-bit counters. (4) Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter applies for both global and array clocking. (5) The f values represent the highest frequency for pipelined data. MAX (6) Sample-tested only for an output change of 500 mV. Table 32 provides pin-out information for EP1810 devices in 68-pin PGA Pin-Out packages. Information Table 32. EP1810 PGA Pin-Outs Pin Function Pin Function Pin Function Pin Function A2 I/O B9 I/O F10 GND K4 INPUT A3 I/O B10 I/O F11 I/O K5 INPUT A4 I/O B11 I/O G1 I/O K6 VCC A5 INPUT C1 I/O G2 I/O K7 INPUT A6 CLK4/INPUT C2 I/O G10 I/O K8 INPUT A7 CLK3/INPUT C10 I/O G11 I/O K9 I/O A8 INPUT C11 I/O H1 I/O K10 I/O A9 I/O D1 I/O H2 I/O K11 I/O A10 I/O D2 I/O H10 I/O L2 I/O B1 I/O D10 I/O H11 I/O L3 I/O B2 I/O D11 I/O J1 I/O L4 INPUT B3 I/O E1 I/O J2 I/O L5 CLK1/INPUT B4 INPUT E2 I/O J10 I/O L6 CLK2/INPUT B5 INPUT E10 I/O J11 I/O L7 INPUT B6 VCC E11 I/O K1 I/O L8 I/O B7 INPUT F1 I/O K2 I/O L9 I/O B8 INPUT F2 GND K3 I/O L10 I/O Altera Corporation 785 Notes: