2559 Protected Quad Power Driver Last Time Buy This part is in production but has been determined to be LAST TIME BUY. This classification indicates that the product is obsolete and notice has been given. Sale of this device is currently restricted to existing customer applications. The device should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer available. Date of status change: November 1, 2010 Deadline for receipt of LAST TIME BUY orders: April 30, 2011 Recommended Substitutions: For existing customer transition, and for new customers or new appli- cations, contact Allegro Sales. NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon- sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 2559 Protected Quad Power Driver Features and Benefits Description ▪ 700 mA output current per channel Providing improved output current limiting, the UDK, ▪ Independent overcurrent protection for each driver UDN, and UDQ2559B, EB, and LB quad power drivers ▪ Thermal protection for device and each driver combine AND logic gates and high-current bipolar outputs ▪ Low output-saturation voltage with complete output protection. Each of the four outputs ▪ Integral output flyback diodes sink 700 mA in the on state. The outputs have a minimum ▪ TTL and 5 V CMOS-compatible inputs breakdown voltage (load dump) of 60 V and a sustaining voltage of 40 V. The inputs are compatible with TTL and 5 V CMOS logic systems. Overcurrent protection for each channel has been designed into these devices and is activated at approximately 1 A. It Packages: protects each output from short circuits with supply voltages up to 25 V. When an output current trip point is reached, that output stage is driven linearly resulting in a reduced output current level. If an over-current or short-circuit condition continues, the thermal-limiting circuits will first sense the rise in junction temperature and then the rise in chip temperature, further decreasing the output current. Under worst-case 16-pin DIP conditions, these devices will tolerate short circuits on all 28-pin PLCC with exposed thermal tabs (Package EB) outputs, simultaneously. (B package) These devices can be used to drive various loads including incandescent lamps (without warming or limiting resistors) or inductive loads such as relays, solenoids, or dc stepping motors. 16-pin SOICW The packages offer fused leads for enhanced thermal dissipation. with internally fused pins Package B is a 16-pin power DIP with exposed tabs, EB is a (LB package) 28-lead power PLCC, and LB is a 16-lead power wide-body Not to scale SOIC for surface-mount applications. They are lead (Pb) free with 100% matte tin leadframe plating. Functional Block Diagram (1 of 4 Channels) V K CC OUT N ENABLE IN N Thermal Limit << 1Ω 29317.14L 2559 Protected Quad Power Driver Selection Guide Ambient Temperature Part Number Package Packing (°C) UDN2559B-T 16-pin DIP, exposed tabs 25 per tube –20 to 85 UDN2559EBTR-T 28-lead PLCC 800 per reel UDQ2559LBTR-T 16-lead SOIC 1000 per reel –40 to 85 UDK2559B-T 16-pin DIP, exposed tabs 25 per tube UDK2559EBTR-T 28-lead PLCC 800 per reel –40 to 125 UDK2559LBTR-T 16-lead SOIC 1000 per reel Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Supply Voltage V 7V CC Input Voltage Range V , V 7V IN EN Output Voltage V 60 V OUT Overcurrent-Protected Output Voltage V 25 V OUT(P) Outputs are peak current limited at approxi- Output Current I mately 1.0 A per driver. See Circuit Description 1.0 A OUT and Application section for further information. Range K –40 to 125 ºC Operating Ambient Temperature T Range N –20 to 85 ºC A Range Q –40 to 85 ºC Maximum Junction Temperature T (max) 150 ºC J Storage Temperature T –55 to 150 ºC stg Allegro MicroSystems, Inc. 2 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2559 Protected Quad Power Driver Pin-out Diagrams Package B Package LB 1 16 IN OUT 4 4 OUT 1 16 IN 4 4 2 15 IN K 3 K 2 15 IN 3 3 14 ENABLE OUT 14 3 3 ENABLE OUT 3 4 GROUND 13 GROUND 4 GROUND 13 GROUND GROUND 5 12 GROUND GROUND 5 12 GROUND OUT 6 11 V OUT 6 11 V 2 CC 2 CC 7 10 K IN 2 K 7 10 IN 2 IN OUT 8 9 9 IN 1 OUT 8 1 1 1 Dwg. PP-017-1 Dwg. PP-017-6 Package EB NC GROUND 5 25 GROUND 6 24 7 23 8 22 9 21 10 20 GROUND 11 19 GROUND NC V CC Dwg. PP-019-1 Allegro MicroSystems, Inc. 3 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 4 OUT OUT 2 3 13 3 K K 14 2 OUT OUT 4 1 NO NO 15 1 CONNECTION CONNECTION 16 28 IN IN 1 4 27 IN 17 IN 3 2 SUPPLY 18 26 ENABLE 2559 Protected Quad Power Driver Thermal Characteristics Characteristic Symbol Test Conditions* Value Units 2 Package B, 2-layer PCB with 0.5 in. exposed copper each side 43 ºC/W R Package Thermal Resistance Package EB, 1-layer PCB with copper limited to solder pads 36 ºC/W θJA Package LB, 1-layer PCB with copper limited to solder pads 90 ºC/W *Additional thermal information available on the Allegro website P = (V x I x dc) + … + (V x I x dc) D OUT1 OUT1 OUTn OUTn + (V x I ) = (T - T )/R CC CC J A JA Allegro MicroSystems, Inc. 4 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Copyright © 1995, 2002 Allegro MicroSystems, Inc. 2559 Protected Quad Power Driver ELECTRICAL CHARACTERISTICS at T = +25°C (preŢ x ‘UDN’) or over operating A temperature range (preŢ x ‘UDK’ or ‘UDQ’), V = 4.75 V to 5.25 V CC Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Output Leakage Current I V = 50 V, V = 0.8 V, V = 2.0 V — <1.0 100 μA CEX OUT IN EN V = 50 V, V = 2.0 V, V = 0.8 V — <1.0 100 μA OUT IN EN Output Sustaining Voltage V I = 100 mA, V = V = 0.8 V 40 — — V OUT(SUS) OUT IN EN Output Saturation Voltage V All Devices, I = 100 mA — — 300 mV OUT(SAT) OUT All Devices, I = 400 mA — — 500 mV OUT B or EB package only, I = 600 mA — — 700 mV OUT Over-Current Trip I — 1.0 — A TRIP Input Voltage Logic 1 V or V 2.0 — — V IN(1) EN(1) Logic 0 V or V — — 0.8 V IN(0) EN(0) Input Current Logic 1 V or V = 2.0 V — — 40 μA IN(1) EN(1) Logic 0 V or V = 0.8 V — — -10 μA IN(0) EN(0) Total Supply Current* I All Outputs ON, V = V = 2.0 V — — 80 mA CC IN EN All Outputs OFF — — 5.0 mA Clamp Diode Forward Voltage V I = 1.0 A — — 1.7 V F F I = 1.5 A — — 2.1 V F Clamp Diode Leakage Current I V = 50 V, D + D or D + D — — 50 μA R R 1 2 3 4 Turn-On Delay t I = 500 mA — — 20 μs PHL OUT t I = 500 mA — — 20 μs PLH OUT Thermal Limit T — 165 — °C J Typical Data is for design information only. Negative current is deŢ ned as coming out of (sourcing) the speciŢ ed terminal. As used here, -100 is deŢ ned as greater than +10 (absolute magnitude convention) and the minimum is implicitly zero. * All inputs simultaneously, all other tests are performed with each input tested separately. Allegro MicroSystems, Inc. 5 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2559 Protected Quad Power Driver CIRCUIT DESCRIPTION AND APPLICATION TYPICAL OUTPUT CHARACTERISTIC INCANDESCENT LAMP DRIVER High incandescent lamp turn-ON/in-rush currents can contribute to poor lamp reliability and destroy semiconductor lamp drivers. Warming or current- limiting resistors protect both driver and lamp but use signiŢ cant power either when the lamp is OFF or when the lamp is ON, respectively. Lamps with steady-state current ratings up to 700 mA can be driven by these devices with- out the need for warming (parallel) or current-limiting (series) resistors. When an incandescent lamp is initially turned ON, the cold Ţ lament is at minimum resistance and would normally allow a 10x to 12x in-rush cur- rent. With these drivers, during turn-ON, the high in-rush current is sensed by the internal low-value sense resistor. Drive current to the output stage is then diverted by the shunting transistor, and the load current is momentarily limited to approximately 1.0 A. During this short transition period, the output cur- rent is reduced to a value dependent on supply voltage and Ţ lament resistance. During lamp warmup, the Ţ lament resistance increases to its maximum value, the output stage goes into saturation and applies maximum rated voltage to the lamp. INDUCTIVE LOAD DRIVER BiŢ lar (unipolar) stepper motors, relays, or solenoids can be driven di- rectly. The internal ţ yback diodes prevent damage to the output transistors by suppressing the high-voltage spikes that occur when turning OFF an inductive TYPICAL OUTPUT BEHAVIOR load. For rapid current decay (fast turn-OFF speeds), the use of Zener diodes will raise the ţ yback voltage and inprove performance. However, the peak voltage must not exceed the speciŢ ed minimum sustaining voltage (V + SUPPLY V + V V ). Z F OUT(SUS) FAULT CONDITIONS In the event of a shorted load, the load current will attempt to increase. As described above, the drive current to the affected output stage is reduced, caus- ing the output stage to go linear, limiting the peak output current to approxi- mately 1 A. As the power dissipation of that output stage increases, a thermal gradient sensing circuit will become operational, further decreasing the drive current to the affected output stage and reducing the output current to a value dependent on supply voltage and load resistance. Continuous or multiple overload conditions causing the chip temperature to reach approximately 165°C will result in an additional reduction in output current to maintain a safe level. If the fault condition is corrected, the output stage will return to its normal saturated condition. Allegro MicroSystems, Inc. 6 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2559 Protected Quad Power Driver B Package, 16-pin DIP with internally fused pins 4, 5, 12, and 13 and external thermal tabs 19.05±0.25 16 +0.10 0.38 –0.05 +0.76 +0.38 6.35 10.92 7.62 –0.25 –0.25 A 1 2 For Reference Only 5.33 MAX (reference JEDEC MS-001 BB) Dimensions in inches, metric dimensions (mm) in brackets, for reference only +0.51 Dimensions exclusive of mold flash, gate burrs, and dambar protrusions 3.30 –0.38 Exact case and lead configuration at supplier discretion within limits shown 1.27 MIN 2.54 A Terminal #1 mark area +0.25 1.52 –0.38 0.46 ±0.12 EB Package, 28-pin PLCC with internally fused pins 5 through 11 and 19 through 25 12.45±0.13 11.51±0.08 21 28 0.51 A 5.21±0.36 12.45±0.13 11.51±0.08 5.21±0.36 0.51 MIN 0.74±0.08 +0.20 28X 4.37 C –0.18 SEATING 0.10 C PLANE 0.43±0.10 For Reference Only 1.27 (reference JEDEC MS-018 AB) Dimensions in millimeters 5.21±0.36 5.21±0.36 Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area Allegro MicroSystems, Inc. 7 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2559 Protected Quad Power Driver LB Package, 16-pin SOICW with internally fused pins 4 and 5, and 12 and 13 10.30±0.20 1.27 0.65 4° ±4 16 16 +0.07 0.27 –0.06 10.30±0.33 7.50±0.10 9.50 A +0.44 0.84 –0.43 2.25 1 2 1 2 0.25 PCB Layout Reference View B 16X C SEATING PLANE SEATING 0.10 C GAUGE PLANE PLANE 0.41 ±0.10 1.27 2.65 MAX 0.20 ±0.10 For Reference Only Pins 4 and 5, and 12 and 13 internally fused Terminal #1 mark area A Dimensions in millimeters (reference JEDEC MS-013 AA) Reference pad layout (reference IPC SOIC127P1030X265-16M) B All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown to meet application process requirements and PCB layout tolerances Copyright ©1995-2010, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail speciŢ cations as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 8 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com