Am79C972 PCnet™-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support DISTINCTIVE CHARACTERISTICS � Integrated Fast Ethernet controller for the � Supports PC97, PC98, and Net PC requirements Peripheral Component Interconnect (PCI) bus — Implements full OnNow features including — 32-bit glueless PCI host interface pattern matching and link status wake-up — Supports PCI clock frequency from DC to — Implements Magic Packet mode 33 MHz independent of network clock — Magic Packet mode and the physical address — Supports network operation with PCI clock loaded from EEPROM at power up without from 15 MHz to 33 MHz requiring PCI clock — High performance bus mastering — Supports PCI Bus Power Management architecture with integrated Direct Memory Interface Specification Version 1.0 Access (DMA) Buffer Management Unit for — Supports Advanced Configuration and low CPU and bus utilization Power Interface (ACPI) Specification — PCI specification revision 2.1 compliant Version 1.0 — Supports PCI Subsystem/Subvendor ID/ — Supports Network Device Class Power Vendor ID programming through the Management Specification Version 1.0 EEPROM interface � Large independent internal TX and RX FIFOs — Supports both PCI 3.3-V and 5.0-V signaling — Programmable FIFO watermarks for both environments transmit and receive operations — Plug and Play compatible — Receive frame queuing for high latency PCI — Supports an unlimited PCI burst length bus host operation — Big endian and little endian byte alignments — Programmable allocation of buffer space supported between transmit and receive queues — Implements optional PCI power management � Dual-speed CSMA/CD (10 Mbps and 100 Mbps) event (PME) pin Media Access Controller (MAC) compliant with � Media Independent Interface (MII) for IEEE/ANSI 802.3 and Blue Book Ethernet connecting external 10/100 megabit per second standards (Mbps) transceivers � EEPROM interface supports jumperless design — IEEE 802.3-compliant MII and provides through-chip programming — Intelligent Auto-Poll™ external PHY status — Supports full programmability of half-/full- monitor and interrupt duplex operation for external 10/100 Mbps — Supports both auto-negotiable and non PHYs through EEPROM mapping auto-negotiable external PHYs — Programmable PHY reset output pin capable — Supports 10BASE-T, 100BASE-TX/FX, of resetting external PHY without needing 100BASE-T4, and 100BASE-T2 IEEE 802.3- buffering compliant MII PHYs at full- or half-duplex � Integrated oscillator circuit eliminates need for � Supports General Purpose Serial Interface external crystal (GPSI) with receive frame tagging support for � Extensive programmable LED status support internetworking applications � Support for operation in industrial temperature � Full-duplex operation supported in MII and GPSI range (-40°C to +85°C) ports with independent Transmit (TX) and Receive (RX) channels Publication# 21485 Rev: D Amendment/0 Issue Date: December 1999 Refer to AMD’s Website (www.amd.com) for the latest information. � Supports up to 1 megabyte (Mbyte) optional � Software compatible with AMD PCnet Family Boot PROM or Flash for diskless node and LANCE/C-LANCE register and descriptor application architecture � Look-Ahead Packet Processing (LAPP) data � Compatible with the existing PCnet Family handling technique reduces system overhead driver and diagnostic software by allowing protocol analysis to begin before � Available in 160-pin PQFP and 176-pin TQFP the end of a receive frame packages � Programmable Inter Packet Gap (IPG) to � +3.3 V power supply with 5 V tolerant I/Os address less network aggressive MAC enables broad system compatibility controllers � Extensive programmable internal/external � Offers the Modified Back-Off algorithm to loopback capabilities address the Ethernet Capture Effect � Supports patented External Address Detection � IEEE 1149.1-compliant JTAG Boundary Scan Interface (EADI) test access port interface and NAND tree test mode for board-level production connectivity test GENERAL DESCRIPTION The Am79C972 PCnet-FAST+ controller is a highly- test interface for board-level testing is also provided, as integrated 32-bit full-duplex, 10/100-Megabit per sec- well as a NAND tree test structure for those systems ond (Mbps) Ethernet controller solution, designed to that cannot support the JTAG interface. address high-performance system application require- The Am79C972 PCnet-FAST+ controller is also com- ments. It is a flexible bus mastering device that can be pliant with the PC97, PC98, and Net PC specifications. used in any application, including network-ready PCs It includes the full implementation of the Microsoft and bridge/router designs. The bus master architecture OnNow and ACPI specifications, which are backward provides high data throughput and low CPU and sys- compatible with the Magic Packet technology, and is tem bus utilization. The Am79C972 controller is fabri- compliant with the PCI Bus Power Management Inter- cated with advanced low-power 3.3-V CMOS process face Specification by supporting the four power man- to provide low operating current for power sensitive ap- agement states (D0, D1, D2, and D3), the optional plications. PME pin, and the necessary configuration and data The Am79C972 PCnet-FAST+ controller also has sev- registers. eral enhancements over its predecessor, the The Am79C972 PCnet-FAST+ controller is ideally Am79C971 PCnet-FAST device. In addition to integrat- suited for Network PC (Net PC), motherboard, network ing the SRAM on chip, it further reduces system imple- interface card (NIC), and embedded designs. It is avail- mentation cost by the addition of a new EEPROM able in a 160-pin Plastic Quad Flat Pack (PQFP) pack- programmable pin (PHY_RST), an internal oscillator age and also in a 176-pin Thin Quad Flat Pack (TQFP) circuit eliminating the need for an external crystal, and package for form factor sensitive designs. the integration of the PAL function needed for Magic Packet application. The PHY_RST pin is implemented The Am79C972 PCnet-FAST+ controller is a complete to reset the external PHY without increasing the load to Ethernet node integrated into a single VLSI device. It the PCI bus and to block RST to the PHY when PG contains a bus interface unit, a Direct Memory Access input is LOW. (DMA) Buffer Management Unit, an ISO/IEC 8802-3 (IEEE 802.3)-compliant Media Access Controller The 32-bit multiplexed bus interface unit provides a di- (MAC), a large Transmit FIFO and a large Receive rect interface to the PCI local bus, simplifying the FIFO, and an IEEE 802.3-compliant MII. Both IEEE design of an Ethernet node in a PC system. The 802.3 compliant full-duplex and half-duplex operations Am79C972 PCnet-FAST+ controller provides the com- are supported on the MII and GPSI interfaces. 10/100 plete interface to an Expansion ROM or Flash device Mbps operation is supported through the MII. allowing add-on card designs with only a single load per PCI bus interface pin. With its built-in support for The Am79C972 PCnet-FAST+ controller is register both little and big endian byte alignment, this controller compatible with the LANCE™ (Am7990) and C- also addresses non-PC applications. The Am79C972 LANCE™ (Am79C90) Ethernet controllers, and all controller’s advanced CMOS design allows the bus in- Ethernet controllers in the PCnet Family except terface to be connected to either a +5-V or a +3.3-V sig- ILACC™ (Am79C900), including the PCnet-ISA™ con- naling environment. A compliant IEEE 1149.1 JTAG troller (Am79C960), PCnet-ISA+™ (Am79C961), 2 Am79C972 PCnet-ISA II™ (Am79C961A), PCnet-32™ The Am79C972 PCnet-FAST+ controller contains (Am79C965), PCnet-PCI™ (Am79C970), 12-kilobyte (Kbyte) buffers, the largest of its class of 10/ PCnet-PCI II™ (Am79C970A), and the PCnet-FAST™ 100 Mbps Ethernet controllers. The large internal (Am79C971). The Buffer Management Unit supports buffer is programmable between the transmit (TX) and the LANCE and PCnet descriptor software models. receive (RX) queues for optimal performance. The Am79C972 PCnet-FAST+ controller supports With the rise of embedded networking applications op- auto-configuration in the PCI configuration space. erating in harsh environments where temperatures Additional Am79C972 controller configuration parame- may exceed the normal commercial temperature win- ters, including the unique IEEE physical address, can dow (0°C to 70°C), an industrial temperature (-40°C to be read from an external nonvolatile memory +85°C) version is available in both the 160-pin PQFP (EEPROM) immediately following system reset. and the 176-pin TQFP package. The Am79C972 PCnet-FAST+ 10/100 Mbps Ethernet controller can be In addition, the device provides programmable on-chip designed with the industrial temperature capable LED drivers for transmit, receive, collision, link integrity, Am79C874 NetPHY-1LP 10/100 Mbps Ethernet PHY Magic Packet status, activity, address match, full-du- for a complete and robust Fast Ethernet solution that plex, or 100 Mbps status. The Am79C972 controller can withstand extreme temperature environments. also provides an EADI to allow external hardware ad- dress filtering in internetworking applications and a re- ceive frame tagging feature. Am79C972 3 BLOCK DIAGRAM EBUA_EBA[7:0] EBDA[15:8] EBD[7:0] EROMCS AS_EBOE EBWE EBCLK Expansion Bus CLK Interface RST TXEN AD[31:0] TXCLK C/BE[3:0] TXDAT GPSI PAR RXEN Port FRAME RXCLK TRDY RXDAT IRDY CLSN Bus MAC STOP Rcv Rcv TX_ER IDSEL FIFO FIFO TXD[3:0] DEVSEL TX_EN PCI Bus REQ TX_CLK Interface 802.3 GNT COL Unit 12K MAC PERR MII RXD[3:0] SRAM Core SERR Port RX_ER INTA RX_CLK RX_DV CRS Bus MAC MDC Xmt Xmt MDIO FIFO FIFO SRDCLK SRD EADI SFBD Network FIFO Port EAR Port Control MIIRXFRTGD/RXFRTGD Manager MIIRXFRTGE/RXFRTGE Buffer PHY_RST Management TBC_IN Unit TBC_EN EECS 93C46 EESK EEPROM EEDI Interface EEDO OnNow LED0 Power TCK JTAG LED LED1 TMS Management Port LED2 Control TDI Unit Control LED3 TDO PME PG RWU WUMI 21485C-1 4 Am79C972 TABLE OF CONTENTS AM79C972 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 DISTINCTIVE CHARACTERISTICS1 BLOCK DIAGRAM4 GENERAL DESCRIPTION2 TABLE OF CONTENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 CONNECTION DIAGRAM (PQR160)8 CONNECTION DIAGRAM (PQL176)9 PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 PIN DESIGNATIONS (PQL176) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 PIN DESIGNATIONS (PQR160, PQL176). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Listed By Driver Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 General Purpose Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Power Supply Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 BASIC FUNCTIONS26 System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 DETAILED FUNCTIONS27 Slave Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Slave I/O Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Master Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Software Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Transmit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Loopback Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 General Purpose Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Automatic Network Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Power Savings Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Magic Packet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 NAND Tree Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Am79C972 5 USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 RAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Receive Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 REGISTER PROGRAMMING SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 Am79C972 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 DC CHARACTERISTICS OVER OPERATING RANGES 190 COMMERCIAL AND INDUSTRIAL SWITCHING CHARACTERISTICS: BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . .194 SWITCHING CHARACTERISTICS: GENERAL-PURPOSE SERIAL INTERFACE . . . . . . . . . . . .195 SWITCHING CHARACTERISTICS: EXTERNAL ADDRESS DETECTION INTERFACE . . . . . . . .196 SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 SWITCHING TEST CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 SWITCHING WAVEFORMS: EXPANSION BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . .204 SWITCHING WAVEFORMS: GENERAL-PURPOSE SERIAL INTERFACE . . . . . . . . . . . . . . . . . .206 SWITCHING WAVEFORMS: EXTERNAL ADDRESS DETECTION INTERFACE. . . . . . . . . . . . . .207 SWITCHING WAVEFORMS: RECEIVE FRAME TAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 PQR160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 Plastic Quad Flat Pack (measured in millimeters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 PQL176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 Thin Quad Flat Pack (measured in millimeters). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 Outline of LAPP Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 LAPP Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 LAPP Rules for Parsing Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 Auto-Negotiation Link Partner Ability Register (Register 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 6 Am79C972 RELATED AMD PRODUCTS Part No. Description Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE) Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver Am79C98 Twisted Pair Ethernet Transceiver (TPEX) Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+) Am79865 100 Mbps Physical Data Transmitter (PDT) Am79866A 100 Mbps Physical Data Receiver (PDR) Am79C871 Quad 100BASE-X Transceiver for Repeater Am79C940 Media Access Controller for Ethernet (MACE™) Am79C961A PCnet-ISA II Single-Chip Full-Duplex Ethernet Controller (with Microsoft® Plug n' Play support) Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 486 and VL buses) Am79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Am79C971 PCnet-FAST Single-Chip Full-Duplex 10/100 Ethernet Controller for PCI Local Bus Am79C972 7 CONNECTION DIAGRAM (PQR160) 1 120 EEDO/LED3/SRD/MIIRXFRTGD IDSEL AD23 2 119 PHY_RST 3 118 VSSB MDIO AD22 4 117 VSSB 116 VDD_PCI 5 MDC AD21 6 115 RXD3 AD20 7 114 RXD2 8 113 VDD VDDB AD19 9 112 RXD1 10 111 AD18 RXD0/RXFRTGD VSSB 11 110 VSS 109 AD17 12 RX_DV/RXFRTGE VDD_PCI 13 108 RX_CLK/RXCLK 107 AD16 14 RX_ER/RXDAT 15 106 C/BE2 VSSB 16 VSS 105 TX_ER 17 104 FRAME TX_CLK/TXCLK IRDY 18 103 TX_EN/TXEN VSSB 19 102 PCnet“-FAST+ TXD0/TXDAT TRDY 20 101 VDDB Am79C972BKC VDD_PCI 21 100 Am79C972 VDD 22 99 TXD1 DEVSEL 23 98 TXD2 STOP VDD 24 97 TXD3 25 96 PERR COL/CLSN SERR 26 95 VSSB VSSB 27 94 CRS/RXEN 28 93 PAR EBD0 VDD_PCI 29 92 EBD1 91 C/BE1 30 EBD2 AD15 31 90 VSS 89 VSS 32 EBD3 AD14 33 88 VDDB 87 AD13 34 EBD4 VSSB 35 86 EBD5 AD12 36 85 EBD6 84 AD11 37 VSSB VDD_PCI 38 83 EBD7 39 82 AD10 EBDA15 AD9 40 81 EBDA14 21485C-2 Pin 1 is marked for orientation. 8 Am79C972 AD8 41 160 C/BE3 C/BE0 42 159 AD24 VSSB 43 158 AD25 AD7 44 157 VSSB VDD_PCI 45 156 AD26 AD6 46 155 VDD_PCI AD5 47 154 AD27 VDD 48 153 AD28 49 152 AD29 AD4 AD3 50 151 AD30 51 150 VSS VSSB VSSB AD2 52 149 VDD_PCI 53 148 AD31 54 147 VDD_PCI AD1 AD0 55 146 REQ VSS 56 145 GNT EROMCS 57 144 CLK EBWE 58 143 RST 59 142 AS_EBOE INTA EBCLK 60 141 PG 61 140 VDD EBUA_EBA0 VSSB 62 139 TDI EBUA_EBA1 63 138 VSSB TDO VDD 64 137 VDDB 65 136 VDDB 66 135 TMS EBUA_EBA2 EBUA_EBA3 67 134 TCK EBUA_EBA4 68 133 RWU EBUA_EBA5 69 132 WUMI EBUA_EBA6 70 131 PME EBUA_EBA7 71 130 VSS VSS 72 129 EAR 73 128 EBDA8 EECS VSSB 74 127 VSSB EBDA9 75 126 EESK/LED1/SFBD EBDA10 76 125 LED2/SRDCLK/MIIRXFRTGE VDDB 77 124 VDDB EBDA11 78 123 TBC_EN EBDA12 79 122 TBC_IN 80 121 EEDI/LED0 EBDA13 CONNECTION DIAGRAM (PQL176) 1 132 NC NC 2 131 NC NC 3 130 EEDO/LED3/SRD/MIIRXFRTGD IDSEL 4 129 PHY_RST AD23 5 128 MDIO VSSB 6 127 VSSB AD22 7 126 MDC VDD_PCI 8 125 RXD3 AD21 9 124 RXD2 AD20 10 123 VDDB VDD 11 122 RXD1 AD19 12 121 RXD0/RXFRTGD AD18 13 120 VSS VSSB 14 119 RX_DV/RXFRTGE AD17 15 118 RX_CLK/RXCLK VDD_PCI 16 117 RX_ER/RXDAT AD16 17 116 VSSB C/BE2 18 115 TX_ER VSS 19 114 TX_CLK/TXCLK FRAME 20 113 TX_EN/TXEN IRDY 21 112 TXD0/TXDAT VSSB PCnet“-FAST+ 22 111 VDDB TRDY 23 110 VDD VDD_PCI Am79C972 Am79C972BVC 24 109 TXD1 DEVSEL 25 108 TXD2 STOP 26 107 TXD3 VDD 27 106 COL/CLSN PERR 28 105 VSSB SERR 29 104 CRS/RXEN VSSB 30 103 EBD0 PAR 31 102 EBD1 VDD_PCI 32 101 EBD2 C/BE1 33 100 VSS AD15 34 99 EBD3 VSS 35 98 VDDB AD14 36 97 EBD4 AD13 37 96 EBD5 VSSB 38 95 EBD6 AD12 39 94 VSSB AD11 40 93 EBD7 VDD_PCI 41 92 EBDA15 AD10 42 91 EBDA14 AD9 43 90 NC NC 44 89 NC NC 21485C-3 Pin 1 is marked for orientation. Am79C972 9 NC 45 176 NC NC 46 175 NC AD8 47 174 C/BE3 C/BE0 48 173 AD24 VSSB 49 172 AD25 AD7 50 171 VSSB VDD_PCI 51 170 AD26 AD6 52 169 VDD_PCI AD5 53 168 AD27 VDD 54 167 AD28 AD4 55 166 AD29 AD3 165 AD30 56 VSSB 164 VSS 57 AD2 163 VSSB 58 VDD_PCI 162 AD31 59 AD1 161 VDD_PCI 60 AD0 160 REQ 61 VSS 159 GNT 62 EROMCS 158 CLK 63 EBWE 157 RST 64 AS_EBOE 156 INTA 65 155 EBCLK PG 66 154 EBUA_EBA0 VDD 67 153 VSSB TDI 68 152 EBUA_EBA1 VSSB 69 151 VDD TDO 70 150 VDDB VDDB 71 149 EBUA_EBA2 TMS 72 148 EBUA_EBA3 TCK 73 147 EBUA_EBA4 RWU 74 146 EBUA_EBA5 75 WUMI 145 EBUA_EBA6 76 PME 144 EBUA_EBA7 77 VSS 143 VSS 78 EAR 142 EBDA8 79 EECS 141 VSSB 80 VSSB 140 EBDA9 81 EESK/LED1/SFBD 139 EBDA10 82 LED2/SRDCLK/MIIRXFRTGE 138 VDDB 83 VDDB 137 EBDA11 84 TBC_EN 136 EBDA12 85 TBC_IN 135 EBDA13 86 EEDI/LED0 134 NC 87 NC 133 NC 88 NC PIN DESIGNATIONS (PQR160) Listed By Pin Number Pin Pin Pin Pin Pin Pin Pin No. Name No. Name No. Name Pin No. Name 1 IDSEL 41 AD8 81 EBDA14 121 EEDI/LED0 2 AD23 42 C/BE0 82 EBDA15 122 TBC_IN 3 VSSB 43 VSSB 83 EBD7 123 TBC_EN 4 AD22 44 AD7 84 VSSB 124 VDDB LED2/SRDCLK/ 5 VDD_PCI 45 VDD_PCI 85 EBD6 125 MIIRXFRTGE 6 AD21 46 AD6 86 EBD5 126 EESK/LED1/SFBD 7 AD20 47 AD5 87 EBD4 127 VSSB 8 VDD 48 VDD 88 VDDB 128 EECS 9 AD19 49 AD4 89 EBD3 129 EAR 10 AD18 50 AD3 90 VSS 130 VSS 11 VSSB 51 VSSB 91 EBD2 131 PME 12 AD17 52 AD2 92 EBD1 132 WUMI 13 VDD_PCI 53 VDD_PCI 93 EBD0 133 RWU 14 AD16 54 AD1 94 CRS/RXEN 134 TCK 15 C/BE2 55 AD0 95 VSSB 135 TMS 16 VSS 56 VSS 96 COL/CLSN 136 VDDB 17 FRAME 57 EROMCS 97 TXD3 137 TDO 18 IRDY 58 EBWE 98 TXD2 138 VSSB 19 VSSB 59 AS_EBOE 99 TXD1 139 TDI 20 TRDY 60 EBCLK 100 VDD 140 VDD 21 VDD_PCI 61 EBUA_EBA0 101 VDDB 141 PG 22 DEVSEL 62 VSSB 102 TXD0/TXDAT 142 INTA 23 STOP 63 EBUA_EBA1 103 TX_EN/TXEN 143 RST 24 VDD 64 VDD 104 TX_CLK/TXCLK 144 CLK 25 PERR 65 VDDB 105 TX_ER 145 GNT 26 SERR 66 EBUA_EBA2 106 VSSB 146 REQ 27 VSSB 67 EBUA_EBA3 107 RX_ER/RXDAT 147 VDD_PCI 28 PAR 68 EBUA_EBA4 108 RX_CLK/RXCLK 148 AD31 29 VDD_PCI 69 EBUA_EBA5 109 RX_DV/RXFRTGE 149 VSSB 30 C/BE1 70 EBUA_EBA6 110 VSS 150 VSS 31 AD15 71 EBUA_EBA7 111 RXD0/RXFRTGD 151 AD30 32 VSS 72 VSS 112 RXD1 152 AD29 33 AD14 73 EBDA8 113 VDDB 153 AD28 34 AD13 74 VSSB 114 RXD2 154 AD27 35 VSSB 75 EBDA9 115 RXD3 155 VDD_PCI 36 AD12 76 EBDA10 116 MDC 156 AD26 37 AD11 77 VDDB 117 VSSB 157 VSSB 38 VDD_PCI 78 EBDA11 118 MDIO 158 AD25 39 AD10 79 EBDA12 119 PHY_RST 159 AD24 EEDO/LED3/SRD/ 40 AD9 80 EBDA13 120 160 C/BE3 MIIRXFRTGD 10 Am79C972 PIN DESIGNATIONS (PQL176) Listed By Pin Number Pin Pin Pin Pin Pin Pin Pin No. Name No. Name No. Name Pin No. Name 1 NC 45 NC 89 NC 133 NC 2 NC 46 NC 90 NC 134 NC 3 IDSEL 47 AD8 91 EBDA14 135 EEDI/LED0 4 AD23 48 C/BE0 92 EBDA15 136 TBC_IN 5 VSSB 49 VSSB 93 EBD7 137 TBC_EN 6 AD22 50 AD7 94 VSSB 138 VDDB LED2/SRDCLK/ 7 VDD_PCI 51 VDD_PCI 95 EBD6 139 MIIRXFRTGE 8 AD21 52 AD6 96 EBD5 140 EESK/LED1/SFBD 9 AD20 53 AD5 97 EBD4 141 VSSB 10 VDD 54 VDD 98 VDDB 142 EECS 11 AD19 55 AD4 99 EBD3 143 EAR 12 AD18 56 AD3 100 VSS 144 VSS 13 VSSB 57 VSSB 101 EBD2 145 PME 14 AD17 58 AD2 102 EBD1 146 WUMI 15 VDD_PCI 59 VDD_PCI 103 EBD0 147 RWU 16 AD16 60 AD1 104 CRS/RXEN 148 TCK 17 C/BE2 61 AD0 105 VSSB 149 TMS 18 VSS 62 VSS 106 COL/CLSN 150 VDDB 19 FRAME 63 EROMCS 107 TXD3 151 TDO 20 IRDY 64 EBWE 108 TXD2 152 VSSB 21 VSSB 65 AS_EBOE 109 TXD1 153 TDI 22 TRDY 66 EBCLK 110 VDD 154 VDD 23 VDD_PCI 67 EBUA_EBA0 111 VDDB 155 PG 24 DEVSEL 68 VSSB 112 TXD0/TXDAT 156 INTA 25 STOP 69 EBUA_EBA1 113 TX_EN/TXEN 157 RST 26 VDD 70 VDD 114 TX_CLK/TXCLK 158 CLK 27 PERR 71 VDDB 115 TX_ER 159 GNT 28 SERR 72 EBUA_EBA2 116 VSSB 160 REQ 29 VSSB 73 EBUA_EBA3 117 RX_ER/RXDAT 161 VDD_PCI 30 PAR 74 EBUA_EBA4 118 RX_CLK/RXCLK 162 AD31 31 VDD_PCI 75 EBUA_EBA5 119 RX_DV/RXFRTGE 163 VSSB 32 C/BE1 76 EBUA_EBA6 120 VSS 164 VSS 33 AD15 77 EBUA_EBA7 121 RXD0/RXFRTGD 165 AD30 34 VSS 78 VSS 122 RXD1 166 AD29 35 AD14 79 EBDA8 123 VDDB 167 AD28 36 AD13 80 VSSB 124 RXD2 168 AD27 37 VSSB 81 EBDA9 125 RXD3 169 VDD_PCI 38 AD12 82 EBDA10 126 MDC 170 AD26 39 AD11 83 VDDB 127 VSSB 171 VSSB 40 VDD_PCI 84 EBDA11 128 MDIO 172 AD25 41 AD10 85 EBDA12 129 PHY_RST 173 AD24 EEDO/LED3/SRD/ 42 AD9 86 EBDA13 130 174 C/BE3 MIIRXFRTGD 43 NC 87 NC 131 NC 175 NC 44 NC 88 NC 132 NC 176 NC Am79C972 11 PIN DESIGNATIONS (PQR160, PQL176) Listed By Group 1 Pin Name Pin Function Type No. of Pins PCI Bus Interface AD[31:0] Address/Data Bus IO 32 C/BE[3:0] Bus Command/Byte Enable IO 4 CLK Bus Clock I 1 DEVSEL Device Select IO 1 FRAME Cycle Frame IO 1 GNT Bus Grant I 1 IDSEL Initialization Device Select I 1 INTA Interrupt O 1 IRDY Initiator Ready IO 1 PAR Parity IO 1 PERR Parity Error IO 1 REQ Bus Request O 1 RST Reset I 1 SERR System Error IO 1 STOP Stop IO 1 TRDY Target Ready IO 1 Board Interface LED0 LED0 O 1 LED1 LED1 O 1 LED2 LED2 O 1 LED3 LED3 O 1 TBC_IN Test Pin I 1 TBC_EN Test Pin I 1 PHY_RST Reset to PHY O 1 EEPROM Interface EECS Serial EEPROM Chip Select O 1 EEDI Serial EEPROM Data In O 1 EEDO Serial EEPROM Data Out I 1 EESK Serial EEPROM Clock IO 1 Expansion ROM Interface AS_EBOE Address Strobe/Expansion Bus Output Enable O 1 EBCLK Expansion Bus Clock I 1 EBD[7:0] Expansion Bus Data [7:0] IO 8 EBDA[15:8] Expansion Bus Data/Address [15:8] IO 8 EBUA_EBA[7:0] Expansion Bus Upper Address /Expansion Bus Address [7:0] O 8 EBWE Expansion Bus Write Enable O 1 EROMCS Expansion Bus ROM Chip Select O 1 Note: 1. Not including test features. 12 Am79C972 PIN DESIGNATIONS Listed By Group 1 Pin Name Pin Function Type No. of Pins Media Independent Interface (MII) COL Collision I 1 CRS Carrier Sense I 1 MDC Management Data Clock O 1 MDIO Management Data I/O IO 1 RX_CLK Receive Clock I 1 RXD[3:0] Receive Data I 4 RX_DV Receive Data Valid I 1 RX_ER Receive Error I 1 TX_CLK Transmit Clock I 1 TXD[3:0] Transmit Data O 4 TX_EN Transmit Data Enable O 1 TX_ER Transmit Error O 1 General Purpose Serial Interface (GPSI) CLSN Collision I 1 RXCLK Receive Clock I 1 RXDAT Receive Data I 1 RXEN Receive Enable I 1 TXCLK Transmit Clock I 1 TXDAT Transmit Data O 1 TXEN Transmit Enable O 1 External Address Detection Interface (EADI) EAR External Address Reject Low I 1 SFBD Start Frame Byte Delimiter O 1 SRD Serial Receive Data O 1 SRDCLK Serial Receive Data Clock O 1 RXFRTGD Receive Frame Tag Data I 1 RXFRTGE Receive Frame Tag Enable I 1 MIIRXFRTGD MII Receive Frame Tag Data I 1 MIIRXFRTGE MII Receive Frame Tag Enable I 1 Power Management Interface RWU Remote Wake Up O 1 PME Power Management Event O 1 WUMI Wake-Up Mode Indication O 1 PG Power Good I 1 IEEE 1149.1 Test Access Port Interface (JTAG) TCK Test Clock I 1 TDI Test Data In I 1 TDO Test Data Out O 1 TMS Test Mode Select I 1 Power Supplies VDD Digital Power P 6 VSS Digital Ground P 8 VDDB I/O Buffer Power P 7 VSSB I/O Buffer Ground P 17 VDD_PCI PCI I/O Buffer Power P 9 Note: 1. Not including test features. Am79C972 13 A sustained tri-state signal is a low active signal that is Listed By Driver Type driven high for one clock period before it is left floating. The following table describes the various types of out- put drivers used in the Am79C972 controller. All I and OL I values shown in the table apply to 3.3 V signaling. OH Name Type I (mA) I (mA) Load (pF) OL OH LED LED 12 -0.4 50 OMII1 Totem Pole 4 -4 50 OMII2 Totem Pole 4 -4 390 O6 Totem Pole 6 -0.4 50 OD6 Open Drain 6 NA 50 STS6 Sustained Tri-State 6 -2 50 TS3 Tri-State 3 -2 50 TS6 Tri-State 6 -2 50 TSMII Tri-State 4 -4 470 14 Am79C972 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79C972B K\V C/I \W ALTERNATE PACKAGING OPTION \W = Trimmed and formed in a tray TEMPERATURE RANGE C = Commercial (0° C to +70° C) I = Industrial (-40° C to +85° C) PACKAGE TYPE K = Plastic Quad Flat Pack (PQR160) V = Thin Quad Flat Pack (PQL176) SPEED OPTION Not applicable DEVICE NUMBER/DESCRIPTION Am79C972B PCnet-FAST+ Enhanced 10/100 Mbps PCI Ether- net Controller with OnNow Support Valid Combinations Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Am79C972B KC\W, AMD sales office to confirm availability of specific VC\W valid combinations and to check on newly released combinations. Am79C972B KI\W, VI\W Am79C972 15 eration section for details. The Am79C972 controller PIN DESCRIPTIONS will support a clock frequency of 0 MHz after certain PCI Interface precautions are taken to ensure data integrity. This clock or a derivation is not used to drive any network AD[31:0] functions. Address and Data Input/Output When RST is active, CLK is an input for NAND tree Address and data are multiplexed on the same bus in- testing. terface pins. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During DEVSEL the subsequent clocks, AD[31:0] contain data. Byte or- Device Select Input/Output dering is little endian by default. AD[7:0] are defined as the least significant byte (LSB) and AD[31:24] are de- The Am79C972 controller drives DEVSEL when it de- fined as the most significant byte (MSB). For FIFO data tects a transaction that selects the device as a target. transfers, the Am79C972 controller can be pro- The device samples DEVSEL to detect if a target grammed for big endian byte ordering. See CSR3, bit 2 claims a transaction that the Am79C972 controller has (BSWP) for more details. initiated. During the address phase of the transaction, when the When RST is active, DEVSEL is an input for NAND tree Am79C972 controller is a bus master, AD[31:2] will ad- testing. dress the active Double Word (DWord). The FRAME Am79C972 controller always drives AD[1:0] to ’00’ dur- ing the address phase indicating linear burst order. Cycle Frame Input/Output When the Am79C972 controller is not a bus master, the FRAME is driven by the Am79C972 controller when it AD[31:0] lines are continuously monitored to determine is the bus master to indicate the beginning and duration if an address match exists for slave transfers. of a transaction. FRAME is asserted to indicate a bus transaction is beginning. FRAME is asserted while During the data phase of the transaction, AD[31:0] are data transfers continue. FRAME is deasserted before driven by the Am79C972 controller when performing the final data phase of a transaction. When the bus master write and slave read operations. Data on Am79C972 controller is in slave mode, it samples AD[31:0] is latched by the Am79C972 controller when FRAME to determine the address phase of a transac- performing bus master read and slave write operations. tion. When RST is active, AD[31:0] are inputs for NAND tree When RST is active, FRAME is an input for NAND tree testing. testing. C/BE[3:0] GNT Bus Command and Byte Enables Input/Output Bus Grant Input Bus command and byte enables are multiplexed on the This signal indicates that the access to the bus has same bus interface pins. During the address phase of been granted to the Am79C972 controller. the transaction, C/BE[3:0] define the bus command. During the data phase, C/BE[3:0] are used as byte en- The Am79C972 controller supports bus parking. When ables. The byte enables define which physical byte the PCI bus is idle and the system arbiter asserts GNT lanes carry meaningful data. C/BE0 applies to byte 0 without an active REQ from the Am79C972 controller, (AD[7:0]) and C/BE3 applies to byte 3 (AD[31:24]). The the device will drive the AD[31:0], C/BE[3:0] and PAR function of the byte enables is independent of the byte lines. ordering mode (BSWP, CSR3, bit 2). When RST is active, GNT is an input for NAND tree When RST is active, C/BE[3:0] are inputs for NAND testing. tree testing. IDSEL CLK Initialization Device Select Input Clock Input This signal is used as a chip select for the Am79C972 This clock is used to drive the system bus interface and controller during configuration read and write transac- the internal buffer management unit. All bus signals are tions. sampled on the rising edge of CLK and all parameters When RST is active, IDSEL is an input for NAND tree are defined with respect to this edge. The Am79C972 testing. controller normally operates over a frequency range of 10 to 33 MHz on the PCI bus due to networking de- mands. See the Frequency Demands for Network Op- 16 Am79C972 . INTA Table 1. Interrupt Flags Interrupt Request Output An attention signal which indicates that one or more of Name Description Mask Bit Interrupt Bit the following status flags is set: EXDINT, IDON, MERR, Excessive EXDINT CSR5, bit 6 CSR5, bit 7 MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT, Deferral TXSTRT, UINT, MCCINT, MPDTINT, MAPINT, MRE- Initialization IDON CSR3, bit 8 CSR0, bit 8 INT, and STINT. Each status flag has either a mask or Done an enable bit which allows for suppression of INTA as- MERR Memory Error CSR3, bit 11 CSR0, bit 11 sertion. Table 1 shows the flag descriptions. By default MISS Missed Frame CSR3, bit 12 CSR0, bit 12 INTA is an open-drain output. For applications that Missed Frame need a high-active edge-sensitive interrupt signal, the MFCO Count Over- CSR4, bit 8 CSR4, bit 9 INTA pin can be configured for this mode by setting IN- flow TLEVEL (BCR2, bit 7) to 1. Magic Packet MPINT CSR5, bit 3 CSR5, bit 4 When RST is active, INTA is the output for NAND tree Interrupt testing. Receive RCVCCO Collision Count CSR4, bit 4 CSR4, bit 5 IRDY Overflow Initiator Ready Input/Output Receive RINT CSR3, bit 10 CSR0, bit 10 Interrupt IRDY indicates the ability of the initiator of the transac- tion to complete the current data phase. IRDY is used SINT System Error CSR5, bit 10 CSR5, bit 11 in conjunction with TRDY. Wait states are inserted until Transmit TINT CSR3, bit 9 CSR0, bit 9 both IRDY and TRDY are asserted simultaneously. A Interrupt data phase is completed on any clock when both IRDY TXSTRT Transmit Start CSR4, bit 2 CSR4, bit 3 and TRDY are asserted. UINT User Interrupt CSR4, bit 7 CSR4, bit 6 When the Am79C972 controller is a bus master, it as- MII serts IRDY during all write data phases to indicate that Management valid data is present on AD[31:0]. During all read data MCCINT Command CSR7, bit 4 CSR7, bit 5 Complete phases, the device asserts IRDY to indicate that it is Interrupt ready to accept the data. MII PHY Detect When the Am79C972 controller is the target of a trans- MPDTINT Transition CSR7, bit 0 CSR7, bit 1 action, it checks IRDY during all write data phases to Interrupt determine if valid data is present on AD[31:0]. During MII Auto-Poll all read data phases, the device checks IRDY to deter- MAPINT CSR7, bit 6 CSR7, bit 7 Interrupt mine if the initiator is ready to accept the data. MII When RST is active, IRDY is an input for NAND tree Management MREINT CSR7, bit 8 CSR7, bit 9 Frame Read testing. Error Interrupt PAR Software Timer STINT CSR7, bit 10 CSR7, bit 11 Interrupt Parity Input/Output Parity is even parity across AD[31:0] and C/BE[3:0]. PERR When the Am79C972 controller is a bus master, it gen- Parity Error Input/Output erates parity during the address and write data phases. It checks parity during read data phases. When the During any slave write transaction and any master read Am79C972 controller operates in slave mode, it checks transaction, the Am79C972 controller asserts PERR parity during every address phase. When it is the target when it detects a data parity error and reporting of the of a cycle, it checks parity during write data phases and error is enabled by setting PERREN (PCI Command it generates parity during read data phases. register, bit 6) to 1. During any master write transaction, the Am79C972 controller monitors PERR to see if the When RST is active, PAR is an input for NAND tree target reports a data parity error. testing. When RST is active, PERR is an input for NAND tree testing. Am79C972 17 taneously. A data phase is completed on any clock REQ when both IRDY and TRDY are asserted. Bus Request Input/Output When the Am79C972 controller is a bus master, it The Am79C972 controller asserts REQ pin as a signal checks TRDY during all read data phases to determine that it wishes to become a bus master. REQ is driven if valid data is present on AD[31:0]. During all write data high when the Am79C972 controller does not request phases, the device checks TRDY to determine if the the bus. In Power Management mode, the REQ pin will target is ready to accept the data. not be driven. When the Am79C972 controller is the target of a trans- When RST is active, REQ is an input for NAND tree action, it asserts TRDY during all read data phases to testing. indicate that valid data is present on AD[31:0]. During RST all write data phases, the device asserts TRDY to indi- cate that it is ready to accept the data. Reset Input When RST is asserted LOW and the PG pin is HIGH, When RST is active, TRDY is an input for NAND tree then the Am79C972 controller performs an internal testing. system reset of the type H_RESET PME (HARDWARE_RESET, see section on RESET). RST must be held for a minimum of 30 clock periods. While Power Management Event Output, Open Drain in the H_RESET state, the Am79C972 controller will PME is an output that can be used to indicate that a disable or deassert all outputs. RST may be asynchro- power management event (a Magic Packet, an OnNow nous to clock when asserted or deasserted. pattern match, or a change in link state) has been de- tected. The PME pin is asserted when either When the PG pin is LOW, RST disables all of the PCI pins except the PME pin. 1. PME_STATUS and PME_EN are both 1, When RST is LOW and PG is HIGH, NAND tree testing 2. PME_EN_OVR and MPMAT are both 1, or is enabled. 3. PME_EN_OVR and LCDET are both 1. SERR The PME signal is asynchronous with respect to the PCI clock. System Error Output During any slave transaction, the Am79C972 controller Board Interface asserts SERR when it detects an address parity error, Note: Before programming the LED pins, see the and reporting of the error is enabled by setting PER- description of LEDPE in BCR2, bit 12. REN (PCI Command register, bit 6) and SERREN (PCI Command register, bit 8) to 1. LED0 By default SERR is an open-drain output. For compo- LED0 Output nent test, it can be programmed to be an active-high This output is designed to directly drive an LED. By de- totem-pole output. fault, LED0 indicates an active link connection. This pin can also be programmed to indicate other network sta- When RST is active, SERR is an input for NAND tree tus (see BCR4). The LED0 pin polarity is programma- testing. ble, but by default it is active LOW. When the LED0 pin STOP polarity is programmed to active LOW, the output is an open drain driver. When the LED0 pin polarity is pro- Stop Input/Output grammed to active HIGH, the output is a totem pole In slave mode, the Am79C972 controller drives the driver. STOP signal to inform the bus master to stop the cur- rent transaction. In bus master mode, the Am79C972 Note: The LED0 pin is multiplexed with the EEDI pin. controller checks STOP to determine if the target wants LED1 to disconnect the current transaction. LED1 Output When RST is active, STOP is an input for NAND tree This output is designed to directly drive an LED. By de- testing. fault, LED1 indicates receive activity on the network. This pin can also be programmed to indicate other net- TRDY work status (see BCR5). The LED1 pin polarity is pro- Target Ready Input/Output grammable, but by default, it is active LOW. When the TRDY indicates the ability of the target of the transac- LED1 pin polarity is programmed to active LOW, the tion to complete the current data phase. Wait states are output is an open drain driver. When the LED1 pin po- inserted until both IRDY and TRDY are asserted simul- 18 Am79C972 larity is programmed to active HIGH, the output is a If no EEPROM is included in the system design or low totem pole driver. current LEDs are used, then the LED3 signal may be directly connected to an LED without buffering. For Note: The LED1 pin is multiplexed with the EESK and more details regarding LED connection, see the sec- SFBD pins. tion on LED Support. The LED1 pin is also used during EEPROM Auto- Note: The LED3 pin is multiplexed with the EEDO, Detection to determine whether or not an EEPROM is SRD, MIIRXFRTGD pins. present at the Am79C972 controller interface. At the last rising edge of CLK while RST is active LOW, LED1 PG is sampled to determine the value of the EEDET bit in Power Good Input BCR19. It is important to maintain adequate hold time The PG pin has two functions: (1) it puts the device into around the rising edge of the CLK at this time to ensure Magic Packet™ mode, and (2) it blocks any resets a correctly sampled value. A sampled HIGH value when the PCI bus power is off. means that an EEPROM is present, and EEDET will be set to 1. A sampled LOW value means that an EE- When PG is LOW and either MPPEN or MPMODE is PROM is not present, and EEDET will be set to 0. See set to 1, the device enters the Magic Packet mode. the EEPROM Auto-Detection section for more details. When PG is LOW, a LOW assertion of the PCI RST pin If no LED circuit is to be attached to this pin, then a pull will only cause the PCI interface pins (except for PME) up or pull down resistor must be attached instead in to be put in the high impedance state. The internal logic order to resolve the EEDET setting. will ignore the assertion of RST. WARNING: The input signal level of LED1 must be When PG is HIGH, assertion of the PCI RST pin insured for correct EEPROM detection before the causes the controller logic to be reset and the configu- deassertion of RST. ration information to be loaded from the EEPROM. LED2 PG input should be kept high during the NAND tree testing. LED2 Output RWU This output is designed to directly drive an LED. This pin can be programmed to indicate various network Remote Wake Up Output status (see BCR6). The LED2 pin polarity is program- RWU is an output that is asserted either when the con- mable, but by default it is active LOW. When the LED2 troller is in the Magic Packet mode and a Magic Packet pin polarity is programmed to active LOW, the output is frame has been detected, or the controller is in the Link an open drain driver. When the LED2 pin polarity is pro- Change Detect mode and a Link Change has been de- grammed to active HIGH, the output is a totem pole tected. driver. This pin can drive the external system management Note: The LED2 pin is multiplexed with the SRDCLK logic that causes the CPU to get out of a low power pin and the MIIRXFRTGE pins. mode of operation. This pin is implemented for designs LED3 that do not support the PME function. LED3 Output Three bits that are loaded from the EEPROM into CSR116 can program the characteristics of this pin: This output is designed to directly drive an LED. By de- fault, LED3 indicates transmit activity on the network. 1. RWU_POL determines the polarity of the RWU sig- This pin can also be programmed to indicate other net- nal. work status (see BCR7). The LED3 pin polarity is pro- 2. If RWU_GATE bit is set, RWU is forced to the high grammable, but by default it is active LOW. When the impedance state when PG input is LOW. LED3 pin polarity is programmed to active LOW, the output is an open drain driver. When the LED3 pin po- 3. RWU_DRIVER determines whether the output is larity is programmed to active HIGH, the output is a open drain or totem pole. totem pole driver. The internal power-on-reset signal forces this output Special attention must be given to the external circuitry into the high impedance state until after the polarity and attached to this pin. When this pin is used to drive an drive type have been determined. LED while an EEPROM is used in the system, then WUMI buffering maybe required between the LED3 pin and the LED circuit. If an LED circuit were directly attached Wake-Up Mode Indicator Output to this pin, it may create an IOL requirement that could This output, which is capable of driving an LED, is as- not be met by the serial EEPROM attached to this pin. serted when the device is in Magic Packet mode. It can Am79C972 19 be used to drive external logic that switches the device during command portions of a read of the entire power source from the main power supply to an auxil- EEPROM, or indirectly by the host system by writing to iary power supply. BCR19, bit 0. Note: The EEDI pin is multiplexed with the LED0 pin. TBC_EN Time Base Clock Enable Input EEDO TBC_EN is an input that controls the selection of the EEPROM Data Out Input source of the Time Base Clock. The Time Base Clock This pin is designed to directly interface to a serial is used in loading the EEPROM, generation of the EEPROM that uses the 93C46 EEPROM interface pro- PHY_RST, and the timing of the MDC and MDIO sig- tocol. EEDO is connected to the EEPROM’s data out- nals. When the input to this pin is LOW, an internal free put pin. It is controlled by either the Am79C972 running oscillator with a maximum frequency of 20 controller during command portions of a read of the en- MHz is used. When the input to this pin is HIGH, the tire EEPROM, or indirectly by the host system by read- TBC_IN pin input is used to inject externally generated ing from BCR19, bit 0. clock into the device. For typical applications which will Note: The EEDO pin is multiplexed with the LED3, use the internal oscillation, this pin should be tied to MIIRXFRTGD, and SRD pins. ground. EESK When RST is active, TBC_EN is an input for NAND tree testing. EEPROM Serial Clock Input/Output This pin is designed to directly interface to a serial TBC_IN EEPROM that uses the 93C46 EEPROM interface pro- Time Base Clock Input Input tocol. EESK is connected to the EEPROM’s clock pin. TBC_IN may be used to connect to an external clock It is controlled by either the Am79C972 controller di- source to drive the internal circuitry that loads the rectly during a read of the entire EEPROM, or indirectly EEPROM and controls the MDC and MDIO signals. by the host system by writing to BCR19, bit 1. This input is selected when the TBC_EN pin is HIGH. Note: The EESK pin is multiplexed with the LED1 and This pin should be tied to ground when the TBC_EN pin SFBD pins. is LOW. The EESK pin is also used during EEPROM Auto- PHY_RST Detection to determine whether or not an EEPROM is PHY Reset Output present at the Am79C972 controller interface. At the rising edge of the last CLK edge while RST is asserted, PHY_RST is an output pin that is used to reset the ex- EESK is sampled to determine the value of the EEDET ternal PHY. This output eliminates the need for a fan bit in BCR19. A sampled HIGH value means that an out buffer for the PCI RST signal, provides polarity for EEPROM is present, and EEDET will be set to 1. A the specific PHY used, and prevents the resetting of sampled LOW value means that an EEPROM is not the PHY when the PG input is LOW. The output polarity present, and EEDET will be set to 0. See the EEPROM is determined by the RST_POL bit(CSR116, bit0). Auto-Detection section for more details. EEPROM Interface If no LED circuit is to be attached to this pin, then a pull EECS up or pull down resistor must be attached instead to re- solve the EEDET setting. EEPROM Chip Select Output This pin is designed to directly interface to a serial EE- WARNING: The input signal level of EESK must be PROM that uses the 93C46 EEPROM interface proto- valid for correct EEPROM detection before the col. EECS is connected to the EEPROM’s chip select deassertion of RST. pin. It is controlled by either the Am79C972 controller Expansion Bus Interface during command portions of a read of the entire EE- PROM, or indirectly by the host system by writing to EBUA_EBA[7:0] BCR19, bit 2. Expansion Bus Upper Address/ Expansion Bus Address [7:0] Output EEDI The EBUA_EBA[7:0] pins provide the least and most EEPROM Data In Output significant bytes of address on the Expansion Bus. The This pin is designed to directly interface to a serial most significant address byte (address bits [19:16] dur- EEPROM that uses the 93C46 EEPROM interface pro- ing boot device accesses) is valid on these pins at the tocol. EEDI is connected to the EEPROM’s data input beginning of a boot device access, at the rising edge of pin. It is controlled by either the Am79C972 controller AS_EBOE. This upper address byte must be stored ex- 20 Am79C972 ternally in a D flip-flop. During subsequent cycles of a Bus cycles depends on the values of the EBCS and boot device access, address bits [7:0] are present on CLK_FAC settings in BCR27. Refer to the SRAM Inter- these pins. face Bandwidth Requirements section for details on de- termining the required EBCLK frequency. If a clock All EBUA_EBA[7:0] outputs are forced to a constant source other than the EBCLK pin is programmed level to conserve power while no access on the Expan- (BCR27, bits 5:3) to be used to run the Expansion Bus sion Bus is being performed. interface, this input should be tied to VDD through a 4.7 kΩ resistor. EBDA[15:8] Expansion Bus Data/Address [15:8] Input/Output EBCLK is not used to drive the bus interface, internal buffer management unit, or the network functions. When EROMCS is asserted low, EBDA[15:8] contain address bits [15:8] for boot device accesses. Media Independent Interface The EBDA[15:8] signals are driven to a constant level TX_CLK to conserve power while no access on the Expansion Transmit Clock Input Bus is being performed. TX_CLK is a continuous clock input that provides the EBD[7:0] timing reference for the transfer of the TX_EN, Expansion Bus Data [7:0] Input/Output TXD[3:0], and TX_ER signals out of the Am79C972 device. TX_CLK must provide a nibble rate clock (25% The EBD[7:0] pins provide data bits [7:0] for EPROM/ of the network data rate). Hence, an MII transceiver op- FLASH accesses. The EBD[7:0] signals are internally erating at 10 Mbps must provide a TX_CLK frequency forced to a constant level to conserve power while no of 2.5 MHz and an MII transceiver operating at 100 access on the Expansion Bus is being performed. Mbps must provide a TX_CLK frequency of 25 MHz. EROMCS Note: The TX_CLK pin is multiplexed with the TXCLK Expansion ROM Chip Select Output pin. EROMCS serves as the chip select for the boot device. TXD[3:0] It is asserted low during the data phases of boot device Transmit Data Output accesses. TXD[3:0] is the nibble-wide MII transmit data bus. Valid AS_EBOE data is generated on TXD[3:0] on every TX_CLK rising Address Strobe/Expansion Bus edge while TX_EN is asserted. While TX_EN is de- Output Enable Output asserted, TXD[3:0] values are driven to a 0. TXD[3:0] transitions synchronous to TX_CLK rising edges. AS_EBOE functions as the address strobe for the upper address bits on the EBUA_EBA[7:0] pins and as Note: The TXD[0] pin is multiplexed with the TXD pin. the output enable for the Expansion Bus. TX_EN As an address strobe, a rising edge on AS_EBOE is Transmit Enable Output supplied at the beginning of boot device accesses. This rising edge provides a clock edge for a ‘374 D-type TX_EN indicates when the Am79C972 device is pre- edge-triggered flip-flop which must store the upper ad- senting valid transmit nibbles on the MII. While TX_EN dress byte during Expansion Bus accesses for is asserted, the Am79C972 device generates TXD[3:0] EPROM/Flash. and TX_ER on TX_CLK rising edges. TX_EN is as- serted with the first nibble of preamble and remains as- AS_EBOE is asserted active LOW during boot device serted throughout the duration of a packet until it is read operations on the expansion bus and is deas- deasserted prior to the first TX_CLK following the final serted during boot device write operations. nibble of the frame. TX_EN transitions synchronous to TX_CLK rising edges. EBWE Expansion Bus Write Enable Output Note: The TX_EN pin is multiplexed with the TXEN pin. EBWE provides the write enable for write accesses to the Flash device. TX_ER EBCLK Transmit Error Output TX_ER is an output that, if asserted while TX_EN is as- Expansion Bus Clock Input serted, instructs the MII PHY device connected to the EBCLK may be used as the fundamental clock to drive Am79C972 device to transmit a code group error. the Expansion Bus and internal SRAM access cycles. TX_ER is unused and is reserved for future use and will The actual internal clock used to drive the Expansion always be driven to a logical zero. Am79C972 21 rising edge which follows this final nibble. RX_DV tran- COL sitions are synchronous to RX_CLK rising edges. Collision Input Note: The RX_DV pin is multiplexed with the COL is an input that indicates that a collision has been RXFRTGE pin. detected on the network medium. If the MII port is not selected, the RX_DV pin can be left Note: The COL pin is multiplexed with the CLSN pin. floating. CRS RX_ER Carrier Sense Input Receive Error Input CRS is an input that indicates that a non-idle medium, RX_ER is an input that indicates that the MII trans- due either to transmit or receive activity, has been de- ceiver device has detected a coding error in the receive tected. frame currently being transferred on the RXD[3:0] pins. Note: The CRS pin is multiplexed with the RXEN pin. When RX_ER is asserted while RX_DV is asserted, a CRC error will be indicated in the receive descriptor for RX_CLK the incoming receive frame. RX_ER is ignored while Receive Clock Input RX_DV is deasserted. Special code groups generated RX_CLK is a clock input that provides the timing refer- on RXD while RX_DV is deasserted are ignored (e.g., ence for the transfer of the RX_DV, RXD[3:0], and Bad SSD in TX and IDLE in T4). RX_ER transitions are RX_ER signals into the Am79C972 device. RX_CLK synchronous to RX_CLK rising edges. must provide a nibble rate clock (25% of the network Note: The RX_ER pin is multiplexed with the RXDAT data rate). Hence, an MII transceiver operating at 10 pin. Mbps must provide an RX_CLK frequency of 2.5 MHz and an MII transceiver operating at 100 Mbps must pro- MDC vide an RX_CLK frequency of 25 MHz. When the exter- Management Data Clock Output nal PHY switches the RX_CLK and TX_CLK, it must MDC is a non-continuous clock output that provides a provide glitch-free clock pulses. timing reference for bits on the MDIO pin. During MII Note: The RX_CLK pin is multiplexed with the RXCLK management port operations, MDC runs at a nominal pin. frequency of 2.5 MHz. When no management opera- tions are in progress, MDC is driven LOW. The MDC is RXD[3:0] derived from the Time Base Clock. Receive Data Input If the MII port is not selected, the MDC pin can be left RXD[3:0] is the nibble-wide MII receive data bus. Data floating. on RXD[3:0] is sampled on every rising edge of RX_CLK while RX_DV is asserted. RXD[3:0] is ignored MDIO while RX_DV is de-asserted. Management Data I/O Input/Output Note: The RXD[0] pin is multiplexed with the MDIO is the bidirectional MII management port data RXFRTGD pin. pin. MDIO is an output during the header portion of the If the MII port is not selected, the RXD[3:0] pin can be management frame transfers and during the data por- left floating. tions of write transfers. MDIO is an input during the data portions of read data transfers. When an operation RX_DV is not in progress on the management port, MDIO is not Receive Data Valid Input driven. MDIO transitions from the Am79C972 controller are synchronous to MDC falling edges. RX_DV is an input used to indicate that valid received data is being presented on the RXD[3:0] pins and If the PHY is attached through an MII physical connec- RX_CLK is synchronous to the receive data. In order tor, then the MDIO pin should be externally pulled down for a frame to be fully received by the Am79C972 de- to VSS with a 10-kΩ ±5% resistor. If the PHY is on vice on the MII, RX_DV must be asserted prior to the board, then the MDIO pin should be externally pulled RX_CLK rising edge, when the first nibble of the Start up to VCC with a 10-kΩ ±5% resistor. of Frame Delimiter is driven on RXD[3:0], and must re- main asserted until after the rising edge of RX_CLK, when the last nibble of the CRC is driven on RXD[3:0]. RX_DV must then be deasserted prior to the RX_CLK 22 Am79C972 Note: The TXEN pin is multiplexed with the TX_EN General Purpose Serial Interface pin. CLSN External Address Detection Interface Collision Input EAR CLSN is an input that indicates a collision has occurred on the network. External Address Reject Low Input The incoming frame will be checked against the inter- Note: The CLSN pin is multiplexed with the COL pin. nally active address detection mechanisms and the re- RXCLK sult of this check will be OR’d with the value on the EAR Receive Clock Input pin. The EAR pin is defined as REJECT. The pin value is OR’d with the internal address detection result to de- RXCLK is an input. The rising edges of the RXCLK sig- termine if the current frame should be accepted or re- nal are used to sample the data on the RXDAT input jected. whenever the RXEN input is HIGH. The EAR pin must not be left unconnected, it should Note: The RXCLK pin is multiplexed with the RX_CLK be tied to VDD through a 10-kΩ ±5% resistor. pin. When RST is active, EAR is an input for NAND tree RXDAT testing. Receive Data Input SFBD RXDAT is an input. The rising edges of the RXCLK sig- nal are used to sample the data on the RXDAT input Start Frame-Byte Delimiter Output whenever the RXEN input is HIGH. For the GPSI port during External Address Detec- tion: Note: The RXDAT pin is multiplexed with the RX_ER pin. An initial rising edge on the SFBD signal indicates that RXEN a start of frame delimiter has been detected. The serial bit stream will follow on the SRD signal, commencing Receive Enable Input with the destination address field. SFBD will go high for RXEN is an input. When this signal is HIGH, it indicates 4 bit times (400 ns when operating at 10 Mbps) after to the core logic that the data on the RXDAT input pin detecting the second “1” in the SFD (Start of Frame De- is valid. limiter) of a received frame. SFBD will subsequently toggle every 4 bit times (1.25 MHz frequency when op- Note: The RXEN pin is multiplexed with the CRS pin. erating at 10 Mbps) with each rising edge indicating the TXCLK first bit of each subsequent byte of the received serial Transmit Clock Input bit stream. TXCLK is an input that provides a clock signal for MAC For the External PHY attached to the Media Inde- activity, both transmit and receive. The rising edges of pendent Interface during External Address Detec- the TXCLK can be used to validate TXDAT output data. tion: Note: The TXCLK pin is multiplexed with the TX_CLK An initial rising edge on the SFBD signal indicates that pin. a start of valid data is present on the RXD[3:0] pins. SFBD will go high for one nibble time (400 ns when op- TXDAT erating at 10 Mbps and 40 ns when operating at 100 Transmit Data Output Mbps) one RX_CLK period after RX_DV has been as- TXDAT is an output that provides the serial bit stream serted and RX_ER is deasserted and the detection of for transmission, including preamble, SFD, data, and the SFD (Start of Frame Delimiter) of a received frame. FCS field, if applicable. Data on the RXD[3:0] will be the start of the destination address field. SFBD will subsequently toggle every nib- Note: The TXDAT pin is multiplexed with the TXD[0] ble time (1.25 MHz frequency when operating at 10 pin. Mbps and 12.5 MHz frequency when operating at 100 TXEN Mbps) indicating the first nibble of each subsequent byte of the received nibble stream. The RX_CLK Transmit Enable Output should be used in conjunction with the SFBD to latch TXEN is an output that provides an enable signal for the correct data for external address matching. SFBD transmission. Data on the TXDAT pin is not valid unless will be active only during frame reception. the TXEN signal is HIGH. Note: The SFBD pin is multiplexed with the EESK and LED1 pins. Am79C972 23 SRD MIIRXFRTGD Serial Receive Data Input/Output MII Receive Frame Tag Enable Input SRD is the decoded NRZ data from the network when When the EADI is enabled (EADISEL, BCR2, bit 3), the in GPSI mode. This signal can be used for external ad- Receive Frame Tagging is enabled (RXFRTG, CSR7, dress detection. bit 14), and the MII is selected, the MIIRXFRTGD pin becomes a data input pin for the Receive Frame Tag. Note: When the MII port is selected, SRD will not gen- See the Receive Frame Tagging section for details. erate transitions and receive data must be derived from the Media Independent Interface RXD[3:0] pins. Note: The MIIRXFRTGD pin is multiplexed with the SRD, EEDO, and LED3 pins. Note also that the SRD pin is multiplexed with the MIIRXFRTGD, EEDO, and LED3 pins. MIIRXFRTGE MII Receive Frame Tag Enable Input SRDCLK When the EADI is enabled (EADISEL, BCR2, bit 3), the Serial Receive Data Clock Output Receive Frame Tagging is enabled (RXFRTG, CSR7, Serial Receive Data is synchronous with reference to bit 14), and the MII is selected, the MIIRXFRTGE pin SRDCLK. becomes a data input enable pin for the Receive Frame Note: When the MII port is selected, SRDCLK will not Tag. See the Receive Frame Tagging section for de- generate transitions and the receive clock must be de- tails. rived from the MII RX_CLK pin. Note: The MIIRXFRTGE pin is multiplexed with the Note also that the SRDCLK pin is multiplexed with the SRDCLK and LED2 pins. MIIRXFRTGE and LED2 pins. IEEE 1149.1 (1990) Test Access Port RXFRTGD Interface Receive Frame Tag Data Input TCK When the EADI is enabled (EADISEL, BCR2, bit 3), the Test Clock Input Receive Frame Tagging is enabled (RXFRTG, CSR7, TCK is the clock input for the boundary scan test mode bit 14), and the MII is not selected, the RXFRTGD pin operation. It can operate at a frequency of up to 10 becomes a data input pin for the Receive Frame Tag. MHz. TCK has an internal pull up resistor. See the Receive Frame Tagging section for details. TDI Note: The RXFRTGD pin is multiplexed with the RXD[0] pin. Test Data In Input RXFRTGE TDI is the test data input path to the Am79C972 con- troller. The pin has an internal pull up resistor. Receive Frame Tag Enable Input TDO When the EADI is enabled (EADISEL, BCR2, bit 3), the Receive Frame Tagging is enabled (RXFRTG, CSR7, Test Data Out Output bit 14), and the MII is not selected, the RXFRTGE pin TDO is the test data output path from the Am79C972 becomes a data input enable pin for the Receive Frame controller. The pin is tri-stated when the JTAG port is in- Tag. See the Receive Frame Tagging section for de- active. tails. TMS Note: The RXFRTGE pin is multiplexed with the RX_DV pin. Test Mode Select Input A serial input bit stream on the TMS pin is used to de- fine the specific boundary scan test to be executed. The pin has an internal pull up resistor. 24 Am79C972 Power Supply Pins VSSB I/O Buffer Ground (17 Pins) Power VDDB There are 17 ground pins that are used by the input/ I/O Buffer Power (7 Pins) Power output buffer drivers. There are seven power supply pins that are used by the input/output buffer drivers. All VDDB pins must be con- VDD nected to a +3.3 V supply. Digital Power (6 Pins) Power VDD_PCI There are six power supply pins that are used by the in- ternal digital circuitry. All VDD pins must be connected PCI I/O Buffer Power (9 Pins) Power to a +3.3 V supply. There are nine power supply pins that are used by the PCI input/output buffer drivers (except PME driver). All VSS VDD_PCI pins must be connected to a +3.3 V supply. Digital Ground (8 Pins) Power There are eight ground pins that are used by the inter- nal digital circuitry. Am79C972 25 or memory space (memory mapped I/O). The I/O Base BASIC FUNCTIONS Address Register in the PCI Configuration Space con- System Bus Interface trols the start address of the address space if it is The Am79C972 controller is designed to operate as a mapped to I/O space. The Memory Mapped I/O Base bus master during normal operations. Some slave I/O Address Register controls the start address of the ad- accesses to the Am79C972 controller are required in dress space if it is mapped to memory space. The 32- normal operations as well. Initialization of the byte address space is used by the software to program Am79C972 controller is achieved through a combina- the Am79C972 controller operating mode, to enable tion of PCI Configuration Space accesses, bus slave and disable various features, to monitor operating sta- accesses, bus master accesses, and an optional read tus, and to request particular functions to be executed of a serial EEPROM that is performed by the by the Am79C972 controller. Am79C972 controller. The EEPROM read operation is The third portion of the software interface is the de- performed through the 93C46 EEPROM interface. The scriptor and buffer areas that are shared between the ISO 8802-3 (IEEE/ANSI 802.3) Ethernet Address may software and the Am79C972 controller during normal reside within the serial EEPROM. Some Am79C972 network operations. The descriptor area boundaries controller configuration registers may also be pro- are set by the software and do not change during nor- grammed by the EEPROM read operation. mal network operations. There is one descriptor area The Address PROM, on-chip board-configuration reg- for receive activity and there is a separate area for isters, and the Ethernet controller registers occupy 32 transmit activity. The descriptor space contains relocat- bytes of address space. I/O and memory mapped I/O able pointers to the network frame data, and it is used accesses are supported. Base Address registers in the to transfer frame status from the Am79C972 controller PCI configuration space allow locating the address to the software. The buffer areas are locations that hold space on a wide variety of starting addresses. frame data for transmission or that accept frame data that has been received. For diskless stations, the Am79C972 controller sup- ports a ROM or Flash-based (both referred to as the Network Interfaces Expansion ROM throughout this specification) boot de- The Am79C972 controller can be connected to an vice of up to 1 Mbyte in size. The host can map the boot IEEE 802.3 or proprietary network via one of two net- device to any memory address that aligns to a 1-Mbyte work interfaces. The Media Independent Interface (MII) boundary by modifying the Expansion ROM Base Ad- provides an IEEE 802.3-compliant nibble-wide inter- dress register in the PCI configuration space. face to an external 100- and/or 10-Mbps transceiver device. The General Purpose Serial Interface (GPSI) is Software Interface functionally equivalent to the GPSI found on the The software interface to the Am79C972 controller is LANCE. divided into three parts. One part is the PCI configura- tion registers used to identify the Am79C972 controller While in auto-selection mode, the interface in use is de- and to setup the configuration of the device. The setup termined by the Network Port Manager. If the quiescent information includes the I/O or memory mapped I/O state of the MII MDIO pin is HIGH, the MII is activated. base address, mapping of the Expansion ROM, and The GPSI port can only be enabled by disabling the the routing of the Am79C972 controller interrupt chan- auto-selection and manually selecting the GPSI as the nel. This allows for a jumperless implementation. network port. The second portion of the software interface is the di- The Am79C972 controller supports both half-duplex rect access to the I/O resources of the Am79C972 con- and full-duplex operation on network interfaces (i.e., troller. The Am79C972 controller occupies 32 bytes of GPSI and MII). address space that must begin on a 32-byte block boundary. The address space can be mapped into I/O 26 Am79C972 select the DWord location in the configuration space. DETAILED FUNCTIONS The Am79C972 controller ignores AD[10:8], because it Slave Bus Interface Unit is a single function device. AD[31:11] are don’t care. The slave bus interface unit (BIU) controls all accesses AD31 AD10 AD7 to the PCI configuration space, the Control and Status AD1 AD0 AD11 AD8 AD2 Registers (CSR), the Bus Configuration Registers DWord (BCR), the Address PROM (APROM) locations, and Don’t care Don’t care 00 index the Expansion ROM. Table 2 shows the response of the Am79C972 controller to each of the PCI commands The active bytes within a DWord are determined by the in slave mode. byte enable signals. Eight-bit, 16-bit, and 32-bit trans- fers are supported. DEVSEL is asserted two clock cy- cles after the host has asserted FRAME. All Table 2. Slave Commands configuration cycles are of fixed length. The Am79C972 controller will assert TRDY on the third C[3:0] Command Use clock of the data phase. Interrupt 0000 Not used The Am79C972 controller does not support burst trans- Acknowledge fers for access to configuration space. When the host 0001 Special Cycle Not used keeps FRAME asserted for a second data phase, the Am79C972 controller will disconnect the transfer. Read of CSR, BCR, APROM, 0010 I/O Read and Reset registers When the host tries to access the PCI configuration space while the automatic read of the EEPROM after Write to CSR, BCR, and 0011 I/O Write H_RESET (see section on RESET) is on-going, the APROM Am79C972 controller will terminate the access on the 0100 Reserved PCI bus with a disconnect/retry response. 0101 Reserved The Am79C972 controller supports fast back-to-back transactions to different targets. This is indicated by the Memory mapped I/O read of Fast Back-To-Back Capable bit (PCI Status register, bit CSR, BCR, APROM, and 0110 Memory Read Reset registers 7), which is hardwired to 1. The Am79C972 controller Read of the Expansion Bus is capable of detecting a configuration cycle even when its address phase immediately follows the data phase Memory mapped I/O write of 0111 Memory Write of a transaction to a different target without any idle CSR, BCR, and APROM state in-between. There will be no contention on the 1000 Reserved DEVSEL, TRDY, and STOP signals, since the Am79C972 controller asserts DEVSEL on the second 1001 Reserved clock after FRAME is asserted (medium timing). Configuration Read of the Configuration 1010 Slave I/O Transfers Read Space After the Am79C972 controller is configured as an I/O Configuration Write to the Configuration 1011 device by setting IOEN (for regular I/O mode) or Write Space MEMEN (for memory mapped I/O mode) in the PCI Memory Read Command register, it starts monitoring the PCI bus for 1100 Aliased to Memory Read Multiple access to its CSR, BCR, or APROM locations. If con- figured for regular I/O mode, the Am79C972 controller Dual Address 1101 Not used Cycle will look for an address that falls within its 32 bytes of I/ O address space (starting from the I/O base address). Memory Read 1110 Aliased to Memory Read The Am79C972 controller asserts DEVSEL if it detects Line an address match and the access is an I/O cycle. If Memory Write configured for memory mapped I/O mode, the 1111 Aliased to Memory Write Invalidate Am79C972 controller will look for an address that falls within its 32 bytes of memory address space (starting Slave Configuration Transfers from the memory mapped I/O base address). The Am79C972 controller asserts DEVSEL if it detects an The host can access the Am79C972 PCI configuration address match and the access is a memory cycle. space with a configuration read or write command. The DEVSEL is asserted two clock cycles after the host has Am79C972 controller will assert DEVSEL during the asserted FRAME. See Figure 1 and Figure 2. address phase when IDSEL is asserted, AD[1:0] are both 0, and the access is a configuration cycle. AD[7:2] Am79C972 27 the internal Buffer Management Unit clock is a divide- by-two version of the CLK signal. CLK The Am79C972 controller does not support burst trans- 1 23456 6 7 fers for access to its I/O resources. When the host keeps FRAME FRAME asserted for a second data phase, the Am79C972 controller will disconnect the transfer. ADDR DATA AD 1010 BE C/BE CLK 1 23456 7 PAR FRAME PAR PAR IRDY AD ADDR DATA TRDY C/BE 1011 BE DEVSEL PAR PAR PAR STOP IRDY IDSEL TRDY DEVSEL is sampled 21485C-4 DEVSEL Figure 1. Slave Configuration Read STOP IDSEL The Am79C972 controller will not assert DEVSEL if it detects an address match, but the PCI command is not of the correct type. In memory mapped I/O mode, the 21485C-5 Am79C972 controller aliases all accesses to the I/O re- Figure 2. Slave Configuration Write sources of the command types Memory Read Multiple and Memory Read Line to the basic Memory Read com- mand. All accesses of the type Memory Write and In- The Am79C972 controller supports fast back-to-back validate are aliased to the basic Memory Write transactions to different targets. This is indicated by the command. Eight-bit, 16-bit, and 32-bit non-burst trans- Fast Back-To-Back Capable bit (PCI Status register, bit actions are supported. The Am79C972 controller de- 7), which is hardwired to 1. The Am79C972 controller codes all 32 address lines to determine which I/O is capable of detecting an I/O or a memory-mapped resource is accessed. I/O cycle even when its address phase immediately fol- The typical number of wait states added to a slave I/O lows the data phase of a transaction to a different target, or memory mapped I/O read or write access on the part without any idle state in-between. There will be no con- of the Am79C972 controller is six to seven clock cycles, tention on the DEVSEL, TRDY, and STOP signals, since depending upon the relative phases of the internal Buff- the Am79C972 controller asserts DEVSEL on the sec- er Management Unit clock and the CLK signal, since ond clock after FRAME is asserted (medium timing) See Figure 3 and Figure 4. 28 Am79C972 CLK 1 2345678 9 10 11 FRAME ADDR DATA AD C/BE 0010 BE PAR PAR PAR IRDY TRDY DEVSEL STOP 21485C-6 Figure 3. Slave Read Using I/O Command CLK 1 2345678 9 10 11 FRAME DATA AD ADDR 0111 BE C/BE PAR PAR PAR IRDY TRDY DEVSEL STOP 21485C-7 Figure 4. Slave Write Using Memory Command Am79C972 29 Expansion ROM Transfers dress register to a value that prevents the Am79C972 controller from claiming any memory cycles not in- The host must initialize the Expansion ROM Base Ad- tended for it. dress register at offset 30H in the PCI configuration space with a valid address before enabling the access The Am79C972 controller will always read four bytes to the device. The Am79C972 controller will not react to for every host Expansion ROM read access. TRDY will any access to the Expansion ROM until both MEMEN not be asserted until all four bytes are loaded into an in- (PCI Command register, bit 1) and ROMEN (PCI Ex- ternal scratch register. The cycle TRDY is asserted de- pansion ROM Base Address register, bit 0) are set to 1. pends on the programming of the Expansion ROM After the Expansion ROM is enabled, the Am79C972 interface timing. The following figure (Figure 5) as- controller will assert DEVSEL on all memory read ac- sumes that ROMTMG (BCR18, bits 15-12) is at its de- cesses with an address between ROMBASE and fault value. ROMBASE + 1M - 4. The Am79C972 controller aliases Note: The Expansion ROM should be read only during all accesses to the Expansion ROM of the command PCI configuration time for the PCI system. types Memory Read Multiple and Memory Read Line to the basic Memory Read command. Eight-bit, 16-bit, When the host tries to write to the Expansion ROM, the and 32-bit read transfers are supported. Am79C972 controller will claim the cycle by asserting DEVSEL. TRDY will be asserted one clock cycle later. Since setting MEMEN also enables memory mapped The write operation will have no effect. Writes to the Ex- access to the I/O resources, attention must be given pansion ROM are done through the BCR30 Expansion the PCI Memory Mapped I/O Base Address register Bus Data Port. See the section on the Expansion Bus before enabling access to the Expansion ROM. The Interface for more details. See Figure 5. host must set the PCI Memory Mapped I/O Base Ad- CLK 1 2345 48 49 50 51 FRAME AD ADDR DATA C/BE CMD BE PAR PAR PAR IRDY TRDY DEVSEL STOP DEVSEL is sampled 21485C-8 Figure 5. Expansion ROM Read 30 Am79C972 During the boot procedure, the system will try to find an Expansion ROM. A PCI system assumes that an Ex- pansion ROM is present when it reads the ROM signa- CLK 1 2345 ture 55H (byte 0) and AAH (byte 1). Slave Cycle Termination FRAME There are three scenarios besides normal completion of a transaction where the Am79C972 controller is the AD ADDR DATA target of a slave cycle and it will terminate the access. Disconnect When Busy C/BE CMD BE The Am79C972 controller cannot service any slave ac- cess while it is reading the contents of the EEPROM. PAR PAR PAR Simultaneous access is not allowed in order to avoid conflicts, since the EEPROM is used to initialize some IRDY of the PCI configuration space locations and most of the BCRs and CSR116. The EEPROM read operation will always happen automatically after the deassertion TRDY of the RST pin. In addition, the host can start the read operation by setting the PREAD bit (BCR19, bit 14). DEVSEL While the EEPROM read is on-going, the Am79C972 controller will disconnect any slave access where it is the target by asserting STOP together with DEVSEL, STOP while driving TRDY high. STOP will stay asserted until the end of the cycle. Note that I/O and memory slave accesses will only be 21485C-9 disconnected if they are enabled by setting the IOEN or MEMEN bit in the PCI Command register. Without the Figure 6. Disconnect Of Slave Cycle When Busy enable bit set, the cycles will not be claimed at all. Since H_RESET clears the IOEN and MEMEN bits for the automatic EEPROM read after H_RESET, the dis- connect only applies to configuration cycles. CLK A second situation where the Am79C972 controller will 1 2345 generate a PCI disconnect/retry cycle is when the host FRAME tries to access any of the I/O resources right after hav- ing read the Reset register. Since the access gener- ates an internal reset pulse of about 1 μs in length, all AD 1st DATA DATA further slave accesses will be deferred until the internal reset operation is completed. See Figure 6. C/BE BE BE Disconnect Of Burst Transfer The Am79C972 controller does not support burst ac- PAR PAR PAR cess to the configuration space, the I/O resources, or to the Expansion Bus. The host indicates a burst transac- tion by keeping FRAME asserted during the data IRDY phase. When the Am79C972 controller sees FRAME and IRDY asserted in the clock cycle before it wants to TRDY assert TRDY, it also asserts STOP at the same time. The transfer of the first data phase is still successful, since IRDY and TRDY are both asserted. See Figure 7. DEVSEL . STOP 21485C-10 Figure 7. Disconnect Of Slave Burst Transfer - No Host Wait States Am79C972 31 If the host is not yet ready when the Am79C972 control- an address parity error when PERREN and SERREN ler asserts TRDY, the device will wait for the host to as- are set to 1. See Figure 9. sert IRDY. When the host asserts IRDY and FRAME is still asserted, the Am79C972 controller will finish the first data phase by deasserting TRDY one clock later. At the same time, it will assert STOP to signal a discon- nect to the host. STOP will stay asserted until the host CLK 1 2345 removes FRAME. See Figure 8. FRAME CLK AD ADDR 1st DATA 1 23456 FRAME CMD C/BE BE AD 1st DATA DATA PAR PAR PAR BE BE C/BE SERR PAR PAR PAR DEVSEL IRDY 21485C-12 TRDY Figure 9. Address Parity Error Response DEVSEL During the data phase of an I/O write, memory-mapped I/O write, or configuration write command that selects STOP the Am79C972 controller as target, the device samples the AD[31:0] and C/BE[3:0] lines for parity on the clock edge, and data is transferred as indicated by the asser- 21485C-11 tion of IRDY and TRDY. PAR is sampled in the following clock cycle. If a parity error is detected and reporting of Figure 8. Disconnect Of Slave Burst Transfer - that error is enabled by setting PERREN (PCI Com- Host Inserts Wait States mand register, bit 6) to 1, PERR is asserted one clock later. The parity error will always set PERR (PCI Status register, bit 15) to 1 even when PERREN is cleared to Parity Error Response 0. The Am79C972 controller will finish a transaction When the Am79C972 controller is not the current bus that has a data parity error in the normal way by assert- master, it samples the AD[31:0], C/BE[3:0], and the ing TRDY. The corrupted data will be written to the ad- PAR lines during the address phase of any PCI com- dressed location. mand for a parity error. When it detects an address par- ity error, the controller sets PERR (PCI Status register, Figure 10 shows a transaction that suffered a parity bit 15) to 1. When reporting of that error is enabled by error at the time data was transferred (clock 7, IRDY setting SERREN (PCI Command register, bit 8) and and TRDY are both asserted). PERR is driven high at the beginning of the data phase and then drops low due PERREN (PCI Command register, bit 6) to 1, the to the parity error on clock 9, two clock cycles after the Am79C972 controller also drives the SERR signal low data was transferred. After PERR is driven low, the for one clock cycle and sets SERR (PCI Status register, Am79C972 controller drives PERR high for one clock bit 14) to 1. The assertion of SERR follows the address cycle, since PERR is a sustained tri-state signal. phase by two clock cycles. The Am79C972 controller will not assert DEVSEL for a PCI transaction that has 32 Am79C972 CLK 1 2345678 9 10 FRAME AD ADDR DATA C/BE CMD BE PAR PAR PAR PERR IRDY TRDY DEVSEL 21485C-13 Figure 10. Slave Cycle Data Parity Error Response Table 3. Master Commands (Continued) Master Bus Interface Unit The master Bus Interface Unit (BIU) controls the acqui- 0111 Memory Write Write to the descriptor sition of the PCI bus and all accesses to the initializa- rings and to the re- tion block, descriptor rings, and the receive and ceive buffer transmit buffer memory. Table 3 shows the usage of 1000 Reserved PCI commands by the Am79C972 controller in master C[3:0] Command Use mode. 1001 Reserved 1010 Configuration Read Not used 1011 Configuration Write Not used Table 3. Master Commands Memory Read Read of the transmit C[3:0] Command Use 1100 Multiple buffer in burst mode Interrupt 0000 Not used 1101 Dual Address Cycle Not used Acknowledge Read of the transmit 0001 Special Cycle Not used 1110 Memory Read Line buffer in burst mode 0010 I/O Read Not used Memory Write 1111 Not used 0011 I/O Write Not used Invalidate 0100 Reserved Bus Acquisition 0101 Reserved The Am79C972 microcode will determine when a DMA Read of the initialization transfer should be initiated. The first step in any block and descriptor Am79C972 bus master transfer is to acquire ownership 0110 Memory Read rings of the bus. This task is handled by synchronous logic Read of the transmit within the BIU. Bus ownership is requested with the buffer in non-burst mode REQ signal and ownership is granted by the arbiter through the GNT signal. Am79C972 33 Figure 11 shows the Am79C972 controller bus acquisi- controller non-burst read accesses are of the PCI tion. REQ is asserted and the arbiter returns GNT while command type Memory Read (type 6). Note that during another bus master is transferring data. The a non-burst read operation, all byte lanes will always be Am79C972 controller waits until the bus is idle (FRAME active. The Am79C972 controller will internally discard and IRDY deasserted) before it starts driving AD[31:0] unneeded bytes. and C/BE[3:0] on clock 5. FRAME is asserted at clock The Am79C972 controller typically performs more than 5 indicating a valid address and command on AD[31:0] one non-burst read transaction within a single bus mas- and C/BE[3:0]. The Am79C972 controller does not use tership period. FRAME is dropped between consecu- address stepping which is reflected by ADSTEP (bit 7) tive non-burst read cycles. REQ however stays in the PCI Command register being hardwired to 0. asserted until FRAME is asserted for the last transac- tion. The Am79C972 controller supports zero wait state read cycles. It asserts IRDY immediately after the ad- dress phase and at the same time starts sampling CLK DEVSEL. Figure 12 shows two non-burst read transac- 1 2345 tions. The first transaction has zero wait states. In the second transaction, the target extends the cycle by as- FRAME serting TRDY one clock later. Basic Burst Read Transfer ADDR AD The Am79C972 controller supports burst mode for all bus master read operations. The burst mode must be C/BE CMD enabled by setting BREADE (BCR18, bit 6). To allow burst transfers in descriptor read operations, the Am79C972 controller must also be programmed to use IRDY SWSTYLE 3 (BCR20, bits 7-0). All burst read accesses to the initialization block and descriptor ring are of the REQ PCI command type Memory Read (type 6). Burst read accesses to the transmit buffer typically are longer than two data phases. When MEMCMD (BCR18, bit 9) is GNT cleared to 0, all burst read accesses to the transmit buffer are of the PCI command type Memory Read Line (type 14). When MEMCMD (BCR18, bit 9) is set to1, all burst read accesses to the transmit buffer are of the 21485C-14 PCI command type Memory Read Multiple (type 12). Figure 11. Bus Acquisition AD[1:0] will both be 0 during the address phase indicat- ing a linear burst order. Note that during a burst read In burst mode, the deassertion of REQ depends on the operation, all byte lanes will always be active. The setting of EXTREQ (BCR18, bit 8). If EXTREQ is Am79C972 controller will internally discard unneeded cleared to 0, REQ is deasserted at the same time as bytes. FRAME is asserted. (The Am79C972 controller never The Am79C972 controller will always perform only a performs more than one burst transaction within a sin- single burst read transaction per bus mastership pe- gle bus mastership period.) If EXTREQ is set to 1, the riod, where transaction is defined as one address Am79C972 controller does not deassert REQ until it phase and one or multiple data phases. The starts the last data phase of the transaction. Am79C972 controller supports zero wait state read cy- Once asserted, REQ remains active until GNT has be- cles. It asserts IRDY immediately after the address come active and independent of subsequent setting of phase and at the same time starts sampling DEVSEL. STOP (CSR0, bit 2) or SPND (CSR5, bit 0). The asser- FRAME is deasserted when the next to last data phase tion of H_RESET or S_RESET, however, will cause is completed. REQ to go inactive immediately. Figure 13 shows a typical burst read access. The Bus Master DMA Transfers Am79C972 controller arbitrates for the bus, is granted There are four primary types of DMA transfers. The access, reads three 32-bit words (DWord) from the sys- Am79C972 controller uses non-burst as well as burst tem memory, and then releases the bus. In the exam- ple, the memory system extends the data phase of cycles for read and write access to the main memory. each access by one wait state. The example assumes Basic Non-Burst Read Transfer that EXTREQ (BCR18, bit 8) is cleared to 0, therefore, By default, the Am79C972 controller uses non-burst REQ is deasserted in the same cycle as FRAME is as- serted. cycles in all bus master read operations. All Am79C972 34 Am79C972 CLK 1 2345678 9 10 11 FRAME AD ADDR DATA ADDR DATA 0000 0110 0000 C/BE 0110 PAR PAR PAR PAR PAR IRDY TRDY DEVSEL REQ GNT 21485C-15 DEVSEL is sampled Figure 12. Non-Burst Read Transfer CLK 1 2345678 9 10 11 FRAME AD ADDR DATA DATA DATA 1110 0000 C/BE PAR PAR PAR PAR PAR IRDY TRDY DEVSEL REQ GNT 21485C-16 DEVSEL is sampled Figure 13. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0) Am79C972 35 Basic Non-Burst Write Transfer Basic Burst Write Transfer By default, the Am79C972 controller uses non-burst The Am79C972 controller supports burst mode for all cycles in all bus master write operations. All bus master write operations. The burst mode must be Am79C972 controller non-burst write accesses are of enabled by setting BWRITE (BCR18, bit 5). To allow the PCI command type Memory Write (type 7). The burst transfers in descriptor write operations, the byte enable signals indicate the byte lanes that have Am79C972 controller must also be programmed to use valid data.The Am79C972 controller typically performs SWSTYLE 3 (BCR20, bits 7-0). All Am79C972 control- more than one non-burst write transaction within a sin- ler burst write transfers are of the PCI command type gle bus mastership period. FRAME is dropped be- Memory Write (type 7). AD[1:0] will both be 0 during the tween consecutive non-burst write cycles. REQ, address phase indicating a linear burst order. The byte however, stays asserted until FRAME is asserted for enable signals indicate the byte lanes that have valid the last transaction. The Am79C972 supports zero wait data. state write cycles except with descriptor write transfers. The Am79C972 controller will always perform a single (See the section Descriptor DMA Transfers for the only burst write transaction per bus mastership period, exception.) It asserts IRDY immediately after the ad- where transaction is defined as one address phase and dress phase. one or multiple data phases. The Am79C972 controller Figure 14 shows two non-burst write transactions. The supports zero wait state write cycles except with the first transaction has two wait states. The target inserts case of descriptor write transfers. (See the section De- one wait state by asserting DEVSEL one clock late and scriptor DMA Transfers for the only exception.) The de- another wait state by also asserting TRDY one clock vice asserts IRDY immediately after the address phase late. The second transaction shows a zero wait state and at the same time starts sampling DEVSEL. write cycle. The target asserts DEVSEL and TRDY in FRAME is deasserted when the next to last data phase the same cycle as the Am79C972 controller asserts is completed. IRDY. CLK 1 2345678 9 10 FRAME AD ADDR DATA ADDR DATA BE 0111 BE C/BE 0111 PAR PAR PAR PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled 21485C-17 Figure 14. Non-Burst Write Transfer 36 Am79C972 Figure 15 shows a typical burst write access. The with data transfer, disconnect without data transfer, and Am79C972 controller arbitrates for the bus, is granted target abort. access, and writes four 32-bit words (DWords) to the Disconnect With Data Transfer system memory and then releases the bus. In this ex- Figure 16 shows a disconnection in which one last data ample, the memory system extends the data phase of transfer occurs after the target asserted STOP. STOP the first access by one wait state. The following three is asserted on clock 4 to start the termination se- data phases take one clock cycle each, which is deter- quence. Data is still transferred during this cycle, since mined by the timing of TRDY. The example assumes both IRDY and TRDY are asserted. The Am79C972 that EXTREQ (BCR18, bit 8) is set to 1, therefore, REQ controller terminates the current transfer with the deas- is not deasserted until the next to last data phase is fin- sertion of FRAME on clock 5 and of IRDY one clock ished. later. It finally releases the bus on clock 7. The Target Initiated Termination Am79C972 controller will again request the bus after When the Am79C972 controller is a bus master, the cy- two clock cycles, if it wants to transfer more data. The cles it produces on the PCI bus may be terminated by starting address of the new transfer will be the address the target in one of three different ways: disconnect of the next non-transferred data. CLK 1 2345678 9 FRAME ADDR DATA DATA DATA DATA AD 0111 BE C/BE PAR PAR PAR PAR PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled 21485C-18 Figure 15. Burst Write Transfer (EXTREQ = 1) Am79C972 37 CLK 1 2 3456789 10 11 FRAME ADDR ADDR +8 AD DATA DATA i i 0111 0000 0111 C/BE PAR PAR PAR IRDY TRDY DEVSEL STOP REQ GNT DEVSEL is sampled 21485C-19 Figure 16. Disconnect With Data Transfer Disconnect Without Data Transfer about the success of the previous data transfers in the current transaction. The Am79C972 controller termi- Figure 17 shows a target disconnect sequence during nates the current transfer with the deassertion of which no data is transferred. STOP is asserted on clock FRAME on clock 5 and of IRDY one clock cycle later. 4 without TRDY being asserted at the same time. The It finally releases the bus on clock 6. Am79C972 controller terminates the access with the deassertion of FRAME on clock 5 and of IRDY one Since data integrity is not guaranteed, the Am79C972 clock cycle later. It finally releases the bus on clock 7. controller cannot recover from a target abort event. The The Am79C972 controller will again request the bus Am79C972 controller will reset all CSR locations to after two clock cycles to retry the last transfer. The their STOP_RESET values. The BCR and PCI config- starting address of the new transfer will be the address uration registers will not be cleared. Any on-going net- of the last non-transferred data. work transmission is terminated in an orderly sequence. If less than 512 bits have been transmitted Target Abort onto the network, the transmission will be terminated Figure 18 shows a target abort sequence. The target immediately, generating a runt packet. If 512 bits or asserts DEVSEL for one clock. It then deasserts more have been transmitted, the message will have the DEVSEL and asserts STOP on clock 4. A target can current FCS inverted and appended at the next byte use the target abort sequence to indicate that it can- boundary to guarantee an FCS error is detected at the not service the data transfer and that it does not want receiving station. the transaction to be retried. Additionally, the Am79C972 controller cannot make any assumption 38 Am79C972 CLK 2 3456789 1 10 11 FRAME AD ADDR DATA ADDR i i C/BE 0111 0000 0111 PAR PAR PAR IRDY TRDY DEVSEL STOP REQ GNT DEVSEL is sampled 21485C-20 Figure 17. Disconnect Without Data Transfer RTABORT (PCI Status register, bit 12) will be set to last transaction, REQ will remain asserted to regain indicate that the Am79C972 controller has received a bus ownership as soon as possible. See Figure 19. target abort. In addition, SINT (CSR5, bit 11) will be set Preemption During Burst Transaction to 1. When SINT is set, INTA is asserted if the enable When the Am79C972 controller operates in burst bit SINTE (CSR5, bit 10) is set to 1. This mechanism mode, it only performs a single transaction per bus can be used to inform the driver of the system error. The mastership period, where transaction is defined as one host can read the PCI Status register to determine the address phase and one or multiple data phases. The exact cause of the interrupt. central arbiter can remove GNT at any time during the Master Initiated Termination transaction. The Am79C972 controller will ignore the There are three scenarios besides normal completion deassertion of GNT and continue with data transfers, of a transaction where the Am79C972 controller will as long as the PCI Latency Timer is not expired. When terminate the cycles it produces on the PCI bus. the Latency Timer is 0 and GNT is deasserted, the Am79C972 controller will finish the current data phase, Preemption During Non-Burst Transaction deassert FRAME, finish the last data phase, and re- When the Am79C972 controller performs multiple non- lease the bus. If EXTREQ (BCR18, bit 8) is cleared to burst transactions, it keeps REQ asserted until the as- 0, it will immediately assert REQ to regain bus owner- sertion of FRAME for the last transaction. When GNT ship as soon as possible. If EXTREQ is set to 1, REQ is removed, the Am79C972 controller will finish the cur- will stay asserted. rent transaction and then release the bus. If it is not the Am79C972 39 The Am79C972 controller will reset all CSR locations to their STOP_RESET values. The BCR and PCI con- CLK figuration registers will not be cleared. Any on-going 1 2 34567 network transmission is terminated in an orderly se- quence. If less than 512 bits have been transmitted FRAME onto the network, the transmission will be terminated immediately, generating a runt packet. If 512 bits or AD ADDR DATA more have been transmitted, the message will have the current FCS inverted and appended at the next byte boundary to guarantee an FCS error is detected at the 0111 0000 C/BE receiving station. RMABORT (in the PCI Status register, bit 13) will be set PAR PAR PAR to indicate that the Am79C972 controller has termi- nated its transaction with a master abort. In addition, IRDY SINT (CSR5, bit 11) will be set to 1. When SINT is set, INTA is asserted if the enable bit SINTE (CSR5, bit 10) TRDY is set to 1. This mechanism can be used to inform the driver of the system error. The host can read the PCI DEVSEL Status register to determine the exact cause of the in- terrupt. See Figure 21. STOP Parity Error Response During every data phase of a DMA read operation, REQ when the target indicates that the data is valid by as- serting TRDY, the Am79C972 controller samples the GNT AD[31:0], C/BE[3:0] and the PAR lines for a data parity error. When it detects a data parity error, the controller sets PERR (PCI Status register, bit 15) to 1. When re- porting of that error is enabled by setting PERREN DEVSEL is sampled 21485C-21 (PCI Command register, bit 6) to 1, the Am79C972 controller also drives the PERR signal low and sets Figure 18. Target Abort DATAPERR (PCI Status register, bit 8) to 1. The asser- tion of PERR follows the corrupted data/byte enables by two clock cycles and PAR by one clock cycle. When the preemption occurs after the counter has counted down to 0, the Am79C972 controller will finish Figure 22 shows a transaction that has a parity error in the current data phase, deassert FRAME, finish the the data phase. The Am79C972 controller asserts last data phase, and release the bus. Note that it is im- PERR on clock 8, two clock cycles after data is valid. portant for the host to program the PCI Latency Timer The data on clock 5 is not checked for parity, since on according to the bus bandwidth requirement of the a read access PAR is only required to be valid one Am79C972 controller. The host can determine this bus clock after the target has asserted TRDY. The bandwidth requirement by reading the PCI MAX_LAT Am79C972 controller then drives PERR high for one and MIN_GNT registers. clock cycle, since PERR is a sustained tri-state signal. Figure 20 assumes that the PCI Latency Timer has During every data phase of a DMA write operation, the counted down to 0 on clock 7. Am79C972 controller checks the PERR input to see if the target reports a parity error. When it sees the PERR Master Abort input asserted, the controller sets PERR (PCI Status The Am79C972 controller will terminate its cycle with a register, bit 15) to 1. When PERREN (PCI Command Master Abort sequence if DEVSEL is not asserted register, bit 6) is set to 1, the Am79C972 controller also within 4 clocks after FRAME is asserted. Master Abort sets DATAPERR (PCI Status register, bit 8) to 1. is treated as a fatal error by the Am79C972 controller. 40 Am79C972 CLK 1 234567 FRAME AD ADDR DATA 0111 BE C/BE PAR PAR PAR IRDY TRDY DEVSEL REQ GNT 21485C-22 DEVSEL is sampled Figure 19. Preemption During Non-Burst Transaction CLK 1 234 5 6 78 9 FRAME ADDR DATA DATA DATA DATA DATA AD C/BE 0111 BE PAR PAR PAR PAR PAR PAR PAR IRDY TRDY DEVSEL REQ GNT 21485C-23 DEVSEL is sampled Figure 20. Preemption During Burst Transaction Am79C972 41 CLK 1 234 5 6 78 9 FRAME AD ADDR DATA 0111 0000 C/BE PAR PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled 21485C-24 Figure 21. Master Abort CLK 1 234 5 78 9 6 FRAME AD ADDR DATA C/BE 0111 BE PAR PAR PAR PERR IRDY TRDY DEVSEL DEVSEL is sampled 21485C-25 Figure 22. Master Cycle Data Parity Error Response 42 Am79C972 Whenever the Am79C972 controller is the current bus will be terminated immediately, generating a runt master and a data parity error occurs, SINT (CSR5, bit packet. 11) will be set to 1. When SINT is set, INTA is asserted If 512 bits or more have been transmitted, the message if the enable bit SINTE (CSR5, bit 10) is set to 1. This will have the current FCS inverted and appended at the mechanism can be used to inform the driver of the sys- next byte boundary to guarantee an FCS error is de- tem error. The host can read the PCI Status register to tected at the receiving station. determine the exact cause of the interrupt. The setting of SINT due to a data parity error is not dependent on APERREN does not affect the reporting of address the setting of PERREN (PCI Command register, bit 6). parity errors or data parity errors that occur when the Am79C972 controller is the target of the transfer. By default, a data parity error does not affect the state of the MAC engine. The Am79C972 controller treats the Initialization Block DMA Transfers data in all bus master transfers that have a parity error During execution of the Am79C972 controller bus mas- as if nothing has happened. All network activity contin- ter initialization procedure, the Am79C972 microcode ues. will repeatedly request DMA transfers from the BIU. During each of these initialization block DMA transfers, Advanced Parity Error Handling the BIU will perform two data transfer cycles reading For all DMA cycles, the Am79C972 controller provides one DWord per transfer and then it will relinquish the a second, more advanced level of parity error handling. bus. When SSIZE32 (BCR20, bit 8) is set to 1 (i.e., the This mode is enabled by setting APERREN (BCR20, bit initialization block is organized as 32-bit software struc- 10) to 1. When APERREN is set to 1, the BPE bits tures), there are seven DWords to transfer during the (RMD1 and TMD1, bit 23) are used to indicate parity bus master initialization procedure, so four bus master- error in data transfers to the receive and transmit buff- ship periods are needed in order to complete the initial- ers. Note that since the advanced parity error handling ization sequence. Note that the last DWord transfer of uses an additional bit in the descriptor, SWSTYLE the last bus mastership period of the initialization se- (BCR20, bits 7-0) must be set to 2 or 3 to program the quence accesses an unneeded location. Data from this Am79C972 controller to use 32-bit software structures. transfer is discarded internally. When SSIZE32 is The Am79C972 controller will react in the following way cleared to 0 (i.e., the initialization block is organized as when a data parity error occurs: 16-bit software structures), then three bus mastership � Initialization block read: STOP (CSR0, bit 2) is set to periods are needed to complete the initialization se- 1 and causes a STOP_RESET of the device. quence. � Descriptor ring read: Any on-going network activity The Am79C972 supports two transfer modes for read- is terminated in an orderly sequence and then STOP ing the initialization block: non-burst and burst mode, (CSR0, bit 2) is set to 1 to cause a STOP_RESET with burst mode being the preferred mode when the of the device. Am79C972 controller is used in a PCI bus application. See Figure 23 and Figure 24. � Descriptor ring write: Any on-going network activity is terminated in an orderly sequence and then STOP When BREADE is cleared to 0 (BCR18, bit 6), all initial- (CSR0, bit 2) is set to 1 to cause a STOP_RESET ization block read transfers will be executed in non- of the device. burst mode. There is a new address phase for every � Transmit buffer read: BPE (TMD1, bit 23) is set in data phase. FRAME will be dropped between the two the current transmit descriptor. Any on-going net- transfers. The two phases within a bus mastership pe- work transmission is terminated in an orderly se- riod will have addresses of ascending contiguous or- quence. der. � Receive buffer write: BPE (RMD1, bit 23) is set in When BREADE is set to 1 (BCR18, bit 6), all initializa- the last receive descriptor associated with the frame. tion block read transfers will be executed in burst mode. AD[1:0] will be 0 during the address phase indicating a Terminating on-going network transmission in an or- linear burst order. derly sequence means that if less than 512 bits have been transmitted onto the network, the transmission Am79C972 43 CLK 1 2345678 9 10 FRAME DATA AD IADD DATA IADD +4 i i C/BE 0110 0000 0110 0000 PAR PAR PAR PAR PAR IRDY TRDY DEVSEL REQ GNT 21485C-26 DEVSEL is sampled Figure 23. Initialization Block Read In Non-Burst Mode CLK 1 234567 FRAME IADD AD DATA DATA i C/BE 0110 0000 PAR PAR PAR PAR IRDY TRDY DEVSEL REQ GNT 21485C-27 DEVSEL is sampled Figure 24. Initialization Block Read In Burst Mode 44 Am79C972 Descriptor DMA Transfers When SWSTYLE is set to 3, the descriptor entries are ordered to allow burst transfers. The Am79C972 con- Am79C972 microcode will determine when a descrip- troller will perform all descriptor write operations in tor access is required. A descriptor DMA read will con- burst mode, if BWRITE is set to 1. See Table 5 for the sist of two data transfers. A descriptor DMA write will descriptor write sequence. consist of one or two data transfers. The descriptor DMA transfers within a single bus mastership period A write transaction to the descriptor ring entries is the will always be of the same type (either all read or all only case where the Am79C972 controller inserts a write). wait state when being the bus master. Every data phase in non-burst and burst mode is extended by one During descriptor read accesses, the byte enable sig- clock cycle, during which IRDY is deasserted. nals will indicate that all byte lanes are active. Should some of the bytes not be needed, then the Am79C972 Note that Figure 26 assumes that the Am79C972 con- controller will internally discard the extraneous informa- troller is programmed to use 32-bit software structures tion that was gathered during such a read. (SWSTYLE = 2 or 3). The byte enable signals for the second data transfer would be 0111b, if the device was The settings of SWSTYLE (BCR20, bits 7-0) and programmed to use 16-bit software structures (SW- BREADE (BCR18, bit 6) affect the way the Am79C972 STYLE = 0). controller performs descriptor read operations. When SWSTYLE is set to 0 or 2, all descriptor read op- erations are performed in non-burst mode. The setting Table 4. Descriptor Read Sequence of BREADE has no effect in this configuration. See Fig- SWSTYLE BREADE ure 25. BCR20[7:0] BCR18[6] AD Bus Sequence When SWSTYLE is set to 3, the descriptor entries are Address = XXXX XX00h ordered to allow burst transfers. The Am79C972 con- Turn around cycle troller will perform all descriptor read operations in Data = MD1[31:24], burst mode, if BREADE is set to 1. See Figure 26. MD0[23:0] 0X Table 4 shows the descriptor read sequence. Idle Address = XXXX XX04h During descriptor write accesses, only the byte lanes which need to be written are enabled. Turn around cycle Data = MD2[15:0], MD1[15:0] If buffer chaining is used, accesses to the descriptors Address = XXXX XX04h of all intermediate buffers consist of only one data transfer to return ownership of the buffer to the system. Turn around cycle When SWSTYLE (BCR20, bits 7-0) is cleared to 0 (i.e., Data = MD1[31:0] the descriptor entries are organized as 16-bit software 2X Idle structures), the descriptor access will write a single Address = XXXX XX00h byte. When SWSTYLE (BCR20, bits 7-0) is set to 2 or Turn around cycle 3 (i.e., the descriptor entries are organized as 32-bit Data = MD0[31:0] software structures), the descriptor access will write a single word. On all single buffer transmit or receive de- Address = XXXX XX04h scriptors, as well as on the last buffer in chain, writes to Turn around cycle the descriptor consist of two data transfers. Data = MD1[31:0] The first data transfer writes a DWord containing status 30 Idle information. The second data transfer writes a byte Address = XXXX XX08h (SWSTYLE cleared to 0), or otherwise a word contain- Turn around cycle ing additional status and the ownership bit (i.e., Data = MD0[31:0] MD1[31]). Address = XXXX XX04h The settings of SWSTYLE (BCR20, bits 7-0) and Turn around cycle 31 BWRITE (BCR18, bit 5) affect the way the Am79C972 Data = MD1[31:0] controller performs descriptor write operations. Data = MD0[31:0] When SWSTYLE is set to 0 or 2, all descriptor write op- erations are performed in non-burst mode. The setting of BWRITE has no effect in this configuration. Am79C972 45 CLK 1 2345678 9 10 FRAME MD1 DATA DATA AD MD0 C/BE 0110 0000 0110 0000 PAR PAR PAR PAR PAR IRDY TRDY DEVSEL REQ GNT 21485C-28 DEVSEL is sampled Figure 25. Descriptor Ring Read In Non-Burst Mode CLK 1 234567 FRAME AD MD1 DATA DATA C/BE 0110 0000 PAR PAR PAR PAR IRDY TRDY DEVSEL REQ GNT 21485C-29 DEVSEL is sampled Figure 26. Descriptor Ring Read In Burst Mode 46 Am79C972 Table 5. Descriptor Write Sequence Non-Burst FIFO DMA Transfers In the default mode, the Am79C972 controller uses SWSTYLE BWRITE non-burst transfers to read and write data when ac- BCR20[7:0] BCR18[5] AD Bus Sequence cessing the FIFOs. Each non-burst transfer will be per- Address = XXXX XX04h formed sequentially with the issue of an address and Data = MD2[15:0], the transfer of the corresponding data with appropriate MD1[15:0] output signals to indicate selection of the active data 0X Idle bytes during the transfer. Address = XXXX XX00h FRAME will be deasserted after every address phase. Data = MD1[31:24] Several factors will affect the length of the bus master- Address = XXXX XX08h ship period. The possibilities are as follows: Data = MD2[31:0] Bus cycles will continue until the transmit FIFO is filled 2X Idle to its high threshold (read transfers) or the receive FIFO Address = XXXX XX04h is emptied to its low threshold (write transfers). The Data = MD1[31:16] exact number of total transfer cycles in the bus master- Address = XXXX XX00h ship period is dependent on all of the following vari- ables: the settings of the FIFO watermarks, the Data = MD2[31:0] conditions of the FIFOs, the latency of the system bus 30 Idle to the Am79C972 controller’s bus request, the speed of Address = XXXX XX04h bus operation and bus preemption events. The TRDY Data = MD1[31:16] response time of the memory device will also affect the Address = XXXX XX00h number of transfers, since the speed of the accesses 31 Data = MD2[31:0] will affect the state of the FIFO. During accesses, the Data = MD1[31:16] FIFO may be filling or emptying on the network end. For example, on a receive operation, a slower TRDY re- FIFO DMA Transfers sponse will allow additional data to accumulate inside Am79C972 microcode will determine when a FIFO of the FIFO. If the accesses are slow enough, a com- DMA transfer is required. This transfer mode will be plete DWord may become available before the end of used for transfers of data to and from the Am79C972 the bus mastership period and, thereby, increase the FIFOs. Once the Am79C972 BIU has been granted bus number of transfers in that period. The general rule is mastership, it will perform a series of consecutive that the longer the Bus Grant latency, the slower the transfer cycles before relinquishing the bus. All trans- bus transfer operations; the slower the clock speed, the fers within the master cycle will be either read or write higher the transmit watermark; or the higher the re- cycles, and all transfers will be to contiguous, ascend- ceive watermark, the longer the bus mastership period ing addresses. Both non-burst and burst cycles are will be. used, with burst mode being the preferred mode when Note: The PCI Latency Timer is not significant during the device is used in a PCI bus application. non-burst transfers. Am79C972 47 CLK 1 2345678 9 10 FRAME AD MD2 DATA MD1 DATA C/BE 0111 0000 0111 0011 PAR PAR PAR PAR PAR IRDY TRDY DEVSEL REQ GNT 21485C-30 DEVSEL is sampled Figure 27. Descriptor Ring Write In Non-Burst Mode CLK 1 235 4 6 7 8 FRAME MD2 AD DATA DATA C/BE 0110 0000 0011 PAR PAR PAR PAR IRDY TRDY DEVSEL REQ GNT 21485C-31 DEVSEL is sampled Figure 28. Descriptor Ring Write In Burst Mode 48 Am79C972 Burst FIFO DMA Transfers Bursting is only performed by the Am79C972 controller CLK if the BREADE and/or BWRITE bits of BCR18 are set. 1 23456 These bits individually enable/disable the ability of the Am79C972 controller to perform burst accesses during FRAME master read operations and master write operations, respectively. ADD AD DATA DATA DATA A burst transaction will start with an address phase, fol- lowed by one or more data phases. AD[1:0] will always C/BE 0111 0001 0000 be 0 during the address phase indicating a linear burst order. PAR PAR PAR PAR During FIFO DMA read operations, all byte lanes will always be active. The Am79C972 controller will inter- nally discard unused bytes. During the first and the last IRDY data phases of a FIFO DMA burst write operation, one or more of the byte enable signals may be inactive. All TRDY other data phases will always write a complete DWord. Figure 29 shows the beginning of a FIFO DMA write DEVSEL with the beginning of the buffer not aligned to a DWord boundary. The Am79C972 controller starts off by writ- ing only three bytes during the first data phase. This op- REQ eration aligns the address for all other data transfers to a 32-bit boundary so that the Am79C972 controller can GNT continue bursting full DWords. If a receive buffer does not end on a DWord boundary, DEVSEL is sampled the Am79C972 controller will perform a non-DWord write on the last transfer to the buffer. Figure 30 shows 21485C-32 the final three FIFO DMA transfers to a receive buffer. Since there were only nine bytes of space left in the re- Figure 29. FIFO Burst Write At Start Of Unaligned ceive buffer, the Am79C972 controller bursts three data Buffer phases. The first two data phases write a full DWord, the last one only writes a single byte. The Am79C972 controller will continue transferring Note that the Am79C972 controller will always perform FIFO data until the transmit FIFO is filled to its high a DWord transfer as long as it owns the buffer space, threshold (read transfers) or the receive FIFO is emp- even when there are less than four bytes to write. For tied to its low threshold (write transfers), or the example, if there is only one byte left for the current re- Am79C972 controller is preempted, and the PCI La- ceive frame, the Am79C972 controller will write a full tency Timer is expired. The host should use the values DWord, containing the last byte of the receive frame in in the PCI MIN_GNT and MAX_LAT registers to deter- the least significant byte position (BSWP is cleared to mine the value for the PCI Latency Timer. 0, CSR3, bit 2). The content of the other three bytes is undefined. The message byte count in the receive de- scriptor always reflects the exact length of the received frame. Am79C972 49 Buffer Management Unit The Buffer Management Unit (BMU) is a microcoded CLK state machine which implements the initialization pro- 1 234567 cedure and manages the descriptors and buffers. The buffer management unit operates at half the speed of FRAME the CLK input. ADD Initialization AD DATA DATA DATA Am79C972 initialization includes the reading of the ini- tialization block in memory to obtain the operating pa- C/BE 0111 0000 1110 rameters. The initialization block can be organized in two ways. When SSIZE32 (BCR20, bit 8) is at its de- PAR PAR PAR PAR PAR fault value of 0, all initialization block entries are logi- cally 16-bits wide to be backwards compatible with the IRDY Am79C90 C-LANCE and Am79C96x PCnet-ISA family. When SSIZE32 (BCR20, bit 8) is set to 1, all initializa- tion block entries are logically 32-bits wide. Note that TRDY the Am79C972 controller always performs 32-bit bus transfers to read the initialization block entries. The ini- DEVSEL tialization block is read when the INIT bit in CSR0 is set. The INIT bit should be set before or concurrent with the REQ STRT bit to insure correct operation. Once the initial- ization block has been completely read in and internal registers have been updated, IDON will be set in GNT CSR0, generating an interrupt (if IENA is set). DEVSEL is sampled The Am79C972 controller obtains the start address of the initialization block from the contents of CSR1 (least 21485C-33 significant 16 bits of address) and CSR2 (most signifi- cant 16 bits of address). The host must write CSR1 and Figure 30. FIFO Burst Write At End Of Unaligned CSR2 before setting the INIT bit. The initialization block Buffer contains the user defined conditions for Am79C972 op- eration, together with the base addresses and length information of the transmit and receive descriptor rings. The exact number of total transfer cycles in the bus mastership period is dependent on all of the following There is an alternate method to initialize the variables: the settings of the FIFO watermarks, the Am79C972 controller. Instead of initialization via the conditions of the FIFOs, the latency of the system bus initialization block in memory, data can be written di- to the Am79C972 controller’s bus request, and the rectly into the appropriate registers. Either method or a speed of bus operation. The TRDY response time of combination of the two may be used at the discretion of the memory device will also affect the number of trans- the programmer. Please refer to Appendix A, Alterna- fers, since the speed of the accesses will affect the tive Method for Initialization for details on this alternate state of the FIFO. During accesses, the FIFO may be method. filling or emptying on the network end. For example, on Re-Initialization a receive operation, a slower TRDY response will allow additional data to accumulate inside of the FIFO. If the The transmitter and receiver sections of the Am79C972 accesses are slow enough, a complete DWord may be- controller can be turned on via the initialization block come available before the end of the bus mastership (DTX, DRX, CSR15, bits 1-0). The states of the trans- period and, thereby, increase the number of transfers in mitter and receiver are monitored by the host through that period. The general rule is that the longer the Bus CSR0 (RXON, TXON bits). The Am79C972 controller Grant latency, the slower the bus transfer operations; should be re-initialized if the transmitter and/or the re- the slower the clock speed, the higher the transmit wa- ceiver were not turned on during the original initializa- termark; or the lower the receive watermark, the longer tion, and it was subsequently required to activate them the total burst length will be. or if either section was shut off due to the detection of an error condition (MERR, UFLO, TX BUFF error). When a FIFO DMA burst operation is preempted, the Am79C972 controller will not relinquish bus ownership until the PCI Latency Timer expires. Re-initialization may be done via the initialization block or by setting the STOP bit in CSR0, followed by writing 50 Am79C972 to CSR15, and then setting the START bit in CSR0. Am79C972 controller will completely receive a receive Note that this form of restart will not perform the same packet if it had already begun. The Am79C972 control- in the Am79C972 controller as in the C-LANCE device. ler will not receive any new packets after the comple- In particular, upon restart, the Am79C972 controller re- tion of the current reception. Additionally, all transmit loads the transmit and receive descriptor pointers with packets stored in the transmit FIFOs and the transmit their respective base addresses. This means that the buffer area in the SRAM (if one is present) will be trans- software must clear the descriptor OWN bits and reset mitted, and all receive packets stored in the receive its descriptor ring pointers before restarting the FIFOs and the receive buffer area in the SRAM (if se- Am79C972 controller. The reload of descriptor base lected) will be transferred into system memory. Since addresses is performed in the C-LANCE device only the FIFO and the SRAM contents are flushed, it may after initialization, so that a restart of the C-LANCE take much longer before the Am79C972 controller en- without initialization leaves the C-LANCE pointing at ters the suspend mode. The amount of time that it the same descriptor locations as before the restart. takes depends on many factors including the size of the SRAM, bus latency, and network traffic level. Suspend Upon completion of the described operations, the The Am79C972 controller offers two suspend modes Am79C972 controller sets the read-version of SPND to that allow easy updating of the CSR registers without 1 and enters the suspend mode. In suspend mode, all going through a full re-initialization of the device. The of the CSR and BCR registers are accessible. As long suspend modes also allow stopping the device with or- as the Am79C972 controller is not reset while in sus- derly termination of all network activity. pend mode (by H_RESET, S_RESET, or by setting the The host requests the Am79C972 controller to enter STOP bit), no re-initialization of the device is required the suspend mode by setting SPND (CSR5, bit 0) to 1. after the device comes out of suspend mode. When The host must poll SPND until it reads back 1 to deter- SPND is set to 0, the Am79C972 controller will leave mine that the Am79C972 controller has entered the the suspend mode and will continue at the transmit and suspend mode. When the host sets SPND to 1, the pro- receive descriptor ring locations where it was when it cedure taken by the Am79C972 controller to enter the entered the suspend mode. suspend mode depends on the setting of the fast sus- See the section on Magic Packet™ technology for de- pend enable bit (FASTSPND, CSR7, bit 15). tails on how that affects suspension of the Am79C972 When a fast suspend is requested (FASTSPND is set controller. to 1), the Am79C972 controller performs a quick entry Buffer Management into the suspend mode. At the time the SPND bit is set, the Am79C972 controller will continue the DMA pro- Buffer management is accomplished through message cess of any transmit and/or receive packets that have descriptor entries organized as ring structures in mem- already begun DMA activity until the network activity ory. There are two descriptor rings, one for transmit and has been completed. In addition, any transmit packet one for receive. Each descriptor describes a single that had started transmission will be fully transmitted buffer. A frame may occupy one or more buffers. If mul- and any receive packet that had begun reception will be tiple buffers are used, this is referred to as buffer chain- fully received. However, no additional packets will be ing. transmitted or received and no additional transmit or re- Descriptor Rings ceive DMA activity will begin after network activity has Each descriptor ring must occupy a contiguous area of ceased. Hence, the Am79C972 controller may enter memory. During initialization, the user-defined base the suspend mode with transmit and/or receive packets address for the transmit and receive descriptor rings, still in the FIFOs or the SRAM. This offers a worst case as well as the number of entries contained in the de- suspend time of a maximum length packet over the scriptor rings are set up. The programming of the soft- possibility of completely emptying the SRAM. Care ware style (SWSTYLE, BCR20, bits 7-0) affects the must be exercised in this mode, because the entire way the descriptor rings and their entries are arranged. memory subsystem of the Am79C972 controller is sus- pended. Any changes to either the descriptor rings or When SWSTYLE is at its default value of 0, the de- the SRAM can cause the Am79C972 controller to start scriptor rings are backwards compatible with the up in an unknown condition and could cause data cor- Am79C90 C-LANCE and the Am79C96x PCnet-ISA ruption. family. The descriptor ring base addresses must be aligned to an 8-byte boundary and a maximum of 128 When FASTSPNDE is 0 and the SPND bit is set, the ring entries is allowed when the ring length is set Am79C972 controller may take longer before entering through the TLEN and RLEN fields of the initialization the suspend mode. At the time the SPND bit is set, the block. Each ring entry contains a subset of the three Am79C972 controller will complete the DMA process of 32-bit transmit or receive message descriptors (TMD, a transmit packet if it had already begun and the RMD) that are organized as four 16-bit structures Am79C972 51 (SSIZE32 (BCR20, bit 8) is set to 0). Note that even To permit the queuing and de-queuing of message though the Am79C972 controller treats the descriptor buffers, ownership of each buffer is allocated to either entries as 16-bit structures, it will always perform 32-bit the Am79C972 controller or the host. The OWN bit bus transfers to access the descriptor entries. The within the descriptor status information, either TMD or value of CSR2, bits 15-8, is used as the upper 8-bits for RMD, is used for this purpose. all memory addresses during bus master transfers. When OWN is set to 1, it signifies that the Am79C972 When SWSTYLE is set to 2 or 3, the descriptor ring controller currently has ownership of this ring descrip- base addresses must be aligned to a 16-byte bound- tor and its associated buffer. Only the owner is permit- ary, and a maximum of 512 ring entries is allowed when ted to relinquish ownership or to write to any field in the the ring length is set through the TLEN and RLEN fields descriptor entry. A device that is not the current owner of the initialization block. Each ring entry is organized of a descriptor entry cannot assume ownership or as three 32-bit message descriptors (SSIZE32 change any field in the entry. A device may, however, (BCR20, bit 8) is set to 1). The fourth DWord is re- read from a descriptor that it does not currently own. served. When SWSTYLE is set to 3, the order of the Software should always read descriptor entries in se- message descriptors is optimized to allow read and quential order. When software finds that the current de- write access in burst mode. scriptor is owned by the Am79C972 controller, then the software must not read ahead to the next descriptor. For any software style, the ring lengths can be set be- The software should wait at a descriptor it does not own yond this range (up to 65535) by writing the transmit until the Am79C972 controller sets OWN to 0 to release and receive ring length registers (CSR76, CSR78) di- ownership to the software. (When LAPPEN (CSR3, bit rectly. 5) is set to 1, this rule is modified. See the LAPPEN de- Each ring entry contains the following information: scription. At initialization, the Am79C972 controller reads the base address of both the transmit and re- � The address of the actual message data buffer in ceive descriptor rings into CSRs for use by the user or host memory Am79C972 controller during subsequent operations. � The length of the message buffer Figure 31 illustrates the relationship between the initial- � Status information indicating the condition of the ization base address, the initialization block, the re- buffer ceive and transmit descriptor ring base addresses, the receive and transmit descriptors, and the receive and transmit data buffers, when SSIZE32 is cleared to 0. 52 Am79C972 N N N N Rcv Descriptor Ring 1st 2nd desc. CSR2 CSR1 desc. IADR[31:16] IADR[15:0] RMD0 RMD RMD RMD RMD Initialization Block MOD Data Data Data Rcv PADR[15:0] Buffer Buffer Buffer Buffers 1 2 N PADR[31:16] PADR[47:32] LADRF[15:0 M M M LADRF[31:16] M LADRF[47:32] LADRF[63:48] Xmt Descriptor RDRA[15:0] Ring RLE RES RDRA[23:16] TDRA[15:0] 2nd 1st TLE RES TDRA[23:16] desc. desc. TMD TMD TMD TMD TMD Data Data Data Xmt Buffer Buffer Buffer Buffers M 1 2 21485C-34 Figure 31. 16-Bit Software Model Note that the value of CSR2, bits 15-8, is used as the (RDTE). It will then use the current transmit descriptor upper 8-bits for all memory addresses during bus mas- address (stored internally) to vector to the appropriate ter transfers. Transmit Descriptor Table Entry (TDTE). The accesses will be made in the following order: RMD1, then RMD0 Figure 32 illustrates the relationship between the initial- of the current RDTE during one bus arbitration, and ization base address, the initialization block, the re- after that, TMD1, then TMD0 of the current TDTE dur- ceive and transmit descriptor ring base addresses, the ing a second bus arbitration. All information collected receive and transmit descriptors, and the receive and during polling activity will be stored internally in the ap- transmit data buffers, when SSIZE32 is set to 1. propriate CSRs, if the OWN bit is set (i.e., CSR18, Polling CSR19, CSR20, CSR21, CSR40, CSR42, CSR50, CSR52). If there is no network channel activity and there is no pre- or post-receive or pre- or post-transmit activity A typical receive poll is the product of the following con- being performed by the Am79C972 controller, then the ditions: Am79C972 controller will periodically poll the current 1. Am79C972 controller does not own the current receive and transmit descriptor entries in order to as- RDTE and the poll time has elapsed and certain their ownership. If the TXDPOLL bit in CSR4 is RXON = 1 (CSR0, bit 5), or set, then the transmit polling function is disabled. 2. Am79C972 controller does not own the next RDTE A typical polling operation consists of the following se- and there is more than one receive descriptor in the quence. The Am79C972 controller will use the current ring and the poll time has elapsed and RXON = 1. receive descriptor address stored internally to vector to the appropriate Receive Descriptor Table Entry Am79C972 53 . N N N N Rcv Descriptor Ring 1st 2nd desc. desc. CSR2 CSR1 start start IADR[31:16] IADR[15:0] RMD RMD RMD RMD RMD Initialization Block TLE RES RLE RES MODE Data Data Data Rcv PADR[31:0] Buffer Buffer Buffer Buffers RES PADR[47:32] 1 2 N LADRF[31:0 LADRF[63:32] M M M RDRA[31:0] M TDRA[31:0] Xmt Descriptor Ring 1st 2nd desc. desc. start start TMD0 TMD0 TMD3 TMD1 TMD2 Data Data Data Xmt Buffer Buffer Buffer Buffers 1 2 M 21485C-35 Figure 32. 32-Bit Software Model If RXON is cleared to 0, the Am79C972 controller will has not been previously established, then an RDTE never poll RDTE locations. poll will be performed ahead of the TDTE poll. If the mi- crocode is not executing the poll counting code when In order to avoid missing frames, the system should the TDMD bit is set, then the demanded poll of the have at least one RDTE available. To minimize poll ac- TDTE will be delayed until the microcode returns to the tivity, two RDTEs should be available. In this case, the poll counting code. poll operation will only consist of the check of the status of the current TDTE. The user may change the poll time value from the de- fault of 65,536 clock periods by modifying the value in A typical transmit poll is the product of the following the Polling Interval register (CSR47). conditions: Transmit Descriptor Table Entry 1. Am79C972 controller does not own the current If, after a Transmit Descriptor Table Entry (TDTE) ac- TDTE and TXDPOLL = 0 (CSR4, bit 12) and cess, the Am79C972 controller finds that the OWN bit TXON = 1 (CSR0, bit 4) and of that TDTE is not set, the Am79C972 controller re- the poll time has elapsed, or sumes the poll time count and re-examines the same 2. Am79C972 controller does not own the current TDTE at the next expiration of the poll time count. TDTE and TXDPOLL = 0 and TXON = 1 and a frame has just been received, or If the OWN bit of the TDTE is set, but the Start of Packet (STP) bit is not set, the Am79C972 controller 3. Am79C972 controller does not own the current will immediately request the bus in order to clear the TDTE and TXDPOLL = 0 and TXON = 1 and OWN bit of this descriptor. (This condition would nor- a frame has just been transmitted. mally be found following a late collision (LCOL) or retry Setting the TDMD bit of CSR0 will cause the microcode (RTRY) error that occurred in the middle of a transmit controller to exit the poll counting code and immedi- frame chain of buffers.) After resetting the OWN bit of ately perform a polling operation. If RDTE ownership this descriptor, the Am79C972 controller will again im- 54 Am79C972 mediately request the bus in order to access the next mit status of the current buffer will be immediately up- TDTE location in the ring. dated. If the buffer does not contain the end of packet, the Am79C972 controller will skip over the rest of the If the OWN bit is set and the buffer length is 0, the OWN frame which experienced the error. This is done by re- bit will be cleared. In the C-LANCE device, the buffer turning to the polling microcode where the Am79C972 length of 0 is interpreted as a 4096-byte buffer. A zero controller will clear the OWN bit for all descriptors with length buffer is acceptable as long as it is not the last OWN = 1 and STP = 0 and continue in like manner until buffer in a chain (STP = 0 and ENP = 1). a descriptor with OWN = 0 (no more transmit frames in If the OWN bit and STP are set, then microcode control the ring) or OWN = 1 and STP = 1 (the first buffer of a proceeds to a routine that will enable transmit data new frame) is reached. transfers to the FIFO. The Am79C972 controller will At the end of any transmit operation, whether success- look ahead to the next transmit descriptor after it has ful or with errors, immediately following the completion performed at least one transmit data transfer from the of the descriptor updates, the Am79C972 controller will first buffer. always perform another polling operation. As described If the Am79C972 controller does not own the next earlier, this polling operation will begin with a check of TDTE (i.e., the second TDTE for this frame), it will com- the current RDTE, unless the Am79C972 controller al- plete transmission of the current buffer and update the ready owns that descriptor. Then the Am79C972 con- status of the current (first) TDTE with the BUFF and troller will poll the next TDTE. If the transmit descriptor UFLO bits being set. If DXSUFLO (CSR3, bit 6) is OWN bit has a 0 value, the Am79C972 controller will cleared to 0, the underflow error will cause the transmit- resume incrementing the poll time counter. If the trans- ter to be disabled (CSR0, TXON = 0). The Am79C972 mit descriptor OWN bit has a value of 1, the Am79C972 controller will have to be re-initialized to restore the controller will begin filling the FIFO with transmit data transmit function. Setting DXSUFLO to 1 enables the and initiate a transmission. This end-of-operation poll Am79C972 controller to gracefully recover from an un- coupled with the TDTE lookahead operation allows the derflow error. The device will scan the transmit descrip- Am79C972 controller to avoid inserting poll time counts tor ring until it finds either the start of a new frame or a between successive transmit frames. TDTE it does not own. To avoid an underflow situation By default, whenever the Am79C972 controller com- in a chained buffer transmission, the system should al- pletes a transmit frame (either with or without error) and ways set the transmit chain descriptor own bits in re- writes the status information to the current descriptor, verse order. then the TINT bit of CSR0 is set to indicate the comple- If the Am79C972 controller does own the second TDTE tion of a transmission. This causes an interrupt signal if in a chain, it will gradually empty the contents of the first the IENA bit of CSR0 has been set and the TINTM bit buffer (as the bytes are needed by the transmit opera- of CSR3 is cleared. The Am79C972 controller provides tion), perform a single-cycle DMA transfer to update the two modes to reduce the number of transmit interrupts. status of the first descriptor (clear the OWN bit in The interrupt of a successfully transmitted frame can TMD1), and then it may perform one data DMA access be suppressed by setting TINTOKD (CSR5, bit 15) to on the second buffer in the chain before executing an- 1. Another mode, which is enabled by setting LTINTEN other lookahead operation. (i.e., a lookahead to the (CSR5, bit 14) to 1, allows suppression of interrupts for third descriptor.) successful transmissions for all but the last frame in a sequence. It is imperative that the host system never reads the TDTE OWN bits out of order. The Am79C972 controller Receive Descriptor Table Entry normally clears OWN bits in strict FIFO order. However, If the Am79C972 controller does not own both the cur- the Am79C972 controller can queue up to two frames rent and the next Receive Descriptor Table Entry in the transmit FIFO. When the second frame uses (RDTE), then the Am79C972 controller will continue to buffer chaining, the Am79C972 controller might return poll according to the polling sequence described ownership out of normal FIFO order. The OWN bit for above. If the receive descriptor ring length is one, then last (and maybe only) buffer of the first frame is not there is no next descriptor to be polled. cleared until transmission is completed. During the If a poll operation has revealed that the current and the transmission the Am79C972 controller will read in buff- next RDTE belong to the Am79C972 controller, then ers for the next frame and clear their OWN bits for all additional poll accesses are not necessary. Future poll but the last one. The first and all intermediate buffers of operations will not include RDTE accesses as long as the second frame can have their OWN bits cleared be- the Am79C972 controller retains ownership of the cur- fore the Am79C972 controller returns ownership for the rent and the next RDTE. last buffer of the first frame. When receive activity is present on the channel, the If an error occurs in the transmission before all of the Am79C972 controller waits for the complete address of bytes of the current buffer have been transferred, trans- Am79C972 55 the message to arrive. It then decides whether to ac- abled through the Receive Frame Queuing mecha- cept or reject the frame based on all active addressing nism. When the SRAM SIZE = 0, then the Am79C972 schemes. If the frame is accepted, the Am79C972 con- controller reverts back to the PCnet PCI II mode of op- troller checks the current receive buffer status register eration. This operation is automatic and does not re- CRST (CSR41) to determine the ownership of the cur- quire any programming by the host. When SRAM is rent buffer. enabled, the Receive Frame Queuing mechanism allows a slow protocol to manage more frames without If ownership is lacking, the Am79C972 controller will the high frame loss rate normally attributed to FIFO immediately perform a final poll of the current RDTE. If based network controllers. ownership is still denied, the Am79C972 controller has no buffer in which to store the incoming message. The The Am79C972 controller will store the incoming MISS bit will be set in CSR0 and the Missed Frame frames in the extended FIFOs until polling takes place; Counter (CSR112) will be incremented. Another poll of if enabled, it discovers it owns an RDTE. The stored the current RDTE will not occur until the frame has fin- frames are not altered in any way until written out into ished. system buffers. When the receive FIFO overflows, fur- ther incoming receive frames will be missed during that If the Am79C972 controller sees that the last poll (ei- time. As soon as the network receive FIFO is empty, in- ther a normal poll, or the final effort described in the coming frames are processed as normal. Status on a above paragraph) of the current RDTE shows valid per frame basis is not kept during the overflow process. ownership, it proceeds to a poll of the next RDTE. Fol- Statistic counters are maintained and accurate during lowing this poll, and regardless of the outcome of this that time. poll, transfers of receive data from the FIFO may begin. During the time that the Receive Frame Queuing mech- Regardless of ownership of the second receive de- anism is in operation, the Am79C972 controller relies scriptor, the Am79C972 controller will continue to per- on the Receive Poll Time Counter (CSR 48) to control form receive data DMA transfers to the first buffer. If the the worst case access to the RDTE. The Receive Poll frame length exceeds the length of the first buffer, and Time Counter is programmed through the Receive Poll- the Am79C972 controller does not own the second ing Interval (CSR49) register. The Received Polling In- buffer, ownership of the current descriptor will be terval defaults to approximately 2 ms. The Am79C972 passed back to the system by writing a 0 to the OWN controller will also try to access the RDTE during nor- bit of RMD1. Status will be written indicating buffer mal descriptor accesses whether they are transmit or (BUFF = 1) and possibly overflow (OFLO = 1) errors. receive accesses. The host can force the Am79C972 If the frame length exceeds the length of the first (cur- controller to immediately access the RDTE by setting rent) buffer, and the Am79C972 controller does own the RDMD (CSR 7, bit 13) to 1. Its operation is similar the second (next) buffer, ownership will be passed back to the transmit one. The polling process can be dis- to the system by writing a 0 to the OWN bit of RMD1 abled by setting the RXDPOLL (CSR7, bit 12) bit. This when the first buffer is full. The OWN bit is the only bit will stop the automatic polling process and the host modified in the descriptor. Receive data transfers to the must set the RDMD bit to initiate the receive process second buffer may occur before the Am79C972 con- into host memory. Receive frames are still stored even troller proceeds to look ahead to the ownership of the when the receive polling process is disabled. third buffer. Such action will depend upon the state of Software Interrupt Timer the FIFO when the OWN bit has been updated in the first descriptor. In any case, lookahead will be per- The Am79C972 controller is equipped with a software formed to the third buffer and the information gathered programmable free-running interrupt timer. The timer is will be stored in the chip, regardless of the state of the constantly running and will generate an interrupt STINT ownership bit. (CSR 7, bit 11) when STINITE (CSR 7, bit 10) is set to 1. After generating the interrupt, the software timer will This activity continues until the Am79C972 controller load the value stored in STVAL and restart. The timer recognizes the completion of the frame (the last byte of value STVAL (BCR31, bits 15-0) is interpreted as an this receive message has been removed from the unsigned number with a resolution of 256 Time Base FIFO). The Am79C972 controller will subsequently up- Clock periods. For instance, a value of 122 ms would date the current RDTE status with the end of frame be programmed with a value of 9531 (253Bh), if the (ENP) indication set, write the message byte count Time Base Clock is running at 20 MHz. The default (MCNT) for the entire frame into RMD2, and overwrite value of STVAL is FFFFh which yields the approximate the “current” entries in the CSRs with the “next” entries. maximum 838 ms timer duration. A write to STVAL re- Receive Frame Queuing starts the timer with the new contents of STVAL. The Am79C972 controller supports the lack of RDTEs when SRAM (SRAM SIZE in BCR 25, bits 7-0) is en- 56 Am79C972 utilization because the pad bytes are not transferred Media Access Control into or out of main memory. The Media Access Control (MAC) engine incorporates the essential protocol requirements for operation of an Framing Ethernet/IEEE 802.3-compliant node and provides the The MAC engine will autonomously handle the con- interface between the FIFO subsystem and the MII. struction of the transmit frame. Once the transmit FIFO has been filled to the predetermined threshold (set by This section describes operation of the MAC engine XMTSP in CSR80) and access to the channel is cur- when operating in half-duplex mode. When operating in rently permitted, the MAC engine will commence the 7- half-duplex mode, the MAC engine is fully compliant to byte preamble sequence (10101010b, where first bit Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard transmitted is a 1). The MAC engine will subsequently 1990 Second Edition) and ANSI/IEEE 802.3 (1985). append the Start Frame Delimiter (SFD) byte When operating in full-duplex mode, the MAC engine (10101011b) followed by the serialized data from the behavior changes as described in the section Full- transmit FIFO. Once the data has been completed, the Duplex Operation. MAC engine will append the FCS (most significant bit The MAC engine provides programmable enhanced first) which was computed on the entire data portion of features designed to minimize host supervision, bus the frame. The data portion of the frame consists of utilization, and pre- or post-message processing. destination address, source address, length/type, and These features include the ability to disable retries after frame data. The user is responsible for the correct or- a collision, dynamic FCS generation on a frame-by- dering and content in each of these fields in the frame. frame basis, automatic pad field insertion and deletion The MAC does not use the content in the length/type to enforce minimum frame size attributes, automatic re- field unless APAD_XMT (CSR4, bit 11) is set and the transmission without reloading the FIFO, and auto- data portion of the frame is shorter than 60 bytes. matic deletion of collision fragments. During GPSI operation, the MAC will discard the first 8 The two primary attributes of the MAC engine are: bits of information before searching for the SFD se- quence. Once the SFD is detected, all subsequent bits � Transmit and receive message data encapsulation are treated as part of the frame. During MII operation, — Framing (frame boundary delimitation, frame the MAC engine will detect the incoming preamble se- synchronization) quence when the RX_DV signal is activated by the ex- — Addressing (source and destination address ternal PHY. The MAC will discard the preamble and handling) begin searching for the SFD except in the case of 100BASE-T4. In that case, the SFD will be the first nib- — Error detection (physical medium transmission ble across the MII interface. Once the SFD is detected, errors) all subsequent nibbles are treated as part of the frame. � Media access management The MAC engine will inspect the length field to ensure minimum frame size, strip unnecessary pad characters — Medium allocation (collision avoidance, except (if enabled), and pass the remaining bytes through the in full-duplex operation) receive FIFO to the host. If pad stripping is performed, — Contention resolution (collision handling, except the MAC engine will also strip the received FCS bytes, in full-duplex operation) although normal FCS computation and checking will Transmit and Receive Message Data Encapsulation occur. Note that apart from pad stripping, the frame will be passed unmodified to the host. If the length field has The MAC engine provides minimum frame size en- a value of 46 or greater, all frame bytes including FCS forcement for transmit and receive frames. When will be passed unmodified to the receive buffer, regard- APAD_XMT (CSR, bit 11) is set to 1, transmit mes- less of the actual frame length. sages will be padded with sufficient bytes (containing 00h) to ensure that the receiving station will observe an If the frame terminates or suffers a collision before 64 information field (destination address, source address, bytes of information (after SFD) have been received, length/type, data, and FCS) of 64 bytes. When the MAC engine will automatically delete the frame ASTRP_RCV (CSR4, bit 10) is set to 1, the receiver will from the receive FIFO, without host intervention. The automatically strip pad bytes from the received mes- Am79C972 controller has the ability to accept runt sage by observing the value in the length field and by packets for diagnostic purposes and proprietary net- stripping excess bytes if this value is below the mini- works. mum data size (46 bytes). Both features can be inde- pendently over-ridden to allow illegally short (less than 64 bytes of frame data) messages to be transmitted Destination Address Handling and/or received. The use of this feature reduces bus The first 6 bytes of information after SFD will be inter- preted as the destination address field. The MAC en- Am79C972 57 gine provides facilities for physical (unicast), logical During the reception, the FCS is generated on every (multicast), and broadcast address reception. nibble (including the dribbling bits) coming from the ca- ble, although the internally saved FCS value is only up- Error Detection dated on the eighth bit (on each byte boundary). The The MAC engine provides several facilities which re- MAC engine will ignore up to 7 additional bits at the end port and recover from errors on the medium. In addi- of a message (dribbling bits), which can occur under tion, it protects the network from gross errors due to normal network operating conditions. The framing error inability of the host to keep pace with the MAC engine is reported to the user as follows: activity. � If the number of dribbling bits are 1 to 7 and there is On completion of transmission, the following transmit no FCS error, then there is no Framing error (FRAM status is available in the appropriate Transmit Message = 0). Descriptor (TMD) and Control and Status Register � If the number of dribbling bits are 1 to 7 and there is (CSR) areas: a FCS error, then there is also a Framing error � The number of transmission retry attempts (ONE, (FRAM = 1). MORE, RTRY, and TRC). � If the number of dribbling bits is 0, then there is no � Whether the MAC engine had to Defer (DEF) due to Framing error. There may or may not be a FCS er- channel activity. ror. � Excessive deferral (EXDEF), indicating that the � If the number of dribbling bits is EIGHT, then there transmitter experienced Excessive Deferral on this is no Framing error. FCS error will be reported and transmit frame, where Excessive Deferral is defined the receive message count will indicate one extra in the ISO 8802-3 (IEEE/ANSI 802.3) standard. byte. � Loss of Carrier (LCAR), indicating that there was an Media Access Management interruption in the ability of the MAC engine to mon- The basic requirement for all stations on the network is itor its own transmission. Repeated LCAR errors in- to provide fairness of channel allocation. The IEEE dicate a potentially faulty transceiver or network 802.3/Ethernet protocols define a media access mech- connection. anism which permits all stations to access the channel � Late Collision (LCOL) indicates that the transmis- with equality. Any node can attempt to contend for the sion suffered a collision after the slot time. This is in- channel by waiting for a predetermined time (Inter dicative of a badly configured network. Late Packet Gap) after the last activity, before transmitting collisions should not occur in a normal operating on the media. The channel is a multidrop communica- network. tions media (with various topological configurations permitted), which allows a single station to transmit and � Collision Error (CERR) indicates that the trans- all other stations to receive. If two nodes simulta- ceiver did not respond with an SQE Test message neously contend for the channel, their signals will inter- within the first 4 μs after a transmission was com- act causing loss of data, defined as a collision. It is the pleted. This may be due to a failed transceiver, dis- responsibility of the MAC to attempt to avoid and connected or faulty transceiver drop cable, or recover from a collision, to guarantee data integrity for because the transceiver does not support this fea- the end-to-end transmission to the receiving station. ture (or it is disabled). SQE Test is only valid for 10- Mbps networks. Medium Allocation In addition to the reporting of network errors, the MAC The IEEE/ANSI 802.3 standard (ISO/IEC 8802-3 1990) engine will also attempt to prevent the creation of any requires that the CSMA/CD MAC monitor the medium network error due to the inability of the host to service for traffic by watching for carrier activity. When carrier is the MAC engine. During transmission, if the host fails detected, the media is considered busy, and the MAC to keep the transmit FIFO filled sufficiently, causing an should defer to the existing message. underflow, the MAC engine will guarantee the message The ISO 8802-3 (IEEE/ANSI 802.3) standard also al- is either sent as a runt packet (which will be deleted by lows optionally a two-part deferral after a receive mes- the receiving station) or as an invalid FCS (which will sage. also cause the receiver to reject the message). See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1: The status of each receive message is available in the appropriate Receive Message Descriptor (RMD) and Note: It is possible for the PLS carrier sense indication CSR areas. All received frames are passed to the host to fail to be asserted during a collision on the media. If regardless of any error. The FRAM error will only be re- the deference process simply times the inter-Frame ported if an FCS error is detected and there is a non- gap based on this indication, it is possible for a short in- integral number of bytes in the message. terFrame gap to be generated, leading to a potential 58 Am79C972 reception failure of a subsequent frame. To enhance is increased from the default value, but the resulting be- system robustness, the following optional measures, havior may improve network performance by reducing as specified in 4.2.8, are recommended when Inter- collisions. The Am79C972 controller uses the same Frame-SpacingPart1 is other than 0: IPG for back-to-back transmits and receive-to-transmit accesses. Changing IFS1 will alter the period for which 1. Upon completing a transmission, start timing the in- the Am79C972 MAC engine will defer to incoming re- terrupted gap, as soon as transmitting and carrier ceive frames. sense are both false. CAUTION: Care must be exercised when altering 2. When timing an inter-frame gap following reception, these parameters. Adverse network activity could reset the inter-frame gap timing if carrier sense be- result! comes true during the first 2/3 of the inter-frame gap timing interval. During the final 1/3 of the interval, This transmit two-part deferral algorithm is imple- the timer shall not be reset to ensure fair access to mented as an option which can be disabled using the the medium. An initial period shorter than 2/3 of the DXMT2PD bit in CSR3. The IFS1 programming will interval is permissible including 0. have no effect when DXMT2PD is set to 1, but the IPG programming value is still valid. Two part deferral after The MAC engine implements the optional receive two transmission is useful for ensuring that severe IPG part deferral algorithm, with an InterFrameSpacing- shrinkage cannot occur in specific circumstances, Part1 time of 6.0 μs. The InterFrameSpacingPart 2 in- causing a transmit message to follow a receive mes- μs. terval is, therefore, 3.4 sage so closely as to make them indistinguishable. The Am79C972 controller will perform the two-part During the time period immediately after a transmission deferral algorithm as specified in Section 4.2.8 (Pro- has been completed, the external transceiver should cess Deference). The Inter Packet Gap (IPG) timer will generate the SQE Test message within 0.6 to 1.6 μs start timing the 9.6 μs InterFrameSpacing after the re- after the transmission ceases. During the time period in ceive carrier is deasserted. During the first part deferral which the SQE Test message is expected, the (InterFrameSpacingPart1 - IFS1), the Am79C972 con- Am79C972 controller will not respond to receive carrier troller will defer any pending transmit frame and re- sense. spond to the receive message. The IPG counter will be cleared to 0 continuously until the carrier deasserts, at See ANSI/IEEE Std 802.3-1993 Edition, 7.2.4.6 (1): which point the IPG counter will resume the 9.6 μs “At the conclusion of the output function, the DTE count once again. Once the IFS1 period of 6.0 μs has opens a time window during which it expects to see elapsed, the Am79C972 controller will begin timing the the signal_quality_error signal asserted on the second part deferral (InterFrameSpacingPart2 - IFS2) Control In circuit. The time window begins when of 3.4 μs. Once IFS1 has completed and IFS2 has com- the CARRIER_STATUS becomes menced, the Am79C972 controller will not defer to a re- CARRIER_OFF. If execution of the output function ceive frame if a transmit frame is pending. This means does not cause CARRIER_ON to occur, no SQE that the Am79C972 controller will not attempt to receive test occurs in the DTE. The duration of the window the receive frame, since it will start to transmit and gen- shall be at least 4.0 μs but no more than 8.0 μs. erate a collision at 9.6 μs. The Am79C972 controller During the time window the Carrier Sense Function will complete the preamble (64-bit) and jam (32-bit) se- is inhibited.” quence before ceasing transmission and invoking the random backoff algorithm. The Am79C972 controller implements a carrier sense The Am79C972 controller allows the user to program “blinding” period of 4.0 μs length starting from the the IPG and the first part deferral (InterFrame- deassertion of carrier sense after transmission. This ef- SpacingPart1 - IFS1) through CSR125. By changing fectively means that when transmit two part deferral is the IPG default value of 96 bit times (60h), the user can enabled (DXMT2PD is cleared), the IFS1 time is from adjust the fairness or aggressiveness of the 4 μs to 6 μs after a transmission. However, since IPG Am79C972 MAC on the network. By programming a shrinkage below 4 μs will rarely be encountered on a lower number of bit times than the ISO/IEC 8802-3 correctly configured network, and since the fragment standard requires, the Am79C972 MAC engine will be- size will be larger than the 4 μs blinding window, the come more aggressive on the network. This aggressive IPG counter will be reset by a worst case IPG shrink- nature will give rise to the Am79C972 controller possi- age/fragment scenario and the Am79C972 controller bly capturing the network at times by forcing other less will defer its transmission. If carrier is detected within aggressive compliant nodes to defer. By programming the 4.0 to 6.0 μs IFS1 period, the Am79C972 controller a larger number of bit times, the Am79C972 MAC will will not restart the “blinding” period, but only restart become less aggressive on the network and may defer IFS1. more often than normal. The performance of the Am79C972 controller may decrease as the IPG value Am79C972 59 Collision Handling collision to access the channel, while the colliding nodes await a reduction in channel activity. Once chan- Collision detection is performed and reported to the nel activity is reduced, the nodes resolving the collision MAC engine via the COL/CLSN input pin. time-out their slot time counters as normal. If a collision is detected before the complete preamble/ This modified backoff algorithm is enabled when EMBA SFD sequence has been transmitted, the MAC engine (CSR3, bit 3) is set to 1. will complete the preamble/SFD before appending the jam sequence. If a collision is detected after the pream- Transmit Operation ble/SFD has been completed, but prior to 512 bits The transmit operation and features of the Am79C972 being transmitted, the MAC engine will abort the trans- controller are controlled by programmable options. The mission and append the jam sequence immediately. Am79C972 controller offers a large transmit FIFO to The jam sequence is a 32-bit all zeros pattern. provide frame buffering for increased system latency, The MAC engine will attempt to transmit a frame a total automatic retransmission with no FIFO reload, and au- of 16 times (initial attempt plus 15 retries) due to nor- tomatic transmit padding. mal collisions (those within the slot time). Detection of Transmit Function Programming collision will cause the transmission to be rescheduled to a time determined by the random backoff algorithm. Automatic transmit features such as retry on collision, If a single retry was required, the 1 bit will be set in the FCS generation/transmission, and pad field insertion transmit frame status. If more than one retry was re- can all be programmed to provide flexibility in the (re-) quired, the MORE bit will be set. If all 16 attempts ex- transmission of messages. perienced collisions, the RTRY bit will be set (1 and Disable retry on collision (DRTY) is controlled by the MORE will be clear), and the transmit message will be DRTY bit of the Mode register (CSR15) in the initializa- flushed from the FIFO. If retries have been disabled by tion block. setting the DRTY bit in CSR15, the MAC engine will abandon transmission of the frame on detection of the Automatic pad field insertion is controlled by the first collision. In this case, only the RTRY bit will be set APAD_XMT bit in CSR4. and the transmit message will be flushed from the The disable FCS generation/transmission feature can FIFO. be programmed as a static feature or dynamically on a If a collision is detected after 512 bit times have been frame-by-frame basis. transmitted, the collision is termed a late collision. The Transmit FIFO Watermark (XMTFW) in CSR80 sets the MAC engine will abort the transmission, append the point at which the BMU requests more data from the jam sequence, and set the LCOL bit. No retry attempt transmit buffers for the FIFO. A minimum of XMTFW will be scheduled on detection of a late collision, and empty spaces must be available in the transmit FIFO the transmit message will be flushed from the FIFO. before the BMU will request the system bus in order to The ISO 8802-3 (IEEE/ANSI 802.3) Standard requires transfer transmit frame data into the transmit FIFO. use of a “truncated binary exponential backoff” algo- Transmit Start Point (XMTSP) in CSR80 sets the point rithm, which provides a controlled pseudo random when the transmitter actually attempts to transmit a mechanism to enforce the collision backoff interval, frame onto the media. A minimum of XMTSP bytes before retransmission is attempted. must be written to the transmit FIFO for the current See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5: frame before transmission of the current frame will be- gin. (When automatically padded packets are being “At the end of enforcing a collision (jamming), the sent, it is conceivable that the XMTSP is not reached CSMA/CD sublayer delays before attempting to re- when all of the data has been transferred to the FIFO. transmit the frame. The delay is an integer multiple In this case, the transmission will begin when all of the of slot time. The number of slot times to delay be- frame data has been placed into the transmit FIFO.) fore the nth retransmission attempt is chosen as a The default value of XMTSP is 01b, meaning there has uniformly distributed random integer r in the range: to be 64 bytes in the transmit FIFO to start a transmis- k sion. 0 ≤ r < 2 where k = min (n,10).” Automatic Pad Generation The Am79C972 controller provides an alternative algo- Transmit frames can be automatically padded to extend rithm, which suspends the counting of the slot time/IPG them to 64 data bytes (excluding preamble). This al- during the time that receive carrier sense is detected. lows the minimum frame size of 64 bytes (512 bits) for This aids in networks where large numbers of nodes IEEE 802.3/Ethernet to be guaranteed with no software are present, and numerous nodes can be in collision. It intervention from the host/controlling process. Setting effectively accelerates the increase in the backoff time the APAD_XMT bit in CSR4 enables the automatic in busy networks and allows nodes not involved in the 60 Am79C972 padding feature. The pad is placed between the LLC defined in the ISO 8802-3 (IEEE/ANSI 802.3) stan- data field and FCS field in the IEEE 802.3 frame. FCS dard). The length value contained in the message is not is always added if the frame is padded, regardless of used by the Am79C972 controller to compute the ac- the state of DXMTFCS (CSR15, bit 3) or ADD_FCS tual number of pad bytes to be inserted. The (TMD1, bit 29). The transmit frame will be padded by Am79C972 controller will append pad bytes dependent bytes with the value of 00H. The default value of on the actual number of bits transmitted onto the net- APAD_XMT is 0, which will disable automatic pad gen- work. Once the last data byte of the frame has com- eration after H_RESET. pleted, prior to appending the FCS, the Am79C972 controller will check to ensure that 544 bits have been It is the responsibility of upper layer software to cor- transmitted. If not, pad bytes are added to extend the rectly define the actual length field contained in the frame size to this value, and the FCS is then added. message to correspond to the total number of LLC See Figure 33. Data bytes encapsulated in the frame (length field as . Preamble SFD Destination Source LLC Length Pad FCS 1010....1010 10101011 Address Address Data 56 8 6 6 2 4 Bits Bits Bytes Bytes Bytes Bytes 46 — 1500 Bytes 21485C-36 Figure 33. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame The 544 bit count is derived from the following: ADD_FCS (TMD1, bit 29) allows the automatic gener- ation and transmission of FCS on a frame-by-frame Minimum frame size (excluding preamble/SFD, basis. DXMTFCS should be set to 1 in this mode. To including FCS) 64 bytes 512 bits generate FCS for a frame, ADD_FCS must be set in all Preamble/SFD size 8 bytes 64 bits descriptors of a frame (STP is set to 1). Note that bit 29 of TMD1 has the function of ADD_FCS if SWSTYLE FCS size 4 bytes 32 bits (BCR20, bits 7-0) is programmed to 0, 2, or 3. At the point that FCS is to be appended, the transmitted Transmit Exception Conditions frame should contain: Exception conditions for frame transmission fall into Preamble/SFD + (Min Frame Size - FCS) two distinct categories: those conditions which are the result of normal network operation, and those which 64 + (512-32) = 544 bits occur due to abnormal network and/or host related A minimum length transmit frame from the Am79C972 events. controller, therefore, will be 576 bits, after the FCS is Normal events which may occur and which are handled appended. autonomously by the Am79C972 controller include col- Transmit FCS Generation lisions within the slot time with automatic retry. The Automatic generation and transmission of FCS for a Am79C972 controller will ensure that collisions which transmit frame depends on the value of DXMTFCS occur within 512 bit times from the start of transmission (CSR15, bit 3). If DXMTFCS is cleared to 0, the trans- (including preamble) will be automatically retried with mitter will generate and append the FCS to the trans- no host intervention. The transmit FIFO ensures this by mitted frame. If the automatic padding feature is guaranteeing that data contained within the FIFO will invoked (APAD_XMT is set in CSR4), the FCS will be not be overwritten until at least 64 bytes (512 bits) of appended to frames shorter than 64 bytes by the preamble plus address, length, and data fields have Am79C972 controller regardless of the state of DXMT- been transmitted onto the network without encounter- FCS or ADD_FCS (TMD1, bit 29). Note that the calcu- ing a collision. Note that if DRTY (CSR15, bit 5) is set lated FCS is transmitted most significant bit first. The to 1 or if the network interface is operating in full-duplex default value of DXMTFCS is 0 after H_RESET. mode, no collision handling is required, and any byte of Am79C972 61 frame data in the FIFO can be overwritten as soon as it Receive Operation is transmitted. The receive operation and features of the Am79C972 If 16 total attempts (initial attempt plus 15 retries) fail, controller are controlled by programmable options. The the Am79C972 controller sets the RTRY bit in the cur- Am79C972 controller offers a large receive FIFO to rent transmit TDTE in host memory (TMD2), gives up provide frame buffering for increased system latency, ownership (resets the OWN bit to 0) for this frame, and automatic flushing of collision fragments (runt packets), processes the next frame in the transmit ring for trans- automatic receive pad stripping, and a variety of ad- mission. dress match options. Abnormal network conditions include: Receive Function Programming Automatic pad field stripping is enabled by setting the � Loss of carrier ASTRP_RCV bit in CSR4. This can provide flexibility in � Late collision the reception of messages using the IEEE 802.3 frame � SQE Test Error (Does not apply to 100-Mbps net- format. works.) All receive frames can be accepted by setting the These conditions should not occur on a correctly con- PROM bit in CSR15. Acceptance of unicast and broad- figured IEEE 802.3 network operating in half-duplex cast frames can be individually turned off by setting the mode. If they do, they will be reported. None of these DRCVPA or DRCVBC bits in CSR15. The Physical Ad- conditions will occur on a network operating in full- dress register (CSR12 to CSR14) stores the address duplex mode. (See the section Full-Duplex Operation that the Am79C972 controller compares to the destina- for more detail.) tion address of the incoming frame for a unicast ad- dress match. The Logical Address Filter register When an error occurs in the middle of a multi-buffer (CSR8 to CSR11) serves as a hash filter for multicast frame transmission, the error status will be written in the address match. current descriptor. The OWN bit(s) in the subsequent descriptor(s) will be cleared until the STP (the next The point at which the BMU will start to transfer data frame) is found. from the receive FIFO to buffer memory is controlled by the RCVFW bits in CSR80. The default established Loss of Carrier during H_RESET is 01b, which sets the watermark flag When operating in half-duplex mode, a loss of carrier at 64 bytes filled. condition will be reported if the Am79C972 controller For test purposes, the Am79C972 controller can be cannot observe receive activity while it is transmitting programmed to accept runt packets by setting RPA in on the GPSI port. CSR124. When the MII port is selected, LCAR will be reported Address Matching for every frame transmitted if the controller detects a loss of carrier. The Am79C972 controller supports three types of ad- dress matching: unicast, multicast, and broadcast. The Late Collision normal address matching procedure can be modified A late collision will be reported if a collision condition by programming three bits in CSR15, the mode register occurs after one slot time (512 bit times) after the trans- (PROM, DRCVPA, and DRCVBC). mit process was initiated (first bit of preamble com- If the first bit received after the SFD (the least signifi- menced). The Am79C972 controller will abandon the cant bit of the first byte of the destination address field) transmit process for that frame, set Late Collision is 0, the frame is unicast, which indicates that the frame (LCOL) in the associated TMD2, and process the next is meant to be received by a single node. If the first bit transmit frame in the ring. Frames experiencing a late received is 1, the frame is multicast, which indicates collision will not be retried. Recovery from this condi- that the frame is meant to be received by a group of tion must be performed by upper layer software. nodes. If the destination address field contains all 1s, SQE Test Error the frame is broadcast, which is a special type of multi- In GPSI mode, CLSN must be asserted after the trans- cast. Frames with the broadcast address in the destina- mission or otherwise CERR will be set. CERR will be tion address field are meant to be received by all nodes asserted in the 10BASE-T mode through the MII after on the local area network. transmit, if the network port is in Link Fail state. CERR When a unicast frame arrives at the Am79C972 con- will never cause INTA to be activated. It will, however, troller, the controller will accept the frame if the destina- set the ERR bit CSR0. tion address field of the incoming frame exactly matches the 6-byte station address stored in the Phys- ical Address registers (PADR, CSR12 to CSR14). The 62 Am79C972 byte ordering is such that the first byte received from If DRCVBC (CSR15, bit 14) is cleared to 0, only BAM, the network (after the SFD) must match the least signif- but not LAFM will be set when a Broadcast frame is re- icant byte of CSR12 (PADR[7:0]), and the sixth byte re- ceived, even if the Logical Address Filter is pro- ceived must match the most significant byte of CSR14 grammed in such a way that a Broadcast frame would (PADR[47:40]). pass the hash filter. If DRCVBC is set to 1 and the Log- ical Address Filter is programmed in such a way that a When DRCVPA (CSR15, bit 13) is set to 1, the Broadcast frame would pass the hash filter, LAFM will Am79C972 controller will not accept unicast frames. be set on the reception of a Broadcast frame. If the incoming frame is multicast, the Am79C972 con- When the Am79C972 controller operates in promiscu- troller performs a calculation on the contents of the ous mode and none of the three match bits is set, it is destination address field to determine whether or not to an indication that the Am79C972 controller only ac- accept the frame. This calculation is explained in the cepted the frame because it was in promiscuous mode. section that describes the Logical Address Filter (LADRF). When the Am79C972 controller is not programmed to be in promiscuous mode, but the EADI interface is en- When all bits of the LADRF registers are 0, no multicast abled, then when none of the three match bits is set, it frames are accepted, except for broadcast frames. is an indication that the Am79C972 controller only ac- Although broadcast frames are classified as special cepted the frame because it was not rejected by driving pin LOW within 64 bytes after SFD. multicast frames, they are treated differently by the the EAR Am79C972 controller hardware. Broadcast frames are See Table 6 for receive address matches. always accepted, except when DRCVBC (CSR15, bit 14) is set and there is no Logical Address match. Table 6. Receive Address Match None of the address filtering described above applies LAF DRC when the Am79C972 controller is operating in the pro- PAM MBAM VBC Comment miscuous mode. In the promiscuous mode, all properly Frame accepted due to formed packets are received, regardless of the con- 00 0 X PROM = 1 or no EADI tents of their destination address fields. The promiscu- reject ous mode overrides the Disable Receive Broadcast bit 1 0 0 X Physical address match (DRCVBC bit l4 in the MODE register) and the Disable Logical address filter Receive Physical Address bit (DRCVPA, CSR15, bit match; 13). 01 00 frame is not of type The Am79C972 controller operates in promiscuous broadcast mode when PROM (CSR15, bit 15) is set. Logical address filter match; In addition, the Am79C972 controller provides the Ex- 01 01 frame can be of type ternal Address Detection Interface (EADI) to allow ex- broadcast ternal address filtering. See the section External 00 10 Broadcast frame Address Detection Interface for further detail. Automatic Pad Stripping The receive descriptor entry RMD1 contains three bits that indicate which method of address matching During reception of an IEEE 802.3 frame, the pad field caused the Am79C972 controller to accept the frame. can be stripped automatically. Setting ASTRP_RCV Note that these indicator bits are only available when (CSR4, bit 0) to 1 enables the automatic pad stripping the Am79C972 controller is programmed to use 32-bit feature. The pad field will be stripped before the frame structures for the descriptor entries (BCR20, bit 7-0, is passed to the FIFO, thus preserving FIFO space for SWSTYLE is set to 2 or 3). additional frames. The FCS field will also be stripped, since it is computed at the transmitting station based on PAM (RMD1, bit 22) is set by the Am79C972 controller the data and pad field characters, and will be invalid for when it accepted the received frame due to a match of a receive frame that has had the pad characters the frame’s destination address with the content of the stripped. physical address register. The number of bytes to be stripped is calculated from LAFM (RMD1, bit 21) is set by the Am79C972 control- the embedded length field (as defined in the ISO 8802- ler when it accepted the received frame based on the 3 (IEEE/ANSI 802.3) definition) contained in the frame. value in the logical address filter register. The length indicates the actual number of LLC data BAM (RMD1, bit 20) is set by the Am79C972 controller bytes contained in the message. Any received frame when it accepted the received frame because the which contains a length field less than 46 bytes will have frame’s destination address is of the type ’Broadcast’. the pad field stripped (if ASTRP_RCV is set). Receive Am79C972 63 frames which have a length field of 46 bytes or greater Figure 34 shows the byte/bit ordering of the received will be passed to the host unmodified. length field for an IEEE 802.3-compatible frame format. 46 — 1500 Bytes 56 8 6 6 2 4 Bits Bits Bytes Bytes Bytes Bytes Preamble SFD Destination Source LLC Length Pad FCS 1010....1010 10101011 Address Address Data 1 — 1500 45 — 0 Bytes Bytes Start of Frame at Time = 0 Bit Bit Bit Bit 0 7 0 7 Increasing Time Most Least Significant Significant Byte Byte 21485C-37 Figure 34. IEEE 802.3 Frame And Length Field Transmission Order Since any valid Ethernet Type field value will always be cally collisions within the slot time and automatic runt greater than a normal IEEE 802.3 Length field (≥46), packet rejection. The Am79C972 controller will ensure the Am79C972 controller will not attempt to strip valid that collisions that occur within 512 bit times from the Ethernet frames. Note that for some network protocols, start of reception (excluding preamble) will be automat- the value passed in the Ethernet Type and/or IEEE ically deleted from the receive FIFO with no host inter- 802.3 Length field is not compliant with either standard vention. The receive FIFO will delete any frame that is and may cause problems if pad stripping is enabled. composed of fewer than 64 bytes provided that the Runt Packet Accept (RPA bit in CSR124) feature has Receive FCS Checking not been enabled and the network interface is operat- Reception and checking of the received FCS is per- ing in half-duplex mode, or the full-duplex Runt Packet formed automatically by the Am79C972 controller. Accept Disable bit (FDRPAD, BCR9, bit 2) is set. This Note that if the Automatic Pad Stripping feature is en- criterion will be met regardless of whether the receive abled, the FCS for padded frames will be verified frame was the first (or only) frame in the FIFO or if the against the value computed for the incoming bit stream receive frame was queued behind a previously re- including pad characters, but the FCS value for a pad- ceived message. ded frame will not be passed to the host. If an FCS Abnormal network conditions include: error is detected in any frame, the error will be reported in the CRC bit in RMD1. � FCS errors Receive Exception Conditions � Late collision Exception conditions for frame reception fall into two Host related receive exception conditions include distinct categories, i.e., those conditions which are the MISS, BUFF, and OFLO. These are described in the result of normal network operation, and those which section, Buffer Management Unit. occur due to abnormal network and/or host related Loopback Operation events. Loopback is a mode of operation intended for system Normal events which may occur and which are handled diagnostics. In this mode, the transmitter and receiver autonomously by the Am79C972 controller are basi- 64 Am79C972 are both operating at the same time so that the control- During the internal loopback, the TXD, TX_CLK, and ler receives its own transmissions. The controller pro- TX_EN pins will toggle appropriately with the correct vides two basic types of loopback. In internal loopback data. mode, the transmitted data is looped back to the re- Miscellaneous Loopback Features ceiver inside the controller without actually transmitting All transmit and receive function programming, such as any data to the external network. The receiver will automatic transmit padding and receive pad stripping, move the received data to the next receive buffer, operates identically in loopback as in normal operation. where it can be examined by software. Alternatively, in external loopback mode, data can be transmitted to Runt Packet Accept is internally enabled (RPA bit in and received from the external network. CSR124 is not affected) when any loopback mode is in- voked. This is to be backwards compatible to the C- Refer to Table 21 for various bit settings required for LANCE (Am79C90) software. Loopback modes. Since the Am79C972 controller has two FCS genera- GPSI Loopback Modes tors, there are no more restrictions on FCS generation When GPSI is the active network port, there are only or checking, or on testing multicast address detection two modes of loopback operation: internal and external as they exist in the half-duplex PCnet family devices loopback. Loopback operation is enabled by setting and in the C-LANCE. On receive, the Am79C972 con- LOOP (CSR15, bit 2) to 1. troller now provides true FCS status. The descriptor for When INTL is set to 1, internal loopback is selected. a frame with an FCS error will have the FCS bit (RMD1, Data coming out of the transmit FIFO is fed directly to bit 27) set to 1. The FCS generator on the transmit side the receive FIFO. All GPSI outputs are inactive; inputs can still be disabled by setting DXMTFCS (CSR15, bit are ignored. 3) to 1. External loopback operation is selected by setting INTL In internal loopback operation, the Am79C972 control- to 0. Data is transmitted to the network and is expected ler provides a special mode to test the collision logic. to be looped back to the GPSI receive pins outside the When FCOLL (CSR15, bit 4) is set to 1, a collision is chip. Collision detection is active in this mode. forced during every transmission attempt. This will re- sult in a Retry error. Media Independent Interface Loopback Features General Purpose Serial Interface Loopback through the MII can be handled in two ways. The Am79C972 controller supports an internal MII The General Purpose Serial Interface (GPSI) provides loopback and an external MII loopback. The MII a direct interface to the MAC section of the Am79C972 loopback requires that the MII port be manually config- controller. All signals are digital and data is non-en- ured through software using ASEL (BCR 2, bit 1) and coded. The GPSI allows use of an external Manchester PORTSEL (CSR 15, bits 8-7). encoder/decoder such as the Am7992B Serial Inter- face Adapter (SIA). In addition, it allows the Am79C972 The external loopback through the MII requires a two- controller to be used as a MAC sublayer engine in re- step operation. The external PHY must be placed into peater designs based on the IMR+ device a loopback mode by writing to the MII Control Register (Am79C981). (BCR33, BCR34). Then the Am79C972 controller must be placed into an external loopback mode by setting GPSI mode is invoked by selecting the interface the Loop bits. through the PORTSEL bits of the Mode register (CSR15, bits 8-7). The internal loopback through the MII is controlled by MIIILP (BCR32, bit 1). When set to 1, this bit will cause The GPSI interface uses some of the same pins as the the internal portion of the MII data port to loopback on interface to the MII. Simultaneous use of both functions itself. The MII management port (MDC, MDIO) is unaf- is not possible. fected by the MIILP bit. The internal MII interface is After an H_RESET, all MII pins are internally config- mapped in the following way: ured to function as the MII interface. When the GPSI in- � The TXD[3:0] nibble data path is looped back onto terface is selected by setting PORTSEL (CSR15, bits the RXD[3:0] nibble data path; 8-7) to 10b, the Am79C972 controller will terminate all further accesses to the MII. � TX_CLK is looped back as RX_CLK; � TX_EN is looped back as RX_DV. GPSI signal functions are described in the pin descrip- tion section under the GPSI subheading. � CRS is correctly OR’d with TX_EN and RX_DV and always encompasses the transmit frame. Full-Duplex Operation � TX_ER is not driven by the Am79C972 and there- The Am79C972 controller supports full-duplex opera- fore not looped back. tion on both network interfaces. Full-duplex operation Am79C972 65 allows simultaneous transmit and receive activity on the � Changes to the Transmit Deferral mechanism: TXDAT and RXDAT pins of the GPSI port, and the — Transmission is not deferred while receive is TXD[3:0] and RXD[3:0] pins of the MII port. Full-duplex active. operation is enabled by the FDEN bit located in BCR9 — The IPG counter which governs transmit deferral for all ports. Full-duplex operation is also enabled during the IPG between back-to-back transmits through Auto-Negotiation when DANAS (BCR 32, bit 7) is started when transmit activity for the first is not enabled on the MII port and the ASEL bit is set, packet ends, instead of when transmit and car- and both the external PHY and its link partner are ca- rier activity ends. pable of Auto-Negotiation and full-duplex operation. � The 4.0 µs carrier sense blinding period after a When operating in full-duplex mode, the following transmission during which the SQE test normally changes to the device operation are made: occurs is disabled. Bus Interface/Buffer Management Unit changes: � The collision indication input to the MAC engine is ignored. � The first 64 bytes of every transmit frame are not preserved in the Transmit FIFO during transmission The MII changes for full-duplex operation are as fol- of the first 512 bits as described in the Transmit Ex- lows: ception Conditions section. Instead, when full-du- � The collision detect (COL) pin is disabled. plex mode is active and a frame is being transmitted, the XMTFW bits (CSR80, bits 9-8) always govern � The SQE test function is disabled. when transmit DMA is requested. � Loss of Carrier (LCAR) reporting is disabled. � Successful reception of the first 64 bytes of every Full-Duplex Link Status LED Support receive frame is not a requirement for Receive DMA to begin as described in the Receive Exception Con- The Am79C972 controller provides bits in each of the ditions section. Instead, receive DMA will be re- LED Status registers (BCR4, BCR5, BCR6, BCR7) to quested as soon as either the RCVFW threshold display the Full-Duplex Link Status. If the FDLSE bit (bit (CSR80, bits 12-13) is reached or a complete valid 8) is set, a value of 1 will be sent to the associated LED- receive frame is detected, regardless of length. This OUT bit when in Full-Duplex. Receive FIFO operation is identical to when the RPA bit (CSR124, bit 3) is set during half-duplex mode operation. The MAC engine changes for full-duplex operation are as follows: 66 Am79C972 (4 bits) data path, TXD(3:0), from the Am79C972 con- Media Independent Interface troller to the external PHY and is synchronous to the The Am79C972 controller fully supports the MII ac- rising edge of TX_CLK. The transmit process starts cording to the IEEE 802.3 standard. This Reconcilia- when the Am79C972 controller asserts the TX_EN, tion Sublayer interface allows a variety of PHYs which indicates to the external PHY that the data on (100BASE-TX, 100BASE-FX, 100BASE-T4, TXD(3:0) is valid. 100BASE-T2, 10BASE-T, etc.) to be attached to the Am79C972 MAC engine without future upgrade prob- Normally, unrecoverable errors are signaled through lems. The MII interface is a 4-bit (nibble) wide data path the MII to the external PHY with the TX_ER output pin. interface that runs at 25 MHz for 100-Mbps networks or The external PHY will respond to this error by generat- 2.5 MHz for 10-Mbps networks. The interface consists ing a TX coding error on the current transmitted frame. of two independent data paths, receive (RXD(3:0)) and The Am79C972 controller does not use this method of transmit (TXD(3:0)), control signals for each data path signaling errors on the transmit side. The Am79C972 (RX_ER, RX_DV, TX_ER, TX_EN), network status sig- controller will invert the FCS on the last byte generating nals (COL, CRS), clocks (RX_CLK, TX_CLK) for each an invalid FCS. The TX_ER pin is reserved for future data path, and a two-wire management interface (MDC use and is actively driven to 0. and MDIO). See Figure 35. MII Receive Interface MII Transmit Interface The MII receive clock is also generated by the external The MII transmit clock is generated by the external PHY and is sent to the Am79C972 controller on the PHY and is sent to the Am79C972 controller on the RX_CLK input pin. The clock will be the same fre- TX_CLK input pin. The clock can run at 25 MHz or 2.5 quency as the TX_CLK but will be out of phase and can MHz, depending on the speed of the network to which run at 25 MHz or 2.5 MHz, depending on the speed of the external PHY is attached. The data is a nibble-wide the network to which the external PHY is attached. 4 RXD(3:0) RX_DV Receive Signals RX_ER RX_CLK CRS Network Status Signals COL 4 Am79C972 TXD(3:0) TX_EN Transmit Signals TX_CLK MDC Management Port Signals MDIO 21485C-38 Figure 35. Media Independent Interface The RX_CLK is a continuous clock during the reception The receive process starts when RX_DV is asserted. of the frame, but can be stopped for up to two RX_CLK RX_DV will remain asserted until the end of the receive periods at the beginning and the end of frames, so that frame. The Am79C972 controller requires CRS (Car- the external PHY can sync up to the network data traffic rier Sense) to toggle in between frames in order to re- necessary to recover the receive clock. During this ceive them properly. Errors in the currently received time, the external PHY may switch to the TX_CLK to frame are signaled across the MII by the RX_ER pin. maintain a stable clock on the receive interface. The RX_ER can be used to signal special conditions out of Am79C972 controller will handle this situation with no band when RX_DV is not asserted. Two defined out-of- loss of data. The data is a nibble-wide (4 bits) data band conditions for this are the 100BASE-TX signaling path, RXD(3:0), from the external PHY to the of bad Start of Frame Delimiter and the 100BASE-T4 Am79C972 controller and is synchronous to the rising indication of illegal code group before the receiver has edge of RX_CLK. synched to the incoming data. The Am79C972 control- ler will not respond to these conditions. All out of band Am79C972 67 MII Interface conditions are currently treated as NULL events. Cer- ware support of the external PHY device without soft- tain in band non-IEEE 802.3u-compliant flow control ware support. The PHY address of 1Fh is reserved and sequences may cause erratic behavior for the should not be used. To access the 31 external PHYs, Am79C972 controller. Consult the switch/bridge/router/ the software driver must have knowledge of the exter- hub manual to disable the in-band flow control se- nal PHY’s address when multiple PHYs are present be- quences if they are being used. fore attempting to address it. MII Network Status Interface The MII Management Interface uses the MII Control, Address, and Data registers (BCR32, 33, 34) to control The MII also provides signals that are consistent and and communicate to the external PHYs. The necessary for IEEE 802.3 and IEEE 802.3u operation. Am79C972 controller generates MII management These signals are CRS (Carrier Sense) and COL (Col- frames to the external PHY through the MDIO pin syn- lision Sense). Carrier Sense is used to detect non-idle chronous to the rising edge of the Management Data activity on the network. Collision Sense is used to indi- Clock (MDC) based on a combination of writes and cate that simultaneous transmission has occurred in a reads to these registers. half-duplex network. MII Management Frames MII Management Interface MII management frames are automatically generated The MII provides a two-wire management interface so by the Am79C972 controller and conform to the MII that the Am79C972 controller can control and receive clause in the IEEE 802.3u standard. status from external PHY devices. The start of the frame is a preamble of 32 ones and The Am79C972 controller can support up to 31 exter- guarantees that all of the external PHYs are synchro- nal PHYs attached to the MII Management Interface nized on the same interface. (See Figure 36.) Loss of with software support and only one such device without synchronization is possible due to the hot-plugging ca- software support. pability of the exposed MII. The Network Port Manager copies the PHYAD after the The IEEE 802.3 specification allows you to drop the Am79C972 controller reads the EEPROM and uses it preamble, if after reading the MII Status Register from to communicate with the external PHY. The PHY ad- the external PHY you can determine that the external dress must be programmed into the EEPROM prior to PHY will support Preamble Suppression (BCR34, bit starting the Am79C972 controller. This is necessary so 6). After having a valid MII Status Register read, the that the internal management controller can work au- Am79C972 controller will then drop the creation of the tonomously from the software driver and can always preamble stream until a reset occurs, receives a read know where to access the external PHY. The error, or the external PHY is disconnected. Am79C972 controller is unique by offering direct hard- OP TA Preamble ST PHY Register Data Idle Z0 Rd 10 Rd 1111....1111 01 Address Address Z 10 Wr 01 Wr 2 32 2 5 5 2 16 1 Bits Bits Bits Bits Bits Bits Bit Bits 21485C-39 Figure 36. Frame Format at the MII Interface Connection This is followed by a start field (ST) and an operation dor. This field is followed by a bus turnaround field. Dur- field (OP). The operation field (OP) indicates whether ing a read operation, the bus turnaround field is used to the Am79C972 controller is initiating a read or write op- determine if the external PHY is responding correctly to eration. This is followed by the external PHY address the read request or not. The Am79C972 controller will (PHYAD) and the register address (REGAD) pro- tri-state the MDIO for both MDC cycles. grammed in BCR33. The PHY address of 1Fh is re- During the second cycle, if the external PHY is syn- served and should not be used. The external PHY may chronized to the Am79C972 controller, the external have a larger address space starting at 10h - 1Fh. This PHY will drive a 0. If the external PHY does not drive a is the address range set aside by the IEEE as vendor 0, the Am79C972 controller will signal a MREINT usable address space and will vary from vendor to ven- (CSR7, bit 9) interrupt, if MREINTE (CSR7, bit 8) is set 68 Am79C972 to a 1, indicating the Am79C972 controller had an MII ensure backwards compatibility with existing software management frame read error and that the data in drivers. To the current software drivers, the Am79C972 BCR34 is not valid. The data field to/from the external controller will look and act like the PCnet-PCI II and will PHY is read or written into the BCR34 register. The last interoperate with existing PCnet drivers from revision field is an IDLE field that is necessary to give ample 2.5 upward. The heart of this system is the Network time for drivers to turn off before the next access. The Port Manager. Am79C972 controller will drive the MDC to 0 and tri- If the external PHY is present and is active, the Net- state the MDIO anytime the MII Management Port is work Port Manager will request status from the external not active. PHY by generating MII management frames. These To help to speed up the reading and writing of the MII frames will be sent roughly every 900 ms. These management frames to the external PHY, the MDC can frames are necessary so that the Network Port Man- be sped up to 10 MHz by setting the FMDC bits in ager can monitor the current active link and can select BCR32. The IEEE 802.3 specification requires use of a different network port if the current link goes down. the 2.5-MHz clock rate, but 5 MHz and 10 MHz are Auto-Negotiation available for the user. The intended applications are that the 10-MHz clock rate can be used for a single ex- Through the external PHY, the following capabilities are ternal PHY on an adapter card or motherboard. The 5- possible: 100BASE-T4, 100BASE-TX Full-/Half-Du- MHz clock rate can be used for an exposed MII with plex, and 10BASE-T Full-/Half-Duplex. The capabilities one external PHY attached. The 2.5-MHz clock rate is are then sent to a link partner that will also send its ca- intended to be used when multiple external PHYs are pabilities. Both sides look to see what is possible and connected to the MII Management Port or if compli- then they will connect at the greatest possible speed ance to the IEEE 802.3u standard is required. and capability as defined in the IEEE 802.3u standard and according to Table 7. Auto-Poll External PHY Status Polling By default, the link partner must be at least 10BASE-T As defined in the IEEE 802.3 standard, the external half-duplex capable. The Am79C972 controller can au- PHY attached to the Am79C972 controller’s MII has no tomatically negotiate with the network and yield the way of communicating important timely status informa- highest performance possible without software sup- tion back to Am79C972 controller. The Am79C972 port. See the section on Network Port Manager for controller has no way of knowing that an external PHY more details. has undergone a change in status without polling the MII status register. To prevent problems from occurring with inadequate host or software polling, the Table 7. Auto-Negotiation Capabilities Am79C972 controller will Auto-Poll when APEP (BCR32, bit 11) is set to 1 to insure that the most cur- Network Speed Physical Network Type rent information is available. See Appendix C, MII 200 Mbps 100BASE-X, Full Duplex Management Registers, for the bit descriptions of the MII Status Register. The contents of the latest read 100 Mbps 100BASE-T4, Half Duplex from the external PHY will be stored in a shadow regis- ter in the Auto-Poll block. The first read of the MII Status 100 Mbps 100BASE-X, Half Duplex Register will just be stored, but subsequent reads will be compared to the contents already stored in the 20 Mbps 10BASE-T, Full Duplex shadow register. If there has been a change in the con- 10 Mbps 10BASE-T, Half Duplex tents of the MII Status Register, a MAPINT (CSR7, bit 7) interrupt will be generated on INTA if the MAPINTE Auto-Negotiation goes further by providing a message- (CSR7, bit 6) is set to 1. The Auto-Poll features can be based communication scheme called, Next Pages, be- disabled if software driver polling is required. fore connecting to the Link Partner. This feature is not The Auto-Poll’s frequency of generating MII manage- supported in Am79C972 unless the DANAS (BCR32, ment frames can be adjusted by setting of the APDW bit 10) is selected and the software driver is capable of bits (BCR32, bits 10-8). The delay can be adjusted controlling the external PHY. A complete bit description from 0 MDC periods to 2048 MDC periods. Auto-Poll by of the MII and Auto-Negotiation registers can be found default will only read the MII Status register in the ex- in Appendix C. ternal PHY. Automatic Network Port Selection Network Port Manager If ASEL (BCR2, bit 0) is set to 1 and DANAS (BCR 32, The Am79C972 controller is unique in that it does not bit 7) is set to 0, then the Network Port Manager will require software intervention to control and configure start to configure the external PHY if it detects the ex- an external PHY attached to the MII. This was done to ternal PHY on the MII Interface. Am79C972 69 Automatic Network Selection: Exceptions pabilities with the XPHYFD (BCR 32, bit 4) and the XPHYSP (BCR32, bit 3) bits programmed from the EE- If ASEL (BCR2, bit 0) is set to 0 or DANAS (BCR 32, bit PROM. The Am79C972 controller will then program the 7) is set to 1, then the Network Port Manager will dis- external PHY with those values. A new read of the ex- continue actively trying to establish the connections. It ternal PHYs MII Status register will be made to see if is assumed that the software driver is attempting to the link is up. If the link does not come up as pro- configure the network port and the Am79C972 control- grammed after a specific time, the Am79C972 control- ler will always defer to the software driver. When The ler will fail the external PHY link. The Network Port ASEL is set to 0, the software driver should then con- Manager will periodically query the external PHY for figure the ports with PORTSEL (CSR15, bits 7-8). The active links. GPSI does not participate in the automatic selection process and should be manually configured with the Automatic Network Selection: External PHY PORTSEL bits. Auto-Negotiable Note: It is highly recommended that ASEL and This case occurs when the MIIPD (BCR32, bit 14) bit is PORTSEL be used when trying to manually configure 1. This indicates that there is an external PHY attached a specific network port. to Am79C972 controller’s MII. If more than one external PHY is attached to the MII Management Interface, then In order to manually configure the External PHY, the the DANAS (BCR32, bit 7) bit must be set to 1 and then recommended procedure is to force the PHY config- all configuration control should revert to software. The urations when Auto-Negotiation is not enabled. Set the Am79C972 controller will read the MII Status register of DANAS bit (BCR32, bit 7) to turn off the Network Port the external PHY to determine its status and network Manager. Then write again to BCR32 with the DANAS capabilities. See Appendix C for the bit descriptions of and XPHANE (BCR32, bit 5) bits cleared, together with the MII Status register. If the external PHY is Auto-Ne- the XPHYFD (BCR32, bit 4) and XPHYSP (BCR32, gotiation capable and/or the XPHYANE (BCR32, bit 5) bit 3) bits set to the desired configuration. The Network bit is set to 1, then the Am79C972 controller will start Port Manager will send a few frames to validate the the external PHY’s Auto-Negotiation process. The configuration. Am79C972 controller will write to the external PHY’s CAUTION: The Network Port Manager utilizes the Advertisement register with the following conditions PHYADD (BCR33, bits 9-5) to communicate with the set: turn off the Next Pages support, set the Technology external PHY during the automatic port selection pro- Ability Field (See Appendix C for the Auto-Negotiation cess. The PHYADD is copied into a shadow register register bit descriptions) from the external PHY MII Sta- after the Am79C972 controller has read the configura- tus register read, and set the Type Selector field to the tion information from the EEPROM. Extreme care must IEEE 802.3 standard. The Am79C972 controller will be exercised by the host software not to access BCR33 then write to the external PHY’s MII Control register in- during this time. A read of PVALID (BCR19, bit 15) be- structing the external PHY to negotiate the link. The fore accessing BCR33 will guarantee that the PHYADD Am79C972 controller will poll the external PHY’s MII has been shadowed. Status register until the Auto-Negotiation Complete bit is set to 1and the Link Status bit is set to 1. The Am79C972’s Automatic Network Port selection mecha- Am79C972 controller will then wait a specific time and nism falls within the following general categories: then again read the external PHY’s MII Status register. � External PHY Not Auto-Negotiable If the Am79C972 controller sees that the external � External PHY Auto-Negotiable PHY’s link is down, it will try to bring up the external PHY’s link manually as described above. A new read of Automatic Network Selection: External PHY Not the external PHY’s MII Status register will be made to Auto-Negotiable see if the link is up. If the link does not come up as pro- This case occurs when the MIIPD (BCR32, bit 14) bit is grammed after a specific time, the Am79C972 control- 1. This indicates that there is an external PHY attached ler will fail the external PHY link and start the process to Am79C972 controller’s MII. If more than one external again. PHY is attached to the MII Management Interface, then Automatic Network Selection: Force External Reset the DANAS (BCR32, bit 7) bit must be set to 1 and then all configuration control should revert to software. The If the XPHYRST bit (BCR32, bit 6) is set to 1, then the Am79C972 controller will read the register of the exter- flow changes slightly. The Am79C972 controller will nal PHY to determine its status and network capabili- write to the external PHY’s MII Control register with the ties. See Appendix C, MII Management Registers, for RESET bit set to 1 (See Appendix C, MII Management the bit descriptions of the MII Status register. If the ex- Registers, for the MII register bit descriptions). This will ternal PHY is not Auto-Negotiation capable and/or the force a complete reset of the external PHY. The XPHYANE (BCR32, bit 5) bit is set to 0, then the Net- Am79C972 controller after a specific time will poll the work Port Manager will match up the external PHY ca- external PHY’s MII Control register to see if the RESET 70 Am79C972 bit is 0. After the RESET bit is cleared, then the normal frame is of the type 'Broadcast', then the frame will be flow continues. accepted regardless of the condition of EAR. When the EADISEL bit of BCR2 is set to 1 and the Am79C972 External Address Detection Interface controller is programmed to promiscuous mode The EADI is provided to allow external address filtering (PROM bit of the Mode Register is set to 1), then all in- and to provide a Receive Frame Tag word for propri- coming frames will be accepted, regardless of any ac- etary routing information. It is selected by setting the tivity on the EAR pin. EADISEL bit in BCR2 to 1. This feature is typically uti- Internal address match is disabled when PROM lized by terminal servers, bridges and/or router prod- (CSR15, bit 15) is cleared to 0, DRCVBC (CSR15, bit ucts. The EADI interface can be used in conjunction 14) and DRCVPA (CSR15, bit 13) are set to 1, and the with external logic to capture the packet destination ad- Logical Address Filter registers (CSR8 to CSR11) are dress from the serial bit stream as it arrives at the programmed to all zeros. Am79C972 controller, to compare the captured ad- dress with a table of stored addresses or identifiers, When the EADISEL bit of BCR2 is set to 1 and internal and then to determine whether or not the Am79C972 address match is disabled, then all incoming frames controller should accept the packet. will be accepted by the Am79C972 controller, unless the EAR pin becomes active during the first 64 bytes of External Address Detection Interface: GPSI Port the frame (excluding preamble and SFD). This allows The EADI interface outputs are delivered directly from external address lookup logic approximately 58 byte the NRZ decoded data and clock recovered by the ex- times after the last destination address bit is available ternal PHY. This allows the external address detection to generate the EAR signal, assuming that the to be performed in parallel with frame reception and ad- Am79C972 controller is not configured to accept runt dress comparison in the MAC Station Address Detec- packets. The EADI logic only samples EAR from 2 bit tion (SAD) block of the Am79C972 controller. times after SFD until 512 bit times (64 bytes) after SFD. The frame will be accepted if EAR has not been as- SRDCLK is provided to allow clocking of the receive bit serted during this window. In order for the EAR pin to stream into the external address detection logic. Once be functional in full-duplex mode, FDRPAD bit (BCR9, a received frame commences and data and clock are bit 2) needs to be set. If Runt Packet Accept (CSR124, available, the EADI logic will monitor the alternating bit 3) is enabled, then the EAR signal must be gener- (“1,0”) preamble pattern until the two 1s of the Start ated prior to the 8 bytes received, if frame rejection is Frame Delimiter (SFD, 10101011 bit pattern) are de- to be guaranteed. Runt packet sizes could be as short tected, at which point the SFBD output will be driven as 12 byte times (assuming 6 bytes for source address, HIGH. 2 bytes for length, no data, 4 bytes for FCS) after the The SFBD signal will initially be LOW. The assertion of last bit of the destination address is available. EAR SFBD is a signal to the external address detection logic must have a pulse width of at least 110 ns. that the SFD has been detected and that subsequent The EADI outputs continue to provide data throughout SRDCLK cycles will deliver packet data to the external the reception of a frame. This allows the external logic logic. Therefore, when SFBD is asserted, the external to capture frame header information to determine pro- address matching logic should begin de-serialization of tocol type, internetworking information, and other use- the SRD data and send the resulting destination ad- ful data. dress to a Content Addressable Memory (CAM) or other address detection device. In order to reduce the The EADI interface will operate as long as the STRT bit amount of logic external to the Am79C972 controller for in CSR0 is set, even if the receiver and/or transmitter multiple address decoding systems, the SFBD signal are disabled by software (DTX and DRX bits in CSR15 will toggle at each new byte boundary within the are set). This configuration is useful as a semi-power- packet, subsequent to the SFD. This eliminates the down mode in that the Am79C972 controller will not need for externally supplying byte framing logic. perform any power-consuming DMA operations. How- ever, external circuitry can still respond to control SRD is the decoded NRZ data from the network. This frames on the network to facilitate remote node control. signal can be used for external address detection. Table 8 summarizes the operation of the EADI inter- The EAR pin should be driven LOW by the external ad- face. dress comparison logic to reject a frame. If an address match is detected by comparison with ei- ther the Physical Address or Logical Address Filter reg- isters contained within the Am79C972 controller or the Am79C972 71 ware mode. The receive frame tagging is not supported in the 16-bit software mode. The RFRTAG field are all Table 8. EADI Operations zeros when either the EADISEL (BCR2, bit3) or the Required Received RXFRTAG (CSR7, bit 14) are set to 0. When EADISEL PROM EAR Timing Frames (BCR2, bit 3) and RXFRTAG (CSR7, bit 14) are set to No timing 1, then the RFRTAG reflects the tag word shifted in dur- 1 X All received frames requirements ing that receive frame. No timing 0 1 All received frames requirements In the MII mode, the two-wire interface will use the MIIRXFRTGD and MIIRXFRTGE pins from the EADI Frame rejected if in Low for two bit 0 0 address match interface. These pins will provide the data input and times plus 10 ns mode data input enable for the receive frame tagging, respec- tively. These pins are normally not used during the MII External Address Detection Interface: External operation. PHY In the GPSI mode, the three-wire interface will use the When using the MII, the EADI interface changes to re- RXFRTGD, SRDCLK, and the RXFRTGE pins from the flect the changes on that interface. Except for the nota- EADI and MII. These pins will provide the data input, tions below the interface conforms to the previous data input clock, and the data input for the receive functionality. The data arrives in nibbles and can be at frame tagging enable, respectively. a rate of 25 MHz or 2.5 MHz. The receive frame tag register is a shift register that The MII provides all necessary data and clock signals shifts data in MSB first, so that less than the 15 bits al- needed for the EADI interface. Consequently, SRDCLK located may be utilized by the user. The upper bits not and SRD are not used and are driven to 0. Data for the utilized will return zeros. The receive frame tag register EADI is the RXD(3:0) receive data provided to the MII. is set to 0 in between reception of frames. After receiv- Instead of deserializing the network data, the user will ing SFBD indication on the EADI, the user can start receive the data as 4 bit nibbles. RX_CLK is provided shifting data into the receive tag register until one net- to allow clocking of the RXD(3:0) receive nibble stream work clock period before the Am79C972 controller re- into the external address detection logic. The RXD(3:0) ceives the end of the current receive frame. data is synchronous to the rising edge of the RX_CLK. In the MII mode, the user must see the RX_CLK to The assertion of SFBD is a signal to the external ad- drive the synchronous receive frame tag data interface. dress detection logic that the SFD has been detected After receiving the SFBD indication, sampled by the ris- and that the first valid data nibble is on the RXD(3:0) ing edge of the RX_CLK, the user will drive the data data bus. The SFBD signal is delayed one RX_CLK input and the data input enable synchronous with the cycle from the above definition and actually signals the rising edge of the RX_CLK. The user has until one net- start of valid data. In order to reduce the amount of work clock period before the deassertion of the RX_DV logic external to the Am79C972 controller for multiple to input the data into the receive frame tag register. At address decoding systems, the SFBD signal will go the deassertion of the RX_DV, the receive frame tag HIGH at each new byte boundary within the packet, register will no longer accept data from the two-wire in- subsequent to the SFD. This eliminates the need for ex- terface. If the user is still driving the data input enable ternally supplying byte framing logic. pin, erroneous or corrupted data may reside in the re- The EAR pin function is the same and should be driven ceive frame tag register. See Figure 37. LOW by the external address comparison logic to reject In the GPSI mode, the user must use the recovered re- a frame. See the External Address Detection Interface: ceive data clock driven on the SRDCLK pin to drive the GPSI Port section for more details. synchronous receive frame tag data interface. After re- External Address Detection Interface: Receive ceiving the SFBD indication, sampled by the rising Frame Tagging edge of the recovered receive data clock, the user will drive the data input and the data input enable synchro- The Am79C972 controller supports receive frame tag- nous with the rising edge of the recovered receive data ging in both GPSI or MII mode. The method remains clock. The user has until one network clock period be- constant, but the chip interface pins will change be- fore the deassertion of the data from the network to tween the MII and the GPSI modes. The receive frame input the data into the receive frame tag register. At the tagging implementation will be a two- and three-wire completion of received network data, the receive frame chip interface, respectively, added to the existing EADI. tag register will no longer accept data from the two-wire The Am79C972 controller supports up to 15 bits of re- interface. If the user is still driving the data input enable ceive frame tagging per frame in the receive frame sta- pin, erroneous or corrupted data may reside in the re- tus (RFRTAG). The RFRTAG bits are in the receive ceive frame tag register. See Figure 38. frame status field in RMD2 (bits 30-16) in 32-bit soft- 72 Am79C972 RX_CLK RX_DV SF/BD MIIRXFRTGE MIIRXFRTGD 21485C-40 Figure 37. MII Receive Frame Tagging SRDCLK .. SFD Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bitx Bity Bitz SRD SFBD .. MIIRXFRTGE .. MIIRXFRTGD .. Note: Bitz is last data bit. 21485C-41 Figure 38. GPSI Mode Frame Tagging The signal EROMCS is connected to the CS/CE input Expansion Bus Interface of the EPROM/Flash. The signal EBWE is connected The Am79C972 controller contains an Expansion Bus to the WE of the Flash device. Interface that supports Flash and EPROM devices as boot devices, as well as provides read/write access to The Expansion Data Bus is configured for 8-bit byte ac- Flash or EPROM. cess during EPROM/Flash accesses. During EPROM/ Flash accesses, EBD[7:0] provides the data byte. See The signal AS_EBOE is provided to strobe the upper 8 Figure 39, Figure 40, and Figure 41. bits of the address into an external ‘374 (D flip-flop) ad- dress latch. AS_EBOE is asserted LOW during Expansion ROM - Boot Device Access EPROM/Flash read operations to control the OE input The Am79C972 controller supports EPROM or Flash of the EPROM/Flash. as an Expansion ROM boot device. Both are config- ured using the same methods and operate the same. The Expansion Bus Address is split into two different See the previous section on Expansion ROM transfers buses, EBUA_EBA[7:0] and EBDA[15:8]. The to get the PCI timing and functional description of the EBUA_EBA[7:0] provides the least and the most signif- transfer method. The Am79C972 controller is function- icant address byte. When accessing EPROM/Flash, ally equivalent to the PCnet-PCI II controller with Ex- the EBUA_EBA[7:0] is strobed into an external ‘374 (D pansion ROM. See Figure 40 and Figure 41. flip-flop) address latch. This constitutes the most signif- icant portion of the Expansion Bus Address. For The Am79C972 controller will always read four bytes for EPROM/Flash accesses, EBUA_EBA[7:0] constitutes every host Expansion ROM read access. The interface the remaining least significant address byte. For byte to the Expansion Bus runs synchronous to the PCI bus oriented EPROM/Flash accesses, EBDA[15:8] consti- interface clock. The Am79C972 controller will start the tutes the upper or middle address byte. EBADDRU read operation to the Expansion ROM by driving the (BCR29, bits 3-0) should be set to 0 when not used, upper 8 bits of the Expansion ROM address on since EBADDRU constitutes the EBUA portion of the EBUA_EBA[7:0]. One-half clock later, AS_EBOE goes EBUA_EBA address byte and is strobed into the exter- high to allow registering of the upper address bits ex- nal ’374 address latch. ternally. The upper portion of the Expansion ROM ad- dress will be the same for all four byte read cycles. Am79C972 73 AS_EBOE is driven high for one-half clock, troller latches in the data on the EBD[7:0] inputs. The EBUA_EBA[7:0] are driven with the upper 8 bits of the register value specifies the time in number of clock cy- Expansion ROM address for one more clock cycle after cles. When ROMTMG is set to nine (the default value), AS_EBOE goes low. Next, the Am79C972 controller EBD[7:0] is sampled with the next rising edge of CLK starts driving the lower 8 bits of the Expansion ROM ten clock cycles after EBUA_EBA[7:0] was driven with address on EBUA_EBA[7:0]. a new address value. The clock edge that is used to sample the data is also the clock edge that generates The time that the Am79C972 controller waits for data to the next Expansion ROM address. All four bytes of Ex- be valid is programmable. ROMTMG (BCR18, bits 15- pansion ROM data are stored in holding registers. One 12) defines the time from when the Am79C972 control- clock cycle after the last data byte is available, the ler drives EBUA_EBA[7:0] with the lower 8 bits of the Am79C972 controller asserts TRDY. Expansion ROM address to when the Am79C972 con- EBD[7:0] EBWE EBUA_EBA[7:0] ’374 D-FF AS_/EBOE A[23:16] EBDA[15:8] A[15:8] A[7:0] FLASH Am79C972 WE DQ[7:0] CS OE 21485C-42 EROMCS Figure 39. Flash Configuration for the Expansion Bus The access time for the Expansion ROM or the EB- tACC = ROMTMG * CLK period *CLK_FAC - (tv_A_D) - DATA (BCR30) device (tACC) during read operations (ts_D) can be calculated by subtracting the clock to output The access time for the Expansion ROM or for the EB- delay for the EBUA_EBA[7:0] outputs (tv_A_D) and by DATA (BCR30) device (tACC) during write operations subtracting the input to clock setup time for the can be calculated by subtracting the clock to output EBD[7:0] inputs (ts_D) from the time defined by delay for the EBUA EBA[7:0] outputs (tv_A_D) and by ROMTMG: 74 Am79C972 adding the input to clock setup time for Flash/EPRO in- The host must program the Expansion ROM Base Ad- puts (ts_D) from the time defined by ROMTMG: dress register in the PCI configuration space before the first access to the Expansion ROM. The Am79C972 tACC = ROMTMG * CLK period * CLK_FAC - (tv_A_D) - controller will not react to any access to the Expansion (ts_D) ROM until both MEMEN (PCI Command register, bit 1) The timing diagram in Figure 42 assumes the default and ROMEN (PCI Expansion ROM Base Address reg- programming of ROMTMG (1001b = 9 CLK). After ister, bit 0) are set to 1. After the Expansion ROM is reading the first byte, the Am79C972 controller reads in enabled, the Am79C972 controller will claim all memory three more bytes by incrementing the lower portion of read accesses with an address between ROMBASE the ROM address. After the last byte is strobed in, and ROMBASE + 1M - 4 (ROMBASE, PCI Expansion TRDY will be asserted on clock 50. When the host tries ROM Base Address register, bits 31-20). The address to perform a burst read of the Expansion ROM, the output to the Expansion ROM is the offset from the ad- Am79C972 controller will disconnect the access at the dress on the PCI bus to ROMBASE. The Am79C972 second data phase. controller aliases all accesses to the Expansion ROM of the command types Memory Read Multiple and Mem- ory Read Line to the basic Memory Read command. EBD[7:0] EBWE A[15:8] A[7:0] EBUA_EBA[7:0] EPROM DQ[7:0] EROMCS CS OE EBDA[15:8] Am79C972 AS_EBOE 21485C-43 Figure 40. EPROM Only Configuration for the Expansion Bus (64K EPROM) Am79C972 75 EBD[7:0] Am79C972 ’374 EBWE D-FF A[23:16] A[15:8] A[7:0] EBUA_EBA[7:0] EPROM DQ[7:0] EROMCS CS OE EBDA[15:8] AS_EBOE 21485C-44 Figure 41. EPROM Only Configuration for the Expansion Bus (>64K EPROM) Since setting MEMEN also enables memory mapped Bus Data port (BCR30). The user must load the upper access to the I/O resources, attention must be given to address EPADDRU (BCR 29, bits 3-0) and then set the the PCI Memory Mapped I/O Base Address register, FLASH (BCR29, bit 15) bit to a 1. The Flash read/write before enabling access to the Expansion ROM. The utilizes the PCI clock instead of the EBCLK during all host must set the PCI Memory Mapped I/O Base Ad- accesses. EPADDRU is not needed if the Flash size is dress register to a value that prevents the Am79C972 64K or less, but still must be programmed. The user will controller from claiming any memory cycles not in- then load the lower 16 bits of address, EPADDRL (BCR tended for it. 28, bits 15-0). During the boot procedure, the system will try to find an Flash/EPROM Read Expansion ROM. A PCI system assumes that an Ex- A read to the Expansion Bus Data Port (BCR30) will pansion ROM is present when it reads the ROM signa- start a read cycle on the Expansion Bus Interface. The ture 55h (byte 0) and AAh (byte 1). Am79C972 controller will drive EBUA_EBA[7:0] with the most significant address byte at the same time the Direct Flash Access Am79C972 controller will drive AS_EBOE high to Am79C972 controller supports Flash as an Expansion strobe the address in the external ‘374 (D flip-flop). On ROM device, as well as providing a read/write data the next clock, the Am79C972 controller will drive path to the Flash. The Am79C972 controller will sup- EBDA[15:8] and EBUA_EBA[7:0] with the middle and port up to 1 Mbyte of Flash on the Expansion Bus. The least significant address bytes. Flash is accessed by a read or write to the Expansion 76 Am79C972 A[19:16] 5 10 15 20 25 30 35 40 45 50 55 60 66 CLK EBUA_EBA [7:0] A[7:2], 0, 0 A[7:2], 0, 1 A[7:2], 1, 0 A[7:2], 1, 1 Latched Address EBDA [15:8] EBD AS_EBO EROMCS FRAME IRDY TRDY DEVSEL 21485C-45 Figure 42. Expansion ROM Bus Read Sequence EBUA[19:16] CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 EBUA_EBA[7:0] EBA[7:0] EBDA[15:8] EBDA[15:8] EBD[7:0] EROMCS AS_EBOE 21485C-46 Figure 43. Flash Read from Expansion Bus Data Port The EROMCS is driven low for the value ROMTMG + (BCR29, bit 15) is set, the EBADDRL address will be 1. Figure 43 assumes that ROMTMG is set to nine. incremented and a continuous series of reads from the EBD[7:0] is sampled with the next rising edge of CLK Expansion Data Port (EBDATA, BCR30) is possible. ten clock cycles after EBUA_EBA[7:0] was driven with The address incrementor will roll over without warning a new address value. This PCI slave access to the and without incrementing the upper address EBAD- Flash/EPROM will result in a retry for the very first ac- DRU. cess. Subsequent accesses may give a retry or not, de- The Flash write is almost the same procedure as the pending on whether or not the data is present and valid. read access, except that the Am79C972 controller will The access time is dependent on the ROMTMG bits not drive AS_EBOE low. The EROMCS and EBWE are (BCR18, bits 15-12) and the Flash/EPROM. This ac- driven low for the value ROMTMG again. The write to cess mechanism differs from the Expansion ROM ac- the FLASH port is a posted write and will not result in a cess mechanism since only one byte is read in this retry to the PCI unless the host tries to write a new manner, instead of the 4 bytes in an Expansion ROM value before the previous write is complete, then the access. The PCI bus will not be held during accesses host will experience a retry. See Figure 44. through the Expansion Bus Data Port. If the LAAINC Am79C972 77 EBUA[19:16] CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 EBUA_EBA[7:0] EBA[7:0] EBDA[15:8] EBDA[15:8] EBD[7:0] EROMCS AS_EBOE EBWE 21485C-47 Figure 44. Flash Write from Expansion Bus Data Port AMD Flash Programming the AMD Flash Embedded Erase Algorithm command sequence, the Flash device will program and verify the AMD’s Flash products are programmed on a byte-by- entire memory for an all zero data pattern prior to elec- byte basis. Programming is a four bus cycle operation. trical erase. The Am79C972 controller is not required There are two “unlock” write cycles. These are followed to provide any controls or timings during these opera- by the program set-up command and data write cycles. tions. The automatic erase begins on the rising edge of Addresses are latched on the falling edge of EBWE the last EBWE pulse in the command sequence and and the data is latched on the rising edge of EBWE. terminates when the data on EBD[7] is 1, at which time The rising edge of EBWE begins programming. the Flash device returns to the read mode. Polling by Upon executing the AMD Flash Embedded Program the Am79C972 controller is not required during the Algorithm command sequence, the Am79C972 con- erase sequence. The following FLASH programming- troller is not required to provide further controls or tim- table excerpt (Table 9) shows the command sequence ing. The AMD Flash product will compliment EBD[7] for byte programming and sector/chip erasure on an during a read of the programmed location until the pro- AMD Flash device. In the following table, PA and PD gramming is complete. The host software should poll stand for programmed address and programmed data, the programmed address until EBD[7] matches the and SA stands for sector address. programmed value. The Am79C972 controller will support only a single AMD Flash byte programming is allowed in any se- sector erase per command and not concurrent sector quence and across sector boundaries. Note that a data erasures. The Am79C972 controller will support most 0 cannot be programmed back to a 1. Only erase oper- FLASH devices as long as there is no timing require- ations can convert zeros to ones. AMD Flash chip ment between the completion of commands. The erase is a six-bus cycle operation. There are two unlock FLASH access time cannot be guaranteed with the write cycles, followed by writing the set-up command. Am79C972 controller access mechanism. The Two more unlock cycles are then followed by the chip Am79C972 controller will also support only Flash de- erase command. Chip erase does not require the user vices that do not require data hold times after write op- to program the device prior to erasure. Upon executing erations. Table 9. Am29Fxxx Flash Command Bus Write Command Cycles First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Sequence Req’d Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Byte Program 4 5555h AAh 2AAAh 55H 5555h A0h PA PD Chip Erase 6 5555h AAh 2AAAh 55H 5555h 80h 5555h AAh 2AAAh 55h 5555h 10h Sector Erase 6 5555h AAh 2AAAh 55H 5555h 80h 5555h AAh 2AAAh 55h SA 3h 78 Am79C972 SRAM Configuration No SRAM Configuration The Am79C972 controller supports SRAM as a FIFO If the SRAM_SIZE (BCR25, bits 7-0) value is 0 in the extension as well as providing a read/write data path to SRAM size register, the Am79C972 controller will as- the SRAM. The Am79C972 controller contains sume that there is no SRAM present and will reconfig- 12 Kbytes of SRAM. ure the four internal FIFOs into two FIFOs, one for transmit and one for receive. The FIFOs will operate Internal SRAM Configuration the same as in the PCnet-PCI II controller. When the The SRAM_SIZE (BCR25, bits 7-0) programs the size SRAM SIZE (BCR25, bits 7-0) value is 0, the SRAM of the SRAM. SRAM_SIZE can be programmed to a BND (BCR26, bits 7-0) are ignored by the Am79C972 smaller value than 12 Kbytes. controller. See Figure 45. The SRAM should be programmed on a 512-byte Low Latency Receive Configuration boundary. However, there should be no accesses to the If the LOLATRX (BCR27, bit 4) bit is set to 1, then the RAM space while the Am79C972 controller is running. Am79C972 controller will configure itself for a low la- The Am79C972 controller assumes that it completely tency receive configuration. In this mode, SRAM is re- owns the SRAM while it is in operation. To specify how quired at all times. If the SRAM_SIZE (BCR25, bits 7- much of the SRAM is allocated to transmit and how 0) value is 0, the Am79C972 controller will not config- much is allocated to receive, the user should program ure for low latency receive mode. The Am79C972 con- SRAM_BND (BCR26, bits 7-0) with the page boundary troller will provide a fast path on the receive side where the receive buffer begins. The SRAM_BND also bypassing the SRAM. All transmit traffic will go to the should be programmed on a 512-byte boundary. The SRAM, so SRAM_BND (BCR26, bits 7-0) has no transmit buffer space starts at 0000h. It is up to the user meaning in low latency receive mode. When the or the software driver to split up the memory for trans- Am79C972 controller has received 16 bytes from the mit or receive; there is no defaulted value. The mini- network, it will start a DMA request to the PCI Bus In- mum SRAM size required is four 512-byte pages for terface Unit. The Am79C972 controller will not wait for each transmit and receive queue, which limits the the first 64 bytes to pass to check for collisions in Low SRAM size to be at least 4 Kbytes. Latency Receive mode. The Am79C972 controller The SRAM_BND upon H_RESET will be reset to must be in STOP before switching to this mode. See 0000h. The Am79C972 controller will not have any Figure 46. transmit buffer space unless SRAM_BND is pro- CAUTION: To provide data integrity when switching grammed. The last configuration parameter necessary into and out of the low latency mode, DO NOT SET is the clock source used to control the Expansion Bus the FASTSPNDE bit when setting the SPND bit. Re- interface. This is programmed through the SRAM Inter- ceive frames WILL be overwritten and the face Control register. The externally driven Expansion Am79C972 controller may give erratic behavior Bus Clock (EBCLK) can be used by specifying a value when it is enabled again. of 010h in EBCS (BCR27, bits 5-3). This allows the user to utilize any clock that may be available. Direct SRAM Access The SRAM can be accessed through the Expansion There are two standard clocks that can be chosen as Bus Data port (BCR30). To access this data port, the well, the PCI clock or the externally provided time base user must load the upper address EPADDRU (BCR29, clock. Use of the internal clock is not recommended. bits 3-0) and set FLASH (BCR29, bit 15) to 0. Then the When the PCI or time base clock is used, the EBCLK user will load the lower 16 bits of address EPADDRL does not have to be driven, but it must be tied to VDD (BCR28, bits 15-0). To initiate a read, the user reads through a resistor. The user must specify an SRAM the Expansion Bus Data Port (BCR30). This slave ac- clock (BCR27, bits 5-3) that will not stop unless the cess from the PCI will result in a retry for the very first Am79C972 controller is stopped. Otherwise, the access. Subsequent accesses may give a retry or not, Am79C972 controller will report buffer overflows, un- depending on whether or not the data is present and derflows, corrupt data, and will hang eventually. valid. The direct SRAM access uses the same FLASH/ The user can decide to use a fast clock and then divide EPROM access except for accessing the SRAM in down the frequency to get a better duty-cycle if re- word format instead of byte format. This access is quired. The choices are a divide by 2 or 4 and is pro- meant to be a diagnostic access only. The SRAM can grammed by the CLK_FAC bits (BCR27, bits 2-0). Note only be accessed while the Am79C972 controller is in that the Am79C972 controller does not support an STOP or SPND (FASTSPNDE is set to 0) mode. SRAM frequency above 33 MHz regardless of the clock and clock factor used. Am79C972 79 . Bus MAC Rcv Rcv FIFO FIFO 802.3 PCI Bus MAC Interface Core Unit MAC Bus Xmt Xmt FIFO FIFO Buffer FIFO Management Control Unit 21485C-48 Figure 45. Block Diagram No SRAM Configuration Bus MAC Rcv Rcv FIFO FIFO PCI Bus Interface 802.3 Unit SRAM MAC Core Bus MAC Xmt Xmt FIFO FIFO Buffer FIFO Management Control Unit 21485C-49 Figure 46. Block Diagram Low Latency Receive Configuration 80 Am79C972 ing which RST is asserted, the Am79C972 controller EEPROM Interface will sample the value of the EESK/LED1/SFBD pin. If The Am79C972 controller contains a built-in capability the sampled value is a 1, then the Am79C972 controller for reading and writing to an external serial 93C46 assumes that an EEPROM is present, and the EE- EEPROM. This built-in capability consists of an inter- PROM read operation begins shortly after the RST pin face for direct connection to a 93C46 compatible is deasserted. If the sampled value of EESK/LED1/ EEPROM, an automatic EEPROM read feature, and a SFBD is a 0, the Am79C972 controller assumes that an user-programmable register that allows direct access external pulldown device is holding the EESK/LED1/ to the interface pins. SFBD pin low, indicating that there is no EEPROM in Automatic EEPROM Read Operation the system. Note that if the designer creates a system that contains an LED circuit on the EESK/LED1/SFBD Shortly after the deassertion of the RST pin, the pin, but has no EEPROM present, then the EEPROM Am79C972 controller will read the contents of the auto-detection function will incorrectly conclude that an EEPROM that is attached to the interface. Because of EEPROM is present in the system. However, this will this automatic-read capability of the Am79C972 con- not pose a problem for the Am79C972 controller, since troller, an EEPROM can be used to program many of the checksum verification will fail. the features of the Am79C972 controller at power-up, allowing system-dependent configuration information Direct Access to the Interface to be stored in the hardware, instead of inside the The user may directly access the port through the device driver. EEPROM register, BCR19. This register contains bits If an EEPROM exists on the interface, the Am79C972 that can be used to control the interface pins. By per- controller will read the EEPROM contents at the end of forming an appropriate sequence of accesses to the H_RESET operation. The EEPROM contents will BCR19, the user can effectively write to and read from be serially shifted into a temporary register and then the EEPROM. This feature may be used by a system sent to various register locations on board the configuration utility to program hardware configuration Am79C972 controller. Access to the Am79C972 con- information into the EEPROM. figuration space, the Expansion ROM or any I/O EEPROM-Programmable Registers resource is not possible during the EEPROM read op- The following registers contain configuration informa- eration. The Am79C972 controller will terminate any tion that will be programmed automatically during the access attempt with the assertion of DEVSEL and EEPROM read operation: STOP while TRDY is not asserted, signaling to the ini- tiator to disconnect and retry the access at a later time. � I/O offsets 0h-Fh Address PROM locations A checksum verification is performed on the data that � BCR2 Miscellaneous Configuration is read from the EEPROM. If the checksum verification � BCR4 LED0 Status passes, PVALID (BCR19, bit 15) will be set to 1. If the � BCR5 LED1 Status checksum verification of the EEPROM data fails, PVALID will be cleared to 0, and the Am79C972 con- � BCR6 LED2 Status troller will force all EEPROM-programmable BCR reg- � BCR7 LED3 Status isters back to their H_RESET default values. However, � BCR9 Full-Duplex Control the content of the Address PROM locations (offsets 0h - Fh from the I/O or memory mapped I/O base ad- � BCR18 Burst and Bus Control dress) will not be cleared. The 8-bit checksum for the � BCR22 PCI Latency entire 68 bytes of the EEPROM should be FFh. � BCR23 PCI Subsystem Vendor ID If no EEPROM is present at the time of the automatic � BCR24 PCI Subsystem ID read operation, the Am79C972 controller will recognize this condition and will abort the automatic read opera- � BCR25 SRAM Size tion and clear both the PREAD and PVALID bits in � BCR26 SRAM Boundary BCR19. All EEPROM-programmable BCR registers � BCR27 SRAM Interface Control will be assigned their default values after H_RESET. The content of the Address PROM locations (offsets � BCR32 MII Control and Status 0h - Fh from the I/O or memory mapped I/O base ad- � BCR33 MII Address dress) will be undefined. � BCR35 PCI Vendor ID EEPROM Auto-Detection �BCR36 PCI Power Management The Am79C972 controller uses the EESK/LED1/SFBD Capabilities (PMC) Alias Regis- pin to determine if an EEPROM is present in the sys- ter tem. At the rising edge of CLK during the last clock dur- Am79C972 81 � BCR37 PCI DATA Register Zero (DATA0) EEPROM MAP Alias Register The automatic EEPROM read operation will access 34 � BCR38 PCI DATA Register One (DATA1) words (i.e., 68 bytes) of the EEPROM. The format of Alias Register the EEPROM contents is shown in Table 10 (next page), beginning with the byte that resides at the low- � BCR39 PCI DATA Register Two (DATA2) est EEPROM address. Alias Register Note: The first bit out of any word location in the EE- � BCR40 PCI DATA Register Three PROM is treated as the MSB of the register being pro- (DATA3) Alias Register grammed. For example, the first bit out of EEPROM � BCR41 PCI DATA Register Four (DATA4) word location 09h will be written into BCR4, bit 15; the Alias Register second bit out of EEPROM word location 09h will be � BCR42 PCI DATA Register Five (DATA5) written into BCR4, bit 14, etc. Alias Register There are two checksum locations within the EE- � BCR43 PCI DATA Register Six (DATA6) PROM. The first checksum will be used by AMD driver Alias Register software to verify that the ISO 8802-3 (IEEE/ANSI 802.3) station address has not been corrupted. The � BCR44 PCI DATA Register Seven value of bytes 0Ch and 0Dh should match the sum of (DATA7) Alias Register bytes 00h through 0Bh and 0Eh and 0Fh. The second �BCR45 OnNow Pattern Matching checksum location (byte 43h) is not a checksum total, Register 1 but is, instead, a checksum adjustment. The value of �BCR46 OnNow Pattern Matching this byte should be such that the total checksum for the Register 2 entire 68 bytes of EEPROM data equals the value FFh. The checksum adjust byte is needed by the Am79C972 �BCR47 OnNow Pattern Matching controller in order to verify that the EEPROM content Register 3 has not been corrupted. � CSR116 OnNow Miscellaneous LED Support If PREAD (BCR19, bit 14) and PVALID (BCR19, bit 15) are cleared to 0, then the EEPROM read has experi- The Am79C972 controller can support up to four LEDs. enced a failure and the contents of the EEPROM pro- LED outputs LED0, LED1, and LED2 allow for direct grammable BCR register will be set to default connection of an LED and its supporting pullup device. H_RESET values. The content of the Address PROM In applications that want to use the pin to drive an LED locations, however, will not be cleared. and also have an EEPROM, it might be necessary to Accesses to the Address PROM I/O locations do not di- buffer the LED3 circuit from the EEPROM connection. rectly access the Address EEPROM itself. Instead, When an LED circuit is directly connected to the these accesses are routed to a set of shadow registers EEDO/LED3/SRD pin, then it is not possible for most on board the Am79C972 controller that are loaded with EEPROM devices to sink enough I to maintain a valid OL a copy of the EEPROM contents during the automatic low level on the EEDO input to the Am79C972 control- read operation that immediately follows the H_RESET ler. Use of buffering can be avoided if a low power LED operation. is used. Each LED can be programmed through a BCR register to indicate one or more of the following network status or activities: Collision Status, Full-Duplex Link Status, Half-Duplex Link Status, Receive Match, Receive Sta- tus, Magic Packet, Disable Transceiver, and Transmit Status. 82 Am79C972 Table 10. EEPROM Map Word Byte Byte Address Address Most Significant Byte Address Least Significant Byte First byte of the ISO 8802-3 (IEEE/ANSI 2nd byte of the ISO 8802-3 (IEEE/ANSI 802.3) 802.3) station physical address for this 00h* 01h 00h station physical address for this node. node, where “first byte” refers to the first byte to appear on the 802.3 medium. 01h 03h 4th byte of the node address 02h 3rd byte of the node address 02h 05h 6th byte of the node address 04h 5th byte of the node address 03h 07h CSR116[15:8] (OnNow Misc. Config.) 06h CSR116[7:0] (OnNow Misc. Config.) Hardware ID; must be 11h if compatibility to 04h 09h 08h Reserved location: must be 00h AMD drivers is desired 05h 0Bh User programmable space 0Ah User programmable space LSB of two-byte checksum, which is the MSB of two-byte checksum, which is the sum 06h 0Dh 0Ch sum of bytes 00h-0Bh and bytes 0Eh and of bytes 00h-0Bh and bytes 0Eh and 0Fh 0Fh Must be ASCII “W” (57h) if compatibility to Must be ASCII “W” (57h) if compatibility to 07h 0Fh 0Eh AMD driver software is desired AMD driver software is desired 08h 11h BCR2[15:8] (Miscellaneous Configuration) 10h BCR2[7:0] (Miscellaneous Configuration) 09h 13h BCR4[15:8] (Link Status LED) 12h BCR4[7:0] (Link Status LED) 0Ah 15h BCR5[15:8] (LED1 Status) 14h BCR5[7:0] (LED1 Status) 0Bh 17h BCR6[15:8] (LED2 Status) 16h BCR6[7:0] (LED2 Status) 0Ch 19h BCR7[15:8] (LED3 Status) 18h BCR7[7:0] (LED3 Status) 0Dh 1Bh BCR9[15:8] (Full-Duplex Control) 1Ah BCR9[7:0] (Full-Duplex Control) 0Eh 1Dh BCR18[15:8] (Burst and Bus Control) 1Ch BCR18[7:0] (Burst and Bus Control) 0Fh 1Fh BCR22[15:8] (PCI Latency) 1Eh BCR22[7:0] (PCI Latency) 10h 21h BCR23[15:8] (PCI Subsystem Vendor ID) 20h BCR23[7:0] (PCI Subsystem Vendor ID) 11h 23h BCR24[15:8] (PCI Subsystem ID) 22h BCR24[7:0] (PCI Subsystem ID) 12h 25h BCR25[15:8] (SRAM Size) 24h BCR25[7:0] (SRAM Size) 13h 27h BCR26[15:8] (SRAM Boundary) 26h BCR26[7:0] (SRAM Boundary) 14h 29h BCR27[15:8] (SRAM Interface Control) 28h BCR27[7:0] (SRAM Interface Control) 15h 2Bh BCR32[15:8] (MII Control and Status) 2Ah BCR32[7:0] (MII Control and Status) 16h 2Dh BCR33[15:8] (MII Address) 2Ch BCR33[7:0] (MII Address) 17h 2Fh BCR35[15:8] (PCI Vendor ID) 2Eh BCR35[7:0] (PCI Vendor ID) 18h 31h BCR36[15:8] (Conf. Space byte 43h alias) 30h BCR36[7:0] (Conf. Space byte 42h alias) 19h 33h BCR37[15:8] (DATA_SCALE alias 0) 32h BCR37[7:0] (Conf. Space byte 47h 0 alias) 1Ah 35h BCR38[15:8] (DATA_SCALE alias 1) 34h BCR38[7:0] (Conf. Space. byte 47h 1 alias) 1Bh 75h BCR39[15:8] (DATA_SCALE alias 2) 36h BCR39[7:0] (Conf. Space. byte 47h 2 alias) 1Ch 39h BCR40[15:8] (DATA_SCALE alias 3) 38h BCR40[7:0] (Conf. Space. byte 47h 3 alias) 1Dh 3Bh BCR41[15:8] (DATA_SCALE alias 4) 3Ah BCR41[7:0] (Conf. Space. byte 47h 4 alias) 1Eh 3Dh BCR42[15:8] (DATA_SCALE alias 0) 3Ch BCR42[7:0] (Conf. Space. byte 47h 5 alias) 1Fh 3Fh BCR43[15:8] (DATA_SCALE alias 0) 3Eh BCR43[7:0] (Conf. Space. byte 47h 6 alias) 20h 41h BCR44[15:8] (DATA_SCALE alias 0) 40h BCR44[7:0] (Conf. Space. byte 47h 7 alias) Checksum adjust byte for the 68 bytes of the 21h 43h EEPROM contents. Checksum of the 68 bytes 42h Reserved location: must be 00h of the EEPROM should total FFh. Unused locations - Ignored by device 3Fh 7Fh Reserved 7Eh Reserved (active high). The output can be stretched to allow the human eye to recognize even short events that last only several microseconds. After H_RESET, the four LED The LED pins can be configured to operate in either outputs are configured as shown in Table 11. open-drain mode (active low) or in totem-pole mode Am79C972 83 Table 11. LED Default Configuration COL COLE LED Output Indication Driver Mode Pulse Stretch FDLS FDLSE Open Drain - LED0 Link Status Active Low Enabled LNKS LNKSE Receive Open Drain - LED1 Status Active Low Enabled RCV RCVE To Open Drain - RCVM Pulse LED2 -- Active Low Enabled Stretcher RCVME Transmit Open Drain - XMT LED3 Status Active Low Enabled XMTE For each LED register, each of the status signals is _SPEED_SEL 100E AND’d with its enable signal, and these signals are all OR’d together to form a combined status signal. Each MPS MPSE LED pin combined status signal can be programmed to 21485C-50 run to a pulse stretcher, which consists of a 3-bit shift register clocked at 38 Hz (26 ms). The data input of Figure 47. LED Control Logic each shift register is normally at logic 0. The OR gate output for each LED register asynchronously sets all The general scheme for the PCnet-FAST+ power man- three bits of its shift register when the output becomes agement is that when a PCI Wake-up event is detected, asserted. The inverted output of each shift register is a signal is generated to cause hardware external to the used to control an LED pin. Thus, the pulse stretcher PCnet-FAST+ device to put the computer into the work- provides 2 to 3 clocks of stretched LED output, or 52 ing (S0) mode. ms to 78 ms. See Figure 47. The PCnet-FAST+ device supports three types of Power Savings Mode wake-up events: Power Management Support 1. Magic Packet Detect PCnet-FAST+ supports power management as defined 2. OnNow Pattern Match Detect in the PCI Bus Power Management Interface Specifica- tion V1.0 and Network Device Class Power Manage- 3. Link State Change ment Reference Specification V1.0.These Figure 48 shows the relationship between these Wake- specifications define the network device power states, up events and the various outputs used to signal to the PCI power management interface including the Capa- external hardware. bilities Data Structure and power management regis- ters block definitions, power management events, and Note: The OnNOW Pattern Match and Link State OnNow network Wake-up events. In addition, Change only work on the MII interface. PCnet-FAST+ supports legacy power management OnNow Wake-Up Sequence schemes, such as Remote Wake-Up (RWU) mode. The system software enables the PME pin by setting When the system is in RWU mode, PCI bus power is the PME_EN bit in the PMCSR register (PCI configura- on, the PCI clock may be slowed down or stopped, and tion registers, offset 44h, bit 8) to 1. When a Wake-up the wake-up output pin may drive the CPU's System event is detected, the PCnet-FAST+ device sets the Management Interrupt (SMI) line. PME_STATUS bit in the PMCSR register (PCI configu- ration registers, offset 44h, bit 15). Setting this bit causes the PME signal to be asserted. Assertion of the PME signal causes external hardware to wake up the CPU. The system software then reads the PMCSR reg- ister of every PCI device in the system to determine which device asserted the PME signal. 84 Am79C972 Magic Packet WUMI MPPEN MPINT PG LED MPMAT SET S Q MPMODE MPEN POR R Q CLR MPDETECT RWU Link Change LCDET LCMODE SET S Q SET S Q Link Change R Q CLR H_RESET R Q CLR POR PME_STATUS DET Q S Pattern Match POR R Q CLR PMAT BCR47 BCR46 BCR45 SET S Q Input Pattern Pattern Match RAM (PMR) R Q CLR POR PME Status PME_EN PME MPMAT PME_EN_OVR LCEVENT 21485C-51 Figure 48. OnNow Functional Diagram When the software determines that the signal came When this bit is set, any change in the Link status will from the PCnet-FAST+ device, it writes to the device’s cause the LCDET bit (CSR116, bit 9) to be set. When PMCSR to put the device into power state D0. The soft- the LCDET bit is set, the RWU pin will be asserted and ware then writes a 0 to the PME_STATUS bit to clear the PME_STATUS bit (PMCSR register, bit 15) will be the bit and turn off the PME signal, and it calls the de- set. If either the PME_EN bit (PMCSR, bit 8) or the vice’s software driver to tell it that the device is now in PME_EN_OVR bit (CSR116, bit 10) are set, then the state D0. The system software can clear the PME will also be asserted. PME_STATUS bit either before, after, or at the same OnNow Pattern Match Mode time that it puts the device back into the D0 state. In the OnNow Pattern Match Mode, the PCnet-FAST+ Link Change Detect compares the incoming packets with up to eight pat- Link change detect is one of Wake-up events defined terns stored in the Pattern Match RAM (PMR). The by the OnNow specification and is supported by the stored patterns can be compared with part or all of in- RWU mode. Link Change Detect mode is set when the coming packets, depending on the pattern length and LCMODE bit (CSR116, bit 8) is set either by software the way the PMR is programmed. When a pattern or loaded through the EEPROM. match has been detected, then PMAT bit (CSR116, bit 7) is set. The setting of the PMAT bit causes the Am79C972 85 PME_STATUS bit (PMCSR, bit 15) to be set, which in and bytes 3 and 2 are ignored in the pattern matching turn will assert the PME pin if the PME_EN bit operation. (PMCSR, bit 8) is set. The contents of the PMR are not affected by Pattern Match RAM (PMR) H_RESET, S_RESET, or STOP. The contents are un- defined after a power up reset (POR). PMR is organized as an array of 64 words by 40 bits as shown in Figure 49. The PMR is programmed indirectly Magic Packet Mode through the BCRs 45, 46, and 47. When the BCR45 is In Magic Packet mode, the PCnet-FAST+ controller re- written and the PMAT_MODE bit (BCR45, bit 7) is set mains fully powered up (all VDD and VDDB pins must to 1, Pattern Match logic is enabled. No bus accesses remain at their supply levels). The device will not gen- into the PMR are possible when the PMAT_MODE bit erate any bus master transfers. No transmit operations is set, and BCR46, BCR47, and all other bits in BCR45 will be initiated on the network. The device will continue are ignored. When PMAT_MODE is set, a read of to receive frames from the network, but all frames will BCR45 returns all bits undefined except for be automatically flushed from the receive FIFO. Slave PMAT_MODE. In order to access the contents of the accesses to the PCnet-FAST+ controller are still possi- PMR, PMAT_MODE bit should be programmed to 0. ble. A Magic Packet is a frame that is addressed to the When BCR45 is written to set the PMAT_MODE bit to PCnet-FAST+ controller and contains a data sequence 0, the Pattern Match logic is disabled and accesses to anywhere in its data field made up of 16 consecutive the PMR are possible. Bits 6:0 of BCR45 specify the copies of the device’s physical address (PADR[47:0]). address of the PMR word to be accessed. Writing to The PCnet-FAST+ controller will search incoming BCR45 does not immediately affect the contents of the frames until it finds a Magic Packet frame. It starts PMR. Following the write to BCR45, the PMR word ad- scanning for the sequence after processing the length dressed by the bits 6:0 of the BCR45 may be read by field of the frame. The data sequence can begin any- reading BCR45, BCR46, and BCR47 in any order. To where in the data field of the frame, but must be de- write to the PMR word, the write to BCR45 must be tected before the PCnet-FAST+ controller reaches the followed by a write to BCR46 and a write to BCR47 in frame’s FCS field. Any deviation of the incoming that order to complete the operation. The PMR will not frame’s data sequence from the required physical ad- actually be written until the write to BCR47 is complete. dress sequence, even by a single bit, will prevent the detection of that frame as a Magic Packet frame. The first two 40-bit words in this RAM serve as pointers and contain enable bits for the eight possible match The PCnet-FAST+ controller supports two different patterns. The remainder of the RAM contains the modes of address detection for a Magic Packet frame. match patterns and associated match pattern control If MPPLBA (CSR5, bit 5) or EMPPLBA (CSR116, bit 6) bits. The byte 0 of the first word contains the Pattern are at their default value of 0, the PCnet-FAST+ con- Enable bits. Any bit position set in this byte enables the troller will only detect a Magic Packet frame if the des- corresponding match pattern in the PMR, as an exam- tination address of the packet matches the content of ple if the bit 3 is set, then the Pattern 3 is enabled for the physical address register (PADR). If MPPLBA or matching. Bytes 1 to 4 in the first word are pointers to EMPPLBA are set to 1, the destination address of the the beginning of the patterns 0 to 3, and bytes 1 to 4 in Magic Packet frame can be unicast, multicast, or the second word are pointers to the beginning of the broadcast. patterns 4 to 7, respectively. Byte 0 of the second word Note: The setting of MPPLBA or EMPPLBA only ef- has no function associated with it.The byte 0 of the fects the address detection of the Magic Packet frame. words 2 to 63 is the Control Field of the PMR. Bit 7 of The Magic Packet’s data sequence must be made up this field is the End of Packet (EOP) bit. When this bit is of 16 consecutive copies of the device’s physical ad- set, it indicates the end of a pattern in the PMR. Bits 6- dress (PADR[47:0]), regardless of what kind of destina- 4 of the Control Field byte are the SKIP bits. The value tion address it has. of the SKIP field indicates the number of the Dwords to be skipped before the pattern in this PMR word is com- pared with data from the incoming frame. A maximum of seven Dwords may be skipped. Bits 3-0 of the Con- trol Field byte are the MASK bits. These bits corre- spond to the pattern match bytes 3-0 of the same PMR word (PMR bytes 4-1). If bit n of this field is 0, then byte n of the corresponding pattern word is ignored. If this field is programmed to 3, then bytes 0 and 1 of the pat- tern match field (bytes 2 and 1 of the word) are used 86 Am79C972 BCR 47 BCR 46 BCR 45 BCR Bit Number 15 8 7 0 15 8 7 0 15 8 PMR_B4 PMR_B3 PMR_B2 PMR_B1 PMR_B0 Pattern Match RAM Bit Number Pattern Match Comments RAM Address 39 32 31 24 23 16 15 8 7 0 Pattern Enable 0 P3 pointer P2 pointer P1 pointer P0 pointer First Address bits Second 1 P7 pointer P6 pointer P5 pointer P4 pointer X Address Start Pattern 2 Data Byte 3 Data Byte 2 Data Byte1 Data Byte 0 Pattern Control P 1 2+n Data Byte 4n+3 Date Byte 4n+2 Data Byte 4n+1 Data Byte 4n+0 Pattern Control End Pattern P 1 J Data Byte 3 Data Byte 2 Data Byte 1 Data Byte 0 Pattern Control Start Pattern P k J+m Data Byte 4m+3 Data Byte 4m+2 Data Byte 4m+1 Data Byte 4m+0 Pattern Control End Pattern P k 63 Last Address 7 6 5 4 3 2 1 0 EOP SKIP MASK 21485C-52 Figure 49. Pattern Match RAM There are two general methods to place the PCnet- Magic Packet Mode when either the PG input is FAST+ into the Magic Packet mode. The first is the soft- deasserted or the MPEN bit is set. WUMI output will be ware method. In this method, either the BIOS or other asserted when the PCnet-FAST+ is in the Magic software, sets the MPMODE bit (CSR5, bit 1). Then Packet mode. Magic Packet mode can be disabled at PCnet-FAST+ controller must be put into suspend any time by asserting PG or clearing MPEN bit. mode (see description of CSR5, bit 0), allowing any When the PCnet-FAST+ controller detects a Magic current network activity to finish. Finally, either PG must Packet frame, it sets the MPMAT bit (CSR116, bit 5), be deasserted (hardware control) or MPEN (CSR5, bit the MPINT bit (CSR5, bit 4), and the PME_STATUS bit 2) must be set to 1 (software control). (PMCSR, bit 15). The setting of the MPMAT bit will also Note: FASTSPNDE (CSR7, bit 15) has no meaning in cause the RWU pin to be asserted and if the PME_EN Magic Packet mode. or the PME_EN_OVR bits are set, then the PME will be asserted as well. If IENA (CSR0, bit 6) and MPINTE The second method is the hardware method. In this (CSR5, bit 3) are set to 1, INTA will be asserted. Any method, the MPPEN bit (CSR116, bit 4) is set at power one of the four LED pins can be programmed to indi- up by the loading of the EEPROM. This bit can also be cate that a Magic Packet frame has been received. set by software. The PCnet-FAST+ will be placed in the Am79C972 87 MPSE (BCR4-7, bit 9) must be set to 1 to enable that Mode Select (TMS) pins. An independent power-on function. reset circuit is provided to ensure that the FSM is in the TEST_LOGIC_RESET state at power-up. Therefore, Note: The polarity of the LED pin can be programmed the TRST is not provided. The FSM is also reset when to be active HIGH by setting LEDPOL (BCR4-7, bit 14) TMS and TDI are high for five TCK periods. to 1. Supported Instructions Once a Magic Packet frame is detected, the PCnet- FAST+ controller will discard the frame internally, but In addition to the minimum IEEE 1149.1 requirements will not resume normal transmit and receive operations (BYPASS, EXTEST, and SAMPLE instructions), three until PG is asserted or MPEN is cleared. Once both of additional instructions (IDCODE, TRIBYP, and SET- these events has occurred, indicating that the system BYP) are provided to further ease board-level testing. has detected the Magic Packet and is awake, the con- All unused instruction codes are reserved. See Table troller will continue polling receive and transmit de- 12 for a summary of supported instructions. scriptor rings where it left off. It is not necessary to re- Table 12. IEEE 1149.1 Supported Instruction initialize the device. If the part is reinitialized, then the Summary descriptor locations will be reset and the PCnet-FAST+ controller will not start where it left off. Instructio Instructi Selected n on Data If magic packet mode is disabled by the assertion of Name Code Description Mode Register PG, then in order to immediately re-enable Magic EXTEST 0000 External Test Test BSR Packet mode, the PG pin must remain asserted for at ID Code least 200 ns before it is deasserted. If Magic Packet IDCODE 0001 Normal ID REG Inspection mode is disabled by clearing MPEN bit, then it may be Sample immediately re-enabled by setting MPEN back to 1. SAMPLE 0010 Normal BSR Boundary The PCI bus interface clock (CLK) is not required to be TRIBYP 0011 Force Float Normal Bypass running while the device is operating in Magic Packet Control mode. Either of the INTA, the LED pins, RWU or the SETBYP 0100 Boundary To Test Bypass PME signal may be used to indicate the receipt of a 1/0 Magic Packet frame when the CLK is stopped. If the BYPASS 1111 Bypass Scan Normal Bypass system wishes to stop the CLK, it will do so after en- abling the Magic Packet mode. Instruction Register and Decoding Logic CAUTION: To prevent unwanted interrupts from other After the TAP FSM is reset, the IDCODE instruction is active parts of the PCnet-FAST+ controller, care must always invoked. The decoding logic gives signals to con- be taken to mask all likely interruptible events during trol the data flow in the Data registers according to the Magic Packet mode. An example would be the inter- current instruction. rupts from the Media Independent Interface, which Boundary Scan Register could occur while the device is in Magic Packet mode. Each Boundary Scan Register (BSR) cell has two IEEE 1149.1 (1990) Test Access Port stages. A flip-flop and a latch are used for the Serial Interface Shift Stage and the Parallel Output Stage, respectively. An IEEE 1149.1-compatible boundary scan Test Ac- There are four possible operation modes in the BSR cess Port is provided for board-level continuity test and cell shown in Table 13. diagnostics. All digital input, output, and input/output pins are tested. The following paragraphs summarize the IEEE 1149.1-compatible test functions imple- Table 13. BSR Mode Of Operation mented in the Am79C972 controller. 1 Capture Boundary Scan Circuit 2 Shift 3 Update The boundary scan test circuit requires four pins (TCK, TMS, TDI, and TDO), defined as the Test Access Port 4 System Function (TAP). It includes a finite state machine (FSM), an in- struction register, a data register array, and a power-on reset circuit. Internal pull-up resistors are provided for the TDI, TCK, and TMS pins. TAP Finite State Machine The TAP engine is a 16-state finite state machine (FSM), driven by the Test Clock (TCK), and the Test 88 Am79C972 Other Data Registers of RST. The result of the NAND tree test can be ob- served on the INTA pin. See Figure 50. Other data registers are the following: Pin 143 (RST) is the first input to the NAND tree. Pin 1. Bypass Register (1 bit) 144 (CLK) is the second input to the NAND tree, fol- 2. Device ID register (32 bits) (Table 14). lowed by pin 145 (GNT). All other PCI bus signals fol- low, counterclockwise, with pin 129 (EAR) being the last. Table 15 shows the complete list of pins connected Table 14. Device ID Register to the NAND tree. Bits 31-28 Version RST must be asserted low to start a NAND tree test se- Bits 27-12 Part Number (0010 0110 0010 0100) quence. Initially, all NAND tree inputs except RST Manufacturer ID. The 11 bit manufacturer ID should be driven high. This will result in a high output Bits 11-1 cod for AMD is 00000000001 in accordance at the INTA pin. If the NAND tree inputs are driven from with JEDEC publication 106-A. high to low in the same order as they are connected to Bit 0 Always a logic 1 build the NAND tree, INTA will toggle every time an ad- ditional input is driven low. INTA will change to low, Note: The content of the Device ID register is the when CLK is driven low and all other NAND tree inputs same as the content of CSR88. stay high. INTA will toggle back to high, when GNT is additionally driven low. The square wave will continue NAND Tree Testing until all NAND tree inputs are driven low. INTA will be The Am79C972 controller provides a NAND tree test high, when all NAND tree inputs are driven low. See mode to allow checking connectivity to the device on a Figure 51. printed circuit board. The NAND tree is built on all PCI Some of the pins connected to the NAND tree are out- bus, TBC_EN, and EAR pins. puts in normal mode of operation. They must not be NAND tree testing is enabled by asserting RST. PG driven from an external source until the Am79C972 input should be driven HIGH during NAND tree testing. controller is configured for NAND tree testing. All PCI bus signals will become inputs on the assertion VDD RST (pin143) CLK (pin 144) Am79C972 GNT (pin 145) Core .... INTA S B INTA (pin 142) O A MUX EAR (pin 129) 21485C-53 Figure 50. NAND Tree Circuitry Am79C972 89 Table 15. NAND Tree Pin Sequence NAND Tree NAND Tree NAND Tree Input No. Pin No. Name Input No. Pin No. Name Input No. Pin No. Name 1 143 RST 18 7 AD20 35 34 AD13 2 144 CLK 19 9 AD19 36 36 AD12 3 145 GNT 20 10 AD18 37 37 AD11 4 146 REQ 21 12 AD17 38 39 AD10 5 148 AD31 22 14 AD16 39 40 AD9 6 151 AD30 23 15 C/BE2 40 41 AD8 7 152 AD29 24 17 FRAME 41 42 C/BE0 8 153 AD28 25 18 IRDY 42 44 AD7 9 154 AD27 26 20 TRDY 43 46 AD6 10 156 AD26 27 22 DEVSEL 44 47 AD5 11 158 AD25 28 23 STOP 45 49 AD4 12 159 AD24 29 25 PERR 46 50 AD3 13 160 C/BE3 30 26 SERR 47 52 AD2 14 1 IDSEL 31 28 PAR 48 54 AD1 15 2 AD23 32 30 C/BE1 49 55 AD0 16 4 AD22 33 31 AD15 50 123 TBC_EN 17 6 AD21 34 33 AD14 51 129 EAR RST CLK GNT REQ AD[31:0] FFFFFFFF 0000FFFF C/BE[3:0] F 7 31 IDSEL FRAME IRDY TRDY DEVSEL STOP PERR SERR PAR ... ... ... INTA 21485C-54 Figure 51. NAND Tree Waveform 90 Am79C972 to terminate all network activity in an orderly sequence Reset before issuing an S_RESET. There are four different types of RESET operations that may be performed on the Am79C972 device, STOP H_RESET, S_RESET, STOP, and POR. The following A STOP reset is generated by the assertion of the is a description of each type of RESET operation. STOP bit in CSR0. Writing a 1 to the STOP bit of CSR0, when the stop bit currently has a value of 0, will initiate H_RESET a STOP reset. If the STOP bit is already a 1, then writ- Hardware Reset (H_RESET) is an Am79C972 reset ing a 1 to the STOP bit will not generate a STOP reset. operation that has been created by the proper asser- tion of the RST pin of the Am79C972 device while the STOP will reset all or some portions of CSR0, 3, and 4 PG pin is HIGH. When the minimum pulse width timing to default values. For the identity of individual CSRs as specified in the RST pin description has been satis- and bit locations that are affected by STOP, see the in- fied, then an internal reset operation will be performed. dividual CSR register descriptions. STOP will not affect any of the BCR and PCI configuration space locations. H_RESET will program most of the CSR and BCR reg- STOP will cause the microcode program to jump to its isters to their default value. Note that there are several reset state. Following the end of the STOP operation, CSR and BCR registers that are undefined after the Am79C972 controller will not attempt to read the H_RESET. See the sections on the individual registers EEPROM device. for details. Note: STOP will not cause a deassertion of the REQ H_RESET will clear most of the registers in the PCI signal, if it happens to be active at the time of the write configuration space. H_RESET will cause the micro- to CSR0. The Am79C972 controller will wait until it code program to jump to its reset state. Following the gains bus ownership and it will first finish all scheduled end of the H_RESET operation, the Am79C972 con- bus master accesses before the STOP reset is exe- troller will attempt to read the EEPROM device through cuted. the EEPROM interface. STOP terminates all network activity abruptly. The host H_RESET will clear DWIO (BCR18, bit 7) and the can use the suspend mode (SPND, CSR5, bit 0) to ter- Am79C972 controller will be in 16-bit I/O mode after minate all network activity in an orderly sequence be- the reset operation. A DWord write operation to the fore setting the STOP bit. RDP (I/O offset 10h) must be performed to set the de- Power on Reset vice into 32-bit I/O mode. Power on Reset (POR) is generated when the S_RESET Am79C972 controller is powered up. POR generates a Software Reset (S_RESET) is an Am79C972 reset op- hardware reset (H_RESET). In addition, it clears some eration that has been created by a read access to the bits that H_RESET does not affect. Reset register, which is located at offset 14h in Word Software Access I/O mode or offset 18h in DWord I/O mode from the Am79C972 I/O or memory mapped I/O base address. PCI Configuration Registers S_RESET will reset all of or some portions of CSR0, 3, The Am79C972 controller implements the 256-byte 4, 15, 80, 100, and 124 to default values. For the iden- configuration space as defined by the PCI specification tity of individual CSRs and bit locations that are af- revision 2.1. The 64-byte header includes all registers fected by S_RESET, see the individual CSR register required to identify the Am79C972 controller and its descriptions. S_RESET will not affect any PCI configu- function. Additionally, PCI Power Management Inter- ration space location. S_RESET will not affect any of face registers are implemented at location 40h - 47h. the BCR register values. S_RESET will cause the mi- The layout of the Am79C972 PCI configuration space crocode program to jump to its reset state. Following is shown in Table 16. the end of the S_RESET operation, the Am79C972 The PCI configuration registers are accessible only by controller will not attempt to read the EEPROM device. configuration cycles. All multi-byte numeric fields follow After S_RESET, the host must perform a full re-initial- little endian byte ordering. All write accesses to Re- ization of the Am79C972 controller before starting net- served locations have no effect; reads from these loca- work activity. S_RESET will cause REQ to deassert tions will return a data value of 0. immediately. STOP (CSR0, bit 2) or SPND (CSR5, bit 0) can be used to terminate any pending bus master- I/O Resources ship request in an orderly sequence. The Am79C972 controller requires 32 bytes of address S_RESET terminates all network activity abruptly. The space for access to all the various internal registers as host can use the suspend mode (SPND, CSR5, bit 0) well as to some setup information stored in an external serial EEPROM. A software reset port is available, too. Am79C972 91 Table 16. PCI Configuration Space Layout 31 24 23 16 15 8 7 0 Offset Device ID Vendor ID 00h Status Command 04h Base-Class Sub-Class Programming IF Revision ID 08h Reserved Header Type Latency Timer Reserved 0Ch I/O Base Address 10h Memory Mapped I/O Base Address 14h Reserved 18h Reserved 1Ch Reserved 20h Reserved 24h Reserved 28h Subsystem ID Subsystem Vendor ID 2Ch Expansion ROM Base Address 30h Reserved CAP-PTR 34h Reserved 38h MAX_LAT MIN_GNT Interrupt Pin Interrupt Line 3Ch PMC NXT_ITM_PTR CAP_ID 40h DATA_REG PMCSR_BSE PMCSR 44H . Reserved . Reserved FCh The Am79C972 controller supports mapping the ad- CSR. The BCR Data Port (BDP) is used to access a dress space to both I/O and memory space. The value BCR. in the PCI I/O Base Address register determines the In order to access a particular CSR location, the RAP start address of the I/O address space. The register is should first be written with the appropriate CSR ad- typically programmed by the PCI configuration utility dress. The RDP will then point to the selected CSR. A after system power-up. The PCI configuration utility read of the RDP will yield the selected CSR data. A must also set the IOEN bit in the PCI Command register write to the RDP will write to the selected CSR. In order to enable I/O accesses to the Am79C972 controller. For to access a particular BCR location, the RAP should memory mapped I/O access, the PCI Memory Mapped first be written with the appropriate BCR address. The I/O Base Address register controls the start address of BDP will then point to the selected BCR. A read of the the memory space. The MEMEN bit in the PCI Com- BDP will yield the selected BCR data. A write to the mand register must also be set to enable the mode. Both BDP will write to the selected BCR. base address registers can be active at the same time. Once the RAP has been written with a value, the RAP The Am79C972 controller supports two modes for ac- value remains unchanged until another RAP write oc- cessing the I/O resources. For backwards compatibility curs, or until an H_RESET or S_RESET occurs. RAP with AMD’s 16-bit Ethernet controllers, Word I/O is the is cleared to all 0s when an H_RESET or S_RESET oc- default mode after power up. The device can be config- curs. RAP is unaffected by setting the STOP bit. ured to DWord I/O mode by software. Address PROM Space I/O Registers The Am79C972 controller allows for connection of a The Am79C972 controller registers are divided into two serial EEPROM. The first 16 bytes of the EEPROM will groups. The Control and Status Registers (CSR) are be automatically loaded into the Address PROM used to configure the Ethernet MAC engine and to ob- (APROM) space after H_RESET. Additionally, the first tain status information. The Bus Control Registers six bytes of the EEPROM will be loaded into CSR12 to (BCR) are used to configure the bus interface unit and CSR14. The Address PROM space is a convenient the LEDs. Both sets of registers are accessed using in- place to store the value of the 48-bit IEEE station ad- direct addressing. dress. It can be overwritten by the host computer and The CSR and BCR share a common Register Address its content has no effect on the operation of the control- Port (RAP). There are, however, separate data ports. ler. The software must copy the station address from The Register Data Port (RDP) is used to access a the Address PROM space to the initialization block in 92 Am79C972 order for the receiver to accept unicast frames directed gramming of the Am79C972 control registers. Table 18 to this station. shows legal I/O accesses in Word I/O mode. The six bytes of the IEEE station address occupy the first six locations of the Address PROM space. The Table 17. I/O Map In Word I/O Mode (DWIO = 0) next six bytes are reserved. Bytes 12 and 13 should No. of match the value of the checksum of bytes 1 through 11 Offset Bytes Register and 14 and 15. Bytes 14 and 15 should each be ASCII 00h - 0Fh 16 APROM “W” (57h). The above requirements must be met in 10h 2 RDP order to be compatible with AMD driver software. APROMWE bit (BCR2, bit 8) must be set to 1 to enable 12h 2 RAP (shared by RDP and BDP) write access to the Address PROM space. 14h 2 Reset Register Reset Register 16h 2 BDP A read of the Reset register creates an internal soft- 18h - 1Fh 8 Reserved ware reset (S_RESET) pulse in the Am79C972 control- Double Word I/O Mode ler. The internal S_RESET pulse that is generated by this access is different from both the assertion of the The Am79C972 controller can be configured to operate hardware RST pin (H_RESET) and from the assertion in DWord (32-bit) I/O mode. The software can invoke of the software STOP bit. Specifically, S_RESET is the the DWIO mode by performing a DWord write access equivalent of the assertion of the RST pin (H_RESET) to the I/O location at offset 10h (RDP). The data of the except that S_RESET has no effect on the BCR or PCI write access must be such that it does not affect the in- Configuration space locations. tended operation of the Am79C972 controller. Setting the device into 32-bit I/O mode is usually the first oper- The NE2100 LANCE-based family of Ethernet cards ation after H_RESET or S_RESET. The RAP register requires that a write access to the Reset register fol- will point to CSR0 at that time. Writing a value of 0 to lows each read access to the Reset register. The CSR0 is a safe operation. DWIO (BCR18, bit 7) will be Am79C972 controller does not have a similar require- set to 1 as an indication that the Am79C972 controller ment. The write access is not required and does not operates in 32-bit I/O mode. have any effect. Note: Even though the I/O resource mapping changes Note: The Am79C972 controller cannot service any when the I/O mode setting changes, the RDP location slave accesses for a very short time after a read access offset is the same for both modes. Once the DWIO bit of the Reset register, because the internal S_RESET has been set to 1, only H_RESET can clear it to 0. The operation takes about 1 μs to finish. The Am79C972 DWIO mode setting is unaffected by S_RESET or set- controller will terminate all slave accesses with the as- ting of the STOP bit. Table 19 shows how the 32 bytes sertion of DEVSEL and STOP while TRDY is not as- of address space are used in DWord I/O mode. serted, signaling to the initiator to disconnect and retry the access at a later time. All I/O resources must be accessed in DWord quanti- ties and on DWord addresses. A read access other Word I/O Mode than listed in Table 20 will yield undefined data, a write After H_RESET, the Am79C972 controller is pro- operation may cause unexpected reprogramming of grammed to operate in Word I/O mode. DWIO (BCR18, the Am79C972 control registers. bit 7) will be cleared to 0. Table 17 shows how the 32 bytes of address space are used in Word I/O mode. All I/O resources must be accessed in word quantities and on word addresses. The Address PROM locations can also be read in byte quantities. The only allowed DWord operation is a write access to the RDP, which switches the device to DWord I/O mode. A read access other than listed in the table below will yield undefined data, a write operation may cause unexpected repro- Am79C972 93 Table 18. Legal I/O Accesses in Word I/O Mode (DWIO = 0) AD[4:0] BE[3:0] Type Comment 0XX00 1110 RD Byte read of APROM location 0h, 4h, 8h or Ch 0XX01 1101 RD Byte read of APROM location 1h, 5h, 9h or Dh 0XX10 1011 RD Byte read of APROM location 2h, 6h, Ah or Eh 0XX11 0111 RD Byte read of APROM location 3h, 7h, Bh or Fh Word read of APROM locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h and 9h or 0XX00 1100 RD Ch and Dh Word read of APROM locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh and Ah or 0XX10 0011 RD Fh and Eh 10000 1100 RD Word read of RDP 10010 0011 RD Word read of RAP 10100 1100 RD Word read of Reset Register 10110 0011 RD Word read of BDP Word write to APROM locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h and 9h or 0XX00 1100 WR Ch and Dh Word write to APROM locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh and Ah or 0XX10 0011 WR Fh and Eh 10000 1100 WR Word write to RDP 10010 0011 WR Word write to RAP 10100 1100 WR Word write to Reset Register 10110 0011 WR Word write to BDP DWord write to RDP, 10000 0000 WR switches device to DWord I/O mode Table 20. Legal I/O Accesses in Double Word I/O Mode (DWIO =1) Table 19. I/O Map In DWord I/O Mode (DWIO = 1) AD[4:0] BE[3:0] Type Comment Offset No. of Bytes Register DWord read of APROM 00h - 0Fh 16 APROM locations 3h (MSB) to 0h 10h 4 RDP 0XX00 0000 RD (LSB), RAP (shared by RDP and 7h to 4h, Bh to 8h or Fh to 14h 4 BDP) Ch 10000 0000 RD DWord read of RDP 18h 4 Reset Register 10100 0000 RD DWord read of RAP 1Ch 4 BDP DWord read of Reset 11000 0000 RD Register DWord write to APROM locations 3h (MSB) to 0h 0XX00 0000 WR (LSB), 7h to 4h, Bh to 8h or Fh to Ch 10000 0000 WR DWord write to RDP 10100 0000 WR DWord write to RAP DWord write to Reset 11000 0000 WR Register 94 Am79C972 The following is a list of the registers that would typi- USER ACCESSIBLE REGISTERS cally need to be programmed once during the setup of The Am79C972 controller has three types of user reg- the Am79C972 controller within a system. The control isters: the PCI configuration registers, the Control and bits in each of these registers typically do not need to Status registers (CSR), and the Bus Control registers be modified once they have been written. However, (BCR). there are no restrictions as to how many times these The Am79C972 controller implements all PCnet-ISA registers may actually be accessed. Note that if the de- (Am79C960) registers, all C-LANCE (Am79C90) regis- fault power up values of any of these registers is ac- ters, plus a number of additional registers. The ceptable to the application, then such registers need Am79C972 CSRs are compatible upon power up with never be accessed at all. both the PCnet-ISA CSRs and all of the C-LANCE Note: Registers marked with “^” may be programma- CSRs. ble through the EEPROM read operation and, there- The PCI configuration registers can be accessed in any fore, do not necessarily need to be written to by the data width. All other registers must be accessed ac- system initialization procedure or by the driver soft- cording to the I/O mode that is currently selected. ware. Registers marked with “*” will be initialized by the When WIO mode is selected, all other register loca- initialization block read operation. tions are defined to be 16 bits in width. When DWIO CSR1 Initialization Block Address[15:0] mode is selected, all these register locations are de- CSR2* Initialization Block Address[31:16] fined to be 32 bits in width, with the upper 16 bits of most register locations marked as reserved locations CSR3 Interrupt Masks and Deferral Control with undefined values. When performing register write CSR4 Test and Features Control operations in DWIO mode, the upper 16 bits should al- ways be written as zeros. When performing register CSR5 Extended Control and Interrupt read operations in DWIO mode, the upper 16 bits of CSR7 Extended Control and Interrupt2 I/O resources should always be regarded as having un- defined values, except for CSR88. CSR8* Logical Address Filter[15:0] The Am79C972 registers can be divided into four CSR9* Logical Address Filter[31:16] groups: PCI Configuration, Setup, Running, and Test. CSR10* Logical Address Filter[47:32] Registers not included in any of these categories can be assumed to be intended for diagnostic purposes. CSR11* Logical Address Filter[63:48] � PCI Configuration Registers CSR12*^ Physical Address[15:0] These registers are intended to be initialized by the CSR13*^ Physical Address[31:16] system initialization procedure (e.g., BIOS device ini- tialization routine) to program the operation of the CSR14*^ Physical Address[47:32] Am79C972 controller PCI bus interface. CSR15* Mode The following is a list of the registers that would typi- CSR24* Base Address of Receive Ring Lower cally need to be programmed once during the initializa- tion of the Am79C972 controller within a system: CSR25* Base Address of Receive Ring Upper — PCI I/O Base Address or Memory Mapped I/O CSR30* Base Address of Transmit Ring Lower Base Address register CSR31* Base Address of Transmit Ring Upper — PCI Expansion ROM Base Address register CSR47* Transmit Polling Interval — PCI Interrupt Line register CSR49* Receive Polling Interval — PCI Latency Timer register CSR76* Receive Ring Length — PCI Status register CSR78* Transmit Ring Length — PCI Command register — OnNow register CSR80 DMA Transfer Counter and FIFO Thresh- old Control � Setup Registers CSR82 Bus Activity Timer These registers are intended to be initialized by the de- vice driver to program the operation of various CSR100 Memory Error Timeout Am79C972 controller features. CSR116^ OnNow Miscellaneous CSR122 Receiver Packet Alignment Control Am79C972 95 CSR125^ MAC Enhanced Configuration Control These registers are intended to be used by the device driver software after the Am79C972 controller is run- BCR2^ Miscellaneous Configuration ning to access status information and to pass control BCR4^ LED0 Status information. BCR5^ LED1 Status The following is a list of the registers that would typi- cally need to be periodically read and perhaps written BCR6^ LED2 Status during the normal running operation of the Am79C972 BCR7^ LED3 Status controller within a system. Each of these registers con- tains control bits, or status bits, or both. BCR9^ Full-Duplex Control RAP Register Address Port BCR18^ Bus and Burst Control CSR0 Am79C972 Controller Status BCR19 EEPROM Control and Status CSR3 Interrupt Masks and Deferral Control BCR20 Software Style CSR4 Test and Features Control BCR22^ PCI Latency CSR5 Extended Control and Interrupt BCR23^ PCI Subsystem Vendor ID CSR7 Extended Control and Interrupt2 BCR24^ PCI Subsystem ID CSR112 Missed Frame Count BCR25^ SRAM Size CSR114 Receive Collision Count BCR26^ SRAM Boundary BCR32 MII Control and Status BCR27^ SRAM Interface Control BCR33 MII Address BCR32^ MII Control and Status BCR34 MII Management Data BCR33^ MII Address � Test Registers BCR35^ PCI Vendor ID These registers are intended to be used only for testing BCR36 PCI Power Management Capabilities and diagnostic purposes. Those registers not included (PMC) Alias Register in any of the above lists can be assumed to be intended for diagnostic purposes. BCR37 PCI DATA Register Zero (DATA0) Alias Register PCI Configuration Registers BCR38 PCI DATA Register One (DATA1) Alias PCI Vendor ID Register Register Offset 00h BCR39 PCI DATA Register Two (DATA2) Alias The PCI Vendor ID register is a 16-bit register that iden- Register tifies the manufacturer of the Am79C972 controller. BCR40 PCI DATA Register Three (DATA3) Alias AMD’s Vendor ID is 1022h. Note that this vendor ID is Register not the same as the Manufacturer ID in CSR88 and CSR89. The vendor ID is assigned by the PCI Special BCR41 PCI DATA Register Four (DATA4) Alias Interest Group. Register The PCI Vendor ID register is located at offset 00h in BCR42 PCI DATA Register Five (DATA5) Alias the PCI Configuration Space. It is read only. Register This register is the same as BCR35 and can be written BCR43 PCI DATA Register Six (DATA6) Alias Reg- by the EEPROM. ister PCI Device ID Register BCR44 PCI DATA Register Seven (DATA7) Alias Offset 02h Register The PCI Device ID register is a 16-bit register that BCR45 OnNow Pattern Matching Register 1 uniquely identifies the Am79C972 controller within BCR46 OnNow Pattern Matching Register 2 AMD's product line. The Am79C972 Device ID is 2000h. Note that this Device ID is not the same as the BCR47 OnNow Pattern Matching Register 3 Part number in CSR88 and CSR89. The Device ID is � Running Registers assigned by AMD. The Device ID is the same as the 96 Am79C972 PCnet-PCI II (Am79C970A) and PCnet-FAST also sets the DATAPERR bit (PCI (Am79C971) devices. Status register, bit 8), when the data parity error occurred during The PCI Device ID register is located at offset 02h in a master cycle. PERREN also the PCI Configuration Space. It is read only. enables reporting address parity PCI Command Register errors through the SERR pin and the SERR bit in the PCI Status Offset 04h register. The PCI Command register is a 16-bit register used to control the gross functionality of the Am79C972 con- PERREN is cleared by troller. It controls the Am79C972 controller’s ability to H_RESET and is not affected by generate and respond to PCI bus cycles. To logically S_RESET or by setting the STOP disconnect the Am79C972 device from all PCI bus cy- bit. cles except configuration cycles, a value of 0 should be written to this register. 5 VGASNOOP VGA Palette Snoop. Read as ze- ro; write operations have no ef- The PCI Command register is located at offset 04h in fect. the PCI Configuration Space. It is read and written by the host. 4 MWIEN Memory Write and Invalidate Cy- cle Enable. Read as zero; write Bit Name Description operations have no effect. The Am79C972 controller only gener- 15-10 RES Reserved locations. Read as ze- ates Memory Write cycles. ros; write operations have no ef- fect. 3 SCYCEN Special Cycle Enable. Read as zero; write operations have no ef- 9 FBTBEN Fast Back-to-Back Enable. Read fect. The Am79C972 controller as zero; write operations have no ignores all Special Cycle opera- effect. The Am79C972 controller tions. will not generate Fast Back-to- Back cycles. 2 BMEN Bus Master Enable. Setting BMEN enables the Am79C972 8 SERREN SERR Enable. Controls the as- controller to become a bus mas- sertion of the SERR pin. SERR is ter on the PCI bus. The host must disabled when SERREN is set BMEN before setting the INIT cleared. SERR will be asserted or STRT bit in CSR0 of the on detection of an address parity Am79C972 controller. error and if both SERREN and PERREN (bit 6 of this register) BMEN is cleared by H_RESET are set. and is not effected by S_RESET or by setting the STOP bit. SERREN is cleared by H_RESET and is not effected by 1 MEMEN Memory Space Access Enable. S_RESET or by setting the STOP The Am79C972 controller will ig- bit. nore all memory accesses when MEMEN is cleared. The host 7 RES Reserved location. Read as ze- must set MEMEN before the first ros; write operations have no ef- memory access to the device. fect. For memory mapped I/O, the 6 PERREN Parity Error Response Enable. host must program the PCI Mem- Enables the parity error response ory Mapped I/O Base Address functions. When PERREN is 0 register with a valid memory ad- and the Am79C972 controller de- dress before setting MEMEN. tects a parity error, it only sets the Detected Parity Error bit in the For accesses to the Expansion PCI Status register. When PER- ROM, the host must program the REN is 1, the Am79C972 control- PCI Expansion ROM Base Ad- ler asserts PERR on the dress register at offset 30h with a detection of a data parity error. It Am79C972 97 valid memory address before set- ferred (TRDY and IRDY are as- ting MEMEN. The Am79C972 serted). controller will only respond to ac-  In master mode, during the data cesses to the Expansion ROM phase of all memory read com- when both ROMEN (PCI Expan- mands. sion ROM Base Address register, bit 0) and MEMEN are set to 1. In master mode, during the data Since MEMEN also enables the phase of the memory write com- memory mapped access to the mand, the Am79C972 controller Am79C972 I/O resources, the sets the PERR bit if the target re- PCI Memory Mapped I/O Base ports a data parity error by as- Address register must be pro- serting the PERR signal. grammed with an address so that the device does not claim cycles PERR is not effected by the state not intended for it. of the Parity Error Response en- able bit (PCI Command register, MEMEN is cleared by H_RESET bit 6). and is not effected by S_RESET or by setting the STOP bit. PERR is set by the Am79C972 controller and cleared by writing a 0 IOEN I/O Space Access Enable. The 1. Writing a 0 has no effect. Am79C972 controller will ignore PERR is cleared by H_RESET all I/O accesses when IOEN is and is not affected by S_RESET cleared. The host must set IOEN or by setting the STOP bit. before the first I/O access to the device. The PCI I/O Base Ad- 14 SERR Signaled SERR. SERR is set dress register must be pro- when the Am79C972 controller grammed with a valid I/O address detects an address parity error before setting IOEN. and both SERREN and PERREN (PCI Command register, bits 8 IOEN is cleared by H_RESET and 6) are set. and is not effected by S_RESET or by setting the STOP bit. SERR is set by the Am79C972 controller and cleared by writing a PCI Status Register 1. Writing a 0 has no effect. Offset 06h SERR is cleared by H_RESET The PCI Status register is a 16-bit register that contains and is not affected by S_RESET status information for the PCI bus related events. It is or by setting the STOP bit. located at offset 06h in the PCI Configuration Space. 13 RMABORT Received Master Abort. RM- Bit Name Description ABORT is set when the Am79C972 controller terminates 15 PERR Parity Error. PERR is set when a master cycle with a master the Am79C972 controller detects abort sequence. a parity error. RMABORT is set by the The Am79C972 controller sam- Am79C972 controller and ples the AD[31:0], C/BE[3:0], and cleared by writing a 1. Writing a 0 the PAR lines for a parity error at has no effect. RMABORT is the following times: cleared by H_RESET and is not affected by S_RESET or by set-  In slave mode, during the ad- ting the STOP bit. dress phase of any PCI bus com- mand. 12 RTABORT Received Target Abort. RT- ABORT is set when a target ter-  In slave mode, for all I/O, mem- minates an Am79C972 master ory and configuration write com- cycle with a target abort se- mands that select the Am79C972 quence. controller when data is trans- 98 Am79C972 RTABORT is set by the fast back-to-back transactions Am79C972 controller and with the first transaction address- cleared by writing a 1. Writing a 0 ing a different target. has no effect. RTABORT is 6-5 RES Reserved locations. Read as cleared by H_RESET and is not zero; write operations have no ef- affected by S_RESET or by set- fect. ting the STOP bit. 4 NEW_CAP New Capabilities. This bit indi- 11 STABORT Send Target Abort. Read as ze- cates whether this function imple- ro; write operations have no ef- ments a list of extended fect. The Am79C972 controller capabilities such as PCI power will never terminate a slave ac- management. When set, this bit cess with a target abort se- indicates the presence of New quence. Capabilities. A value of 0 means STABORT is read only. that this function does not imple- ment New Capabilities. 10-9 DEVSEL Device Select Timing. DEVSEL is set to 01b (medium), which Read as one; write operations means that the Am79C972 con- have no effect. The Am79C972 troller will assert DEVSEL two controller supports the Linked clock periods after FRAME is as- Additional Capabilities List. serted. 3-0 RES Reserved locations. Read as DEVSEL is read only. zero; write operations have no ef- fect. 8 DATAPERR Data Parity Error Detected. DATAPERR is set when the PCI Revision ID Register Am79C972 controller is the cur- Offset 08h rent bus master and it detects a The PCI Revision ID register is an 8-bit register that data parity error and the Parity specifies the Am79C972 controller revision number. Error Response enable bit (PCI The value of this register is 3Xh with the lower four bits Command register, bit 6) is set. being silicon-revision dependent. During the data phase of all The PCI Revision ID register is located at offset 08h in memory read commands, the the PCI Configuration Space. It is read only. Am79C972 controller checks for PCI Programming Interface Register parity error by sampling the AD[31:0] and C/BE[3:0] and the Offset 09h PAR lines. During the data phase The PCI Programming Interface register is an 8-bit reg- of all memory write commands, ister that identifies the programming interface of the Am79C972 controller checks Am79C972 controller. PCI does not define any specific the PERR input to detect whether register-level programming interfaces for network devic- the target has reported a parity es. The value of this register is 00h. error. The PCI Programming Interface register is located at offset 09h in the PCI Configuration Space. It is read only. DATAPERR is set by the Am79C972 controller and PCI Sub-Class Register cleared by writing a 1. Writing a 0 Offset 0Ah has no effect. DATAPERR is The PCI Sub-Class register is an 8-bit register that iden- cleared by H_RESET and is not tifies specifically the function of the Am79C972 control- affected by S_RESET or by set- ler. The value of this register is 00h which identifies the ting the STOP bit. Am79C972 device as an Ethernet controller. 7 FBTBC Fast Back-To-Back Capable. The PCI Sub-Class register is located at offset 0Ah in Read as one; write operations the PCI Configuration Space. It is read only. have no effect. The Am79C972 controller is capable of accepting Am79C972 99 PCI Base-Class Register 6-0 LAYOUT PCI configuration space layout. Read as zeros; write operations Offset 0Bh have no effect. The layout of the The PCI Base-Class register is an 8-bit register that PCI configuration space loca- broadly classifies the function of the Am79C972 con- tions 10h to 3Ch is as shown in troller. The value of this register is 02h which classifies the table at the beginning of this the Am79C972 device as a network controller. section. The PCI Base-Class register is located at offset 0Bh in PCI I/O Base Address Register the PCI Configuration Space. It is read only. Offset 10h PCI Latency Timer Register The PCI I/O Base Address register is a 32-bit register Offset 0Dh that determines the location of the Am79C972 I/O re- The PCI Latency Timer register is an 8-bit register that sources in all of I/O space. It is located at offset 10h in specifies the minimum guaranteed time the Am79C972 the PCI Configuration Space. controller will control the bus once it starts its bus mas- Bit Name Description tership period. The time is measured in clock cycles. Every time the Am79C972 controller asserts FRAME at the beginning of a bus mastership period, it will copy the 31-5 IOBASE I/O base address most significant value of the PCI Latency Timer register into a counter 27 bits. These bits are written by and start counting down. The counter will freeze at 0. the host to specify the location of When the system arbiter removes GNT while the the Am79C972 I/O resources in all of I/O space. IOBASE must be counter is non-zero, the Am79C972 controller will con- written with a valid address be- tinue with its data transfers. It will only release the bus fore the Am79C972 controller when the counter has reached 0. slave I/O mode is turned on by The PCI Latency Timer is only significant in burst trans- setting the IOEN bit (PCI Com- actions, where FRAME stays asserted until the last data mand register, bit 0). phase. In a non-burst transaction, FRAME is only as- serted during the address phase. The internal latency When the Am79C972 controller counter will be cleared and suspended while FRAME is is enabled for I/O mode (IOEN is deasserted. set), it monitors the PCI bus for a valid I/O command. If the value All eight bits of the PCI Latency Timer register are pro- on AD[31:5] during the address grammable. The host should read the Am79C972 PCI phase of the cycles matches the MIN_GNT and PCI MAX_LAT registers to determine the value of IOBASE, the Am79C972 latency requirements for the device and then initialize controller will drive DEVSEL indi- the Latency Timer register with an appropriate value. cating it will respond to the ac- The PCI Latency Timer register is located at offset 0Dh cess. in the PCI Configuration Space. It is read and written by the host. The PCI Latency Timer register is cleared by IOBASE is read and written by H_RESET and is not effected by S_RESET or by setting the host. IOBASE is cleared by the STOP bit. H_RESET and is not affected by S_RESET or by setting the STOP PCI Header Type Register bit. Offset 0Eh The PCI Header Type register is an 8-bit register that 4-2 IOSIZE I/O size requirements. Read as describes the format of the PCI Configuration Space zeros; write operations have no locations 10h to 3Ch and that identifies a device to be effect. single or multi-function. The PCI Header Type register IOSIZE indicates the size of the is located at address 0Eh in the PCI Configuration I/O space the Am79C972 control- Space. It is read only. ler requires. When the host writes Bit Name Description a value of FFFF FFFFh to the I/O Base Address register, it will read 7 FUNCT Single-function/multi-function de- back a value of 0 in bits 4-2. That vice. Read as zero; write opera- indicates an Am79C972 I/O tions have no effect. The space requirement of 32 bytes. Am79C972 controller is a single function device. 100 Am79C972 1 RES Reserved location. Read as zero; ter, it will read back a value of 0 in write operations have no effect. bit 4. That indicates a Am79C972 memory space requirement of 32 0 IOSPACE I/O space indicator. Read as one; bytes. write operations have no effect. Indicating that this base address 3 PREFETCH Prefetchable. Read as zero; write register describes an I/O base operations have no effect. Indi- address. cates that memory space con- trolled by this base address PCI Memory Mapped I/O Base Address Register register is not prefetchable. Data in the memory mapped I/O space Offset 14h cannot be prefetched. Because The PCI Memory Mapped I/O Base Address register is one of the I/O resources in this a 32-bit register that determines the location of the address space is a Reset regis- Am79C972 I/O resources in all of memory space. It is ter, the order of the read access- located at offset 14h in the PCI Configuration Space. es is important. Bit Name Description 2-1 TYPE Memory type indicator. Read as 31-5 MEMBASE Memory mapped I/O base ad- zeros; write operations have no dress most significant 27 bits. effect. Indicates that this base ad- These bits are written by the host dress register is 32 bits wide and to specify the location of the mapping can be done anywhere Am79C972 I/O resources in all of in the 32-bit memory space. memory space. MEMBASE must 0 MEMSPACE Memory space indicator. Read be written with a valid address as zero; write operations have no before the Am79C972 controller effect. Indicates that this base ad- slave memory mapped I/O mode dress register describes a memo- is turned on by setting the ME- ry base address. MEN bit (PCI Command register, bit 1). PCI Subsystem Vendor ID Register When the Am79C972 controller Offset 2Ch is enabled for memory mapped The PCI Subsystem Vendor ID register is a 16-bit reg- I/O mode (MEMEN is set), it mon- ister that together with the PCI Subsystem ID uniquely itors the PCI bus for a valid mem- identifies the add-in card or subsystem the Am79C972 ory command. If the value on controller is used in. Subsystem Vendor IDs can be ob- AD[31:5] during the address tained from the PCI SIG. A value of 0 (the default) indi- phase of the cycles matches the cates that the Am79C972 controller does not support value of MEMBASE, the subsystem identification. The PCI Subsystem Vendor Am79C972 controller will drive ID is an alias of BCR23, bits 15-0. It is programmable DEVSEL indicating it will respond through the EEPROM. to the access. The PCI Subsystem Vendor ID register is located at off- MEMBASE is read and written by set 2Ch in the PCI Configuration Space. It is read only. the host. MEMBASE is cleared PCI Subsystem ID Register by H_RESET and is not affected by S_RESET or by setting the Offset 2Eh STOP bit. The PCI Subsystem ID register is a 16-bit register that together with the PCI Subsystem Vendor ID uniquely 4 MEMSIZE Memory mapped I/O size re- identifies the add-in card or subsystem the Am79C972 quirements. Read as zeros; write controller is used in. The value of the Subsystem ID is operations have no effect. up to the system vendor. A value of 0 (the default) indi- cates that the Am79C972 controller does not support MEMSIZE indicates the size of subsystem identification. The PCI Subsystem ID is an the memory space the alias of BCR24, bits 15-0. It is programmable through Am79C972 controller requires. the EEPROM. When the host writes a value of FFFF FFFFh to the Memory The PCI Subsystem ID register is located at offset 2Eh Mapped I/O Base Address regis- in the PCI Configuration Space. It is read only. Am79C972 101 PCI Expansion ROM Base Address Register 19-1, indicating an Expansion ROM size of 1M. Offset 30h The PCI Expansion ROM Base Address register is a Note that ROMSIZE only speci- 32-bit register that defines the base address, size and fies the maximum size of Expan- address alignment of an Expansion ROM. It is located sion ROM the Am79C972 at offset 30h in the PCI Configuration Space. controller supports. A smaller ROM can be used, too. The actu- Bit Name Description al size of the code in the Expan- sion ROM is always determined 31-20 ROMBASE Expansion ROM base address by reading the Expansion ROM most significant 12 bits. These header. bits are written by the host to specify the location of the Expan- 0 ROMEN Expansion ROM Enable. Written sion ROM in all of memory space. by the host to enable access to ROMBASE must be written with a the Expansion ROM. The valid address before the Am79C972 controller will only re- Am79C972 Expansion ROM ac- spond to accesses to the Expan- cess is enabled by setting sion ROM when both ROMEN ROMEN (PCI Expansion ROM and MEMEN (PCI Command reg- Base Address register, bit 0) and ister, bit 1) are set to 1. MEMEN (PCI Command register, bit 1). ROMEN is read and written by the host. ROMEN is cleared by Since the 12 most significant bits H_RESET and is not effected by of the base address are program- S_RESET or by setting the STOP mable, the host can map the Ex- bit. pansion ROM on any 1M boundary. PCI Capabilities Pointer Register Offset 34h When the Am79C972 controller is enabled for Expansion ROM Bit Name Description access (ROMEN and MEMEN 7-0 CAP_PTR The PCI Capabilities pointer are set to 1), it monitors the PCI Register is an 8-bit register that bus for a valid memory com- points to a linked list of capabili- mand. If the value on AD[31:2] ties implemented on this device. during the address phase of the This register has a default value cycle falls between ROMBASE of 40h. and ROMBASE + 1M - 4, the Am79C972 controller will drive The PCI Capabilities register is DEVSEL indicating it will respond located at offset 34h in the PCI to the access. Configuration Space. It is read only. ROMBASE is read and written by the host. ROMBASE is cleared PCI Interrupt Line Register by H_RESET and is not affected Offset 3Ch by S_RESET or by setting the The PCI Interrupt Line register is an 8-bit register that STOP bit. is used to communicate the routing of the interrupt. 19-1 ROMSIZE ROM size. Read as zeros; write This register is written by the POST software as it ini- operation have no effect. ROM- tializes the Am79C972 controller in the system. The SIZE indicates the maximum size register is read by the network driver to determine the of the Expansion ROM the interrupt channel which the POST software has as- Am79C972 controller can sup- signed to the Am79C972 controller. The PCI Interrupt port. The host can determine the Line register is not modified by the Am79C972 control- Expansion ROM size by writing ler. It has no effect on the operation of the device. FFFF FFFFh to the Expansion The PCI Interrupt Line register is located at offset 3Ch ROM Base Address register. It in the PCI Configuration Space. It is read and written by will read back a value of 0 in bit 102 Am79C972 the host. It is cleared by H_RESET and is not affected The PCI Capabilities Identifier by S_RESET or by setting the STOP bit. register is located at offset 40h in the PCI Configuration Space. It is PCI Interrupt Pin Register read only. Offset 3Dh PCI Next Item Pointer Register This PCI Interrupt Pin register is an 8-bit register that indicates the interrupt pin that the Am79C972 controller Offset 41h is using. The value for the Am79C972 Interrupt Pin reg- Bit Name Description ister is 01h, which corresponds to INTA. The PCI Interrupt Pin register is located at offset 3Dh 7-0 NXT_ITM_PTR in the PCI Configuration Space. It is read only. The Next Item Pointer Register PCI MIN_GNT Register points to the starting address of Offset 3Eh the next capability. The pointer at The PCI MIN_GNT register is an 8-bit register that this offset is a null pointer, indi- specifies the minimum length of a burst period that the cating that this is the last capabil- Am79C972 device needs to keep up with the network ity in the linked list of the activity. The length of the burst period is calculated as- capabilities. This register has a suming a clock rate of 33 MHz. The register value spec- default value of 0h. ifies the time in units of 1/4 μs. The PCI MIN_GNT The PCI Next Pointer Register is register is an alias of BCR22, bits 7-0. It is recom- located at offset 41h in the PCI mended that the BCR22 be programmed to a value of Configuration Space. It is read 1818h. only. The host should use the value in this register to deter- mine the setting of the PCI Latency Timer register. PCI Power Management Capabilities Register (PMC) The PCI MIN_GNT register is located at offset 3Eh in the PCI Configuration Space. It is read only. Offset 42h Note: All bits of this register are loaded from PCI MAX_LAT Register EEPROM. The register is aliased to BCR36 for testing Offset 3Fh purposes. The PCI MAX_LAT register is an 8-bit register that spec- Bit Name Description ifies the maximum arbitration latency the Am79C972 controller can sustain without causing problems to the 15-11 PME_SPT PME Support. This 5-bit field indi- network activity. The register value specifies the time in cates the power states in which units of 1/4 µs. The MAX_LAT register is an alias of the function may assert PME. A BCR22, bits 15-8. It is recommended that BCR22 be value of 0b for any bit indicates programmed to a value of 1818h. that the function is not capable of The host should use the value in this register to deter- asserting the PME signal while in mine the setting of the PCI Latency Timer register. that power state. The PCI MAX_LAT register is located at offset 3Fh in Bit(11) XXXX1b - PME can be the PCI Configuration Space. It is read only asserted from D0. PCI Capability Identifier Register Bit(12) XXX1Xb - PME can be Offset 40h asserted from D1. Bit Name Description Bit(13) XX1XXb - PME can be 7-0 CAP_ID This register, when set to 1, iden- asserted from D2. tifies the linked list item as being Bit(14) X1XXXb - PME can be the PCI Power Management reg- asserted from D3hot. isters. This register has a default value of 1h. Bit(15) 1XXXXb - PME can be asserted from D3cold. Read only. Am79C972 103 10 D2_SPT D2 Support. If this bit is a 1, this 2-0 PMIS_VER Power Management Interface function supports the D2 Power Specification Version. A value of Management State. 001b indicates that this function complies with the revision 1.0 of Read only. the PCI Power Management In- terface Specification. 9 D1_SPT D1 Support. If this bit is a 1, this function supports the D1 Power PCI Power Management Control/Status Register Management State. (PMCSR) Offset 44h Read only. Bit Name Description 8-6 RES Reserved locations. Written as zeros and read as undefined. 15 PME_STATUS PME Status. This bit is set when the function would normally as- 5 DSI Device Specific Initialization. sert the PME signal independent When this bit is 1, it indicates that of the state of the PME_EN bit. special initialization of the func- tion is required (beyond the stan- Writing a 1 to this bit will clear it dard PCI configuration header) and cause the function to stop as- before the generic class device serting a PME (if enabled). Writ- driver is able to use it. ing a 0 has no effect. Read only. If the function supports PME from D3cold then this bit is sticky and 4 AUXPS Auxiliary Power Source. This bit must be explicitly cleared by the is only meaningful if bit 15 operating system each time the (D3cold supporting PME) is a 1. operating system is initially load- When this bit is also a 1, it indi- ed. cates that support for PME in D3cold requires auxiliary power Read/write accessible always. supplied by the system by way of Sticky bit. This bit is reset by a proprietary delivery vehicle. POR. H_RESET, S_RESET, or setting the STOP bit has no ef- A 0 in this bit indicates that the fect. function supplies its own auxiliary power source. 14-13 DATA_SCALE If the function does not support Data Scale. This two bit read- PME while in D3cold, (bit15=0) only field indicates the scaling then this field must always return factor to be used when interpret- 0. ing the value of the Data register. The value and meaning of this Read only. field will vary depending on the DATA_SCALE field. 3 PME_CLK PME Clock. When this bit is a 1, it indicates that the function relies Read only. on the presence of the PCI clock for PME operation. When this bit 12-9 DATA_SEL Data Select. This optional four-bit is a 0 it indicates that no PCI field is used to select which data clock is required for the function is reported through the Data reg- to generate PME. ister and DATA_SCALE field. Functions that do not support Read/write accessible always. PME generation in any state Sticky bit. This bit is reset by must return 0 for this field. POR. H_RESET, S_RESET, or setting the STOP bit has no ef- Read only. fect. 104 Am79C972 8 PME_EN PME Enable. When a 1, PCI Data Register PME_EN enables the function to Offset 47h assert PME. When a 0, PME as- Note: All bits of this register are loaded from EE- sertion is disabled. PROM. The register is aliased to lower bytes of the BCR37-44 for testing purposes. This bit defaults to “0” if the func- tion does not support PME gener- Bit Name Description ation from D3cold. 7-0 DATA_REG The PCI Data Register is an 8-bit If the function supports PME from register. Refer to the “PCI Bus D3cold, then this bit is sticky and Power Management Interface must be explicitly cleared by the Specification” version 1.0 for a operating system each time the more detailed description of this operating system is initially load- register. ed. The PCI DATA register is located Read/write accessible always. at offset 47h in the PCI Configu- Sticky bit. This bit is reset by ration Space. It is read only. POR. H_RESET, S_RESET, or setting the STOP bit has no ef- RAP Register fect. The RAP (Register Address Pointer) register is used to gain access to CSR and BCR registers on board the 7-2 RES Reserved locations. Read only. Am79C972 controller. The RAP contains the address 1-0 PWR_STATE Power State. This 2-bit field is of a CSR or BCR. used both to determine the cur- As an example of RAP use, consider a read access to rent power state of a function and CSR4. In order to access this register, it is necessary to set the function into a new to first load the value 0004h into the RAP by performing power state. The definition of the a write access to the RAP offset of 12h (12h when WIO field values is given below. mode has been selected, 14h when DWIO mode has been selected). Then a second access is performed, 00b - D0. this time to the RDP offset of 10h (for either WIO or 01b - D1. DWIO mode). The RDP access is a read access, and 10b - D2. since RAP has just been loaded with the value of 0004h, 11b - D3. the RDP read will yield the contents of CSR4. A read of the BDP at this time (offset of 16h when WIO mode has These bits can be written and been selected, 1Ch when DWIO mode has been select- read, but their contents have no ed) will yield the contents of BCR4, since the RAP is effect on the operation of the de- used as the pointer into both BDP and RDP space. vice. RAP: Register Address Port Read/write accessible always. Bit Name Description PCI PMCSR Bridge Support Extensions Register 31-16 RES Reserved locations. Written as Offset 46h zeros and read as undefined. Bit Name Description 15-8 RES Reserved locations. Read and 7-0 PMCSR_BSE The PCI PMCSR Bridge Support written as zeros. Extensions Register is an 8-bit register. PMCSR Bridge Support 7-0 RAP Register Address Port. The value Extensions are not supported. of these 8 bits determines which This register has a default value CSR or BCR will be accessed of 00h. when an I/O access to the RDP or BDP port, respectively, is per- The PCI PMCSR Bridge Support formed. Extensions register is located at offset 46h in the PCI Configura- A write access to undefined CSR tion Space. It is read only. or BCR locations may cause un- expected reprogramming of the Am79C972 105 Am79C972 control registers. A When the MII port is selected, read access will yield undefined CERR is only reported when the values. external PHY is operating as a half-duplex 10BASE-T PHY. Read/Write accessible always. RAP is cleared by H_RESET or CERR assertion will not result in S_RESET and is unaffected by an interrupt being generated. setting the STOP bit. CERR assertion will set the ERR bit. Control and Status Registers Read/Write accessible always. The CSR space is accessible by performing accesses CERR is cleared by the host by to the RDP (Register Data Port). The particular CSR writing a 1. Writing a 0 has no ef- that is read or written during an RDP access will depend fect. CERR is cleared by upon the current setting of the RAP. RAP serves as a H_RESET, S_RESET, or by set- pointer into the CSR space. ting the STOP bit. CSR0: Am79C972 Controller Status and Control 12 MISS Missed Frame is set by the Register Am79C972 controller when it has Certain bits in CSR0 indicate the cause of an interrupt. lost an incoming receive frame The register is designed so that these indicator bits are resulting from a Receive Descrip- cleared by writing ones to those bit locations. This tor not being available. This bit is means that the software can read CSR0 and write back the only immediate indication that the value just read to clear the interrupt condition. receive data has been lost since there is no current receive de- scriptor. The Missed Frame Bit Name Description Counter (CSR112) also incre- ments each time a receive frame 31-16 RES Reserved locations. Written as is missed. zeros and read as undefined. When MISS is set, INTA is as- 15 ERR Error is set by the OR of CERR, serted if IENA is 1 and the mask MISS, and MERR. ERR remains bit MISSM (CSR3, bit 12) is 0. set as long as any of the error MISS assertion will set the ERR flags are true. bit, regardless of the settings of IENA and MISSM. Read accessible always. ERR is read only. Write operations are Read/Write accessible always. ignored. MISS is cleared by the host by writing a 1. Writing a 0 has no ef- 14 RES Reserved locations. Read/Write fect. MISS is cleared by accessible always. Read returns H_RESET, S_RESET, or by set- zero. ting the STOP bit. 13 CERR Collision Error is set by the 11 MERR Memory Error is set by the Am79C972 controller when the Am79C972 controller when it re- device operates in half-duplex quests the use of the system in- mode and the collision inputs to terface bus by asserting REQ the GPSI port failed to activate and has not received GNT asser- within 20 network bit times after tion after a programmable length the chip terminated transmission of time. The length of time in mi- (SQE Test). This feature is a croseconds before MERR is as- transceiver test feature. CERR serted will depend upon the reporting is disabled when the setting of the Bus Timeout Regis- GPSI port is active and the ter (CSR100). The default setting Am79C972 controller operates in of CSR100 will give a MERR after full-duplex mode. 153.6 μs of bus latency. 106 Am79C972 When MERR is set, INTA is as- 8 IDON Initialization Done is set by the serted if IENA is 1 and the mask Am79C972 controller after the bit MERRM (CSR3, bit 11) is 0. initialization sequence has com- MERR assertion will set the ERR pleted. When IDON is set, the bit, regardless of the settings of Am79C972 controller has read IENA and MERRM. the initialization block from mem- ory. Read/Write accessible always. MERR is cleared by the host by When IDON is set, INTA is as- writing a 1. Writing a 0 has no ef- serted if IENA is 1 and the mask fect. MERR is cleared by bit IDONM (CSR3, bit 8) is 0. H_RESET, S_RESET, or by set- Read/Write accessible always. ting the STOP bit. IDON is cleared by the host by 10 RINT Receive Interrupt is set by the writing a 1. Writing a 0 has no ef- Am79C972 controller after the fect. IDON is cleared by last descriptor of a receive frame H_RESET, S_RESET, or by set- has been updated by writing a 0 ting the STOP bit. to the OWNership bit. RINT may 7 INTR Interrupt Flag indicates that one also be set when the first descrip- or more following interrupt caus- tor of a receive frame has been ing conditions has occurred: updated by writing a 0 to the EXDINT, IDON, MERR, MISS, OWNership bit if the LAPPEN bit MFCO, RCVCCO, RINT, SINT, of CSR3 has been set to a 1. TINT, TXSTRT, UINT, STINT, When RINT is set, INTA is assert- MREINT, MCCINT, MIIPDTINT, ed if IENA is 1 and the mask bit MAPINT and the associated RINTM (CSR3, bit 10) is 0. mask or enable bit is pro- grammed to allow the event to Read/Write accessible always. cause an interrupt. If IENA is set RINT is cleared by the host by to 1 and INTR is set, INTA will be writing a 1. Writing a 0 has no ef- active. When INTR is set by SINT fect. RINT is cleared by or SLPINT, INTA will be active in- H_RESET, S_RESET, or by set- dependent of the state of IENA. ting the STOP bit. Read accessible always. INTR is 9 TINT Transmit Interrupt is set by the read only. INTR is cleared by Am79C972 controller after the clearing all of the active individual OWN bit in the last descriptor of a interrupt bits that have not been transmit frame has been cleared masked out. to indicate the frame has been sent or an error occurred in the 6 IENA Interrupt Enable allows INTA to transmission. be active if the Interrupt Flag is set. If IENA = 0, then INTA will be When TINT is set, INTA is assert- disabled regardless of the state ed if IENA is 1 and the mask bit of INTR. TINTM (CSR3, bit 9) is 0. Read/Write accessible always. TINT will not be set if TINTOKD IENA is set by writing a 1 and (CSR5, bit 15) is set to 1 and the cleared by writing a 0. IENA is transmission was successful. cleared by H_RESET or S_RESET and setting the STOP Read/Write accessible always. bit. TINT is cleared by the host by writing a 1. Writing a 0 has no ef- 5 RXON Receive On indicates that the re- fect. TINT is cleared by ceive function is enabled. RXON H_RESET, S_RESET, or by set- is set if DRX (CSR15, bit 0) is set ting the STOP bit. to 0 after the START bit is set. If INIT and START are set together, Am79C972 107 RXON will not be set until after STOP will override STRT and the initialization block has been INIT. read in. Read/Write accessible always. Read accessible always. RXON STOP is set by writing a 1, by is read only. RXON is cleared by H_RESET or S_RESET. Writing H_RESET or S_RESET and set- a 0 has no effect. STOP is ting the STOP bit. cleared by setting either STRT or INIT. 4 TXON Transmit On indicates that the transmit function is enabled. 1 STRT STRT assertion enables TXON is set if DTX (CSR15, bit 1) Am79C972 controller to send and is set to 0 after the START bit is receive frames, and perform buff- set. If INIT and START are set to- er management operations. Set- gether, TXON will not be set until ting STRT clears the STOP bit. If after the initialization block has STRT and INIT are set together, been read in. the Am79C972 controller initial- ization will be performed first. This bit will reset if the DXSUFLO bit (CSR3, bit 6) is reset and there Read/Write accessible always. is an underflow condition encoun- STRT is set by writing a 1. Writing tered. a 0 has no effect. STRT is cleared by H_RESET, S_RESET, or by Read accessible always. TXON setting the STOP bit. is read only. TXON is cleared by H_RESET or S_RESET and set- 0 INIT INIT assertion enables the ting the STOP bit. Am79C972 controller to begin the initialization procedure which 3 TDMD Transmit Demand, when set, reads in the initialization block causes the Buffer Management from memory. Setting INIT clears Unit to access the Transmit De- the STOP bit. If STRT and INIT scriptor Ring without waiting for are set together, the Am79C972 the poll-time counter to elapse. If controller initialization will be per- TXON is not enabled, TDMD bit formed first. INIT is not cleared will be reset and no Transmit De- when the initialization sequence scriptor Ring access will occur. has completed. TDMD is required to be set if the Read/Write accessible always. TXDPOLL bit in CSR4 is set. Set- INIT is set by writing a 1. Writing ting TDMD while TXDPOLL = 0 a 0 has no effect. INIT is cleared merely hastens the Am79C972 by H_RESET, S_RESET, or by controller’s response to a Trans- setting the STOP bit. mit Descriptor Ring Entry. CSR1: Initialization Block Address 0 Read/Write accessible always. Bit Name Description TDMD is set by writing a 1. Writ- ing a 0 has no effect. TDMD will 31-16 RES Reserved locations. Written as be cleared by the Buffer Manage- zeros and read as undefined. ment Unit when it fetches a Transmit Descriptor. TDMD is 15-0 IADR[15:0] Lower 16 bits of the address of cleared by H_RESET or the Initialization Block. Bit loca- S_RESET and setting the STOP tions 1 and 0 must both be 0 to bit. align the initialization block to a DWord boundary. 2 STOP STOP assertion disables the chip from all DMA activity. The chip re- This register is aliased with mains inactive until either STRT CSR16. or INIT are set. If STOP, STRT and INIT are all set together, 108 Am79C972 Read/Write accessible only when the upper 8 bits of the initializa- either the STOP or the SPND bit tion address. is set. Unaffected by H_RESET This register is aliased with or S_RESET, or by setting the CSR17. STOP bit. Read/Write accessible only when CSR2: Initialization Block Address 1 either the STOP or the SPND bit Bit Name Description is set. Unaffected by H_RESET, S_RESET, or by setting the 31-16 RES Reserved locations. Written as STOP bit. zeros and read as undefined. 7-0 IADR[23:16] Bits 23 through 16 of the address 15-8 IADR[31:24] If SSIZE32 is set (BCR20, bit 8), of the Initialization Block. When- then the IADR[31:24] bits will be ever this register is written, used strictly as the upper 8 bits of CSR17 is updated with CSR2’s the initialization block address. contents. However, if SSIZE32 is reset Read/Write accessible only when (BCR20, bit 8), then the either the STOP or the SPND bit IADR[31:24] bits will be used to is set. Unaffected by H_RESET, generate the upper 8 bits of all S_RESET, or by setting the bus mastering addresses, as re- STOP bit. quired for a 32-bit address bus. Note that the 16-bit software CSR3: Interrupt Masks and Deferral Control structures specified by the SSIZE32=0 setting will yield Bit Name Description only 24 bits of address for the 31-16 RES Reserved locations. Written as Am79C972 bus master access- zeros and read as undefined. es, while the 32-bit hardware for which the Am79C972 controller is 15-13 RES Reserved locations. Read and intended will require 32 bits of ad- written as zero. dress. Therefore, whenever SSIZE32=0, the IADR[31:24] 12 MISSM Missed Frame Mask. If MISSM is bits will be appended to the 24-bit set, the MISS bit will be masked initialization address, to each 24- and unable to set the INTR bit. bit descriptor base address and to each beginning 24-bit buffer Read/Write accessible always. address in order to form complete MISSM is cleared by H_RESET 32-bit addresses. The upper 8 or S_RESET and is not affected bits that exist in the descriptor ad- by STOP. dress registers and the buffer ad- dress registers which are stored 11 MERRM Memory Error Mask. If MERRM on board the Am79C972 control- is set, the MERR bit will be ler will be overwritten with the masked and unable to set the IADR[31:24] value, so that CSR INTR bit. accesses to these registers will Read/Write accessible always. show the 32-bit address that in- MERRM is cleared by H_RESET cludes the appended field. or S_RESET and is not affected If SSIZE32 = 1, then software will by STOP. provide 32-bit pointer values for 10 RINTM Receive Interrupt Mask. If RINTM all of the shared software struc- is set, the RINT bit will be masked tures - i.e., descriptor bases and and unable to set the INTR bit. buffer addresses, and therefore, IADR[31:24] will not be written to Read/Write accessible always. the upper 8 bits of any of these RINTM is cleared by H_RESET resources, but it will be used as Am79C972 109 or S_RESET and is not affected will be signaled through the RINT by STOP. bit of CSR0. 9 TINTM Transmit Interrupt Mask. If Setting LAPPEN to a 1 also en- TINTM is set, the TINT bit will be ables the Am79C972 controller to masked and unable to set the read the STP bit of receive de- INTR bit. scriptors. The Am79C972 con- troller will use the STP Read/Write accessible always. information to determine where it TINTM is cleared by H_RESET should begin writing a receive or S_RESET and is not affected packet’s data. Note that while in by STOP. this mode, the Am79C972 con- troller can write intermediate 8 IDONM Initialization Done Mask. If packet data to buffers whose de- IDONM is set, the IDON bit will be scriptors do not contain STP bits masked and unable to set the set to 1. Following the write to the INTR bit. last descriptor used by a packet, the Am79C972 controller will Read/Write accessible always. scan through the next descriptor IDONM is cleared by H_RESET entries to locate the next STP bit or S_RESET and is not affected that is set to a 1. The Am79C972 by STOP. controller will begin writing the next packets data to the buffer 7 RES Reserved location. Read and pointed to by that descriptor. written as zeros. Note that because several de- 6 DXSUFLO Disable Transmit Stop on Under- scriptors may be allocated by the flow error. host for each packet, and not all messages may need all of the de- When DXSUFLO (CSR3, bit 6) is scriptors that are allocated be- set to 0, the transmitter is turned tween descriptors that contain off when an UFLO error occurs STP = 1, then some descriptors/ (CSR0, TXON = 0). buffers may be skipped in the When DXSUFLO is set to 1, the ring. While performing the search Am79C972 controller gracefully for the next STP bit that is set to recovers from an UFLO error. It 1, the Am79C972 controller will scans the transmit descriptor ring advance through the receive de- until it finds the start of a new scriptor ring regardless of the frame and starts a new transmis- state of ownership bits. If any of sion. the entries that are examined during this search indicate Read/Write accessible always. Am79C972 controller ownership DXSUFLO is cleared by of the descriptor but also indicate H_RESET or S_RESET and is STP=0, then the Am79C972 not affected by STOP. controller will reset the OWN bit to 0 in these entries. If a scanned 5 LAPPEN Look Ahead Packet Processing entry indicates host ownership Enable. When set to a 1, the with STP=0, then the LAPPEN bit will cause the Am79C972 controller will not al- Am79C972 controller to generate ter the entry, but will advance to an interrupt following the descrip- the next entry. tor write operation to the first buff- er of a receive frame. This When the STP bit is found to be interrupt will be generated in ad- true, but the descriptor that con- dition to the interrupt that is gen- tains this setting is not owned by erated following the descriptor the Am79C972 controller, then write operation to the last buffer the Am79C972 controller will stop of a receive packet. The interrupt advancing through the ring en- 110 Am79C972 tries and begin periodic polling of 2 BSWP Byte Swap. This bit is used to this entry. When the STP bit is choose between big and little En- found to be true, and the descrip- dian modes of operation. When tor that contains this setting is BSWP is set to a 1, big Endian owned by the Am79C972 control- mode is selected. When BSWP is ler, then the Am79C972 control- set to 0, little Endian mode is se- ler will stop advancing through lected. the ring entries, store the descrip- When big Endian mode is select- tor information that it has just ed, the Am79C972 controller will read, and wait for the next re- swap the order of bytes on the AD ceive to arrive. bus during a data phase on ac- This behavior allows the host cesses to the FIFOs only. Specif- software to pre-assign buffer ically, AD[31:24] becomes Byte space in such a manner that the 0, AD[23:16] becomes Byte 1, header portion of a receive pack- AD[15:8] becomes Byte 2, and et will always be written to a par- AD[7:0] becomes Byte 3 when ticular memory area, and the data big Endian mode is selected. portion of a receive packet will al- When little Endian mode is se- ways be written to a separate lected, the order of bytes on the memory area. The interrupt is AD bus during a data phase is: generated when the header bytes AD[31:24] is Byte 3, AD[23:16] is have been written to the header Byte 2, AD[15:8] is Byte 1, and memory area. AD[7:0] is Byte 0. Read/Write accessible always. Byte swap only affects data The LAPPEN bit will be reset to 0 transfers that involve the FIFOs. by H_RESET or S_RESET and Initialization block transfers are will be unaffected by STOP. not affected by the setting of the BSWP bit. Descriptor transfers See Appendix B for more infor- are not affected by the setting of mation on the Look Ahead Pack- the BSWP bit. RDP, RAP, BDP et Processing concept. and PCI configuration space ac- cesses are not affected by the 4 DXMT2PD Disable Transmit Two Part Defer- setting of the BSWP bit. Address ral (see Medium Allocation sec- PROM transfers are not affected tion in the Media Access by the setting of the BSWP bit. Management section for more Expansion ROM accesses are details). If DXMT2PD is set, not affected by the setting of the Transmit Two Part Deferral will BSWP bit. be disabled. Note that the byte ordering of the Read/Write accessible always. PCI bus is defined to be little En- DXMT2PD is cleared by dian. BSWP should not be set to H_RESET or S_RESET and is 1 when the Am79C972 controller not affected by STOP. is used in a PCI bus application. 3 EMBA Enable Modified Back-off Algo- Read/Write accessible always. rithm (see Contention Resolution BSWP is cleared by H_RESET or section in Media Access Man- S_RESET and is not affected by agement section for more de- STOP. tails). If EMBA is set, a modified back-off algorithm is implement- 1-0 RES Reserved location. The default ed. value of this bit is a 0. Writing a 1 to this bit has no effect on device Read/Write accessible always. function. If a 1 is written to this bit, EMBA is cleared by H_RESET or then a 1 will be read back. Exist- S_RESET and is not affected by ing drivers may write a 1 to this bit STOP. for compatibility, but new drivers Am79C972 111 should write a 0 to this bit and tire frame, including pad, and ap- should treat the read value as un- pended after the pad field. defined. APAD_XMT will override the pro- gramming of the DXMTFCS bit CSR4: Test and Features Control (CSR15, bit 3) and of the ADD_FCS bit (TMD1, bit 29) for Certain bits in CSR4 indicate the cause of an interrupt. frames shorter than 64 bytes. The register is designed so that these indicator bits are cleared by writing ones to those bit locations. This Read/Write accessible always. means that the software can read CSR4 and write back APAD_XMT is cleared by the value just read to clear the interrupt condition. H_RESET or S_RESET and is Bit Name Description unaffected by the STOP bit. 10 ASTRP_RCV Auto Strip Receive. When set, 31-16 RES Reserved locations. Written as ASTRP_RCV enables the auto- zeros and read as undefined. matic pad stripping feature. The 15 RES Reserved location. It is OK for pad and FCS fields will be legacy software to write a 1 to this stripped from receive frames and location. This bit must be set not placed in the FIFO. back to 0 before setting INIT or Read/Write accessible always. STRT bits. ASTRP_RCV is cleared by Read/Write accessible always. H_RESET or S_RESET and is This bit is cleared by H_RESET unaffected by the STOP bit. or S_RESET and is unaffected by 9 MFCO Missed Frame Counter Overflow the STOP bit. is set by the Am79C972 control- 14 DMAPLUS Writing and reading from this bit ler when the Missed Frame has no effect. DMAPLUS is al- Counter (CSR112 and CSR114) ways set to 1. has wrapped around. 13 RES Reserved Location. Written as When MFCO is set, INTA is as- zero and read as undefined. serted if IENA is 1 and the mask bit MFCOM is 0. 12 TXDPOLL Disable Transmit Polling. If TXD- POLL is set, the Buffer Manage- Read/Write accessible always. ment Unit will disable transmit MFCO is cleared by the host by polling. Likewise, if TXDPOLL is writing a 1. Writing a 0 has no ef- cleared, automatic transmit poll- fect. MFCO is cleared by ing is enabled. If TXDPOLL is set, H_RESET, S_RESET, or by set- TDMD bit in CSR0 must be set in ting the STOP bit. order to initiate a manual poll of a 8 MFCOM Missed Frame Counter Overflow transmit descriptor. Transmit de- Mask. If MFCOM is set, the scriptor polling will not take place MFCO bit will be masked and un- if TXON is reset. Transmit polling able to set the INTR bit. will take place following Receive activities. Read/Write accessible always. MFCOM is set to 1 by H_RESET Read/Write accessible always. or S_RESET and is not affected TXDPOLL is cleared by by the STOP bit. H_RESET or S_RESET and is unaffected by the STOP bit. 7 UINTCMD User Interrupt Command. UINTCMD can be used by the 11 APAD_XMT Auto Pad Transmit. When set, host to generate an interrupt un- APAD_XMT enables the auto- related to any network activity. matic padding feature. Transmit When UINTCMD is set, INTA is frames will be padded to extend asserted if IENA is set to 1. them to 64 bytes including FCS. The FCS is calculated for the en- 112 Am79C972 Writing a 1 to UNIT will clear fect. TXSTRT is cleared by UNITCMD and stop interrupts. H_RESET, S_RESET, or by set- ting the STOP bit. Read/Write accessible always. UINTCMD is cleared by 2 TXSTRTM Transmit Start Mask. If TX- H_RESET or S_RESET or by STRTM is set, the TXSTRT bit setting the STOP bit. will be masked and unable to set the INTR bit. 6 UINT User Interrupt. UINT is set by the Am79C972 controller after the Read/Write accessible always. host has issued a user interrupt TXSTRTM is set to 1 by command by setting UINTCMD H_RESET or S_RESET and is (CSR4, bit 7) to 1. not affected by the STOP bit. Read/Write accessible always. 1-0 RES Reserved locations. Written as UINT is cleared by the host by zeros and read as undefined. writing a 1. Writing a 0 has no ef- CSR5: Extended Control and Interrupt 1 fect. UINT is cleared by H_RESET or S_RESET or by Certain bits in CSR5 indicate the cause of an interrupt. setting the STOP bit. The register is designed so that these indicator bits are cleared by writing ones to those bit locations. This 5 RCVCCO Receive Collision Counter Over- means that the software can read CSR5 and write back flow is set by the Am79C972 con- the value just read to clear the interrupt condition. troller when the Receive Collision Bit Name Description Counter (CSR114 and CSR115) has wrapped around. 31-16 RES Reserved locations. Written as When RCVCCO is set, INTA is zeros and read as undefined. asserted if IENA is 1 and the 15 TOKINTD Transmit OK Interrupt Disable. If mask bit RCVCCOM is 0. TOKINTD is set to 1, the TINT bit Read/Write accessible always. in CSR0 will not be set when a RCVCCO is cleared by the host transmission was successful. by writing a 1. Writing a 0 has no Only a transmit error will set the effect. RCVCCO is cleared by TINT bit. H_RESET, S_RESET, or by set- TOKINTD has no effect when ting the STOP bit. LTINTEN (CSR5, bit 14) is set to 4 RCVCCOM Receive Collision Counter Over- 1. A transmit descriptor with flow Mask. If RCVCCOM is set, LTINT set to 1 will always cause the RCVCCO bit will be masked TINT to be set to 1, independent and unable to set the INTR bit. of the success of the transmis- sion. Read/Write accessible always. RCVCCOM is set to 1 by Read/Write accessible always. H_RESET or S_RESET and is TOKINTD is cleared by not affected by the STOP bit. H_RESET or S_RESET and is unaffected by STOP. 3 TXSTRT Transmit Start status is set by the Am79C972 controller whenever it 14 LTINTEN Last Transmit Interrupt Enable. begins transmission of a frame. When set to 1, the LTINTEN bit will cause the Am79C972 control- When TXSTRT is set, INTA is as- ler to read bit 28 of TMD1 as serted if IENA is 1 and the mask LTINT. The setting LTINT will de- bit TXSTRTM is 0. termine if TINT will be set at the end of the transmission. Read/Write accessible always. TXSTRT is cleared by the host by writing a 1. Writing a 0 has no ef- Am79C972 113 Read/Write accessible always. Deferral is defined in the ISO LTINTEN is cleared by 8802-3 (IEEE/ANSI 802.3) stan- H_RESET or S_RESET and is dard. unaffected by STOP. When EXDINT is set, INTA is as- 13-12 RES Reserved locations. Written as serted if the enable bit EXDINTE zeros and read as undefined. is 1. 11 SINT System Interrupt is set by the Read/Write accessible always. Am79C972 controller when it de- EXDINT is cleared by the host by tects a system error during a bus writing a 1. Writing a 0 has no ef- master transfer on the PCI bus. fect. EXDINT is cleared by System errors are data parity er- H_RESET and is not affected by ror, master abort, or a target S_RESET or setting the STOP abort. The setting of SINT due to bit. data parity error is not dependent 6 EXDINTE Excessive Deferral Interrupt En- on the setting of PERREN (PCI able. If EXDINTE is set, the Command register, bit 6). EXDINT bit will be able to set the When SINT is set, INTA is assert- INTR bit. ed if the enable bit SINTE is 1. Read/Write accessible always. Note that the assertion of an in- EXDINTE is set to 0 by terrupt due to SINT is not depen- H_RESET and is not affected by dent on the state of the INEA bit, S_RESET or setting the STOP since INEA is cleared by the bit. STOP reset generated by the system error. 5 MPPLBA Magic Packet Physical Logical Broadcast Accept. If MPPLBA is Read/Write accessible always. at its default value of 0, the SINT is cleared by the host by Am79C972 controller will only de- writing a 1. Writing a 0 has no ef- tect a Magic Packet frame if the fect. The state of SINT is not af- destination address of the packet fected by clearing any of the PCI matches the content of the physi- Status register bits that get set cal address register (PADR). If when a data parity error MPPLBA is set to 1, the destina- (DATAPERR, bit 8), master abort tion address of the Magic Packet (RMABORT, bit 13), or target frame can be unicast, multicast, abort (RTABORT, bit 12) occurs. or broadcast. Note that the set- SINT is cleared by H_RESET or ting of MPPLBA only affects the S_RESET and is not affected by address detection of the Magic setting the STOP bit. Packet frame. The Magic Packet 10 SINTE System Interrupt Enable. If SIN- frame’s data sequence must be TE is set, the SINT bit will be able made up of 16 consecutive phys- to set the INTR bit. ical addresses (PADR[47:0]) re- gardless of what kind of Read/Write accessible always. destination address it has. This SINTE is set to 0 by H_RESET or bit is OR’ed with EMPPLBA bit S_RESET and is not affected by (CSR116, bit 6). setting the STOP bit. Read/Write accessible always. 9-8 RES Reserved locations. Written as MPPLBA is set to 0 by H_RESET zeros and read as undefined. or S_RESET and is not affected by setting the STOP bit. 7 EXDINT Excessive Deferral Interrupt is set by the Am79C972 controller 4 MPINT Magic Packet Interrupt. Magic when the transmitter has experi- Packet Interrupt is set by the enced Excessive Deferral on a Am79C972 controller when the transmit frame, where Excessive device is in the Magic Packet 114 Am79C972 mode and the Am79C972 con- out of suspend mode. SPND can troller receives a Magic Packet only be set to 1 if STOP (CSR0, frame. When MPINT is set to 1, bit 2) is set to 0. H_RESET, INTA is asserted if IENA (CSR0, S_RESET or setting the STOP bit bit 6) and the enable bit MPINTE will get the Am79C972 controller are set to 1. out of suspend mode. Read/Write accessible always. Requesting entrance into the MPINT is cleared by the host by suspend mode by the host de- writing a 1. Writing a 0 has no af- pends on the setting of the fect. MPINT is cleared by FASTSPNDE bit (CSR7, bit 15). H_RESET, S_RESET, or by set- Refer to the bit description of the ting the STOP bit. FASTSPNDE bit and the Sus- pend section in Detailed Func- 3 MPINTE Magic Packet Interrupt Enable. If tions, Buffer Management Unit MPINTE is set to 1, the MPINT bit for details. will be able to set the INTR bit. In suspend mode, all of the CSR Read/Write accessible always. and BCR registers are accessi- MPINT is cleared to 0 by ble. As long as the Am79C972 H_RESET or S_RESET and is controller is not reset while in not affected by setting the STOP suspend mode (by H_RESET, bit. S_RESET or by setting the STOP bit), no re-initialization of the de- 2 MPEN Magic Packet Enable. MPEN al- vice is required after the device lows activation of the Magic comes out of suspend mode. The Packet mode by the host. The Am79C972 controller will contin- Am79C972 controller will enter ue at the transmit and receive de- the Magic Packet mode when scriptor ring locations, from both MPEN and MPMODE are where it had left, when it entered set to 1. the suspend mode. Read/Write accessible always. Read/Write accessible always. MPEN is cleared to 0 by SPND is cleared by H_RESET, H_RESET or S_RESET and is S_RESET, or by setting the not affected by setting the STOP STOP bit. bit. CSR6: RX/TX Descriptor Table Length 1 MPMODE The Am79C972 controller will en- Bit Name Description ter the Magic Packet mode when MPMODE is set to 1 and either 31-16 RES Reserved locations. Written as PG is asserted or MPEN is set to zeros and read as undefined. 1. 15-12 TLEN Contains a copy of the transmit Read/Write accessible always. encoded ring length (TLEN) field MPMODE is cleared to 0 by read from the initialization block H_RESET or S_RESET and is during the Am79C972 controller not affected by setting the STOP initialization. This field is written bit during the Am79C972 controller 0 SPND Suspend. Setting SPND to 1 will initialization routine. cause the Am79C972 controller Read accessible only when either to start requesting entrance into the STOP or the SPND bit is set. suspend mode. The host must Write operations have no effect poll SPND until it reads back 1 to and should not be performed. determine that the Am79C972 TLEN is only defined after initial- controller has entered the sus- ization. These bits are unaffected pend mode. Setting SPND to 0 will get the Am79C972 controller Am79C972 115 by H_RESET, S_RESET, or may enter the suspend mode STOP. with transmit and/or receive packets still in the FIFOs or the 11-8 RLEN Contains a copy of the receive SRAM. encoded ring length (RLEN) read from the initialization block during When FASTSPNDE is 0 and the Am79C972 controller initializa- SPND bit is set, the Am79C972 tion. This field is written during controller may take longer before the Am79C972 controller initial- entering the suspend mode. At ization routine. the time the SPND bit is set, the Am79C972 controller will com- Read accessible only when either plete the DMA process of a trans- the STOP or the SPND bit is set. mit packet if it had already begun Write operations have no effect and the Am79C972 controller will and should not be performed. completely receive a receive RLEN is only defined after initial- packet if it had already begun. ization. These bits are unaffected Additionally, all transmit packets by H_RESET, S_RESET, or stored in the transmit FIFOs and STOP. the transmit buffer area in the SRAM (if one is enabled) will be 7-0 RES Reserved locations. Read as 0s. transmitted and all receive pack- Write operations are ignored. ets stored in the receive FIFOs, and the receive buffer area in the CSR7: Extended Control and Interrupt 2 SRAM (if one is enabled) will be Certain bits in CSR7 indicate the cause of an interrupt. transferred into system memory. The register is designed so that these indicator bits are Since the FIFO and SRAM con- cleared by writing ones to those bit locations. This tents are flushed, it may take means that the software can read CSR7 and write back much longer before the the value just read to clear the interrupt condition. Am79C972 controller enters the suspend mode. The amount of Bit Name Description time that it takes depends on many factors including the size of 31-16 RES Reserved locations. Written as the SRAM, bus latency, and net- zeros and read as undefined. work traffic level. 15 FASTSPNDE Fast Suspend Enable. When When a write to CSR5 is per- FASTSPNDE is set to 1, the formed with bit 0 (SPND) set to 1, Am79C972 controller performs a the value that is simultaneously fast suspend whenever the written to FASTSPNDE is used to SPND bit is set. determine which approach is used to enter suspend mode. When a fast suspend is request- ed, the Am79C972 controller per- Read/Write accessible always. forms a quick entry into the FASTSPNDE is cleared by suspend mode. At the time the H_RESET, S_RESET or by set- SPND bit is set, the Am79C972 ting the STOP bit. controller will complete the DMA process of any transmit and/or re- 14 RXFRTG Receive Frame Tag. When Re- ceive packet that had already be- ceive Frame Tag is set to 1, a tag gun DMA activity. In addition, any word is put into the receive de- transmit packet that had started scriptor supplied by the EADI. transmission will be fully transmit- See the section Receive Frame ted and any receive packet that Tagging for details. This bit is had begun reception will be fully valid only when the EADISEL received. However, no additional (BCR2, bit 3) is set to 1. packets will be transmitted or re- ceived and no additional transmit Read/Write accessible always. or receive DMA activity will begin. RXFRTG is cleared by Hence, the Am79C972 controller H_RESET. RXFRTG is unaffect- 116 Am79C972 ed by S_RESET or by setting the When STINT is set to 1, INTA is STOP bit. asserted if the enable bit STINTE is set to 1. 13 RDMD Receive Demand, when set, causes the Buffer Management Read/Write accessible always. Unit to access the Receive De- STINT is cleared by the host by scriptor Ring without waiting for writing a 1. Writing a 0 has no ef- the receive poll-time counter to fect. STINT is cleared by elapse. If RXON is not enabled, H_RESET and is not affected by RDMD has no meaning and no S_RESET or setting the STOP receive Descriptor Ring access bit. will occur. 10 STINTE Software Timer Interrupt Enable. RDMD is required to be set if the If STINTE is set, the STINT bit RXDPOLL bit in CSR7 is set. Set- will be able to set the INTR bit. ting RDMD while RXDPOLL = 0 Read/Write accessible always. merely hastens the Am79C972 STINTE is set to 0 by H_RESET controller’s response to a receive and is not affected by S_RESET Descriptor Ring Entry. or setting the STOP bit Read/Write accessible always. 9 MREINT MII Management Read Error In- RDMD is set by writing a 1. Writ- terrupt. The MII Read Error inter- ing a 0 has no effect. RDMD will rupt is set by the Am79C972 be cleared by the Buffer Manage- controller to indicate that the cur- ment Unit when it fetches a re- rently read register from the ex- ceive Descriptor. RDMD is ternal PHY is invalid. The cleared by H_RESET. RDMD is contents of BCR34 are incorrect unaffected by S_RESET or by and that the operation should be setting the STOP bit. performed again. The indication 12 RXDPOLL Receive Disable Polling. If RXD- of an incorrect read comes from POLL is set, the Buffer Manage- the PHY. During the read turn- ment Unit will disable receive around time of the MII manage- polling. Likewise, if RXDPOLL is ment frame the external PHY cleared, automatic receive poll- should drive the MDIO pin to a ing is enabled. If RXDPOLL is LOW state. If this does not hap- set, RDMD bit in CSR7 must be pen, it indicates that the PHY and set in order to initiate a manual the Am79C972 controller have poll of a receive descriptor. Re- lost synchronization. ceive Descriptor Polling will not When MREINT is set to 1, INTA is take place if RXON is reset. asserted if the enable bit MREIN- Read/Write accessible always. TE is set to 1. RXDPOLL is cleared by Read/Write accessible always. H_RESET. RXDPOLL is unaf- MREINT is cleared by the host by fected by S_RESET or by setting writing a 1. Writing a 0 has no ef- the STOP bit. fect. MREINT is cleared by 11 STINT Software Timer Interrupt. The H_RESET and is not affected by Software Timer interrupt is set by S_RESET or setting the STOP the Am79C972 controller when bit. the Software Timer counts down 8 MREINTE MII Management Read Error In- to 0. The Software Timer will im- terrupt Enable. If MREINTE is mediately load the STVAL (BCR set, the MREINT bit will be able to 31, bits 5-0) into the Software set the INTR bit. Timer and begin counting down. Read/Write accessible always. MREINTE is set to 0 by Am79C972 117 H_RESET and is not affected by S_RESET or setting the STOP S_RESET or setting the STOP bit bit. 7 MAPINT MII Management Auto-Poll Inter- 4 MCCINTE MII Management Command rupt. The MII Auto-Poll interrupt is Complete Interrupt Enable. If set by the Am79C972 controller MCCINTE is set to 1, the MC- to indicate that the currently read CINT bit will be able to set the status does not match the stored INTR bit when the host reads or previous status indicating a writes to the MII Data Port change in state for the external (BCR34) only. Internal MII Man- PHY. A change in the Auto-Poll agement Commands will not gen- Access Method (BCR32, Bit 11) erate an interrupt. For instance will reset the shadow register and Auto-Poll state machine generat- will not cause an interrupt on the ed MII management frames will first access from the Auto-Poll not generate an interrupt upon section. Subsequent accesses completion unless there is a com- will generate an interrupt if the pare error which get reported shadow register and the read through the MAPINT (CSR7, bit register produce differences. 6) interrupt or the MCCIINTE is set to 1. When MAPINT is set to 1, INTA is asserted if the enable bit MAP- Read/Write accessible always. INTE is set to 1. MCCINTE is set to 0 by H_RESET and is not affected by Read/Write accessible always. S_RESET or setting the STOP MAPINT is cleared by the host by bit. writing a 1. Writing a 0 has no ef- fect. MAPINT is cleared by 3 MCCIINT MII Management Command H_RESET and is not affected by Complete Internal Interrupt. The S_RESET or setting the STOP MII Management Command bit. Complete Interrupt is set by the Am79C972 controller when a 6 MAPINTE MII Auto-Poll Interrupt Enable. If read or write operation on the MII MAPINTE is set, the MAPINT bit management port is complete will be able to set the INTR bit. from an internal operation. Exam- ples of internal operations are Read/Write accessible always. Auto-Poll or MII Management MAPINTE is set to 0 by Port generated MII management H_RESET and is not affected by frames. These are normally hid- S_RESET or setting the STOP bit den to the host. 5 MCCINT MII Management Command When MCCIINT is set to 1, INTA Complete Interrupt. The MII Man- is asserted if the enable bit MC- agement Command Complete In- CINTE is set to 1. terrupt is set by the Am79C972 controller when a read or write Read/Write accessible always. operation to the MII Data Port MCCIINT is cleared by the host (BCR34) is complete. by writing a 1. Writing a 0 has no effect. MCCIINT is cleared by When MCCINT is set to 1, INTA H_RESET and is not affected by is asserted if the enable bit MC- S_RESET or setting the STOP CINTE is set to 1. bit. Read/Write accessible always. 2 MCCIINTE MII Management Command MCCINT is cleared by the host by Complete Internal Interrupt En- writing a 1. Writing a 0 has no ef- able. If MCCIINTE is set to 1, the fect. MCCINT is cleared by MCCIINT bit will be able to set H_RESET and is not affected by the INTR bit when the internal state machines generate MII 118 Am79C972 management frames. For in- is set. These bits are unaffected stance, when MCCIINTE is set to by H_RESET, S_RESET, or 1 and the Auto-Poll state ma- STOP. chine generates a MII manage- CSR9: Logical Address Filter 1 ment frame, the MCCIINT will set the INTR bit upon completion of Bit Name Description the MII management frame re- gardless of the comparison out- 31-16 RES Reserved locations. Written as come. zeros and read as undefined. Read/Write accessible always. 15-0 LADRF[31:16] Logical Address Filter, LADRF- MCCIINTE is set to 0 by [31:16]. The content of this regis- H_RESET and is not affected by ter is undefined until loaded from S_RESET or setting the STOP the initialization block after the bit. INIT bit in CSR0 has been set or a direct register write has been 1 MIIPDTINT MII PHY Detect Transition Inter- performed on this register. rupt. The MII PHY Detect Transi- tion Interrupt is set by the Read/Write accessible only when Am79C972 controller whenever either the STOP or the SPND bit the MIIPD bit (BCR32, bit 14) is set. These bits are unaffected transitions from 0 to 1 or vice ver- by H_RESET, S_RESET, or sa. STOP. Read/Write accessible always. CSR10: Logical Address Filter 2 MIIPDTINT is cleared by the host Bit Name Description by writing a 1. Writing a 0 has no effect. MIIPDTINT is cleared by 31-16 RES Reserved locations. Written as H_RESET and is not affected by zeros and read as undefined. S_RESET or setting the STOP bit. 15-0LADRF[47:32]Logical Address Filter, LADRF[47:32]. The content of 0 MIIPDTINTE MII PHY Detect Transition Inter- this register is undefined until rupt Enable. If MIIPDTINTE is set loaded from the initialization to 1, the MIIPDTINT bit will be block after the INIT bit in CSR0 able to set the INTR bit. has been set or a direct register write has been performed on this Read/Write accessible always. register. MIIPDTINTE is set to 0 by H_RESET and is not affected by Read/Write accessible only when S_RESET or setting the STOP either the STOP or the SPND bit bit. is set. These bits are unaffected by H_RESET, S_RESET, or CSR8: Logical Address Filter 0 STOP. Bit Name Description CSR11: Logical Address Filter 3 31-16 RES Reserved locations. Written as Bit Name Description zeros and read as undefined. 31-16 RES Reserved locations. Written as 15-0 LADRF[15:0] Logical Address Filter, LADRF- zeros and read as undefined. [15:0]. The content of this register is undefined until loaded from the 15-0LADRF[63:48]Logical Address Filter, initialization block after the INIT LADRF[63:48]. The content of bit in CSR0 has been set or a di- this register is undefined until rect register write has been per- loaded from the initialization formed on this register. block after the INIT bit in CSR0 has been set or a direct register Read/Write accessible only when either the STOP or the SPND bit Am79C972 119 write has been performed on this This register can also be loaded register. from the initialization block after the INIT bit in CSR0 has been set Read/Write accessible only when or a direct register write has been either the STOP or the SPND bit performed on this register. is set. These bits are unaffected by H_RESET, S_RESET, or Read/Write accessible only when STOP. either the STOP or the SPND bit is set. These bits are unaffected CSR12: Physical Address Register 0 by H_RESET, S_RESET, or STOP. Note: Bits 15-0 in this register are programmable CSR14: Physical Address Register 2 through the EEPROM. Note: Bits 15-0 in this register are programmable Bit Name Description through the EEPROM. 31-16 RES Reserved locations. Written as Bit Name Description zeros and read as undefined. 15-0 PADR[15:0]Physical Address Register, 31-16 RES Reserved locations. Written as PADR[15:0]. The contents of this zeros and read as undefined. register are loaded from EE- PROM after H_RESET or by an 15-0 PADR[47:32]Physical Address Register, EEPROM read command PADR[47:32].The contents of (PRGAD, BCR19, bit 14). If the this register are loaded from EE- EEPROM is not present, the con- PROM after H_RESET or by an tents of this register are unde- EEPROM read command fined. (PRGAD, BCR19, bit 14). If the EEPROM is not present, the con- This register can also be loaded tents of this register are unde- from the initialization block after fined. the INIT bit in CSR0 has been set or a direct register write has been This register can also be loaded performed on this register. from the initialization block after the INIT bit in CSR0 has been set Read/Write accessible only when or a direct register write has been either the STOP or the SPND bit performed on this register. is set. These bits are unaffected by H_RESET, S_RESET, or Read/Write accessible only when STOP. either the STOP or the SPND bit is set. These bits are unaffected CSR13: Physical Address Register 1 by H_RESET, S_RESET, or STOP. Note: Bits 15-0 in this register are programmable through the EEPROM. CSR15: Mode Bit Name Description This register’s fields are loaded during the Am79C972 controller initialization routine with the corresponding 31-16 RES Reserved locations. Written as Initialization Block values, or when a direct register write zeros and read as undefined. has been performed on this register. 15-0 PADR[31:16]Physical Address Register, Bit Name Description PADR[31:16]. The contents of this register are loaded from EE- 31-16 RES Reserved locations. Written as PROM after H_RESET or by an zeros and read as undefined. EEPROM read command (PRGAD, BCR19, bit 14). If the 15 PROM Promiscuous Mode. When EEPROM is not present, the con- PROM = 1, all incoming receive tents of this register are unde- frames are accepted. fined. 120 Am79C972 Read/Write accessible only when 5 DRTY Disable Retry. When DRTY is set either the STOP or the SPND bit to 1, the Am79C972 controller will is set. attempt only one transmission. In this mode, the device will not pro- 14 DRCVBC Disable Receive Broadcast. tect the first 64 bytes of frame When set, disables the data in the Transmit FIFO from Am79C972 controller from re- being overwritten, because auto- ceiving broadcast messages. matic retransmission will not be Used for protocols that do not necessary. When DRTY is set to support broadcast addressing, 0, the Am79C972 controller will except as a function of multicast. attempt 16 transmissions before DRCVBC is cleared by activation signaling a retry error. of H_RESET or S_RESET (broadcast messages will be re- Read/Write accessible only when ceived) and is unaffected by either the STOP or the SPND bit STOP. is set. Read/Write accessible only when 4 FCOLL Force Collision. This bit allows either the STOP or the SPND bit the collision logic to be tested. is set. The Am79C972 controller must be in internal loopback for FCOLL 13 DRCVPA Disable Receive Physical Ad- to be valid. If FCOLL = 1, a colli- dress. When set, the physical ad- sion will be forced during loop- dress detection (Station or node back transmission attempts, ID) of the Am79C972 controller which will result in a Retry Error. will be disabled. Frames ad- If FCOLL = 0, the Force Collision dressed to the nodes individual logic will be disabled. FCOLL is physical address will not be rec- defined after the initialization ognized. block is read. Read/Write accessible only when Read/Write accessible only when either the STOP or the SPND bit either the STOP or the SPND bit is set. is set. 12-9 RES Reserved locations. Written as 3 DXMTFCS Disable Transmit CRC (FCS). zeros and read as undefined. When DXMTFCS is set to 0, the transmitter will generate and ap- 8-7 PORTSEL[1:0] Port Select bits allow for software pend an FCS to the transmitted controlled selection of the net- frame. When DXMTFCS is set to work medium. The only legal val- 1, no FCS is generated or sent ues for this field are 11 and 10. with the transmitted frame. DXMTFCS is overridden when A value of 11 selects the MII port ADD_FCS and ENP bits are set and a value of 10 selects the in TMD1. GPSI port. When APAD_XMT bit (CSR4, Read/Write accessible only when bit11) is set to 1, the setting of either the STOP or the SPND bit DXMTFCS has no effect on is set. Cleared by H_RESET or frames shorter than 64 bytes. S_RESET and is unaffected by STOP. If DXMTFCS is set and ADD_FCS is clear for a particular 6 INTL Internal Loopback. See the de- frame, no FCS will be generated. scription of LOOP (CSR15, bit 2). If ADD_FCS is set for a particular frame, the state of DXMTFCS is Read/Write accessible only when ignored and a FCS will be ap- either the STOP or the SPND bit pended on that frame by the is set. transmit circuitry. See also the ADD_FCS bit in TMD1. Am79C972 121 This bit was called DTCR in the Read/Write accessible only when LANCE (Am7990) device. either the STOP or the SPND bit is set. Read/Write accessible only when either the STOP or the SPND bit CSR16: Initialization Block Address Lower is set. Bit Name Description 2 LOOP Loopback Enable allows the 31-16 RES Reserved locations. Written as Am79C972 controller to operate zeros and read as undefined. in full-duplex mode for test pur- poses. The setting of the full- 15-0 IADRL This register is an alias of CSR1. duplex control bits in BCR9 have no effect when the device oper- Read/Write accessible only when ates in loopback mode. When either the STOP or the SPND bit LOOP = 1, loopback is enabled. is set. In combination with INTL and MIIILP, various loopback modes CSR17: Initialization Block Address Upper are defined as follows in Table Bit Name Description 21. 31-16 RES Reserved locations. Written as Table 21. Loopback Configuration zeros and read as undefined. LOOP INTL MIIILP Function 15-0 IADRH This register is an alias of CSR2. 0 0 0 Normal Operation GPSI 1 1 0 Internal Loop Read/Write accessible only when 1 0 0 External Loop either the STOP or the SPND bit is set. 0 0 0 Normal Operation MII 0 0 1 Internal Loop CSR18: Current Receive Buffer Address Lower 1 0 0 External Loop Bit Name Description Refer to Loop Back Operation section for more details. 31-16 RES Reserved locations. Written as zeros and read as undefined. Read/Write accessible only when either the STOP or the 15-0 CRBAL Contains the lower 16 bits of the SPND bit is set. LOOP is cleared current receive buffer address at by H_RESET or S_RESET and which the Am79C972 controller is unaffected by STOP. will store incoming frame data. 1 DTX Disable Transmit results in Read/Write accessible only when Am79C972 controller not access- either the STOP or the SPND bit ing the Transmit Descriptor Ring is set. These bits are unaffected and, therefore, no transmissions by H_RESET, S_RESET, or are attempted. DTX = 0, will set STOP. TXON bit (CSR0 bit 4) if STRT (CSR0 bit 1) is asserted. CSR19: Current Receive Buffer Address Upper Read/Write accessible only when Bit Name Description either the STOP or the SPND bit is set. 31-16 RES Reserved locations. Written as zeros and read as undefined. 0 DRX Disable Receiver results in the Am79C972 controller not access- 15-0 CRBAU Contains the upper 16 bits of the ing the Receive Descriptor Ring current receive buffer address at and, therefore, all receive frame which the Am79C972 controller data are ignored. DRX = 0, will will store incoming frame data. set RXON bit (CSR0 bit 5) if STRT (CSR0 bit 1) is asserted. 122 Am79C972 Read/Write accessible only when CSR23: Next Receive Buffer Address Upper either the STOP or the SPND bit Bit Name Description is set. These bits are unaffected by H_RESET, S_RESET, or 31-16 RES Reserved locations. Written as STOP. zeros and read as undefined. CSR20: Current Transmit Buffer Address Lower 15-0 NRBAU Contains the upper 16 bits of the Bit Name Description next receive buffer address to which the Am79C972 controller will store incoming frame data. 31-16 RES Reserved locations. Written as zeros and read as undefined. Read/Write accessible only when either the STOP or the SPND bit 15-0 CXBAL Contains the lower 16 bits of the is set. These bits are unaffected current transmit buffer address by H_RESET, S_RESET, or from which the Am79C972 con- STOP. troller is transmitting. CSR24: Base Address of Receive Ring Lower Read/Write accessible only when either the STOP or the SPND bit Bit Name Description is set. These bits are unaffected by H_RESET, S_RESET, or 31-16 RES Reserved locations. Written as STOP. zeros and read as undefined. CSR21: Current Transmit Buffer Address Upper 15-0 BADRL Contains the lower 16 bits of the base address of the Receive Bit Name Description Ring. 31-16 RES Reserved locations. Written as Read/Write accessible only when zeros and read as undefined. either the STOP or the SPND bit is set. These bits are unaffected 15-0 CXBAU Contains the upper 16 bits of the by H_RESET, S_RESET, or current transmit buffer address STOP. from which the Am79C972 con- troller is transmitting. CSR25: Base Address of Receive Ring Upper Read/Write accessible only when Bit Name Description either the STOP or the SPND bit is set. These bits are unaffected 31-16 RES Reserved locations. Written as by H_RESET, S_RESET, or zeros and read as undefined. STOP. 15-0 BADRU Contains the upper 16 bits of the CSR22: Next Receive Buffer Address Lower base address of the Receive Ring. Bit Name Description Read/Write accessible only when 31-16 RES Reserved locations. Written as either the STOP or the SPND bit zeros and read as undefined. is set. These bits are unaffected by H_RESET, S_RESET, or 15-0 NRBAL Contains the lower 16 bits of the STOP. next receive buffer address to which the Am79C972 controller CSR26: Next Receive Descriptor Address Lower will store incoming frame data. Bit Name Description Read/Write accessible only when either the STOP or the SPND bit 31-16 RES Reserved locations. Written as is set. These bits are unaffected zeros and read as undefined. by H_RESET, S_RESET, or STOP. 15-0 NRDAL Contains the lower 16 bits of the next receive descriptor address pointer. Am79C972 123 Read/Write accessible only when CSR30: Base Address of Transmit Ring Lower either the STOP or the SPND bit Bit Name Description is set. These bits are unaffected by H_RESET, S_RESET, or 31-16 RES Reserved locations. Written as STOP. zeros and read as undefined. CSR27: Next Receive Descriptor Address Upper 15-0 BADXL Contains the lower 16 bits of the Bit Name Description base address of the Transmit Ring. 31-16 RES Reserved locations. Written as Read/Write accessible only when zeros and read as undefined. either the STOP or the SPND bit 15-0 NRDAU Contains the upper 16 bits of the is set. These bits are unaffected next receive descriptor address by H_RESET, S_RESET, or pointer. STOP. Read/Write accessible only when CSR31: Base Address of Transmit Ring Upper either the STOP or the SPND bit Bit Name Description is set. These bits are unaffected by H_RESET, S_RESET, or 31-16 RES Reserved locations. Written as STOP. zeros and read as undefined. CSR28: Current Receive Descriptor Address Lower 15-0 BADXU Contains the upper 16 bits of the Bit Name Description base address of the Transmit Ring. 31-16 RES Reserved locations. Written as Read/Write accessible only when zeros and read as undefined. either the STOP or the SPND bit 15-0 CRDAL Contains the lower 16 bits of the is set. These bits are unaffected current receive descriptor ad- by H_RESET, S_RESET, or dress pointer. STOP. Read/Write accessible only when CSR32: Next Transmit Descriptor Address Lower either the STOP or the SPND bit Bit Name Description is set. These bits are unaffected by H_RESET, S_RESET, or 31-16 RES Reserved locations. Written as STOP. zeros and read as undefined. CSR29: Current Receive Descriptor Address Upper 15-0 NXDAL Contains the lower 16 bits of the Bit Name Description next transmit descriptor address pointer. 31-16 RES Reserved locations. Written as Read/Write accessible only when zeros and read as undefined. either the STOP or the SPND bit 15-0 CRDAU Contains the upper 16 bits of the is set. These bits are unaffected current receive descriptor ad- by H_RESET, S_RESET, or dress pointer. STOP. Read/Write accessible only when CSR33: Next Transmit Descriptor Address Upper either the STOP or the SPND bit Bit Name Description is set. These bits are unaffected by H_RESET, S_RESET, or 31-16 RES Reserved locations. Written as STOP. zeros and read as undefined. 15-0 NXDAU Contains the upper 16 bits of the next transmit descriptor address pointer. 124 Am79C972 Read/Write accessible only when CSR37: Next Next Receive Descriptor Address either the STOP or the SPND bit Upper is set. These bits are unaffected Bit Name Description by H_RESET, S_RESET, or STOP. 31-16 RES Reserved locations. Written as zeros and read as undefined. CSR34: Current Transmit Descriptor Address Lower 15-0 NNRDAU Contains the upper 16 bits of the Bit Name Description next next receive descriptor ad- dress pointer. 31-16 RES Reserved locations. Written as Read/Write accessible only when zeros and read as undefined. either the STOP or the SPND bit 15-0 CXDAL Contains the lower 16 bits of the is set. These bits are unaffected current transmit descriptor ad- by H_RESET, S_RESET, or dress pointer. STOP. Read/Write accessible only when CSR38: Next Next Transmit Descriptor Address either the STOP or the SPND bit Lower is set. These bits are unaffected Bit Name Description by H_RESET, S_RESET, or STOP. 31-16 RES Reserved locations. Written as zeros and read as undefined. CSR35: Current Transmit Descriptor Address Upper 15-0 NNXDAL Contains the lower 16 bits of the Bit Name Description next next transmit descriptor ad- dress pointer. 31-16 RES Reserved locations. Written as Read/Write accessible only when zeros and read as undefined. either the STOP or the SPND bit 15-0 CXDAU Contains the upper 16 bits of the is set. These bits are unaffected current transmit descriptor ad- by H_RESET, S_RESET, or dress pointer. STOP. Read/Write accessible only when CSR39: Next Next Transmit Descriptor Address either the STOP or the SPND bit Upper is set. These bits are unaffected Bit Name Description by H_RESET, S_RESET, or STOP. 31-16 RES Reserved locations. Written as zeros and read as undefined. CSR36: Next Next Receive Descriptor Address Lower 15-0 NNXDAU Contains the upper 16 bits of the Bit Name Description next next transmit descriptor ad- dress pointer. 31-16 RES Reserved locations. Written as Read/Write accessible only when zeros and read as undefined. either the STOP or the SPND bit 15-0 NNRDAL Contains the lower 16 bits of the is set. These bits are unaffected next next receive descriptor ad- by H_RESET, S_RESET, or dress pointer. STOP. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. Am79C972 125 CSR40: Current Receive Byte Count CSR43: Current Transmit Status Bit Name Description Bit Name Description 31-16 RES Reserved locations. Written as 31-16 RES Reserved locations. Written as zeros and read as undefined. zeros and read as undefined. 15-12 RES Reserved locations. Read and 15-0 CXST Current Transmit Status. This written as zeros. field is a copy of bits 31-16 of TMD1 of the current transmit de- 11-0 CRBC Current Receive Byte Count. scriptor. This field is a copy of the BCNT field of RMD1 of the current re- Read/Write accessible only when ceive descriptor. either the STOP or the SPND bit is set. These bits are unaffected Read/Write accessible only when by H_RESET, S_RESET, or either the STOP or the SPND bit STOP. is set. These bits are unaffected by H_RESET, S_RESET, or CSR44: Next Receive Byte Count STOP. Bit Name Description CSR41: Current Receive Status 31-16 RES Reserved locations. Written as Bit Name Description zeros and read as undefined. 31-16 RES Reserved locations. Written as 15-12 RES Reserved locations. Read and zeros and read as undefined. written as zeros. 15-0 CRST Current Receive Status. This 11-0 NRBC Next Receive Byte Count. This field is a copy of bits 31-16 of field is a copy of the BCNT field of RMD1 of the current receive de- RMD1 of the next receive de- scriptor. scriptor. Read/Write accessible only when Read/Write accessible only when either the STOP or the SPND bit either the STOP or the SPND bit is set. These bits are unaffected is set. These bits are unaffected by H_RESET, S_RESET, or by H_RESET, S_RESET, or STOP. STOP. CSR42: Current Transmit Byte Count CSR45: Next Receive Status Bit Name Description Bit Name Description 31-16 RES Reserved locations. Written as 31-16 RES Reserved locations. Written as zeros and read as undefined. zeros and read as undefined. 15-12 RES Reserved locations. Read and 15-0 NRST Next Receive Status. This field is written as zeros. a copy of bits 31-16 of RMD1 of the next receive descriptor. 11-0 CXBC Current Transmit Byte Count. This field is a copy of the BCNT Read/Write accessible only when field of TMD1 of the current trans- either the STOP or the SPND bit mit descriptor. is set. These bits are unaffected by H_RESET, S_RESET, or Read/Write accessible only when STOP. either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. 126 Am79C972 CSR46: Transmit Poll Time Counter user must set STOP (CSR0, bit 2). Then the user may write to Bit Name Description CSR47 and then set STRT in CSR0. In this way, the default 31-16 RES Reserved locations. Written as value of 0000h in CSR47 will be zeros and read as undefined. overwritten with the desired user value. 15-0 TXPOLL Transmit Poll Time Counter. This counter is incremented by the If the user does not use the stan- Am79C972 controller microcode dard initialization procedure and is used to trigger the transmit (standard implies use of an initial- descriptor ring polling operation ization block in memory and set- of the Am79C972 controller. ting the INIT bit of CSR0), but instead, chooses to write directly Read/Write accessible only when to each of the registers that are either the STOP or the SPND bit involved in the INIT operation, is set. These bits are unaffected then it is imperative that the user by H_RESET, S_RESET, or also writes all zeros to CSR47 as STOP. part of the alternative initialization sequence. CSR47: Transmit Polling Interval Bit Name Description Read/Write accessible only when either the STOP or the SPND bit 31-16 RES Reserved locations. Written as is set. These bits are unaffected zeros and read as undefined. by H_RESET, S_RESET, or STOP. 15-0 TXPOLLINT Transmit Polling Interval. This register contains the time that the CSR48: Receive Poll Time Counter Am79C972 controller will wait be- Bit Name Description tween successive polling opera- tions. The TXPOLLINT value is 31-16 RES Reserved locations. Written as expressed as the two’s comple- zeros and read as undefined. ment of the desired interval, where each bit of TXPOLLINT 15-0 RXPOLL Receive Poll Time Counter. This represents 1 clock period of time. counter is incremented by the TXPOLLINT[3:0] are ignored. Am79C972 controller microcode (TXPOLLINT[16] is implied to be and is used to trigger the receive a one, so TXPOLLINT[15] is sig- descriptor ring polling operation nificant and does not represent of the Am79C972 controller. the sign of the two’s complement TXPOLLINT value.) Read/Write accessible only when either the STOP or the SPND bit The default value of this register is set. These bits are unaffected is 0000h. This corresponds to a by H_RESET, S_RESET, or polling interval of 65,536 clock STOP. periods (1.966 ms when CLK=33 MHz). The TXPOL- CSR49: Receive Polling Interval LINT value of 0000h is created Bit Name Description during the microcode initialization routine and, therefore, might not 31-16 RES Reserved locations. Written as be seen when reading CSR47 af- zeros and read as undefined. ter H_RESET or S_RESET. 15-0 RXPOLLINT Receive Polling Interval. This reg- If the user desires to program a ister contains the time that the value for POLLINT other than the Am79C972 controller will wait be- default, then the correct proce- tween successive polling opera- dure is to first set INIT only in tions. The RXPOLLINT value is CSR0. Then, when the initializa- expressed as the two’s comple- tion sequence is complete, the Am79C972 127 ment of the desired interval, CSR58: Software Style where each bit of RXPOLLINT This register is an alias of the location BCR20. Accesses approximately represents one to and from this register are equivalent to accesses to clock time period. RXPOL- BCR20. LINT[3:0] are ignored. (RXPOL- Bit Name Description LINT[16] is implied to be a 1, so RXPOLLINT[15] is significant and does not represent the sign 31-16 RES Reserved locations. Written as of the two’s complement RXPOL- zeros and read as undefined. LINT value.) 15-11 RES Reserved locations. Written as The default value of this register zeros and read as undefined. is 0000h. This corresponds to a 10 APERREN Advanced Parity Error Handling polling interval of 65,536 clock Enable. When APERREN is set periods (1.966 ms when to 1, the BPE bits (RMD1 and CLK=33 MHz). The RXPOL- TMD1, bit 23) start having a LINT value of 0000h is created meaning. BPE will be set in the during the microcode initialization descriptor associated with the routine and, therefore, might not buffer that was accessed when a be seen when reading CSR49 af- data parity error occurred. Note ter H_RESET or S_RESET. that since the advanced parity er- If the user desires to program a ror handling uses an additional bit in the descriptor, SWSTYLE (bits value for RXPOLLINT other than 7-0 of this register) must be set to the default, then the correct pro- 2 or 3 to program the Am79C972 cedure is to first set INIT only in controller to use 32-bit software CSR0. Then, when the initializa- structures. tion sequence is complete, the user must set STOP (CSR0, bit APERREN does not affect the re- 2). Then the user may write to porting of address parity errors or CSR49 and then set STRT in data parity errors that occur when CSR0. In this way, the default the Am79C972 controller is the value of 0000h in CSR47 will be target of the transfer. overwritten with the desired user value. Read anytime, write accessible only when either the STOP or the If the user does not use the stan- SPND bit is set. APERREN is dard initialization procedure cleared by H_RESET and is not (standard implies use of an initial- affected by S_RESET or STOP. ization block in memory and set- ting the INIT bit of CSR0), but 9 RES Reserved locations. Written as instead, chooses to write directly zeros and read as undefined. to each of the registers that are involved in the INIT operation, 8 SSIZE32 Software Size 32 bits. When set, then it is imperative that the user this bit indicates that the also writes all zeros to CSR49 as Am79C972 controller utilizes 32- part of the alternative initialization bit software structures for the ini- sequence. tialization block and the transmit and receive descriptor entries. Read/Write accessible only when When cleared, this bit indicates either the STOP or the SPND bit that the Am79C972 controller uti- is set. These bits are unaffected lizes 16-bit software structures for by H_RESET, S_RESET, or the initialization block and the STOP. transmit and receive descriptor entries. In this mode, the Am79C972 controller is back- wards compatible with the 128 Am79C972 Am7990 LANCE and Am79C960 7-0 SWSTYLE Software Style register. The val- PCnet-ISA controllers. ue in this register determines the style of register and memory re- The value of SSIZE32 is deter- sources that shall be used by the mined by the Am79C972 control- Am79C972 controller. The Soft- ler according to the setting of the ware Style selection will affect the Software Style (SWSTYLE, bits interpretation of a few bits within 7-0 of this register). the CSR space, the order of the descriptor entries and the width of Read accessible always. the descriptors and initialization SSIZE32 is read only; write oper- block entries. ations will be ignored. SSIZE32 will be cleared after H_RESET All Am79C972 controller CSR (since SWSTYLE defaults to 0) bits and BCR bits and all descrip- and is not affected by S_RESET tor, buffer, and initialization block or STOP. entries not cited in Table 22 are unaffected by the Software Style If SSIZE32 is reset, then bits selection and are, therefore, al- IADR[31:24] of CSR2 will be ways fully functional as specified used to generate values for the in the CSR and BCR sections. upper 8 bits of the 32-bit address bus during master accesses initi- Read/Write accessible only when ated by the Am79C972 controller. either the STOP or the SPND bit This action is required, since the is set. The SWSTYLE register will 16-bit software structures speci- contain the value 00h following fied by the SSIZE32 = 0 setting H_RESET and will be unaffected will yield only 24 bits of address by S_RESET or STOP. for the Am79C972 controller bus master accesses. CSR60: Previous Transmit Descriptor Address Lower If SSIZE32 is set, then the soft- Bit Name Description ware structures that are common to the Am79C972 controller and 31-16 RES Reserved locations. Written as the host system will supply a full zeros and read as undefined. 32 bits for each address pointer that is needed by the Am79C972 15-0 PXDAL Contains the lower 16 bits of the controller for performing master previous transmit descriptor ad- accesses. dress pointer. The Am79C972 controller has the capability to The value of the SSIZE32 bit has stack multiple transmit frames. no effect on the drive of the upper 8 address bits. The upper 8 ad- Read/Write accessible only when dress pins are always driven, re- either the STOP or the SPND bit gardless of the state of the is set. These bits are unaffected SSIZE32 bit. by H_RESET, S_RESET, or STOP. Note that the setting of the SSIZE32 bit has no effect on the defined width for I/O resources. I/O resource width is determined by the state of the DWIO bit (BCR18, bit 7). Am79C972 129 Table 22. Software Styles SWSTYLE Style Initialization Block [7:0] Name SSIZE32 Entries Descriptor Ring Entries LANCE/ 16-bit software structures, 16-bit software structures, 00h 0 PCnet-ISA non-burst or burst access non-burst access only controller 01h RES 1 RES RES 32-bit software structures, 32-bit software structures, PCnet-PCI 02h 1 controller non-burst or burst access non-burst access only PCnet-PCI 32-bit software structures, 32-bit software structures, 03h 1 controller non-burst or burst access non-burst or burst access All Other Reserved Undefined Undefined Undefined CSR61: Previous Transmit Descriptor Address CSR63: Previous Transmit Status Upper Bit Name Description Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 PXST Previous Transmit Status. This field is a copy of bits 31-16 of 15-0 PXDAU Contains the upper 16 bits of the TMD1 of the previous transmit previous transmit descriptor ad- descriptor. dress pointer. The Am79C972 controller has the capability to Read/Write accessible only when stack multiple transmit frames. either the STOP or the SPND bit is set. These bits are unaffected Read/Write accessible only when by H_RESET, S_RESET, or either the STOP or the SPND bit STOP. is set. These bits are unaffected by H_RESET, S_RESET, or CSR64: Next Transmit Buffer Address Lower STOP. Bit Name Description CSR62: Previous Transmit Byte Count Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 31-16 RES Reserved locations. Written as 15-0 NXBAL Contains the lower 16 bits of the zeros and read as undefined. next transmit buffer address from which the Am79C972 controller 15-12 RES Reserved locations. will transmit an outgoing frame. 11-0 PXBC Previous Transmit Byte Count. Read/Write accessible only when This field is a copy of the BCNT either the STOP or the SPND bit field of TMD1 of the previous is set. These bits are unaffected transmit descriptor. by H_RESET, S_RESET, or Read/Write accessible only when STOP. either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. 130 Am79C972