16-Bit, 250 kSPS, Unipolar/Bipolar ® Programmable Input PulSAR ADC AD7610 FEATURES FUNCTIONAL BLOCK DIAGRAM Multiple pins/software programmable input ranges: TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND 5 V, 10 V, ±5 V, ±10 V OVDD AGND Pins or serial SPI®-compatible input ranges/mode selection AD7610 REF OGND AVDD AMP Throughput: 250 kSPS SERIAL REF PDREF DATAPORT 16-bit resolution with no missing codes SERIAL PDBUF CONFIGURATION INL: ±0.75 LSB typ, ±1.5 LSB max (±23 ppm of FSR) PORT IN+ 16 SWITCHED D[15:0] CAP DAC SNR: 94 dB @ 2 kHz IN– SER/PAR iCMOS® process technology BYTESWAP 5 V internal reference: typical drift 3 ppm/°C; PARALLEL OB/2C CLOCK INTERFACE CNVST On-chip temperature sensor BUSY PD CONTROL LOGIC AND No pipeline delay (SAR architecture) RD CALIBRATION CIRCUITRY RESET Parallel (16- or 8-bit bus) and serial 5 V/3.3 V interface CS SPI-/QSPI™-/MICROWIRE™-/DSP-compatible Power dissipation BIPOLAR TEN 90 mW @ 250 kSPS Figure 1. 10 mW @ 1 kSPS 48-lead LQFP and LFCSP (7 mm × 7 mm) packages APPLICATIONS Process control Medical instruments High speed data acquisition Digital signal processing Instrumentation Spectrum analysis ATE GENERAL DESCRIPTION Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection The AD7610 is a 16-bit charge redistribution successive approxi- 100 kSPS to 500 kSPS to 800 kSPS to >1000 mation register (SAR), architecture analog-to-digital converter Type 250 kSPS 570 kSPS 1000 kSPS kSPS (ADC) fabricated on Analog Devices, Inc.’s iCMOS high voltage Pseudo AD7651 AD7650 AD7653 Differential AD7660 AD7652 AD7667 process. The device is configured through hardware or via a AD7661 AD7664 dedicated write only serial configuration port for input range AD7666 and operating mode. The AD7610 contains a high speed 16-bit True Bipolar AD7610 AD7665 AD7612 AD7671 sampling ADC, an internal conversion clock, an internal reference AD7663 AD7951 (and buffer), error correction circuits, and both serial and parallel True AD7675 AD7676 AD7677 AD7621 system interface ports. A falling edge on CNVST samples the Differential AD7622 analog input on IN+ with respect to a ground sense, IN−. The AD7623 AD7610 features four different analog input ranges: 0 V to 5 V, 0 V 18-Bit, True AD7678 AD7679 AD7674 AD7641 Differential AD7643 to 10 V, ±5 V, and ±10 V. Power consumption is scaled linearly Multichannel/ AD7654 with throughput. The device is available in Pb-free 48-lead, low- Simultaneous AD7655 profile quad flat package (LQFP) and a lead frame chip-scale (LFCSP_VQ) package. Operation is specified from −40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06395-001 AD7610 TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 20 Applications....................................................................................... 1 Voltage Reference Input/Output .............................................. 20 Functional Block Diagram .............................................................. 1 Power Supplies............................................................................ 21 General Description ......................................................................... 1 Conversion Control ................................................................... 22 Revision History ............................................................................... 2 Interfaces.......................................................................................... 23 Specifications..................................................................................... 3 Digital Interface.......................................................................... 23 Timing Specifications .................................................................. 5 Parallel Interface......................................................................... 23 Absolute Maximum Ratings............................................................ 7 Serial Interface ............................................................................ 24 ESD Caution.................................................................................. 7 Master Serial Interface............................................................... 24 Pin Configuration and Function Descriptions............................. 8 Slave Serial Interface .................................................................. 26 Typical Performance Characteristics ........................................... 11 Hardware Configuration ........................................................... 28 Terminology .................................................................................... 15 Software Configuration ............................................................. 28 Theory of Operation ...................................................................... 16 Microprocessor Interfacing....................................................... 29 Overview...................................................................................... 16 Application Information................................................................ 30 Converter Operation.................................................................. 16 Layout Guidelines....................................................................... 30 Transfer Functions...................................................................... 17 Evaluating Performance ............................................................ 30 Typical Connection Diagram ................................................... 18 Outline Dimensions....................................................................... 31 Analog Inputs.............................................................................. 19 Ordering Guide .......................................................................... 31 REVISION HISTORY 10/06—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD7610 SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range, VIN VIN+ − VIN− = 0 V to 5 V −0.1 +5.1 V VIN+ − VIN− = 0 V to 10 V −0.1 +10.1 V V − V = ±5 V −5.1 +5.1 V IN+ IN− V − V = ±10 V −10.1 +10.1 V IN+ IN− VIN− to AGND −0.1 +0.1 V Analog Input CMRR fIN = 100 kHz 75 dB 1 Input Current VIN = ±5 V, ±10 V @ 250 kSPS 100 μA Input Impedance See Analog Inputs section THROUGHPUT SPEED Complete Cycle 4 μs Throughput Rate 250 kSPS DC ACCURACY 2 3 Integral Linearity Error −1.5 ±0.75 +1.5 LSB 2 No Missing Codes 16 Bits 2 Differential Linearity Error −1 +1.5 LSB Transition Noise 0.55 LSB Zero Error (Unipolar or Bipolar) −35 +35 LSB Zero Error Temperature Drift ±1 ppm/°C Bipolar Full-Scale Error −50 +50 LSB Unipolar Full-Scale Error −70 +70 LSB Full-Scale Error Temperature Drift ±1 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% 3 LSB AC ACCURACY 4 Dynamic Range VIN = 0 V to 5 V, fIN = 2 kHz, −60 dB 92.5 93.5 dB VIN = 0 V to 10 V, ±5 V, fIN = 2 kHz, −60 dB 94 dB V = ±10 V, f = 2 kHz, −60 dB 94.5 dB IN IN Signal-to-Noise Ratio V = 0 V to 5 V, 0 V to 10 V, f = 2 kHz 92 93 dB IN IN VIN = ±5 V, ±10 V, fIN = 2 kHz 94 dB VIN = 0 V to 5 V, fIN = 20 kHz 93.5 dB Signal-to-(Noise + Distortion) (SINAD) VIN = ±5 V, fIN = 2 kHz 92.5 dB V = 0 V to 10 V, ±5 V, f = 2 kHz 93 dB IN IN V = ±10 V, f = 2 kHz 93.5 dB IN IN Total Harmonic Distortion fIN = 2 kHz −107 dB Spurious-Free Dynamic Range fIN = 2 kHz 107 dB –3 dB Input Bandwidth VIN = 0 V to 5 V 650 kHz Aperture Delay 2 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 500 ns INTERNAL REFERENCE PDREF = PDBUF = low Output Voltage REF @ 25°C 4.965 5.000 5.035 V Temperature Drift –40°C to +85°C ±3 ppm/°C Line Regulation AVDD = 5 V ± 5% ±15 ppm/V Long-Term Drift 1000 hours 50 ppm Turn-On Settling Time C = 22 μF 10 ms REF REFERENCE BUFFER PDREF = high REFBUFIN Input Voltage Range 2.4 2.5 2.6 V Rev. 0 | Page 3 of 32 AD7610 Parameter Conditions/Comments Min Typ Max Unit EXTERNAL REFERENCE PDREF = PDBUF = high Voltage Range REF 4.75 5 AVDD + 0.1 V Current Drain 250 kSPS throughput 30 μA TEMPERATURE PIN Voltage Output @ 25°C 311 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.33 kΩ DIGITAL INPUTS Logic Levels VIL −0.3 +0.6 V V 2.1 OVDD + 0.3 V IH I −1 +1 μA IL IIH −1 +1 μA DIGITAL OUTPUTS Data Format Parallel or serial 16-bit 5 Pipeline Delay VOL ISINK = 500 μA 0.4 V V I = –500 μA OVDD − 0.6 V OH SOURCE POWER SUPPLIES Specified Performance 6 AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V OVDD 2.7 5.25 V VCC 7 15 15.75 V VEE −15.75 −15 0 V 7 , 8 Operating Current @ 250 kSPS throughput AVDD With Internal Reference 8 mA With Internal Reference Disabled 6.3 mA DVDD 3.3 mA OVDD 0.3 mA VCC VCC = 15 V, with internal reference buffer 1.4 mA VCC = 15 V 0.8 mA VEE VEE = −15 V 0.7 mA Power Dissipation @ 250 kSPS throughput With Internal Reference PDREF = PDBUF = low 90 110 mW With Internal Reference Disabled PDREF = PDBUF = high 70 90 mW 9 In Power-Down Mode PD = high 10 μW 10 TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 With V = 0 V to 5 V or 0 V to 10 V ranges, the input current is typically 40 μA. In all input ranges, the input current scales with throughput. See the Analog Inputs section. IN 2 Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference. 3 LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference. 4 All specifications in dB are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 5 Conversion results are available immediately after completed conversion. 6 4.75 V or VREF – 0.1 V, whichever is larger. 7 Tested in parallel reading mode. 8 With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low. 9 With all digital inputs forced to OVDD. 10 Consult sales for extended temperature range. Rev. 0 | Page 4 of 32 AD7610 TIMING SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit CONVERSION AND RESET (See Figure 33 and Figure 34) Convert Pulse Width t1 10 ns Time Between Conversions t2 4 μs CNVST Low to BUSY High Delay t3 35 ns BUSY High (Except Master Serial Read After Convert) t 1.45 μs 4 Aperture Delay t 2 ns 5 End of Conversion to BUSY Low Delay t6 10 ns Conversion Time t7 1.45 μs Acquisition Time t8 380 ns RESET Pulse Width t 10 ns 9 PARALLEL INTERFACE MODES (See Figure 35 and Figure 37) CNVST Low to DATA Valid Delay t 1.41 μs 10 DATA Valid to BUSY Low Delay t 20 ns 11 Bus Access Request to DATA Valid t 40 ns 12 Bus Relinquish Time t13 2 15 ns 1 MASTER SERIAL INTERFACE MODES (See Figure 39 and Figure 40) CS Low to SYNC Valid Delay t 10 ns 14 1 CS Low to Internal SDCLK Valid Delay t15 10 ns CS Low to SDOUT Delay t16 10 ns CNVST Low to SYNC Delay, Read During Convert t17 560 ns SYNC Asserted to SDCLK First Edge Delay t 3 ns 18 2 Internal SDCLK Period t 30 45 ns 19 2 Internal SDCLK High t 15 ns 20 2 Internal SDCLK Low t21 10 ns 2 SDOUT Valid Setup Time t22 4 ns 2 SDOUT Valid Hold Time t23 5 ns 2 SDCLK Last Edge to SYNC Delay t 5 ns 24 CS High to SYNC HI-Z t 10 ns 25 CS High to Internal SDCLK HI-Z t26 10 ns CS High to SDOUT HI-Z t27 10 ns 2 BUSY High in Master Serial Read After Convert t28 See Table 4 CNVST Low to SYNC Delay, Read After Convert t 1.31 μs 29 SYNC Deasserted to BUSY Low Delay t 25 ns 30 1 SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES (See Figure 42, Figure 43, and Figure 45) External SDCLK, SCCLK Setup Time t 5 ns 31 External SDCLK Active Edge to SDOUT Delay t 2 18 ns 32 SDIN/SCIN Setup Time t33 5 ns SDIN/SCIN Hold Time t34 5 ns External SDCLK/SCCLK Period t35 25 ns External SDCLK/SCCLK High t 10 ns 36 External SDCLK/SCCLK Low t 10 ns 37 1 In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load C of 10 pF; otherwise, the load is 60 pF maximum. L 2 In serial master read during convert mode. See Table 4 for serial mode read after convert mode. Rev. 0 | Page 5 of 32 AD7610 Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SDCLK First Edge Delay Minimum t18 3 20 20 20 ns Internal SDCLK Period Minimum t 30 60 120 240 ns 19 Internal SDCLK Period Maximum t 45 90 180 360 ns 19 Internal SDCLK High Minimum t20 15 30 60 120 ns Internal SDCLK Low Minimum t21 10 25 55 115 ns SDOUT Valid Setup Time Minimum t22 4 20 20 20 ns SDOUT Valid Hold Time Minimum t 5 8 35 90 ns 23 SDCLK Last Edge to SYNC Delay Minimum t 5 7 35 90 ns 24 BUSY High Width Maximum t 2.25 3.00 4.40 7.30 μs 28 1.6mA I OL TO OUTPUT 1.4V PIN C L 60pF 2V 500µA I 0.8V OH t t DELAY DELAY NOTES 1. IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND 2V 2V SDOUT ARE DEFINED WITH A MAXIMUM LOAD 0.8V 0.8V C OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L Figure 2. Load Circuit for Digital Interface Timing, Figure 3. Voltage Reference Levels for Timing SDOUT, SYNC, and SCLK Outputs, CL = 10 pF Rev. 0 | Page 6 of 32 06395-002 06395-003 AD7610 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Analog Inputs/Outputs rating only; functional operation of the device at these or any 1 IN+, IN− to AGND VEE − 0.3 V to VCC + 0.3 V other conditions above those indicated in the operational REF, REFBUFIN, TEMP, AVDD + 0.3 V to section of this specification is not implied. Exposure to absolute AGND − 0.3 V REFGND to AGND maximum rating conditions for extended periods may affect Ground Voltage Differences device reliability. AGND, DGND, OGND ±0.3 V ESD CAUTION Supply Voltages AVDD, DVDD, OVDD −0.3 V to +7 V AVDD to DVDD, AVDD to OVDD ±7 V DVDD to OVDD ±7 V VCC to AGND, DGND –0.3 V to +16.5 V VEE to GND +0.3 V to −16.5 V Digital Inputs −0.3 V to OVDD +0.3 V 2 PDREF, PDBUF ±20 mA 3 Internal Power Dissipation 700 mW 4 Internal Power Dissipation 2.5 W Junction Temperature 125°C Storage Temperature Range −65°C to +125°C 1 See the Analog Inputs section. 2 See the Voltage Reference Input section. 3 Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W, θ = 30°C/W. JC 4 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W. Rev. 0 | Page 7 of 32 AD7610 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 BIPOLAR PIN 1 AVDD 2 35 CNVST AGND 3 34 PD BYTESWAP 4 33 RESET OB/2C 5 AD7610 32 CS TOP VIEW OGND 6 31 RD (Not to Scale) OGND 7 30 TEN 8 29 SER/PAR BUSY 9 28 D0 D15/SCCS 10 27 D1 D14/SCCLK 11 26 D13/SCIN D2/DIVSCLK[0] D3/DIVSCLK[1] 12 25 D12/HW/SW 13 14 15 16 17 18 19 20 21 22 23 24 Figure 4. Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 3, 42 AGND P Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be referenced to AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and OGND voltages should be at the same potential. 2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. 4 BYTESWAP DI Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. 2 5 OB/2C DI Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary. When low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6, 7, 17 OGND P Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be connected to the system digital ground ideally at the same potential as AGND and DGND. 8 SER/PAR DI Serial/Parallel Selection Input. When SER/PAR = low, the parallel mode is selected. When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port and the remaining data bits are high impedance outputs. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the parallel port data output bus. These pins are always outputs regardless of the state of SER/PAR. 11, 12 D[2:3] or DI/O In parallel mode, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. DIVSCLK[0:1] Serial Data Division Clock Selection. In serial master read after convert mode (SER/PAR = high, EXT/INT = low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial data clock that clocks the data output. In other serial modes, these pins are high impedance outputs. 13 D4 or DI/O In parallel mode, this output is used as Bit 4 of the parallel port data output bus. Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated (master) or INT EXT/ external (slave) serial data clock for the AD7610 output data. When EXT/INT = low, master mode; the internal serial data clock is selected on SDCLK output. When EXT/INT = high, slave mode; the output data is synchronized to an external clock signal (gated by CS) connected to the SDCLK input. Rev. 0 | Page 8 of 32 D4/EXT/INT PDBUF D5/INVSYNC PDREF D6/INVSCLK REFBUFIN D7/RDC/SDIN TEMP OGND AVDD OVDD IN+ DVDD AGND DGND VEE D8/SDOUT VCC D9/SDCLK IN– D10/SYNC REFGND REF D11/RDERROR 06395-004 AD7610 1 Pin No. Mnemonic Type Description 14 D5 or DI/O In parallel mode, this output is used as Bit 5 of the parallel port data output bus. INVSYNC PAR INT Serial Data Invert Sync Select. In serial master mode (SER/ = high, EXT/ = low). This input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. 15 D6 or DI/O In parallel mode, this output is used as Bit 6 of the parallel port data output bus. INVSCLK In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK. When INVSCLK = low, the rising edge of SDCLK/SCCLK are used. When INVSCLK = high, the falling edge of SDCLK/SCCLK are used. 16 D7 or DI/O In parallel mode, this output is used as Bit 7 of the parallel port data output bus. RDC or Serial Data Read During Convert. In serial master mode (SER/PAR = high, EXT/INT = low) RDC is used to select the read mode. See the Master Serial Interface section. When RDC = low, the current result is read after conversion. Note the maximum throughput is not attainable in this mode. When RDC = high, the previous conversion result is read during the current conversion. SDIN PAR Serial Data In. In serial slave mode (SER/ = high EXT/INT = high) SDIN can be used as a data input to daisy- chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface 2.5 V, 3 V, or 5 V and decoupled with 10 μF and 100 nF capacitors. 19 DVDD P Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be supplied from AVDD. 20 DGND P Digital Power Ground. Ground reference point for digital outputs. Should be connected to system digital ground ideally at the same potential as AGND and OGND. 21 D8 or DO In parallel mode, this output is used as Bit 8 of the parallel port data output bus. SDOUT Serial Data output. In all serial modes this pin is used as the serial data output synchronized to SDCLK. Conversion results are stored in an on-chip register. The AD7610 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. INT When EXT/ = low, (master mode) SDOUT is valid on both edges of SDCLK. When EXT/INT = high (slave mode). When INVSCLK = low, SDOUT is updated on SDCLK rising edge. When INVSCLK = high, SDOUT is updated on SDCLK falling edge. 22 D9 or DI/O In parallel mode, this output is used as Bit 9 of the parallel port data output bus. SDCLK Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent on the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin. 23 D10 or DO In parallel mode, this output is used as Bit 10 of the parallel port data output bus. SYNC Serial Data Frame Synchronization. In serial master mode (SER/PAR = high, EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the SDOUT output is valid. 24 D11 or DO In parallel mode, this output is used as Bit 11 of the parallel port data output bus. RDERROR Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as an incomplete data read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high. 25 D12 or DI/O In parallel mode, this output is used as Bit 12 of the parallel port data output bus. HW/SW Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure the AD7610 by hardware or software. See the Hardware Configuration section and Software Configuration section. When HW/SW = low, the AD7610 is configured through software using the serial configuration register. When HW/SW = high, the AD7610 is configured through dedicated hardware input pins. 26 D13 or DI/O In parallel mode, this output is used as Bit 13 of the parallel port data output bus. SCIN PAR SW Serial Configuration Data Input. In serial software configuration mode (SER/ = high, HW/ = low) this input is used to serially write in, MSB first, the configuration data into the serial configuration register. The data on this input is latched with SCCLK. See the Software Configuration section. Rev. 0 | Page 9 of 32 AD7610 1 Pin No. Mnemonic Type Description 27 D14 or DI/O In parallel mode, this output is used as Bit 14 of the parallel port data output bus. SCCLK PAR SW Serial Configuration Clock. In serial software configuration mode (SER/ = high, HW/ = low) this input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on the logic state of the INVSCLK pin. See the Software Configuration section. 28 D15 or DI/O In parallel mode, this output is used as Bit 15 of the parallel port data output bus. SCCS PAR SW Serial Configuration Chip Select. In serial software configuration mode (SER/ = high, HW/ = low) this input enables the serial configuration port. See the Software Configuration section. 29 BUSY DO Busy Output. Transitions high when a conversion is started, and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be PAR INT used as a data ready clock signal. Note that in master read after convert mode (SER/ = high, EXT/ = low, RDC = low) the busy time changes according to Table 4. 2 30 TEN DI Input Range Select. Used in conjunction with BIPOLAR per the following: Input Range BIPOLAR TEN 0 V to 5 V Low Low 0 V to 10 V Low High ±5 V High Low ±10 V High High 31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode (not used for serial programmable port). 33 RESET DI Reset Input. When high, reset the AD7610. Current conversion, if any, is aborted. The falling edge of RESET resets the data outputs to all zero’s (with OB/2C = high) and clears the configuration register. See the Digital Interface section. If not used, this pin can be tied to OGND. 2 34 PD DI Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. The digital interface remains active during power down. 35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. 2 36 BIPOLAR DI Input Range Select. See description for Pin 30. 37 REF AI/O Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF is required with or without the internal reference and buffer. See the Reference Decoupling section. 38 REFGND AI Reference Input Analog Ground. Connected to analog ground plane. 39 IN− AI Analog Input Ground Sense. Should be connected to the analog ground plane or to a remote sense ground. 40 VCC P High Voltage Positive Supply. Normally +7 V to +15 V. 41 VEE P High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges). 43 IN+ AI Analog Input. Referenced to IN−. 45 TEMP AO Temperature Sensor Analog Output. Enabled when the internal reference is turned on (PDREF = PDBUF = low). See the Temperature Sensor section. 46 REFBUFIN AI Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the Voltage Reference Input section. 47 PDREF DI Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down, and an external reference must be used. 48 PDBUF DI Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered-down. 1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. 2 PAR SW In serial configuration mode (SER/ = high, HW/ = low), this input is programmed with the serial configuration register and this pin is a don’t care. See the Hardware Configuration section and Software Configuration section. Rev. 0 | Page 10 of 32 AD7610 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; TA = 25°C. 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 0 16384 32768 49152 65536 0 16384 32768 49152 65536 CODE CODE Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 250 180 NEGATIVE INL NEGATIVE DNL 160 POSITIVE INL POSITIVE DNL 200 140 120 150 100 80 100 60 40 50 20 0 0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 INL DISTRIBUTION (LSB) DNL DISTRIBUTION (LSB) Figure 6. Integral Nonlinearity Distribution (296 Devices) Figure 9. Differential Nonlinearity Distribution (296 Devices) 250000 140000 132700 σ = 0.44 σ = 0.51 127179 211404 120000 200000 100000 150000 80000 60000 100000 40000 50000 27510 20000 22202 1072 00 4 0 0 00 169 00 0 0 7FFF 8000 8001 8002 8003 8004 8005 8006 8000 8001 8002 8003 8004 8005 8006 8007 CODE IN HEX CODE IN HEX Figure 7. Histogram of 261,120 Conversions of a DC Input Figure 10. Histogram of 261,120 Conversions of a DC Input at the Code Center at the Code Transition Rev. 0 | Page 11 of 32 COUNTS INL (LSB) NUMBER OF UNITS 06395-006 06395-007 06395-005 COUNTS NUMBER OF UNITS DNL (LSB) 06395-009 06395-010 06395-008 AD7610 0 95.0 f = 250kSPS S SNR f = 19.95kHz SINAD IN –20 SNR = 93.4dB ±10V ±5V THD = –107dB SFDR = 114dB –40 94.5 SINAD = 93dB –60 –80 94.0 0V TO 10V 0V TO 5V –100 93.5 –120 –140 –160 93.0 –60 –50 –40 –30 –20 –10 0 0 25 50 75 100 125 FREQUENCY (kHz) INPUT LEVEL (dB) Figure 14. SNR and SINAD vs. Input Level (Referred to Full Scale) Figure 11. FFT 20 kHz –70 120 96 16.0 SNR 94 15.8 –80 110 SINAD 92 15.6 SFDR –90 100 90 15.4 ENOB –100 THD 90 88 15.2 THIRD 86 15.0 HARMONIC –110 80 SECOND HARMONIC 84 14.8 –120 70 82 14.6 80 14.4 –130 60 1 10 100 1 10 100 FREQUENCY (kHz) FREQUENCY (kHz) Figure 15. THD, Harmonics, and SFDR vs. Frequency Figure 12. SNR, SINAD, and ENOB vs. Frequency 96 96 VIN = 0V TO 5V VIN = 0V TO 5V VIN = 0V TO 10V VIN = 0V TO 10V VIN = ±5V VIN = ±5V 95 95 VIN = ±10V VIN = ±10V 94 94 93 93 92 92 91 91 90 90 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. SINAD vs. Temperature Figure 13. SNR vs. Temperature Rev. 0 | Page 12 of 32 SNR, SINAD (dB) AMPLITUDE (dB OF FULL SCALE) SNR (dB) 06395-013 06395-011 ENOB (Bits) 06395-012 THD, HARMONICS (dB) SINAD (dB) SNR, SINAD REFERRED TO FULL SCALE (dB) 06395-014 06395-016 SFDR (dB) 06395-015 AD7610 –96 126 VIN = 0V TO 5V VIN = 0V TO 5V VIN = 0V TO 10V VIN = 0V TO 10V 124 –100 VIN = ±5V VIN = ±5V VIN = ±10V VIN = ±10V 122 –104 120 –108 118 116 –112 114 –116 112 –120 110 –124 108 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. THD vs. Temperature Figure 20. SFDR vs. Temperature (Excludes Harmonics) 5 5.012 ZERO ERROR 4 POSITIVE FS ERROR 5.010 NEGATIVE FS ERROR 3 5.008 2 5.006 1 0 5.004 –1 5.002 –2 5.000 –3 4.998 –4 –5 4.996 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. Zero Error, Positive and Negative Full Scale vs. Temperature Figure 21. Typical Reference Voltage Output vs. Temperature (3 Devices) 60 100000 10000 50 DVDD 1000 40 100 10 AVDD 30 VCC +15V 1 VEE –15V 20 ALL MODES 0.1 OVDD 10 0.01 PDREF = PDBUF = HIGH 0 0.001 10 08 1234 567 100 1000 10000 100000 1000000 REFERENCE DRIFT (ppm/°C) SAMPLING RATE (SPS) Figure 19. Reference Voltage Temperature Coefficient Distribution (247 Devices) Figure 22. Operating Currents vs. Sample Rate Rev. 0 | Page 13 of 32 ZERO ERROR, FULL SCALE ERROR (LSB) THD (dB) NUMBER OF UNITS 06395-019 06395-017 06395-018 OPERATING CURRENTS (µA) VREF (V) SFDR (dB) 06395-020 06395-021 06395-022 AD7610 50 700 PD = PDBUF = PDREF = HIGH OVDD = 2.7V @ 85°C 45 VEE = –15V 600 VCC = +15V OVDD = 2.7V @ 25°C DVDD 40 OVDD AVDD 500 35 30 400 25 OVDD = 5V @ 85°C 300 20 OVDD = 5V @ 25°C 15 200 10 100 5 0 0 0 50 100 150 200 –55 –35 –15 5 25 45 65 85 105 TEMPERATURE (°C) C (pF) L Figure 23. Power-Down Operating Currents vs. Temperature Figure 24. Typical Delay vs. Load Capacitance C L Rev. 0 | Page 14 of 32 POWER-DOWN OPERATING CURRENTS (nA) 06395-023 t DELAY (ns) 12 06395-024 AD7610 TERMINOLOGY Least Significant Bit (LSB) Total Harmonic Distortion (THD) The least significant bit, or LSB, is the smallest increment that THD is the ratio of the rms sum of the first five harmonic can be represented by a converter. For an analog-to-digital con- components to the rms value of a full-scale input signal and verter with N bits of resolution, the LSB expressed in volts is is expressed in decibels. V (max) Signal-to-(Noise + Distortion) Ratio (SINAD) INp-p LSB(V)= N SINAD is the ratio of the rms value of the actual input signal to 2 the rms sum of all other spectral components below the Nyquist Integral Nonlinearity Error (INL) frequency, including harmonics but excluding dc. The value for Linearity error refers to the deviation of each individual code SINAD is expressed in decibels. from a line drawn from negative full-scale through positive full- Spurious-Free Dynamic Range (SFDR) scale. The point used as negative full-scale occurs a ½ LSB before The difference, in decibels (dB), between the rms amplitude of the first code transition. Positive full-scale is defined as a level the input signal and the peak spurious signal. 1½ LSBs beyond the last code transition. The deviation is meas- ured from the middle of each code to the true straight line. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave Differential Nonlinearity Error (DNL) input. It is related to SINAD and is expressed in bits by In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It − 1.76)/6.02] ENOB = [(SINADdB is often specified in terms of resolution for which no missing Aperture Delay codes are guaranteed. Aperture delay is a measure of the acquisition performance Bipolar Zero Error measured from the falling edge of the CNVST input to when The difference between the ideal midscale input voltage (0 V) the input signal is held for a conversion. and the actual voltage producing the midscale output code. Transient Response Unipolar Offset Error The time required for the AD7610 to achieve its rated accuracy The first transition should occur at a level ½ LSB above analog after a full-scale step function is applied to its input. ground. The unipolar offset error is the deviation of the actual Reference Voltage Temperature Coefficient transition from that point. Reference voltage temperature coefficient is derived from the Full-Scale Error typical shift of output voltage at 25°C on a sample of parts at the The last transition (from 111…10 to 111…11) should occur for maximum and minimum reference output voltage (VREF) meas- an analog voltage 1½ LSB below the nominal full-scale. The full- ured at T , T(25°C), and T . It is expressed in ppm/°C as MIN MAX scale error is the deviation in LSB (or % of full-scale range) of V (Max)–V (Min) REF REF 6 the actual level of the last transition from the ideal level and TCV ( ppm/°C)= ×10 REF V (25°C)× (T –T ) includes the effect of the offset error. Closely related is the gain REF MAX MIN error (also in LSB or % of full-scale range), which does not where: include the effects of the offset error. V (Max) = maximum V at T , T(25°C), or T . REF REF MIN MAX Dynamic Range VREF (Min) = minimum VREF at TMIN, T(25°C), or TMAX. Dynamic range is the ratio of the rms value of the full-scale to VREF (25°C) = VREF at 25°C. the rms noise measured for an input typically at −60 dB. The TMAX = +85°C. value for dynamic range is expressed in decibels. TMIN = –40°C. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Rev. 0 | Page 15 of 32 AD7610 THEORY OF OPERATION IN+ REF REFGND SWITCHES CONTROL SW MSB LSB A 32,768C 16,384C 4C 2C C C BUSY CONTROL COMP LOGIC OUTPUT IN– CODE 65,536C SW B CNVST Figure 25. ADC Simplified Schematic OVERVIEW CONVERTER OPERATION The AD7610 is a very fast, low power, precise, 16-bit analog-to- The AD7610 is a successive approximation ADC based on a digital converter (ADC) using successive approximation capacitive charge redistribution DAC. Figure 25 shows the simplified digital-to-analog converter (CDAC) architecture. schematic of the ADC. The CDAC consists of two identical arrays of 16 binary weighted capacitors, which are connected The AD7610 can be configured at any time for one of four input to the two comparator inputs. ranges with inputs in parallel and serial hardware modes or by a dedicated write only, SPI-compatible interface via a configure- During the acquisition phase, terminals of the array tied to the tion register in serial software mode. The AD7610 uses Analog comparator’s input are connected to AGND via SW+ and SW−. Device’s patented iCMOS high voltage process to accommodate All independent switches are connected to the analog inputs. 0 to 5 V, 0 to 10 V, ±5 V, and ±10 V input ranges without the use Thus, the capacitor arrays are used as sampling capacitors and of conventional thin films. Only one acquisition cycle, t8, is required acquire the analog signal on IN+ and IN− inputs. A conversion for the inputs to latch to the correct configuration. Resetting or phase is initiated once the acquisition phase is complete and the power cycling is not required for reconfiguring the ADC. CNVST input goes low. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then The AD7610 is capable of converting 250,000 samples per disconnected from the inputs and connected to the REFGND second (250 kSPS) and power consumption scales linearly with input. Therefore, the differential voltage between the inputs (IN+ throughput making it useful for battery powered systems. and IN−) captured at the end of the acquisition phase is applied The AD7610 provides the user with an on-chip track-and-hold, to the comparator inputs, causing the comparator to become successive approximation ADC that does not exhibit any pipe- unbalanced. By switching each element of the capacitor array line or latency, making it ideal for multiple multiplexed channel between REFGND and REF, the comparator input varies by applications. binary weighted voltage steps (V /2, V /4 through V /65536). REF REF REF For unipolar input ranges, the AD7610 typically requires three The control logic toggles these switches, starting with the MSB supplies; VCC, AVDD (which can supply DVDD), and OVDD first, in order to bring the comparator back into a balanced which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic. condition. For bipolar input ranges, the AD7610 requires the use of the After the completion of this process, the control logic generates additional VEE supply. the ADC output code and brings the BUSY output low. The device is housed in Pb-free, 48-lead LQFP or tiny LFCSP 7 mm × 7 mm packages that combine space savings with flexi- bility. In addition, the AD7610 can be configured as either a parallel or serial SPI-compatible interface. Rev. 0 | Page 16 of 32 06395-025 AD7610 TRANSFER FUNCTIONS 111...111 Using the OB/2C digital input or via the configuration register, 111...110 111...101 the AD7610 offers two output codings: straight binary and twos complement. See Figure 26 and Table 7 for the ideal transfer char- acteristic and digital output codes for the different analog input ranges, V . Note that when using the configuration register, the IN 2C OB/ input is a don’t care and should be tied to either high or low. 000...010 000...001 000...000 –FSR + 1 LSB +FSR – 1 LSB –FSR –FSR + 0.5 LSB +FSR – 1.5 LSB ANALOG INPUT Figure 26. ADC Ideal Transfer Function Table 7. Output Codes and Ideal Input Voltages V = 5 V Digital Output Code REF Description V = 5 V V = 10 V V = ±5 V V = ±10 V Straight Binary Twos Complement IN IN IN IN 1 1 FSR −1 LSB 4.999924 V 9.999847 V +4.999847 V +9.999695 V 0xFFFF 0x7FFF FSR − 2 LSB 4.999847 V 9.999695 V +4.999695 V +9.999390 V 0xFFFE 0x7FFE Midscale + 1 LSB 2.500076 V 5.000153 V +152.6 μV +305.2 μV 0x8001 0x0001 Midscale 2.5 V 5.000000 V 0 V 0 V 0x8000 0x0000 Midscale − 1 LSB 2.499924 V 4.999847 V −152.6 μV −305.2 μV 0x7FFF 0xFFFF −FSR + 1 LSB 76.3 μV 152.6 μV −4.999847 V −9.999695 V 0x0001 0x8001 2 2 −FSR 0 V 0 V −5 V −10 V 0x0000 0x8000 1 This is also the code for overrange analog input (VIN+ − VIN− above VREF − VREFGND). 2 This is also the code for overrange analog input (V − V below V − V ). IN+ IN− REF REFGND Rev. 0 | Page 17 of 32 ADC CODE (Straight Binary) 06395-026 AD7610 TYPICAL CONNECTION DIAGRAM Figure 27 shows a typical connection diagram for the AD7610 using the internal reference, serial data and serial configuration interfaces. Different circuitry from that shown in Figure 27 is optional and is discussed in the following sections. DIGITAL SUPPLY (+5V) NOTE 5 DIGITAL 10Ω INTERFACE ANALOG SUPPLY SUPPLY (+5V) (+2.5V, +3.3V, OR +5V) 100nF 10µF 10µF 100nF 100nF 10µF AVDD AGND DGND DVDD OVDD OGND +7V TO +15.75V SUPPLY MICROCONVERTER/ VCC BUSY 100nF MICROPROCESSOR/ 10µF DSP SDCLK SERIAL PORT 1 SDOUT 100nF 10µF SCCLK –7V TO –15.75V VEE SERIAL SUPPLY PORT 2 SCIN NOTE 6 NOTE 3 REF SCCS C REF REFBUFIN NOTE 7 22µF NOTE 4 100nF 50Ω D CNVST REFGND AD7610 OB/2C NOTE 2 SER/PAR OVDD 15Ω IN+ U1 HW/SW ANALOG INPUT + BIPOLAR C 2.7nF C TEN CLOCK ANALOG IN– NOTE 3 INPUT– NOTE 1 PDREF PDBUF PD RD CS RESET NOTES 1. SEE ANALOG INPUT SECTION. ANALOG INPUT(–) IS REFERENCED TO AGND ±0.1V. 2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION. 4. A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ4YB1A226M). SEE VOLTAGE REFERENCE INPUT SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6. THE VCC AND VEE SUPPLIES SHOULD BE VCC = [VIN(MAX) +2V] and VEE = [VIN(MIN) –2V] FOR BIPOLAR INPUT RANGES. FOR UNIPOLAR INPUT RANGES, VEE CAN BE 0V. SEE POWER SUPPLY SECTION. 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port Rev. 0 | Page 18 of 32 06395-027 AD7610 For instance, by using IN− to sense a remote signal ground, ANALOG INPUTS ground potential differences between the sensor and the local Input Range Selection ADC ground are eliminated. In parallel mode and serial hardware mode, the input range is 100 selected by using the BIPOLAR (bipolar) and TEN (10 Volt range) 90 inputs. See Table 6 for pin details and the Hardware 80 Configuration section and Software Configuration section for programming the mode selection with either pins or configuration 70 register. Note that when using the configuration register, the 60 BIPOLAR and TEN inputs are don’t cares and should be tied to 50 either high or low. 40 Input Structure 30 Figure 28 shows an equivalent circuit for the input structure of 20 the AD7610. 10 0 TO 5V RANGE ONLY 0 1 10 100 1000 10000 AVDD VCC FREQUENCY (kHz) D1 D3 Figure 29. Analog Input CMRR vs. Frequency C R IN IN IN+ OR IN– During the acquisition phase for ac signals, the impedance of C D2 D4 PIN the analog inputs, IN+ and IN−, can be modeled as a parallel VEE combination of Capacitor CPIN and the network formed by AGND the series connection of RIN and CIN. CPIN is primarily the pin Figure 28. AD7610 Simplified Analog Input capacitance. R is typically 5 kΩ and is a lumped component IN The four diodes, D1 to D4, provide ESD protection for the analog comprised of serial resistors and the on resistance of the switches. inputs, IN+ and IN−. Care must be taken to ensure that the analog C is primarily the ADC sampling capacitor and depending on IN input signal never exceeds the supply rails by more than 0.3 V, the input range selected is typically 48 pF in the 0 V to 5 V range, because this causes the diodes to become forward-biased and to typically 24 pF in the 0 V to 10 V and ±5 V ranges and typically start conducting current. These diodes can handle a forward- 12 pF in the ±10 V range. During the conversion phase, when biased current of 120 mA maximum. For instance, these conditions the switches are opened, the input impedance is limited to CPIN. could eventually occur when the input buffer’s U1 supplies are Since the input impedance of the AD7610 is very high, it can be different from AVDD, VCC, and VEE. In such a case, an input directly driven by a low impedance source without gain error. buffer with a short-circuit current limitation can be used to protect To further improve the noise filtering achieved by the AD7610 the part although most op amps’ short circuit current is <100 mA. analog input circuit, an external, one-pole RC filter between the Note that D3 and D4 are only used in the 0 V to 5 V range to amplifier’s outputs and the ADC analog inputs can be used, as allow for additional protection in applications that are switching shown in Figure 27. However, large source impedances signifi- from the higher voltage ranges. antly affect the ac performance, especially total harmonic This analog input structure allows the sampling of the differential distortion (THD). The maximum source impedance depends signal between IN+ and IN−. By using this differential input, on the amount of THD that can be tolerated. The THD degrades small signals common to both inputs are rejected as shown in as a function of the source impedance and the maximum input Figure 29, which represents the typical CMRR over frequency. frequency. Rev. 0 | Page 19 of 32 06395-028 CMRR (dB) 06395-029 AD7610 The AD8021 meets these requirements and is appropriate for DRIVER AMPLIFIER CHOICE almost all applications. The AD8021 needs a 10 pF external Although the AD7610 is easy to drive, the driver amplifier must compensation capacitor that should have good linearity as an meet the following requirements: NPO ceramic or mica type. Moreover, the use of a noninverting • For multichannel, multiplexed applications, the driver +1 gain arrangement is recommended and helps to obtain the amplifier and the AD7610 analog input circuit must be best signal-to-noise ratio. able to settle for a full-scale step of the capacitor array at a The AD8022 can also be used when a dual version is needed 16-bit level (0.0015%). For the amplifier, settling at 0.1% to and a gain of 1 is present. The AD829 is an alternative in appli- 0.01% is more commonly specified. This differs significantly cations where high frequency (above 100 kHz) performance is not from the settling time at a 16-bit level and should be verified required. In applications with a gain of 1, an 82 pF compensation prior to driver selection. The AD8021 op amp combines ultra- capacitor is required. The AD8610 is an option when low bias low noise and high gain bandwidth and meets this settling current is needed in low frequency applications. time requirement even when used with gains of up to 13. Since the AD7610 uses a large geometry, high voltage input • The noise generated by the driver amplifier needs to be switch, the best linearity performance is obtained when using kept as low as possible to preserve the SNR and transition the amplifier at its maximum full power bandwidth. Gaining noise performance of the AD7610. The noise coming from the amplifier to make use of the more dynamic range of the the driver is filtered by the external 1-pole low-pass filter ADC results in increased linearity errors. For applications as shown in Figure 27. The SNR degradation due to the requiring more resolution, the use of an additional amplifier amplifier is with gain should precede a unity follower driving the AD7610. ⎛ ⎞ See Table 8 for a list of recommended op amps. ⎜ ⎟ V ⎜ ⎟ NADC SNR = 20log LOSS Table 8. Recommended Driver Amplifiers ⎜ ⎟ π 2 2 ⎜ V + f () Ne ⎟ NADC N ⎜ −3dB ⎟ Amplifier Typical Application 2 ⎝ ⎠ ADA4841-x 12 V supply, very low noise, low distortion, where: low power, low frequency VNADC is the noise of the ADC, which is: AD829 ±15 V supplies, very low noise, low frequency AD8021 ±12 V supplies, very low noise, high frequency V INp-p AD8022 ±12 V supplies, very low noise, high 2 2 V = frequency, dual NADC SNR 20 AD8610/AD8620 ±13 V supplies, low bias current, low 10 frequency, single/dual f–3dB is the cutoff frequency of the input filter (3.9 MHz). N is the noise factor of the amplifier (+1 in buffer VOLTAGE REFERENCE INPUT/OUTPUT configuration). The AD7610 allows the choice of either a very low temperature e is the equivalent input voltage noise density of the op N drift internal voltage reference, an external reference or an external amp, in nV/√Hz. buffered reference. • The driver needs to have a THD performance suitable to The internal reference of the AD7610 provides excellent perfor- that of the AD7610. Figure 15 shows the THD vs. frequency mance and can be used in almost all applications. However, the that the driver should exceed. linearity performance is guaranteed only with an external reference. Rev. 0 | Page 20 of 32 AD7610 Temperature Sensor Internal Reference (REF = 5 V) (PDREF = Low, PDBUF = Low) When the internal reference is enabled (PDREF = PDBUF = low), the on-chip temperature sensor output (TEMP) is enabled To use the internal reference, the PDREF and PDBUF inputs and can be use to measure the temperature of the AD7610. To must be low. This enables the on-chip band gap reference, buffer, improve the calibration accuracy over the temperature range, the and TEMP sensor resulting in a 5.00 V reference on the REF pin. output of the TEMP pin is applied to one of the inputs of the The internal reference is temperature-compensated to 5.000 V analog switch (such as ADG779), and the ADC itself is used to ±35 mV. The reference is trimmed to provide a typical drift of measure its own temperature. This configuration is shown in 3 ppm/°C. This typical drift characteristic is shown in Figure 19. Figure 30. External 2.5 V Reference and Internal Buffer (REF = 5 V) TEMP ADG779 (PDREF = High, PDBUF = Low) To use an external reference with the internal buffer, PDREF TEMPERATURE IN+ ANALOG INPUT SENSOR should be high and PDBUF should be low. This powers down AD7610 C C the internal reference and allows the 2.5 V reference to be applied to REFBUFIN producing 5 V on the REF pin. The internal ref- Figure 30. Use of the Temperature Sensor erence buffer is useful in multiconverter applications since a POWER SUPPLIES buffer is typically required in these applications. The AD7610 uses five sets of power supply pins: External 5 V Reference (PDREF = High, PDBUF = High) To use an external reference directly on the REF pin, PDREF • AVDD: analog 5 V core supply and PDBUF should both be high. PDREF and PDBUF power • VCC: analog high voltage positive supply down the internal reference and the internal reference buffer, VEE: high voltage negative supply • respectively. For improved drift performance, an external ref- erence such as the ADR445 or ADR435 is recommended. • DVDD: digital 5 V core supply Reference Decoupling • OVDD: digital input/output interface supply Whether using an internal or external reference, the AD7610 Core Supplies voltage reference input (REF) has a dynamic input impedance; The AVDD and DVDD supply the AD7610 analog and digital therefore, it should be driven by a low impedance source with cores respectively. Sufficient decoupling of these supplies is efficient decoupling between the REF and REFGND inputs. This required consisting of at least a 10 μF capacitor and 100 nF on decoupling depends on the choice of the voltage reference, but each supply. The 100 nF capacitors should be placed as close as usually consists of a low ESR capacitor connected to REF and possible to the AD7610. To reduce the number of supplies needed, REFGND with minimum parasitic inductance. A 22 μF (X5R, the DVDD can be supplied through a simple RC filter from the 1206 size) ceramic chip capacitor (or 47 μF tantalum capacitor) analog supply, as shown in Figure 27. is appropriate when using either the internal reference or the High Voltage Supplies ADR445/ADR435 external reference. The high voltage bipolar supplies, VCC and VEE are required The placement of the reference decoupling is also important to and must be at least 2 V larger than the maximum input, V . IN the performance of the AD7610. The decoupling capacitor should For example, if using the bipolar 10 V range, the supplies should be mounted on the same side as the ADC right at the REF pin be ±12 V minimum. Sufficient decoupling of these supplies is with a thick PCB trace. The REFGND should also connect to also required consisting of at least a 10 μF capacitor and 100 nF the reference decoupling capacitor with the shortest distance on each supply. For unipolar operation, the VEE supply can be and to the analog ground plane with several vias. grounded with some slight THD performance degradation. For applications that use multiple AD7610 or other PulSAR Digital Output Supply devices, it is more effective to use the internal reference buffer to buffer the external 2.5 V reference voltage. The OVDD supplies the digital outputs and allows direct interface with any logic working between 2.3 V and 5.25 V. OVDD should The voltage reference temperature coefficient (TC) directly be set to the same level as the system interface. Sufficient decou- impacts full scale; therefore, in applications where full-scale pling is required consisting of at least a 10 μF capacitor and 100 nF accuracy matters, care must be taken with the TC. For instance, a with the 100 nF placed as close as possible to the AD7610. ±15 ppm/°C TC of the reference changes full-scale by ±1 LSB/°C. Rev. 0 | Page 21 of 32 06395-030 AD7610 Power Down Power Sequencing Setting PD = high powers down the AD7610, thus reducing The AD7610 is independent of power supply sequencing and is supply currents to their minimums as shown in Figure 23. When very insensitive to power supply variations on AVDD over a wide the ADC is in power down, the current conversion (if any) is frequency range as shown in Figure 31. completed and the digital bus remains active. To further reduce 80 EXT REF the digital supply currents, drive the inputs to OVDD or OGND. 75 Power down can also be programmed with the configuration 70 INT REF register. See the Software Configuration section for details. Note 65 that when using the configuration register, the PD input is a 60 don’t care and should be tied to either high or low. 55 CONVERSION CONTROL 50 CNVST The AD7610 is controlled by the input. A falling edge 45 CNVST on is all that is necessary to initiate a conversion. Detailed 40 timing diagrams of the conversion process are shown in Figure 33. 35 Once initiated, it cannot be restarted or aborted, even by the 30 power-down input, PD, until the conversion is complete. The 1 10 100 1000 10000 CNVST CS RD signal operates independently of and signals. FREQUENCY (kHz) Figure 31. AVDD PSRR vs. Frequency t 2 t 1 Power Dissipation vs. Throughput CNVST The AD7610 automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low, which allows a significant BUSY t power savings when the conversion rate is reduced (see Figure 32). 4 t 3 This feature makes the AD7610 ideal for very low power, battery- t 6 t 5 operated applications. MODE ACQUIRE CONVERT ACQUIRE CONVERT It should be noted that the digital interface remains active even t t 7 8 during the acquisition phase. To reduce the operating digital supply Figure 33. Basic Conversion Timing currents even further, drive the digital inputs close to the power rails (that is, OVDD and OGND). Although CNVST is a digital signal, it should be designed with 1000 special care with fast, clean edges, and levels with minimum overshoot, undershoot, or ringing. CNVST The trace should be shielded with ground and a low value (such as 50 Ω) serial resistor termination should be added close 100 to the output of the component that drives this line. For applications where SNR is critical, the CNVST signal should have very low jitter. This can be achieved by using a dedicated 10 oscillator for CNVST generation, or by clocking CNVST with a high frequency, low jitter clock, as shown in Figure 27. PDREF = PDBUF = HIGH 1 1 10 100 1000 10000 100000 1000000 SAMPLING RATE (kSPS) Figure 32. Power Dissipation vs. Sample Rate Rev. 0 | Page 22 of 32 POWER DISSIPATION (mW) PSRR (dB) 06395-031 06395-032 06395-033 AD7610 INTERFACES CS = RD = 0 DIGITAL INTERFACE t 1 CNVST The AD7610 has a versatile digital interface that can be set up as either a serial or a parallel interface with the host system. The t 10 serial interface is multiplexed on the parallel data bus. The AD7610 BUSY digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In t 4 t 3 t most applications, the OVDD supply pin is connected to the host 11 system interface 2.5 V to 5.25 V digital supply. Finally, by using DATA PREVIOUS CONVERSION DATA NEW DATA 2C input pin, both twos complement or straight binary BUS the OB/ coding can be used. Figure 35. Master Parallel Data Timing for Reading (Continuous Read) CS RD Two signals, and , control the interface. When at least Slave Parallel Interface one of these signals is high, the interface outputs are in high In slave parallel reading mode, the data can be read either after CS impedance. Usually, allows the selection of each AD7610 each conversion, which is during the next acquisition phase, or in multicircuit applications and is held low in a single AD7610 during the following conversion, as shown in Figure 36 and design. RD is generally used to enable the conversion result on Figure 37, respectively. When the data is read during the conver- the data bus. sion, it is recommended that it is read only during the first half RESET of the conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface and the most The RESET input is used to reset the AD7610. A rising edge on critical analog conversion circuitry. RESET aborts the current conversion (if any) and tristates the data bus. The falling edge of RESET resets the AD7610 and clears CS the data bus and configuration register. See Figure 34 for the RESET timing details. t 9 RD RESET BUSY BUSY DATA BUS DATA t CURRENT 8 BUS CONVERSION CNVST t t 12 13 Figure 36. Slave Parallel Data Timing for Reading (Read After Convert) Figure 34. RESET Timing PARALLEL INTERFACE CS = 0 The AD7610 is configured to use the parallel interface when CNVST, t 1 RD PAR SER/ is held low. Master Parallel Interface CS RD Data can be continuously read by tying and low, thus BUSY t 4 requiring minimal microprocessor connections. However, in this mode, the data bus is always driven and cannot be used in t 3 shared bus applications (unless the device is held in RESET). Figure 35 details the timing for this mode. DATA PREVIOUS BUS CONVERSION t t 12 13 Figure 37. Slave Parallel Data Timing for Reading (Read During Convert) Rev. 0 | Page 23 of 32 06395-034 06395-036 06395-037 06395-035 AD7610 8-Bit Interface (Master or Slave) MASTER SERIAL INTERFACE The BYTESWAP pin allows a glueless interface to an 8-bit bus. The pins multiplexed on D[10:2] and used for the master serial As shown in Figure 38, when BYTESWAP is low, the LSB byte interface are: DIVSCLK[0], DIVSCLK[1], EXT/INT, INVSYNC, is output on D[7:0] and the MSB is output on D[15:8]. When INVSCLK, RDC, SDOUT, SDCLK and SYNC. BYTESWAP is high, the LSB and MSB bytes are swapped; the PAR INT Internal Clock (SER/ = High, EXT/ = Low) LSB is output on D[15:8] and the MSB is output on D[7:0]. By The AD7610 is configured to generate and provide the serial connecting BYTESWAP to an address line, the 16-bit data can data clock, SDCLK, when the EXT/INT pin is held low. The be read in two bytes on either D[15:8] or D[7:0]. This interface can be used in both master and slave parallel reading modes. AD7610 also generates a SYNC signal to indicate to the host when the serial data is valid. The SDCLK, and the SYNC signals can be inverted, if desired using the INVSCLK and INVSYNC CS inputs, respectively. Depending on the input, RDC, the data can be read during the following conversion or after each conver- RD sion. Figure 39 and Figure 40 show detailed timing diagrams of these two modes. BYTESWAP Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) HI-Z HI-Z Setting RDC = low, allows the read after conversion mode. HIGH BYTE LOW BYTE PINS D[15:8] Since the AD7610 is limited to 250kSPS and the time between t t t 12 12 13 conversions, t2 = 4μs, this mode is the most recommended HI-Z HI-Z PINS D[7:0] LOW BYTE HIGH BYTE serial mode. Unlike the other serial modes, the BUSY signal returns low after the 16 data bits are pulsed out and not at the Figure 38. 8-Bit and 16-Bit Parallel Interface end of the conversion phase, resulting in a longer BUSY width SERIAL INTERFACE (See Table 4 for BUSY timing specifications). The The AD7610 has a serial interface (SPI-compatible) multiplexed DIVSCLK[1:0] inputs control the SDCLK period and SDOUT on the data pins D[15:2]. The AD7610 is configured to use the data rate. As a result, the maximum throughput can only be PAR serial interface when SER/ is held high. achieved in two of the DIVSCLK[1:0] settings. In this mode, the Data Interface AD7610 generates a discontinuous SDCLK however, a fixed The AD7610 outputs 16 bits of data, MSB first, on the SDOUT pin. period and hosts supporting both SPI and serial ports can also This data is synchronized with the 16 clock pulses provided on be used. the SDCLK pin. The output data is valid on both the rising and Read During Convert (RDC = High) falling edge of the data clock. Setting RDC = high, allows the master read (previous conver- Serial Configuration Interface sion result) during conversion mode. In this mode, the serial The AD7610 can be configured through the serial configuration clock and data toggle at appropriate instances, minimizing register only in serial mode as the serial configuration pins are potential feed through between digital activity and critical also multiplexed on the data pins D[15:12]. See the Hardware conversion decisions. In this mode, the SDCLK period changes Configuration section and Software Configuration section for since the LSBs require more time to settle and the SDCLK is more information. derived from the SAR conver-sion cycle. In this mode, the AD7610 generates a discontinuous SDCLK of two different periods and the host should use an SPI interface. Rev. 0 | Page 24 of 32 06395-038 AD7610 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 EXT/INT = 0 CS, RD t 3 CNVST BUSY t 28 t 30 t 29 t 25 SYNC t t 14 18 t 19 t 24 t t 20 21 t 26 12 3 14 15 16 SDCLK t 15 t 27 SDOUT D15 D14 D2 D1 D0 X t t 16 23 t 22 Figure 39. Master Serial Data Timing for Reading (Read After Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t 14 t 19 t t 20 21 t 24 t 26 t 15 SDCLK 12 3 14 15 16 t 18 t 27 SDOUT X D15 D14 D2 D1 D0 t 16 t 23 t 22 Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 25 of 32 06395-040 06395-039 AD7610 CNVST SLAVE SERIAL INTERFACE signal. Note that the SDIN input is latched on the opposite edge of SDCLK used to shift out the data on SDOUT (SDCLK The pins multiplexed on D[11:4] used for slave serial interface are: falling edge when INVSCLK = low). Therefore, the MSB of the EXT/INT, INVSCLK, SDIN, SDOUT, SDCLK and RDERROR. upstream converter follows the LSB of the down-stream converter PAR INT External Clock (SER/ = High, EXT/ = High) on the next SDCLK cycle. In this mode, the 40 MHz SDCLK INT rate cannot be used since the SDIN to SDCLK setup time, t33, is Setting the EXT/ = high allows the AD7610 to accept an less than the minimum time specified. (SDCLK to SDOUT delay, externally supplied serial data clock on the SDCLK pin. In this t , is the same for all converters when simultaneously sampled). 32 mode, several methods can be used to read the data. The external For proper operation, the SDCLK edge for latching SDIN (or ½ serial clock is gated by CS. When CS and RD are both low, the period of SDCLK) needs to be: data can be read after each conversion or during the following conversion. A clock can be either normally high or normally low t = t + t 1/ 2SDCLK 32 33 when inactive. For detailed timing diagrams, see Figure 42 and Or the max SDCLK frequency needs to be: Figure 43. 1 f = While the AD7610 is performing a bit decision, it is important SDCLK 2(t + t ) 32 33 that voltage transients be avoided on digital input/output pins, If not using the daisy-chain feature, the SDIN input should be or degradation of the conversion result may occur. This is par- tied either high or low. ticularly important during the last 475 ns of the conversion phase because the AD7610 provides error correction circuitry that can BUSY OUT correct for an improper bit decision made during the first part of the conversion phase. For this reason, it is recommended that BUSY BUSY any external clock provided, is a discontinuous clock that transi- AD7610 AD7610 #2 #1 tions only when BUSY is low, or, more importantly, that it does (UPSTREAM) (DOWNSTREAM) DATA not transition during the last 475 ns of BUSY high. RDC/SDIN SDOUT RDC/SDIN SDOUT OUT External Discontinuous Clock Data Read After CNVST CNVST Conversion CS CS Since the AD7610 is limited to 250 kSPS, the time between con- SCLK SCLK versions, t4 = 4 μs, and the conversion time, t7 = 1.45 μs. This makes the read after conversion mode the most recommended SCLK IN CS IN serial slave mode since the time to read the data is t4 − t7. Figure 42 CNVST IN shows the detailed timing diagrams for this method. After a Figure 41. Two AD7610 Devices in a Daisy-Chain Configuration conversion is complete, indicated by BUSY returning low, the External Clock Data Read During Previous Conversion CS RD conversion result can be read while both and are low. Data is shifted out MSB first with 16 clock pulses and, depending Figure 43 shows the detailed timing diagrams for this method. on the SDCLK frequency, can be valid on the falling and rising During a conversion, while both CS and RD are low, the result edges of the clock. of the previous conversion can be read. The data is shifted out, MSB first, with 16 clock pulses, and is valid on both the rising One advantage of this method is that conversion performance is and falling edge of the clock. The 16 bits have to be read before not degraded because there are no voltage transients on the digital the current conversion is complete; otherwise, RDERROR is interface during the conversion process. Another advantage is pulsed high and can be used to interrupt the host interface to the ability to read the data at any speed up to 40 MHz, which prevent incomplete data reading. accommodates both the slow digital host interface and the fastest serial reading. To reduce performance degradation due to digital activity, a fast discontinuous clock of at least 40 MHz is recommended to ensure Daisy-Chain Feature that all the bits are read during the first half of the SAR Also in the read after convert mode, the AD7610 provides a daisy- conversion phase. chain feature for cascading multiple converters together using the serial data input, SDIN, pin. This feature is useful for reducing The daisy-chain feature should not be used in this mode since component count and wiring connections when desired, for digital activity occurs during the second half of the SAR instance, in isolated multiconverter applications. See Figure 42 conversion phase likely resulting in performance degradation. for the timing details. An example of the concatenation of two devices is shown in Figure 41. Simultaneous sampling is possible by using a common Rev. 0 | Page 26 of 32 06395-041 AD7610 discontinuous SDCLK whenever possible to minimize potential External Clock Data Read After/During Conversion incorrect bit decisions. For the different modes, the use of a slower It is also possible to begin to read data after conversion and SDCLK such as 20 MHz in warp mode, 15 MHz in normal mode continue to read the last bits after a new conversion has been and 13 MHz in impulse mode can be used. initiated. This method allows the full throughput and the use of a slower SDCLK frequency. Again, it is recommended to use a SER/PAR = 1 EXT/INT = 1 INVSCLK = 0 RD = 0 CS BUSY t t t t 31 35 36 31 SDCLK X* 1 2 3 4 14 15 16 17 18 19 t 32 t 37 SDOUT D15 D14 D13 D2 D1 D0 X15 X14 t 16 SDIN X15 X14 X13 X2 X1 X0 Y15 Y14 t t 33 34 *A DISCONTINUOUS SDCLK IS RECOMMENDED. Figure 42. Slave Serial Data Timing for Reading (Read After Convert) SER/PAR = 1 EXT/INT = 1 INVSCLK = 0 RD = 0 CS CNVST BUSY t t t t 31 35 36 31 SDCLK X* X* X* X* X* X* 12 3 15 16 t 32 t 37 SDOUT D15 D14 D1 D0 DATA = SDIN t t 16 27 *A DISCONTINUOUS SDCLK IS RECOMMENDED. Figure 43. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 27 of 32 06395-043 06395-042 AD7610 attainable because the time required for SCP access is (t + 9 × 1/ HARDWARE CONFIGURATION 31 SCCLK +t ) minimum. If the full throughput is required, the 8 The AD7610 can be configured at any time with the dedicated SCP can be written to during conversion, however it is not hardware pins BIPOLAR, TEN, OB/2C, and PD for parallel mode recommended to write to the SCP during the last 475 ns of PAR PAR (SER/ = low) or serial hardware mode (SER/ = high, conversion (BUSY = high) or performance degradation can SW HW/ = high). Programming the AD7610 for input range result. In addition, the SCP can be accessed in both serial configuration can be done before or during conversion. Like master and serial slave read during and read after convert modes. the RESET input, the ADC requires at least one acquisition Note that at power up, the configuration register is undefined. time to settle as indicated in Figure 44. See Table 6 for pin descrip- The RESET input clears the configuration register (sets all bits tions. Note that these inputs are high impedance when using to 0), thus placing the configuration to 0 V to 5 V input, normal the software configuration mode. mode, and twos complemented output. SOFTWARE CONFIGURATION Table 9. Configuration Register Description The pins multiplexed on D[15:12] used for software configu- Bit Name Description ration are: HW/SW, SCIN, SCCLK, and SCCS. The AD7610 is 8 START SCCS START bit. With the SCP enabled ( = low), programmed using the dedicated write-only serial configurable when START is high, the first rising edge of SCCLK port (SCP) for conversion mode, input range selection, output (INVSCLK = low) begins to load the register with coding, and power-down using the serial configuration register. the new configuration. See Table 9 for details of each bit in the configuration register. 7 BIPOLAR Input Range Select. Used in conjunction with Bit 6, TEN, per the following: The SCP can only be used in serial software mode selected with Input Range BIPOLAR TEN PAR SW SER/ = high and HW/ = low since the port is multiplexed 0 V to 5 V Low Low on the parallel interface. 0 V to 10 V Low High The SCP is accessed by asserting the port’s chip select, SCCS, ±5 V High Low ±10 V High High and then writing SCIN synchronized with SCCLK, which (like 6 TEN Input Range Select. See Bit 7, BIPOLAR. SDCLK) is edge sensitive depending on the state of INVSCLK. 5 PD Power Down. See Figure 45 for timing details. SCIN is clocked into the con- PD = Low, normal operation. figuration register MSB first. The configuration register is an PD = High, power down the ADC. The SCP is th internal shift register that begins with Bit 8, the start bit. The 9 accessible while in power down. To power up the SPPCLK edge updates the register and allows the new settings to be ADC, write PD = low on the next configuration setting. used. As indicated in the timing diagram, at least one acquisition th 4 RSV Reserved. time is required from the 9 SCCLK edge. Bits [4:3] and [1:0] are 3 RSV Reserved. reserved bits and are not written to while the SCP is being 2 OB/2C Output Coding updated. OB/2C = Low, use twos complement output. The SCP can be written to at any time, up to 40 MHz, and it is 2C OB/ = High, use straight binary output. recommended to write to while the AD7610 is not busy convert- 1 RSV Reserved. ing, as detailed in Figure 45. In this mode, the full 750 kSPS is not 0 RSV Reserved. HW/SW = 0 PD = 0 SER/PAR = 0, 1 t t 8 8 CNVST BUSY BIPOLAR, TEN WARP, IMPULSE Figure 44. Hardware Configuration Timing Rev. 0 | Page 28 of 32 06395-044 AD7610 WARP = 0 OR 1 BIP = 0 OR 1 SER/PAR = 1 INVSCLK = 0 t IMPULSE = 0 OR 1 TEN = 0 OR 1 HW/SW = 0 PD = 0 8 CNVST BUSY t 31 SCCS t 31 t t 35 36 SCCLK 123 4 5 67 89 t 37 SCIN X BIPOLAR TEN PD X X OB/2C START X t 33 t 34 Figure 45. Serial Configuration Port Timing The reading process can be initiated in response to the end-of- MICROPROCESSOR INTERFACING conversion signal (BUSY going low) using an interrupt line of The AD7610 is ideally suited for traditional dc measurement appli- the DSP. The serial peripheral interface (SPI) on the ADSP-219x cations supporting a microprocessor, and ac signal processing is configured for master mode (MSTR) = 1, clock polarity bit applications interfacing to a digital signal processor. The AD7610 is (CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable designed to interface with a parallel 8-bit or 16-bit wide inter- (TIMOD) = 0 by writing to the SPI control register (SPICLTx). face, or with a general-purpose serial port or I/O ports on a micro- controller. A variety of external buffers can be used with the It should be noted that to meet all timing requirements, the SPI AD7610 to prevent digital noise from coupling into the ADC. clock should be limited to 17 Mbps allowing it to read an ADC result in less than 1 μs. When a higher sampling rate is desired, SPI Interface use one of the parallel interface modes. The AD7610 is compatible with SPI and QSPI digital hosts DVDD and DSPs such as Blackfin® ADSP-BF53x and ADSP-218x/ AD7610* ADSP-219x* ADSP-219x. Figure 46 shows an interface diagram between the SER/PAR AD7610 and the SPI-equipped ADSP-219x. To accommodate BUSY PFx EXT/INT the slower speed of the DSP, the AD7610 acts as a slave device, and CS SPIxSEL (PFx) SDOUT MISOx data must be read after conversion. This mode also allows the RD SCLK SCKx daisy-chain feature. The convert command could be initiated CNVST PFx OR TFSx INVSCLK in response to an internal timer interrupt. *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 46. Interfacing the AD7610 to SPI Interface Rev. 0 | Page 29 of 32 06395-045 06395-046 AD7610 APPLICATION INFORMATION The DVDD supply of the AD7610 can be either a separate supply LAYOUT GUIDELINES or come from the analog supply, AVDD, or from the digital While the AD7610 has very good immunity to noise on the interface supply, OVDD. When the system digital supply is noisy, power supplies, exercise care with the grounding layout. To facil- or fast switching digital signals are present, and no separate supply itate the use of ground planes that can be easily separated, design is available, it is recommended to connect the DVDD digital supply the printed circuit board that houses the AD7610 so that the to the analog supply AVDD through an RC filter, and to connect analog and digital sections are separated and confined to certain the system supply to the interface digital supply OVDD and the areas of the board. Digital and analog ground planes should be remaining digital circuitry. See Figure 27 for an example of this joined in only one place, preferably underneath the AD7610, or configuration. When DVDD is powered from the system supply, as close as possible to the AD7610. If the AD7610 is in a system it is useful to insert a bead to further reduce high frequency spikes. where multiple devices require analog-to-digital ground connect- ions, the connections should still be made at one point only, a The AD7610 has four different ground pins: REFGND, AGND, star ground point, established as close as possible to the AD7610. DGND, and OGND. To prevent coupling noise onto the die, avoid radiating noise, • REFGND senses the reference voltage and, because it carries and to reduce feedthrough: pulsed currents, should be a low impedance return to the reference. • Do not run digital lines under the device. • AGND is the ground to which most internal ADC analog • Do run the analog ground plane under the AD7610. signals are referenced; it must be connected with the least CNVST • Do shield fast switching signals, like or clocks, with resistance to the analog ground plane. digital ground to avoid radiating noise to other sections of • DGND must be tied to the analog or digital ground plane the board, and never run them near analog signal paths. depending on the configuration. • Avoid crossover of digital and analog signals. • OGND is connected to the digital system ground. • Run traces on different but close layers of the board, at right The layout of the decoupling of the reference voltage is important. angles to each other, to reduce the effect of feedthrough through To minimize parasitic inductances, place the decoupling capacitor the board. close to the ADC and connect it with short, thick traces. The power supply lines to the AD7610 should use as large a trace as EVALUATING PERFORMANCE possible to provide low impedance paths and reduce the effect of A recommended layout for the AD7610 is outlined in the EVAL- glitches on the power supply lines. Good decoupling is also AD7610CB evaluation board documentation. The evaluation important to lower the impedance of the supplies presented to board package includes a fully assembled and tested evaluation the AD7610, and to reduce the magnitude of the supply spikes. board, documentation, and software for controlling the board Decoupled ceramic capacitors, typically 100 nF, should be placed from a PC via the EVAL-CONTROL BRD3. on each of the power supplies pins, AVDD, DVDD, and OVDD, VCC, and VEE. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 μF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. Rev. 0 | Page 30 of 32 PAD AD7610 OUTLINE DIMENSIONS 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0.45 48 37 1 36 PIN 1 7.20 TOP VIEW 7.00 SQ 1.45 (PINS DOWN) 0.20 6.80 1.40 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 SEATING 0.05 0.08 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 47. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.60 MAX 0.18 PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED TOP 5.25 6.75 VIEW BSC SQ 5.10 SQ (BOTTOM VIEW) 4.95 0.50 25 12 0.40 24 13 0.30 0.25 MIN 5.50 REF PADDLE CONNECTED TO VEE. 0.80 MAX 1.00 THIS CONNECTION IS NOT 12° MAX 0.65 TYP REQUIRED TO MEET THE 0.85 0.05 MAX ELECTRICAL PERFORMANCES. 0.80 0.02 NOM COPLANARITY 0.50 BSC 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 48. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7610BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 1 AD7610BCPZ-RL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 1 AD7610BSTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 1 AD7610BSTZ-RL −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 2 EVAL-AD7610CB Evaluation Board 3 EVAL-CONTROL BRD3 Controller Board 1 Z = Pb-free part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending with the CB designators. Rev. 0 | Page 31 of 32 051706-A AD7610 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06395-0-10/06(0) Rev. 0 | Page 32 of 32