Revision 9 eX Family FPGAs FuseLock • Single-Chip Solution Leading Edge Performance • Nonvolatile • 240 MHz System Performance • Live on Power-Up • 350 MHz Internal Performance • No Power-Up/Down Sequence Required for Supply • 3.9 ns Clock-to-Out (Pad-to-Pad) Voltages • Configurable Weak-Resistor Pull-Up or Pull-Down for Tristated Outputs during Power-Up Specifications • Individual Output Slew Rate Control • 3,000 to 12,000 Available System Gates • 2.5V, 3.3V, and 5.0V Mixed-Voltage Operation with • Maximum 512 Flip-Flops (Using CC Macros) 5.0V Input Tolerance and 5.0V Drive Strength • 0.22 µm CMOS Process Technology • Software Design Support with Microsemi Designer and ® Libero Integrated Design Environment (IDE) Tools • Up to 132 User-Programmable I/O Pins • Up to 100% Resource Utilization with 100% Pin Locking • Deterministic Timing Features • Unique In-System Diagnostic and Verification Capability with Silicon Explorer II • High-Performance, Low-Power Antifuse FPGA • Boundary Scan Testing in Compliance with IEEE • LP/Sleep Mode for Additional Power Savings Standard 1149.1 (JTAG) • Advanced Small-Footprint Packages • Fuselock™ Secure Programming Technology Prevents • Hot-Swap Compliant I/Os Reverse Engineering and Design Theft Product Profile Device eX64 eX128 eX256 Capacity 3,000 6,000 12,000 System Gates 2,000 4,000 8,000 Typical Gates Register Cells Dedicated Flip-Flops 64 128 256 Maximum Flip-Flops 128 256 512 Combinatorial Cells 128 256 512 Maximum User I/Os 84 100 132 Global Clocks Hardwired 1 1 1 Routed 2 2 2 Speed Grades –F, Std, –P –F, Std, –P –F, Std, –P Temperature Grades* C, I, A C, I, A C, I, A Package (by pin count) TQFP 64, 100 64, 100 100 Note: *Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings. June 2011 I © 2011 Microsemi Corporation Ordering Information eX128 P TQ G 100 Application (Ambient Temperature Range) Blank = Commercial (0°C to 70°C) I = Industrial (-40°C to 85°C) A = Automotive (-40°C to 125°C) PP = Pre-production Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS Compliant Packaging Package Type = TQ Thin Quad Flat Pack (0.5 mm pitch) Speed Grade Blank = Standard Speed P = Approximately 30% Faster than Standard F = Approximately 40% Slower than Standard Part Number eX64 = 64 Dedicated Flip-Flops (3,000 System Gates) eX128 = 128 Dedicated Flip-Flops (6,000 System Gates) eX256 = 256 Dedicated Flip-Flops (12,000 System Gates) eX Device Status eX Devices Status eX64 Production eX128 Production eX256 Production Plastic Device Resources User I/Os (Including Clock Buffers) Device TQFP 64-Pin TQFP 100-Pin eX64 41 56 eX128 46 70 eX256 — 81 Note: TQFP = Thin Quad Flat Pack, II Revision 9 eX Family FPGAs Temperature Grade Offerings Device\Package TQFP 64-Pin TQFP 100-Pin eX64 C, I, A C, I, A eX128 C, I, A C, I, A eX256 C, I, A C, I, A Note: C = Commercial I = Industrial A = Automotive Speed Grade and Temperature Grade Matrix –F Std –P C ✓✓ ✓ I ✓✓ A ✓ Note: P = Approximately 30% faster than Standard –F = Approximately 40% slower than Standard Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings. Contact your local Microsemi representative for device availability. Revision 9 III eX Family FPGAs Table of Contents eX FPGA Architecture and Characteristics General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 eX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 2.5 V / 3.3 V /5.0 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 2.5 V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 3.3 V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 5.0 V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 eX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 eX Family Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Package Pin Assignments 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Revision 9 IV 1 – eX FPGA Architecture and Characteristics General Description The eX family of FPGAs is a low-cost solution for low-power, high-performance designs. The inherent low power attributes of the antifuse technology, coupled with an additional low static power mode, make these devices ideal for power-sensitive applications. Fabricated with an advanced 0.22 mm CMOS antifuse technology, these devices achieve high performance with no power penalty. eX Family Architecture Microsemi's eX family is implemented on a high-voltage twin-well CMOS process using 0.22 µm design rules. The eX family architecture uses a “sea-of-modules” structure where the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. Interconnection among these logic modules is achieved using Microsemi’s patented metal-to-metal programmable antifuse interconnect elements. The antifuse interconnect is made up of a combination of amorphous silicon and dielectric material with barrier metals and has an "on" state resistance of 25Ω with a capacitance of 1.0fF for low-signal impedance. The antifuses are normally open circuit and, when programmed, form a permanent low-impedance connection. The eX family provides two types of logic modules, the register cell (R-cell) and the combinatorial cell (C-cell). The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals (Figure 1-1). The R-cell registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional flexibility while allowing mapping of synthesized functions into the eX FPGA. The clock source for the R-cell can be chosen from either the hard-wired clock or the routed clock. The C-cell implements a range of combinatorial functions up to five inputs (Figure 1-2 on page 1-2). Inclusion of the DB input and its associated inverter function enables the implementation of more than 4,000 combinatorial functions in the eX architecture in a single module. Two C-cells can be combined together to create a flip-flop to imitate an R-cell via the use of the CC macro. This is particularly useful when implementing non-timing-critical paths and when the design engineer is running out of R-cells. More information about the CC macro can be found in the Maximizing Logic Utilization in eX, SX and SX-A FPGA Devices Using CC Macros application note. Routed Data Input S1 S0 PSET DirectConnect Input DQ Y HCLK CLKA, CLR CLKB, Internal Logic CKS CKP Figure 1-1 • R-Cell Revision 9 1-1 eX FPGA Architecture and Characteristics Module Organization C-cell and R-cell logic modules are arranged into horizontal banks called Clusters, each of which contains two C-cells and one R-cell in a C-R-C configuration. Clusters are further organized into modules called SuperClusters for improved design efficiency and device performance, as shown in Figure 1-3. Each SuperCluster is a two-wide grouping of Clusters. D0 D1 Y D2 D3 Sa Sb DB A1 B1 A0 B0 Figure 1-2 • C-Cell R-Cell C-Cell Routed D0 S1 Data Input D1 S0 PSET Y D2 DirectConnect D3 Q D Y Input Sa Sb HCLK CLKA, CLR CLKB, DB Internal Logic CKS CKP A0 B0 A1 B1 Cluster Cluster SuperCluster Figure 1-3 • Cluster Organization 1-2 Revision 9 eX Family FPGAs Routing Resources Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within Clusters and SuperClusters (Figure 1-4). This routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance. DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring R-cell in a given SuperCluster. DirectConnect uses a hard-wired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns (–P speed grade). FastConnect enables horizontal routing between any two logic modules within a given SuperCluster and vertical routing with the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering maximum pin-to-pin propagation of 0.3 ns (–P speed grade). In addition to DirectConnect and FastConnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. Microsemi’s segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the fully automatic place-and- route software to minimize signal propagation delays. DirectConnect SuperClusters • No antifuses • 0.1 ns routing delay FastConnect • One antifuse • 0.5 ns routing delay Routing Segments • Typically 2 antifuses • Max. 5 antifuses Figure 1-4 • DirectConnect and FastConnect for SuperClusters Clock Resources eX’s high-drive routing structure provides three clock networks. The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in each R-Cell. HCLK cannot be connected to combinational logic. This provides a fast propagation path for the clock signal, enabling the 3.9 ns clock- to-out (pad-to-pad) performance of the eX devices. The hard-wired clock is tuned to provide a clock skew of less than 0.1 ns worst case. If not used, the HCLK pin must be tied LOW or HIGH and must not be left floating. Figure 1-5 describes the clock circuit used for the constant load HCLK. HCLK does not function until the fourth clock cycle each time the device is powered up to prevent false output levels due to any possible slow power-on-reset signal and fast start-up clock circuit. To activate HCLK from the first cycle, the TRST pin must be reserved in the Design software and the pin must be tied to GND on the board. (See the "TRST, I/O Boundary Scan Reset Pin" on page 1-31). The remaining two clocks (CLKA, CLKB) are global routed clock networks that can be sourced from external pins or from internal logic signals (via the CLKINT routed clock buffer) within the eX device. CLKA and CLKB may be connected to sequential cells or to combinational logic. If CLKA or CLKB is sourced from internal logic signals, the external clock pin cannot be used for any other input and must be tied LOW or HIGH and must not float. Figure 1-6 describes the CLKA and CLKB circuit used in eX devices. Table 1-1 describes the possible connections of the routed clock networks, CLKA and CLKB. Revision 9 1-3 eX FPGA Architecture and Characteristics Unused clock pins must not be left floating and must be tied to HIGH or LOW. Constant Load Clock Network HCLKBUF Figure 1-5 • eX HCLK Clock Pad Clock Network From Internal Logic CLKBUF CLKBUFI CLKINT CLKINTI Figure 1-6 • eX Routed Clock Buffer Table 1-1 • Connections of Routed Clock Networks, CLKA and CLKB Module Pins C-Cell A0, A1, B0 and B1 R-Cell CLKA, CLKB, S0, S1, PSET, and CLR I/O-Cell EN 1-4 Revision 9 eX Family FPGAs Other Architectural Features Performance The combination of architectural features described above enables eX devices to operate with internal clock frequencies exceeding 350 MHz for very fast execution of complex logic functions. The eX family is an optimal platform upon which the functionality previously contained in CPLDs can be integrated. eX devices meet the performance goals of gate arrays, and at the same time, present significant improvements in cost and time to market. Using timing-driven place-and-route tools, designers can achieve highly deterministic device performance. User Security The Microsemi FuseLock advantage ensures that unauthorized users will not be able to read back the contents of a Microsemi antifuse FPGA. In addition to the inherent strengths of the architecture, special security fuses that prevent internal probing and overwriting are hidden throughout the fabric of the device. They are located such that they cannot be accessed or bypassed without destroying the rest of the device, making both invasive and more-subtle noninvasive attacks ineffective against Microsemi antifuse FPGAs. Look for this symbol to ensure your valuable IP is secure. FuseLock Figure 1-7 • Fuselock For more information, refer to Actel's Implementation of Security in Actel Antifuse FPGAs application note. I/O Modules Each I/O on an eX device can be configured as an input, an output, a tristate output, or a bidirectional pin. Even without the inclusion of dedicated I/O registers, these I/Os, in combination with array registers, can achieve clock-to-out (pad-to-pad) timing as fast as 3.9 ns. I/O cells in eX devices do not contain embedded latches or flip-flops and can be inferred directly from HDL code. The device can easily interface with any other device in the system, which in turn enables parallel design of system components and reduces overall design time. All unused I/Os are configured as tristate outputs by Microsemi's Designer software, for maximum flexibility when designing new boards or migrating existing designs. Each I/O module has an available pull-up or pull-down resistor of approximately 50 kΩ that can configure the I/O in a known state during power-up. Just shortly before V reaches 2.5 V, the resistors are disabled and the I/Os will be CCA controlled by user logic. Table 1-2 describes the I/O features of eX devices. For more information on I/Os, refer to Actel eX, SX-A, and RT54SX-S I/Os application note. The eX family supports mixed-voltage operation and is designed to tolerate 5.0 V inputs in each case. A detailed description of the I/O pins in eX devices can be found in "Pin Description" on page 1-30. Hot-Swapping eX I/Os are configured to be hot-swappable. During power-up/down (or partial up/down), all I/Os are tristated, provided V ramps up within a diode drop of V . V and V do not have to be stable CCA CCI CCA CCI during power-up/down, and they do not require a specific power-up or power-down sequence in order to avoid damage to the eX devices. In addition, all outputs can be programmed to have a weak resistor pull- Revision 9 1-5 eX FPGA Architecture and Characteristics Table 1-2 • I/O Features Function Description Input Buffer Threshold • 5.0V TTL Selection • 3.3V LVTTL • 2.5V LVCMOS2 Nominal Output Drive • 5.0V TTL/CMOS • 3.3V LVTTL • 2.5V LVCMOS 2 Output Buffer “Hot-Swap” Capability • I/O on an unpowered device does not sink current • Can be used for “cold sparing” Selectable on an individual I/O basis Individually selectable low-slew option Power-Up Individually selectable pull ups and pull downs during power-up (default is to power up in tristate) Enables deterministic power-up of device V and V can be powered in any order CCA CCI up or pull-down for output tristate at power-up. After the eX device is plugged into an electrically active system, the device will not degrade the reliability of or cause damage to the host system. The device's output pins are driven to a high impedance state until normal chip operating conditions are reached. Please see the application note, Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications, which also applies to the eX devices, for more information on hot swapping. Power Requirements Power consumption is extremely low for the eX family due to the low capacitance of the antifuse interconnects. The antifuse architecture does not require active circuitry to hold a charge (as do SRAM or EPROM), making it the lowest-power FPGA architecture available today. Low Power Mode The eX family has been designed with a Low Power Mode. This feature, activated with setting the special LP pin to HIGH for a period longer than 800 ns, is particularly useful for battery-operated systems where battery life is a primary concern. In this mode, the core of the device is turned off and the device consumes minimal power with low standby current. In addition, all input buffers are turned off, and all outputs and bidirectional buffers are tristated when the device enters this mode. Since the core of the device is turned off, the states of the registers are lost. The device must be re-initialized when returning to normal operating mode. I/Os can be driven during LP mode. For details, refer to the Design for Low Power in Actel Antifuse FPGAs application note under the section Using the LP Mode Pin on eX Devices. Clock pins should be driven either HIGH or LOW and should not float; otherwise, they will draw current and burn power. The device must be re-initialized when exiting LP mode. To exit the LP mode, the LP pin must be driven LOW for over 200µs to allow for the charge pumps to power-up and device initialization can begin. Table 1-3 illustrates the standby current of eX devices in LP mode. Table 1-3 • Standby Power of eX Devices in LP Mode Typical Conditions, V , V = 2.5 V, T = 25° C CCA CCI J Product Low Power Standby Current Units eX64 100 µA eX128 111 µA eX256 134 µA 1-6 Revision 9 eX Family FPGAs Figure 1-8 to Figure 1-11 on page 1-8 show some sample power characteristics of eX devices. Notes: 1. Device filled with 16-bit counters. 2. VCCA, VCCI = 2.7 V, device tested at room temperature. Figure 1-8 • eX Dynamic Power Consumption – High Frequency Notes: 1. Device filled with 16-bit counters. 2. VCCA, VCCI = 2.7 V, device tested at room temperature. Figure 1-9 • eX Dynamic Power Consumption – Low Frequency Revision 9 1-7 eX FPGA Architecture and Characteristics Figure 1-10 • Total Dynamic Power (mW) Figure 1-11 • System Power at 5%, 10%, and 15% Duty Cycle 1-8 Revision 9 eX Family FPGAs Boundary Scan Testing (BST) All eX devices are IEEE 1149.1 compliant. eX devices offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. These functions are controlled through the special test pins (TMS, TDI, TCK, TDO and TRST). The functionality of each pin is defined by two available modes: Dedicated and Flexible, and is described in Table 1-4. In the dedicated test mode, TCK, TDI, and TDO are dedicated pins and cannot be used as regular I/Os. In flexible mode (default mode), TMS should be set HIGH through a pull-up resistor of 10 kΩ. TMS can be pulled LOW to initiate the test sequence. Table 1-4 • Boundary Scan Pin Functionality Dedicated Test Mode Flexible Mode TCK, TDI, TDO are dedicated BST pins TCK, TDI, TDO are flexible and may be used as I/Os No need for pull-up resistor for TMS and TDI Use a pull-up resistor of 10 kΩ on TMS Dedicated Test Mode In Dedicated mode, all JTAG pins are reserved for BST; designers cannot use them as regular I/Os. An internal pull-up resistor is automatically enabled on both TMS and TDI pins, and the TMS pin will function as defined in the IEEE 1149.1 (JTAG) specification. To select Dedicated mode, users need to reserve the JTAG pins in Microsemi's Designer software by checking the Reserve JTAG box in the Device Selection Wizard (Figure 1-12). JTAG pins comply with LVTTL/TTL I/O specification regardless of whether they are used as a user I/O or a JTAG I/O. Refer to the "3.3 V LVTTL Electrical Specifications" section and "5.0 V TTL Electrical Specifications" section on page 1-17 for detailed specifications. Figure 1-12 • Device Selection Wizard Flexible Mode In Flexible Mode, TDI, TCK and TDO may be used as either user I/Os or as JTAG input pins. The internal resistors on the TMS and TDI pins are disabled in flexible JTAG mode, and an external 10 kΩ pull- resistor to V is required on the TMS pin. CCI To select the Flexible mode, users need to clear the check box for Reserve JTAG in the Device Selection Wizard in Microsemi's Designer software. The functionality of TDI, TCK, and TDO pins is controlled by the BST TAP controller. The TAP controller receives two control inputs, TMS and TCK. Upon power-up, the TAP controller enters the Test-Logic-Reset state. In this state, TDI, TCK, and TDO function as user I/Os. The TDI, TCK, and TDO pins are transformed from user I/Os into BST pins when the TMS pin is LOW at the first rising edge of TCK. The TDI, TCK, and TDO pins return to user I/Os when TMS is held HIGH for at least five TCK cycles. Revision 9 1-9 eX FPGA Architecture and Characteristics Table 1-5 describes the different configuration requirements of BST pins and their functionality in different modes. Table 1-5 • Boundary-Scan Pin Configurations and Functions Mode Designer "Reserve JTAG" Selection TAP Controller State Dedicated (JTAG) Checked Any Flexible (User I/O) Unchecked Test-Logic-Reset Flexible (JTAG) Unchecked Any EXCEPT Test-Logic-Reset TRST Pin The TRST pin functions as a dedicated Boundary-Scan Reset pin when the Reserve JTAG Test Reset option is selected, as shown in Figure 1-12. An internal pull-up resistor is permanently enabled on the TRST pin in this mode. It is recommended to connect this pin to GND in normal operation to keep the JTAG state controller in the Test-Logic-Reset state. When JTAG is being used, it can be left floating or be driven HIGH. When the Reserve JTAG Test Reset option is not selected, this pin will function as a regular I/O. If unused as an I/O in the design, it will be configured as a tristated output. JTAG Instructions Table 1-6 lists the supported instructions with the corresponding IR codes for eX devices. Table 1-6 • JTAG Instruction Code Instructions (IR4: IR0) Binary Code EXTEST 00000 SAMPLE / PRELOAD 00001 INTEST 00010 USERCODE 00011 IDCODE 00100 HIGHZ 01110 CLAMP 01111 Diagnostic 10000 BYPASS 11111 Reserved All others 1-10 Revision 9 eX Family FPGAs Table 1-7 lists the codes returned after executing the IDCODE instruction for eX devices. Note that bit 0 is always "1." Bits 11-1 are always "02F", which is Microsemi SoC Products Group's (formerly Actel) manufacturer code. Table 1-7 • IDCODE for eX Devices Device Revision Bits 31-28 Bits 27-12 eX64 0 8 40B2, 42B2 eX128 0 9 40B0, 42B0 eX256 0 9 40B5, 42B5 eX64 1 A 40B2, 42B2 eX128 1 B 40B0, 42B0 eX256 1 B 40B5, 42B5 Programming Device programming is supported through Silicon Sculptor series of programmers. In particular, Silicon Sculptor II is a compact, robust, single-site and multi-site device programmer for the PC. With standalone software, Silicon Sculptor II allows concurrent programming of multiple units from the same PC, ensuring the fastest programming times possible. Each fuse is subsequently verified by Silicon Sculptor II to insure correct programming. In addition, integrity tests ensure that no extra fuses are programmed. Silicon Sculptor II also provides extensive hardware self-testing capability. The procedure for programming an eX device using Silicon Sculptor II is as follows: 1. Load the *.AFM file 2. Select the device to be programmed 3. Begin programming When the design is ready to go to production, Microsemi offers device volume-programming services either through distribution partners or via in-house programming from the factory. For more details on programming eX devices, please refer to the Programming Antifuse Devices application note and the Silicon Sculptor II User's Guide. Probing Capabilities eX devices provide internal probing capability that is accessed with the JTAG pins. The Silicon Explorer II Diagnostic hardware is used to control the TDI, TCK, TMS and TDO pins to select the desired nets for debugging. The user simply assigns the selected internal nets in the Silicon Explorer II software to the PRA/PRB output pins for observation. Probing functionality is activated when the BST pins are in JTAG mode and the TRST pin is driven HIGH or left floating. If the TRST pin is held LOW, the TAP controller will remain in the Test-Logic-Reset state so no probing can be performed. The Silicon Explorer II automatically places the device into JTAG mode, but the user must drive the TRST pin HIGH or allow the internal pull-up resistor to pull TRST HIGH. When you select the Reserve Probe Pin box, as shown in Figure 1-12 on page 1-9, the layout tool reserves the PRA and PRB pins as dedicated outputs for probing. This reserve option is merely a guideline. If the Layout tool requires that the PRA and PRB pins be user I/Os to achieve successful layout, the tool will use these pins for user I/Os. If you assign user I/Os to the PRA and PRB pins and select the Reserve Probe Pin option, Designer Layout will override the "Reserve Probe Pin" option and place your user I/Os on those pins. To allow for probing capabilities, the security fuse must not be programmed. Programming the security fuse will disable the probe circuitry. Table1-8 on page1-12 summarizes the possible device configurations for probing once the device leaves the Test-Logic-Reset JTAG state. Revision 9 1-11 eX FPGA Architecture and Characteristics Silicon Explorer II Probe Silicon Explorer II is an integrated hardware and software solution that, in conjunction with Microsemi’s Designer software tools, allow users to examine any of the internal nets of the device while it is operating in a prototype or a production system. The user can probe into an eX device via the PRA and PRB pins without changing the placement and routing of the design and without using any additional resources. Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle. Silicon Explorer II does not require re-layout or additional MUXes to bring signals out to an external pin, which is necessary when using programmable logic devices from other suppliers. Silicon Explorer II samples data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds. The Silicon Explorer II tool uses the boundary scan ports (TDI, TCK, TMS and TDO) to select the desired nets for verification. The selected internal nets are assigned to the PRA/PRB pins for observation. Figure 1-13 on page 1-13 illustrates the interconnection between Silicon Explorer II and the eX device to perform in-circuit verification. Design Considerations The TDI, TCK, TDO, PRA, and PRB pins should not be used as input or bidirectional ports. Since these pins are active during probing, critical signals input through these pins are not available while probing. In addition, the Security Fuse should not be programmed because doing so disables the probe circuitry. It is recommended to use a series 70Ω termination resistor on every probe connector (TDI, TCK, TMS, TDO, PRA, PRB). The 70Ω series termination is used to prevent data transmission corruption during probing and reading back the checksum. Table 1-8 • Device Configuration Options for Probe Capability (TRST pin reserved) Security Fuse 1 2 2 JTAG Mode TRST Programmed PRA, PRB TDI, TCK, TDO 3 Dedicated LOW No User I/O Probing Unavailable 3 3 Flexible LOW No User I/O User I/O Dedicated HIGH No Probe Circuit Outputs Probe Circuit Inputs Flexible HIGH No Probe Circuit Outputs Probe Circuit Inputs – – Yes Probe Circuit Secured Probe Circuit Secured Notes: 1. If TRST pin is not reserved, the device behaves according to TRST = HIGH in the table. 2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input signals will not pass through these pins and may cause contention. 3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by Microsemi’s Designer software. 1-12 Revision 9 eX Family FPGAs 16 Pin Connection eX FPGAs TDI TCK Serial TMS Silicon Explorer II Connection TDO PRA PRB 22 Pin Connection Additional 16 Channels (Logic Analyzer) Figure 1-13 • Silicon Explorer II Probe Setup Development Tool Support The eX family of FPGAs is fully supported by both Libero® Integrated Design Environment and Designer FPGA Development software. Libero IDE is a design management environment that streamlines the design flow. Libero IDE provides an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes ® ® ® Synplify for Microsemi from Synplicity , ViewDraw for Microsemi from Mentor Graphics, ModelSim ® HDL Simulator from Mentor Graphics , WaveFormer Lite™ from SynaptiCAD™, and Designer software from Microsemi. Refer to the Libero IDE flow (located on Microsemi SoC Product Group’s website) diagram for more information. Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes timing-driven place-and-route, and a world-class integrated static timing analyzer and constraints editor. With the Designer software, a user can lock his/her design pins before layout while minimally impacting the results of place-and-route. Additionally, the back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Microsemi’s integrated verification and logic analysis tool. Another tool included in the Designer software is the SmartGen core generator, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Microsemi's Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. Revision 9 1-13 eX FPGA Architecture and Characteristics Related Documents Datasheet eX Automotive Family FPGAs http://www.actel.com/documents/eX_Auto_DS.pdf Application Notes Maximizing Logic Utilization in eX, SX and SX-A FPGA Devices Using CC Macros http://www.actel.com/documents/CC_Macro_AN.pdf Actel's Implementation of Security in Actel Antifuse FPGAs http://www.actel.com/documents/Antifuse_Security_AN.pdf Actel eX, SX-A, and RT54SX-S I/Os http://www.actel.com/documents/antifuseIO_AN.pdf Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications http://www.actel.com/documents/HotSwapColdSparing_AN.pdf Design For Low Power in Actel Antifuse FPGAs http://www.actel.com/documents/Low_Power_AN.pdf Programming Antifuse Devices http://www.actel.com/documents/AntifuseProgram_AN.pdf User Guides Silicon Sculptor II User's Guide http://www.actel.com/documents/SiliSculptII_Sculpt3_ug.pdf Miscellaneous Libero IDE flow http://www.actel.com/products/tools/libero/flow.html 1-14 Revision 9 eX Family FPGAs 2.5 V / 3.3 V /5.0 V Operating Conditions Table 1-9 • Absolute Maximum Ratings* Symbol Parameter Limits Units VCCI DC Supply Voltage for I/Os –0.3 to +6.0 V VCCA DC Supply Voltage for Array –0.3 to +3.0 V VI Input Voltage –0.5 to +5.75 V VO Output Voltage –0.5 to +V V CCI T Storage Temperature –65 to +150 °C STG Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 1-10 • Recommended Operating Conditions Parameter Commercial Industrial Units Temperature Range* 0 to +70 –40 to +85 °C 2.5V Power Supply Range (VCCA, VCCI) 2.3 to 2.7 2.3 to 2.7 V 3.3V Power Supply Range (VCCI) 3.0 to 3.6 3.0 to 3.6 V 5.0V Power Supply Range (VCCI) 4.75 to 5.25 4.75 to 5.25 V Note: *Ambient temperature (T ). A Table 1-11 • Typical eX Standby Current at 25°C VCCA= 2.5 V VCCA = 2.5 V VCCA = 2.5 V Product VCCI = 2.5 V VCCI = 3.3 V VCCI = 5.0 V eX64 397 µA 497 µA 700 µA eX128 696 µA 795 µA 1,000 µA eX256 698 µA 796 µA 2,000 µA Revision 9 1-15 eX FPGA Architecture and Characteristics 2.5 V LVCMOS2 Electrical Specifications Commercial Industrial Symbol Parameter Min. Max. Min. Max. Units VOH VCCI = MIN, VI = VIH or VIL (IOH = –100 mA) 2.1 2.1 V VCCI = MIN, VI = VIH or VIL (IOH = –1 mA) 2.0 2.0 V VCCI = MIN, VI = VIH or VIL (IOH = –2 mA) 1.7 1.7 V VOL VCCI = MIN, VI = VIH or VIL (IOL = 100 mA) 0.2 0.2 V VCCI = MIN, VI = VIH or VIL (IOL = 1mA) 0.4 0.4 V VCCI = MIN,VI = VIH or VIL (IOL = 2 mA) 0.7 0.7 V VIL Input Low Voltage, VOUT ≤ VOL (max.) –0.3 0.7 -0.3 0.7 V VIH Input High Voltage, VOUT ≥ VOH (min.) 1.7 VCCI + 0.3 1.7 VCCI + 0.3 V IIL/ IIH Input Leakage Current, VIN = VCCI or –10 10 –10 10 µA GND IOZ 3-State Output Leakage Current, –10 10 –10 10 µA VOUT = VCCI or GND t , t Input Transition Time 10 10 ns R F1,2 C I/O Capacitance 10 10 pF IO 3,4 ICC Standby Current 1.0 3.0 mA IV Curve Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html. Notes: 1. t is the transition time from 0.7 V to 1.7 V. R 2. t is the transition time from 1.7 V to 0.7 V. F 3. I max Commercial –F = 5.0 mA CC 4. I = I + I CC CCI CCA 1-16 Revision 9 eX Family FPGAs 3.3 V LVTTL Electrical Specifications Commercial Industrial Symbol Parameter Min. Max. Min. Max. Units VOH VCCI = MIN, VI = VIH or VIL (IOH = –8 mA) 2.4 2.4 V VOL VCCI = MIN, VI = VIH or VIL (IOL = 12 mA) 0.4 0.4 V VIL Input Low Voltage 0.8 0.8 V VIH Input High Voltage 2.0 VCCI +0.5 2.0 VCCI +0.5 V IIL/ IIH Input Leakage Current, VIN=VCCI or –10 10 –10 10 µA GND IOZ 3-State Output Leakage Current, –10 10 –10 10 µA VOUT = VCCI or GND t , t Input Transition Time 10 10 ns R F1,2 C I/O Capacitance 10 10 pF IO 3,4 ICC Standby Current 1.5 10 mA IV Curve Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html. Notes: 1. t is the transition time from 0.8 V to 2.0 V. R 2. t is the transition time from 2.0 V to 0.8 V. F 3. ICC max Commercial –F = 5.0 mA 4. ICC = ICCI + ICCA 5. JTAG pins comply with LVTTL/TTL I/O specification regardless of whether they are used as a user I/O or a JTAG I/O. 5.0 V TTL Electrical Specifications Commercial Industrial Symbol Parameter Min. Max. Min. Max. Units VOH VCCI = MIN, VI = VIH or VIL (IOH = –8 mA) 2.4 2.4 V VOL VCCI = MIN, VI = VIH or VIL (IOL= 12 mA) 0.4 0.4 V VIL Input Low Voltage 0.8 0.8 V VIH Input High Voltage 2.0 VCCI +0.5 2.0 VCCI +0.5 V IIL/ IIH Input Leakage Current, VIN = VCCI or GND –10 10 –10 10 µA IOZ 3-State Output Leakage Current, –10 10 –10 10 µA VOUT = VCCI or GND t , t Input Transition Time 10 10 ns R F1,2 C I/O Capacitance 10 10 pF IO 3,4 ICC Standby Current 15 20 mA IV Curve Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html. Note: 1. t is the transition time from 0.8 V to 2.0 V. R 2. t is the transition time from 2.0 V to 0.8 V. F 3. ICC max Commercial –F=20mA 4. ICC = ICCI + ICCA 5. JTAG pins comply with LVTTL/TTL I/O specification regardless of whether they are used as a user I/O or a JTAG I/O. Revision 9 1-17 eX FPGA Architecture and Characteristics Power Dissipation Power consumption for eX devices can be divided into two components: static and dynamic. Static Power Component The power due to standby current is typically a small component of the overall power. Typical standby current for eX devices is listed in the Table 1-11 on page 1-15. For example, the typical static power for is: eX128 at 3.3 V V CCI ICC * VCCA = 795 µA x 2.5 V = 1.99 mW Dynamic Power Component Power dissipation in CMOS devices is usually dominated by the dynamic power dissipation. This component is frequency-dependent and a function of the logic and the external I/O. Dynamic power dissipation results from charging internal chip capacitance due to PC board traces and load device inputs. An additional component of the dynamic power dissipation is the totem pole current in the CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent dynamic power dissipation. 2 x F Dynamic power dissipation = CEQ * VCCA where: CEQ = Equivalent capacitance F = switching frequency Equivalent capacitance is calculated by measuring ICCA at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown below. CEQ Values for eX Devices Combinatorial modules (Ceqcm) 1.70 pF Sequential modules (Ceqsm) 1.70 pF Input buffers (Ceqi) 1.30 pF Output buffers (Ceqo) 7.40 pF Routed array clocks (Ceqcr) 1.05 pF The variable and fixed capacitance of other device components must also be taken into account when estimating the dynamic power dissipation. Table 1-12 shows the capacitance of the clock components of eX devices. Table 1-12 • Capacitance of Clock Components of eX Devices eX64 eX128 eX256 Dedicated array clock – variable (Ceqhv) 0.85 pF 0.85 pF 0.85 pF Dedicated array clock – fixed (Ceqhf) 18.00 pF 20.00 pF 25.00 pF Routed array clock A (r1) 23.00 pF 28.00 pF 35.00 pF Routed array clock B (r2) 23.00 pF 28.00 pF 35.00 pF 1-18 Revision 9 eX Family FPGAs The estimation of the dynamic power dissipation is a piece-wise linear summation of the power dissipation of each component. 2 Dynamic power dissipation = VCCA * [(m * C * fm ) + (m * C * fm ) c eqcm C Comb Modules s eqsm S Seq Modules + (n * C * fn) + (0.5 * (q1 * C * fq1) + (r1 * fq1)) + (0.5 * (q2 * C * fq2) eqi Input Buffers eqcr RCLKA eqcr 2 + (r2 * fq2)) + (0.5 * (s1 * C * fs1)+(C * fs1)) ] + V * [(p * (C + C ) RCLKB eqhv eqhf HCLK CCI eqo L * fp) ] Output Buffers where: m = Number of combinatorial cells switching at frequency fm, typically 20% of C-cells c m = Number of sequential cells switching at frequency fm, typically 20% of R-cells s n = Number of input buffers switching at frequency fn, typically number of inputs / 4 p = Number of output buffers switching at frequency fp, typically number of outputs / 4 q1 = Number of R-cells driven by routed array clock A q2 = Number of R-cells driven by routed array clock B r1 = Fixed capacitance due to routed array clock A r2 = Fixed capacitance due to routed array clock B s1 = Number of R-cells driven by dedicated array clock C = Equivalent capacitance of combinatorial modules eqcm C = Equivalent capacitance of sequential modules eqsm C = Equivalent capacitance of input buffers eqi C = Equivalent capacitance of routed array clocks eqcr C = Variable capacitance of dedicated array clock eqhv C = Fixed capacitance of dedicated array clock eqhf C = Equivalent capacitance of output buffers eqo C = Average output loading capacitance, typically 10 pF L fm = Average C-cell switching frequency, typically F/10 c fm = Average R-cell switching frequency, typically F/10 s fn = Average input buffer switching frequency, typically F/5 fp = Average output buffer switching frequency, typically F/5 fq1 = Frequency of routed clock A fq2 = Frequency of routed clock B fs1 = Frequency of dedicated array clock The eX, SX-A and RTSX-S Power Calculator can be used to estimate the total power dissipation (static and dynamic) of eX devices: http://www.actel.com/techdocs/calculators.aspx. Revision 9 1-19 eX FPGA Architecture and Characteristics Thermal Characteristics The temperature variable in the Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. EQ 1, shown below, can be used to calculate junction temperature. EQ 1 (1) Junction Temperature = ΔT + T a Where: T = Ambient Temperature a ΔT = Temperature gradient between junction (silicon) and ambient = θ * P ja P = Power θ = Junction to ambient of package. θ numbers are located in the "Package Thermal Characteristics" ja ja section below. Package Thermal Characteristics The device junction-to-case thermal characteristic is θ , and the junction-to-ambient air characteristic is jc θ . The thermal characteristics for θ are shown with two different air flow rates. θ ja ja jc is provided for reference. The maximum junction temperature is 150°C. The maximum power dissipation allowed for eX devices is a function of θ A sample calculation of the ja. absolute maximum power dissipation allowed for a TQFP 100-pin package at commercial temperature and still air is as follows: Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C7 – 0°C ------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------- Maximum Power Allowed = = = 2.39W θ (°C/W) 33.5°C/W ja θ ja 1.0 m/s 2.5 m/s Package Type Pin Count θ Still Air 200 ft/min 500 ft/min Units jc Thin Quad Flat Pack (TQFP) 64 12.0 42.4 36.3 34.0 °C/W Thin Quad Flat Pack (TQFP) 100 14.0 33.5 27.4 25.0 °C/W 1-20 Revision 9 eX Family FPGAs eX Timing Model Input Delays Internal Delays Predicted Output Delays Routing Delays Combinatorial t I/O Module = 0.3 ns I/O Module IRD1 Cell t = 0.7 ns t = 0.4 ns INYH IRD2 t = 2.6 ns t = 0.7 ns DHL PD t = 0.3 ns RD1 t = 0.7 ns RD4 t = 1.2 ns RD8 I/O Module Register Cell t = 1.9 ns ENZL DQ t t = 0.5 ns = 0.3 ns SUD RD1 t = 0.0 ns HD t = 2.6 ns DHL Routed t = 1.3 ns RCKH Clock t = 0.6 ns (100% Load) RCO I/O Module Register Cell I/O Module t = 1.3 ns t = 1.9 ns INYH ENZL t = 0.3 ns IRD1 DQ t t = 0.5 ns = 0.3 ns SUD RD1 t = 0.0 ns HD t = 2.6 ns DHL Hard-Wired Clock t = 1.1 ns t = 0.6 ns HCKH RCO Note: Values shown for eX128–P, worst-case commercial conditions (5.0 V, 35 pF Pad Load). Figure 1-14 • eX Timing Model Hardwired Clock External Setup = t + t + t – t INYH IRD1 SUD HCKH = 0.7 + 0.3 + 0.5 – 1.1 = 0.4 ns Clock-to-Out (Pad-to-Pad), typical = t + t + t + t HCKH RCO RD1 DHL = 1.1 + 0.6 + 0.3 + 2.6 = 4.6 ns Routed Clock External Setup = t + t + t – t INYH IRD2 SUD RCKH = 0.7 + 0.4 + 0.5 – 1.3= 0.3 ns Clock-to-Out (Pad-to-Pad), typical = t + t + t + t RCKH RCO RD1 DHL = 1.3+ 0.6 + 0.3 + 2.6 = 4.8 ns Revision 9 1-21 eX FPGA Architecture and Characteristics Output Buffer Delays E D PAD To AC Test Loads (shown below) TRIBUFF VCC VCC VCC In 50% 50% GND 50% 50% En En GND 50% 50% GND VOH VCC VOH Out Out 1.5 V 1.5 V 1.5 V 10% Out 1.5 V 90% VOL VOL GND t t t t t t DHL DLH ENZL ENLZ ENZH ENHZ Table 1-13 • Output Buffer Delays AC Test Loads Load 3 Load 1 Load 2 (Used to measure disable delays) (used to measure (Used to measure enable delays) propagation delay) V CC GND VCC GND To the output under test R to VCC for t R to V for t CC PLZ PZL 35 pF To the output To the output R to GND for t R to GND for t PHZ PHZ under test under test R = 1 kΩ R = 1 kΩ 35 pF 5 pF Figure 1-15 • AC Test Loads 1-22 Revision 9 eX Family FPGAs Input Buffer Delays Y PAD INBUF 3 V In 0 V 1.5 V 1.5 V VCC Out 50% 50% GND t t INY INY Table 1-14 • Input Buffer Delays C-Cell Delays S A Y B VCC S, A or B 50% 50% GND VCC 50% Out 50% GND t t PD PD Out V CC GND 50% 50% t t PD PD Table 1-15 • C-Cell Delays Revision 9 1-23 eX FPGA Architecture and Characteristics Cell Timing Characteristics D Q PRESET CLK CLR (Positive edge triggered) t HD D t t , t HP SUD HPWH t RPWH CLK , t t HPWL RPWL t RCO Q t t PRESET CLR CLR t WASYN PRESET Figure 1-16 • Flip-Flops 1-24 Revision 9 eX Family FPGAs Timing Characteristics Timing characteristics for eX devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all eX family members. Internal routing delays are device-dependent. Design dependency means actual delays are not determined until after placement and routing of the user’s design are complete. Delay values may then be determined by using the Timer utility or performing simulation with post-layout delays. Critical Nets and Typical Nets Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to six percent of the nets in a design may be designated as critical. Long Tracks Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three to five antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, no more than six percent of nets in a fully utilized device require long tracks. Long tracks contribute approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout routing delays. Timing Derating eX devices are manufactured with a CMOS process. Therefore, device performance varies according to temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. Temperature and Voltage Derating Factors Table 1-16 • Temperature and Voltage Derating Factors (Normalized to Worst-Case Commercial, T = 70°C, VCCA = 2.3V) J Junction Temperature (T ) J VCCA –55 –40 0 25 70 85 125 2.3 0.79 0.80 0.87 0.88 1.00 1.04 1.13 2.5 0.74 0.74 0.81 0.83 0.93 0.97 1.06 2.7 0.69 0.70 0.76 0.78 0.88 0.91 1.00 Revision 9 1-25 eX FPGA Architecture and Characteristics eX Family Timing Characteristics Table 1-17 • eX Family Timing Characteristics = 70°C) (Worst-Case Commercial Conditions, VCCA = 2.3 V, T J –P Speed Std Speed –F Speed Parameter Description Min. Max. Min. Max. Min. Max. Units 1 C-Cell Propagation Delays t Internal Array Module 0.7 1.0 1.4 ns PD 2 Predicted Routing Delays t FO=1 Routing Delay, DirectConnect 0.1 0.1 0.2 ns DC t FO=1 Routing Delay, FastConnect 0.3 0.5 0.7 ns FC t FO=1 Routing Delay 0.3 0.5 0.7 ns RD1 t FO=2 Routing Delay 0.4 0.6 0.8 ns RD2 t FO=3 Routing Delay 0.5 0.8 1.1 ns RD3 t FO=4 Routing Delay 0.7 1.0 1.3 ns RD4 t FO=8 Routing Delay 1.2 1.7 2.4 ns RD8 t FO=12 Routing Delay 1.7 2.5 3.5 ns RD12 R-Cell Timing t Sequential Clock-to-Q 0.6 0.9 1.3 ns RCO t Asynchronous Clear-to-Q 0.6 0.8 1.2 ns CLR t Asynchronous Preset-to-Q 0.7 0.9 1.3 ns PRESET t Flip-Flop Data Input Set-Up 0.5 0.7 1.0 ns SUD t Flip-Flop Data Input Hold 0.0 0.0 0.0 ns HD t Asynchronous Pulse Width 1.3 1.9 2.6 ns WASYN t Asynchronous Recovery Time 0.3 0.5 0.7 ns RECASYN t Asynchronous Hold Time 0.3 0.5 0.7 ns HASYN 2.5 V Input Module Propagation Delays t Input Data Pad-to-Y HIGH 0.6 0.9 1.3 ns INYH t Input Data Pad-to-Y LOW 0.8 1.1 1.5 ns INYL 3.3 V Input Module Propagation Delays t Input Data Pad-to-Y HIGH 0.7 1.0 1.4 ns INYH t Input Data Pad-to-Y LOW 0.9 1.3 1.8 ns INYL 5.0 V Input Module Propagation Delays t Input Data Pad-to-Y HIGH 0.7 1.0 1.4 ns INYH t Input Data Pad-to-Y LOW 0.9 1.3 1.8 ns INYL 2 Input Module Predicted Routing Delays t FO=1 Routing Delay 0.3 0.4 0.5 ns IRD1 t FO=2 Routing Delay 0.4 0.6 0.8 ns IRD2 t FO=3 Routing Delay 0.5 0.8 1.1 ns IRD3 t FO=4 Routing Delay 0.7 1.0 1.3 ns IRD4 t FO=8 Routing Delay 1.2 1.7 2.4 ns IRD8 t FO=12 Routing Delay 1.7 2.5 3.5 ns IRD12 Notes: 1. For dual-module macros, use t + t + t , t + t + t or t + t + t , whichever is appropriate. PD RD1 PDn RCO RD1 PDn PD1 RD1 SUD 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. 1-26 Revision 9 eX Family FPGAs Table 1-18 • eX Family Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.3 V, VCCI = 4.75 V, T = 70°C) J –P Speed Std Speed –F Speed Parameter Description Min. Max. Min. Max. Min. Max. Units Dedicated (Hard-Wired) Array Clock Networks t Input LOW to HIGH 1.1 1.6 2.3 ns HCKH (Pad to R-Cell Input) t Input HIGH to LOW 1.1 1.6 2.3 ns HCKL (Pad to R-Cell Input) t Minimum Pulse Width HIGH 1.4 2.0 2.8 ns HPWH t Minimum Pulse Width LOW 1.4 2.0 2.8 ns HPWL t Maximum Skew <0.1 <0.1 <0.1 ns HCKSW t Minimum Period 2.8 4.0 5.6 ns HP f Maximum Frequency 357 250 178 MHz HMAX Routed Array Clock Networks t Input LOW to HIGH (Light Load) 1.1 1.6 2.2 ns RCKH (Pad to R-Cell Input) MAX. t Input HIGH to LOW (Light Load) 1.0 1.4 2.0 ns RCKL (Pad to R-Cell Input) MAX. t Input LOW to HIGH (50% Load) 1.2 1.7 2.4 ns RCKH (Pad to R-Cell Input) MAX. t Input HIGH to LOW (50% Load) 1.2 1.7 2.4 ns RCKL (Pad to R-Cell Input) MAX. t Input LOW to HIGH (100% Load) 1.3 1.9 2.6 ns RCKH (Pad to R-Cell Input) MAX. t Input HIGH to LOW (100% Load) 1.3 1.9 2.6 ns RCKL (Pad to R-Cell Input) MAX. t Min. Pulse Width HIGH 1.5 2.1 3.0 ns RPWH t Min. Pulse Width LOW 1.5 2.1 3.0 ns RPWL t * Maximum Skew (Light Load) 0.2 0.3 0.4 ns RCKSW t * Maximum Skew (50% Load) 0.1 0.2 0.3 ns RCKSW t * Maximum Skew (100% Load) 0.1 0.1 0.2 ns RCKSW Note: *Clock skew improves as the clock network becomes more heavily loaded. Revision 9 1-27 eX FPGA Architecture and Characteristics Table 1-19 • eX Family Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.3V, VCCI = 2.3 V or 3.0V, T = 70°C) J ‘–P’ Speed ‘Std’ Speed ‘–F’ Speed Parameter Description Min. Max. Min. Max. Min. Max. Units Dedicated (Hard-Wired) Array Clock Networks t Input LOW to HIGH 1.1 1.6 2.3 ns HCKH (Pad to R-Cell Input) t Input HIGH to LOW 1.1 1.6 2.3 ns HCKL (Pad to R-Cell Input) t Minimum Pulse Width HIGH 1.4 2.0 2.8 ns HPWH t Minimum Pulse Width LOW 1.4 2.0 2.8 ns HPWL t Maximum Skew <0.1 <0.1 <0.1 ns HCKSW t Minimum Period 2.8 4.0 5.6 ns HP f Maximum Frequency 357 250 178 MHz HMAX Routed Array Clock Networks t Input LOW to HIGH (Light Load) 1.0 1.4 2.0 ns RCKH (Pad to R-Cell Input) MAX. t Input HIGH to LOW (Light Load) 1.0 1.4 2.0 ns RCKL (Pad to R-Cell Input) MAX. t Input LOW to HIGH (50% Load) 1.2 1.7 2.4 ns RCKH (Pad to R-Cell Input) MAX. t Input HIGH to LOW (50% Load) 1.2 1.7 2.4 ns RCKL (Pad to R-Cell Input) MAX. t Input LOW to HIGH (100% Load) 1.4 2.0 2.8 ns RCKH (Pad to R-Cell Input) MAX. t Input HIGH to LOW (100% Load) 1.4 2.0 2.8 ns RCKL (Pad to R-Cell Input) MAX. t Min. Pulse Width HIGH 1.4 2.0 2.8 ns RPWH t Min. Pulse Width LOW 1.4 2.0 2.8 ns RPWL t * Maximum Skew (Light Load) 0.2 0.3 0.4 ns RCKSW t * Maximum Skew (50% Load) 0.2 0.2 0.3 ns RCKSW t * Maximum Skew (100% Load) 0.1 0.1 0.2 ns RCKSW Note: *Clock skew improves as the clock network becomes more heavily loaded. 1-28 Revision 9 eX Family FPGAs Table 1-20 • eX Family Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.3 V, T = 70°C) J –P Speed Std Speed –F Speed Parameter Description Min. Max. Min. Max. Min. Max. Units 1 2.5 V LVCMOS Output Module Timing (VCCI = 2.3 V) t Data-to-Pad LOW to HIGH 3.3 4.7 6.6 ns DLH t Data-to-Pad HIGH to LOW 3.5 5.0 7.0 ns DHL t Data-to-Pad HIGH to LOW—Low Slew 11.6 16.6 23.2 ns DHLS t Enable-to-Pad, Z to L 2.5 3.6 5.1 ns ENZL t Enable-to-Pad Z to L—Low Slew 11.8 16.9 23.7 ns ENZLS t Enable-to-Pad, Z to H 3.4 4.9 6.9 ns ENZH t Enable-to-Pad, L to Z 2.1 3.0 4.2 ns ENLZ t Enable-to-Pad, H to Z 2.4 5.67 7.94 ns ENHZ d Delta Delay vs. Load LOW to HIGH 0.034 0.046 0.066 ns/pF TLH d Delta Delay vs. Load HIGH to LOW 0.016 0.022 0.05 ns/pF THL d Delta Delay vs. Load HIGH to LOW— 0.05 0.072 0.1 ns/pF THLS Low Slew 1 3.3 V LVTTL Output Module Timing (VCCI = 3.0 V) t Data-to-Pad LOW to HIGH 2.8 4.0 5.6 ns DLH t Data-to-Pad HIGH to LOW 2.7 3.9 5.4 ns DHL t Data-to-Pad HIGH to LOW—Low Slew 9.7 13.9 19.5 ns DHLS t Enable-to-Pad, Z to L 2.2 3.2 4.4 ns ENZL t Enable-to-Pad Z to L—Low Slew 9.7 13.9 19.6 ns ENZLS t Enable-to-Pad, Z to H 2.8 4.0 5.6 ns ENZH t Enable-to-Pad, L to Z 2.8 4.0 5.6 ns ENLZ t Enable-to-Pad, H to Z 2.6 3.8 5.3 ns ENHZ d Delta Delay vs. Load LOW to HIGH 0.02 0.03 0.046 ns/pF TLH d Delta Delay vs. Load HIGH to LOW 0.016 0.022 0.05 ns/pF THL d Delta Delay vs. Load HIGH to LOW— 0.05 0.072 0.1 ns/pF THLS Low Slew 5.0 V TTL Output Module Timing* (VCCI = 4.75 V) t Data-to-Pad LOW to HIGH 2.0 2.9 4.0 ns DLH t Data-to-Pad HIGH to LOW 2.6 3.7 5.2 ns DHL t Data-to-Pad HIGH to LOW—Low Slew 6.8 9.7 13.6 ns DHLS t Enable-to-Pad, Z to L 1.9 2.7 3.8 ns ENZL t Enable-to-Pad Z to L—Low Slew 6.8 9.8 13.7 ns ENZLS t Enable-to-Pad, Z to H 2.1 3.0 4.1 ns ENZH t Enable-to-Pad, L to Z 3.3 4.8 6.6 ns ENLZ Note: *Delays based on 35 pF loading. Revision 9 1-29 eX FPGA Architecture and Characteristics Pin Description CLKA/B Routed Clock A and B These pins are clock inputs for clock distribution networks. Input levels are compatible with standard TTL or LVTTL specifications. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. GND Ground LOW supply voltage. HCLK Dedicated (Hardwired) Array Clock This pin is the clock input for sequential modules. Input levels are compatible with standard TTL or LVTTL specifications. This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. I/O Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Based on certain configurations, input and output levels are compatible with standard TTL or LVTTL specifications. Unused I/O pins are automatically tristated by the Designer software. LP Low Power Pin Controls the low power mode of the eX devices. The device is placed in the low power mode by connecting the LP pin to logic HIGH. In low power mode, all I/Os are tristated, all input buffers are turned OFF, and the core of the device is turned OFF. To exit the low power mode, the LP pin must be set LOW. The device enters the low power mode 800 ns after the LP pin is driven to a logic HIGH. It will resume normal operation 200 μs after the LP pin is driven to a logic LOW. LP pin should not be left floating. Under normal operating condition it should be tied to GND via 10 kΩ resistor. NC No Connection This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. PRA/PRB, I/O Probe A/B The Probe pin is used to output data from any user-defined design node within the device. This diagnostic pin can be used independently or in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device. The Probe pin can be used as a user-defined I/O when verification has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. TCK, I/O Test Clock Test clock input for diagnostic probe and device programming. In flexible mode, TCK becomes active when the TMS pin is set LOW (refer to Table 1-4 on page 1-9). This pin functions as an I/O when the boundary scan state machine reaches the “logic reset” state. TDI, I/O Test Data Input Serial input for boundary scan testing and diagnostic probe. In flexible mode, TDI is active when the TMS pin is set LOW (refer to Table 1-4 on page 1-9). This pin functions as an I/O when the boundary scan state machine reaches the “logic reset” state. TDO, I/O Test Data Output Serial output for boundary scan testing. In flexible mode, TDO is active when the TMS pin is set LOW (refer to Table 1-4 on page 1-9). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. When Silicon Explorer is being used, TDO will act as an output when the "checksum" command is run. It will return to user I/O when "checksum" is complete. 1-30 Revision 9 eX Family FPGAs TMS Test Mode Select The TMS pin controls the use of the IEEE 1149.1 Boundary scan pins (TCK, TDI, TDO, TRST). In flexible mode when the TMS pin is set LOW, the TCK, TDI, and TDO pins are boundary scan pins (refer to Table 1-4 on page 1-9). Once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the “logic reset” state. At this point, the boundary scan pins will be released and will function as regular I/O pins. The “logic reset” state is reached five TCK cycles after the TMS pin is set HIGH. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications. TRST, I/O Boundary Scan Reset Pin Once it is configured as the JTAG Reset pin, the TRST pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. The TRST pin is equipped with an internal pull-up resistor. This pin functions as an I/O when the Reserve JTAG Reset Pin is not selected in the Designer software. VCCI Supply Voltage Supply voltage for I/Os. VCCA Supply Voltage Supply voltage for Array. Revision 9 1-31 2 – Package Pin Assignments 64-Pin TQFP 64 1 64-Pin TQFP Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. Package Pin Assignments 64-Pin TQFP 64-Pin TQFP eX64 eX128 eX64 eX128 Pin Number Function Function Pin Number Function Function 1GND GND 33 GND GND 2 TDI, I/O TDI, I/O 34 I/O I/O 3 I/O I/O 35 I/O I/O 4TMS TMS 36 VCCA VCCA 5GND GND 37 VCCI VCCI 6 VCCI VCCI 38 I/O I/O 7 I/O I/O 39 I/O I/O 8 I/O I/O 40 NC I/O 9NC I/O 41 NC I/O 10 NC I/O 42 I/O I/O 11 TRST, I/O TRST, I/O 43 I/O I/O 12 I/O I/O 44 VCCA VCCA 13 NC I/O 45* GND/LP GND/ LP 14 GND GND 46 GND GND 15 I/O I/O 47 I/O I/O 16 I/O I/O 48 I/O I/O 17 I/O I/O 49 I/O I/O 18 I/O I/O 50 I/O I/O 19 VCCI VCCI 51 I/O I/O 20 I/O I/O 52 VCCI VCCI 21 PRB, I/O PRB, I/O 53 I/O I/O 22 VCCA VCCA 54 I/O I/O 23 GND GND 55 CLKA CLKA 24 I/O I/O 56 CLKB CLKB 25 HCLK HCLK 57 VCCA VCCA 26 I/O I/O 58 GND GND 27 I/O I/O 59 PRA, I/O PRA, I/O 28 I/O I/O 60 I/O I/O 29 I/O I/O 61 VCCI VCCI 30 I/O I/O 62 I/O I/O 31 I/O I/O 63 I/O I/O 32 TDO, I/O TDO, I/O 64 TCK, I/O TCK, I/O Note: *Please read the LP pin descriptions for restrictions on their use. 2-2 Revision 9 eX Family FPGAs 100-Pin TQFP 100 1 100-Pin TQFP Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. Revision 9 2-3 Package Pin Assignments 100-Pin TQFP 100-Pin TQFP eX64 eX128 eX256 eX64 eX128 eX256 Pin Number Function Function Function Pin Number Function Function Function 1 GND GND GND 36 GND GND GND 2 TDI, I/O TDI, I/O TDI, I/O 37 NC NC NC 3NC NC I/O 38 I/O I/O I/O 4NC NC I/O 39 HCLK HCLK HCLK 5NC NC I/O 40 I/O I/O I/O 6 I/O I/O I/O 41 I/O I/O I/O 7 TMS TMS TMS 42 I/O I/O I/O 8 VCCI VCCI VCCI 43 I/O I/O I/O 9 GND GND GND 44 VCCI VCCI VCCI 10 NC I/O I/O 45 I/O I/O I/O 11 NC I/O I/O 46 I/O I/O I/O 12 I/O I/O I/O 47 I/O I/O I/O 13 NC I/O I/O 48 I/O I/O I/O 14 I/O I/O I/O 49 TDO, I/O TDO, I/O TDO, I/O 15 NC I/O I/O 50 NC I/O I/O 16 TRST, I/O TRST, I/O TRST, I/O 51 GND GND GND 17 NC I/O I/O 52 NC NC I/O 18 I/O I/O I/O 53 NC NC I/O 19 NC I/O I/O 54 NC NC I/O 20 VCCI VCCI VCCI 55 I/O I/O I/O 21 I/O I/O I/O 56 I/O I/O I/O 22 NC I/O I/O 57 VCCA VCCA VCCA 23 NC NC I/O 58 VCCI VCCI VCCI 24 NC NC I/O 59 NC I/O I/O 25 I/O I/O I/O 60 I/O I/O I/O 26 I/O I/O I/O 61 NC I/O I/O 27 I/O I/O I/O 62 I/O I/O I/O 28 I/O I/O I/O 63 NC I/O I/O 29 I/O I/O I/O 64 I/O I/O I/O 30 I/O I/O I/O 65 NC I/O I/O 31 I/O I/O I/O 66 I/O I/O I/O 32 I/O I/O I/O 67 VCCA VCCA VCCA 33 I/O I/O I/O 68 GND/LP GND/LP GND/LP 34 PRB, I/O PRB, I/O PRB, I/O 69 GND GND GND 35 VCCA VCCA VCCA 70 I/O I/O I/O Note: *Please read the LP pin descriptions for restrictions on their use. 2-4 Revision 9 eX Family FPGAs 100-Pin TQFP eX64 eX128 eX256 Pin Number Function Function Function 71 I/O I/O I/O 72 NC I/O I/O 73 NC NC I/O 74 NC NC I/O 75 NC NC I/O 76 NC I/O I/O 77 I/O I/O I/O 78 I/O I/O I/O 79 I/O I/O I/O 80 I/O I/O I/O 81 I/O I/O I/O 82 VCCI VCCI VCCI 83 I/O I/O I/O 84 I/O I/O I/O 85 I/O I/O I/O 86 I/O I/O I/O 87 CLKA CLKA CLKA 88 CLKB CLKB CLKB 89 NC NC NC 90 VCCA VCCA VCCA 91 GND GND GND 92 PRA, I/O PRA, I/O PRA, I/O 93 I/O I/O I/O 94 I/O I/O I/O 95 I/O I/O I/O 96 I/O I/O I/O 97 I/O I/O I/O 98 I/O I/O I/O 99 I/O I/O I/O 100 TCK, I/O TCK, I/O TCK, I/O Note: *Please read the LP pin descriptions for restrictions on their use. Revision 9 2-5 eX Family FPGAs 3 – Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Revision Changes Page Revision 9 The versioning system for datasheets has been changed. Datasheets are assigned a II (June 2011) revision number that increments each time the datasheet is revised. The "eX Device Status" table indicates the status for each device in the device family. The Chip Scale packages (CS49, CS128, CS181) are no longer offered for eX devices. N/A They have been removed from the product family information. Pin tables for CSP packages have been removed from the datasheet (SAR 32002). Revision 8 The "Ordering Information" was updated with RoHS information. The TQFP II (v4.3, June 2006) measurement was also updated. The "Dedicated Test Mode" was updated. 1-9 Note 5 was added to the "3.3 V LVTTL Electrical Specifications" and "5.0 V TTL 1-17 Electrical Specifications" tables The "LP Low Power Pin" description was updated. 1-30 Revision 7 The "eX Timing Model" was updated. 1-21 (v4.2, June 2004) v4.1 The "Development Tool Support" section was updated. 1-13 The "Package Thermal Characteristics" section was updated. 1-20 v4.0 The "Product Profile" section was updated. 1-I The "Ordering Information" section was updated. 1-II The "Temperature Grade Offerings" section is new. 1-III The "Speed Grade and Temperature Grade Matrix" section is new. 1-III The "eX FPGA Architecture and Characteristics" section was updated. 1-1 The "Clock Resources" section was updated. 1-3 Table 1-1 •Connections of Routed Clock Networks, CLKA and CLKB is new. 1-4 The "User Security" section was updated. 1-5 The "I/O Modules" section was updated. 1-5 The "Hot-Swapping" section was updated. 1-5 The "Power Requirements" section was updated. 1-6 The "Low Power Mode" section was updated. 1-6 The "Boundary Scan Testing (BST)" section was updated. 1-9 The "Dedicated Test Mode" section was updated. 1-9 The "Flexible Mode" section was updated. 1-9 Table 1-5 •Boundary-Scan Pin Configurations and Functions is new. 1-10 The "TRST Pin" section was updated. 1-10 The "Probing Capabilities" section is new. 1-11 The "Programming" section was updated. 1-11 Revision 9 3-1 Datasheet Information Revision Changes Page v4.0 The "Probing Capabilities" section was updated. 1-11 (continued) The "Silicon Explorer II Probe" section was updated. 1-12 The "Design Considerations" section was updated. 1-12 The "Development Tool Support" section was updated. 1-13 The "Absolute Maximum Ratings*" section was updated. 1-15 The "Temperature and Voltage Derating Factors" section was updated. 1-25 The "TDI, I/O Test Data Input" section was updated. 1-30 The "TDO, I/O Test Data Output" section was updated. 1-30 The "TMS Test Mode Select" section was updated. 1-31 The "TRST, I/O Boundary Scan Reset Pin" section was updated. 1-31 All VSV pins were changed to VCCA. The change affected the following pins: 64-Pin TQFP – Pin 36 100-Pin TQFP – Pin 57 49-Pin CSP – Pin D5 128-Pin CSP– Pin H11 and Pin J1 for eX256 180-Pin CSP – Pins J12 and K2 v3.0 The "Recommended Operating Conditions" section has been changed. 1-15 The "3.3 V LVTTL Electrical Specifications" section has been updated. 1-17 The "5.0 V TTL Electrical Specifications" section has been updated. 1-17 The "Total Dynamic Power (mW)" section is new. 1-8 The "System Power at 5%, 10%, and 15% Duty Cycle" section is new. 1-8 The "eX Timing Model" section has been updated. 1-21 v2.0.1 The I/O Features table, Table 1-2 on page 1-6, was updated. 1-6 The table, "Standby Power of eX Devices in LP Mode Typical Conditions, VCCA, VCCI 1-6 = 2.5 V, TJ = 25° C" section, was updated. "Typical eX Standby Current at 25°C" section is a new table. 1-15 The table in the section, "Package Thermal Characteristics" section has been updated 1-20 for the 49-Pin CSP. The "eX Timing Model" section has been updated. 1-21 The timing numbers found in, "eX Family Timing Characteristics" section have been 1-26 updated. The V pin has been added to the "Pin Description" section. 1-30 SV Please see the following pin tables for the V pin and an important footnote including 2-1, 2-3, SV the pin: "64-Pin TQFP", "100-Pin TQFP", "128-Pin CSP", and "180-Pin CSP". 2-6, 2-11 The figure, "64-Pin TQFP" section has been updated. 2-1 Advance v0.4 In the Product Profile, the Maximum User I/Os for eX64 was changed to 84. 1-I In the Product Profile table, the Maximum User I/Os for eX128 was changed to 100. 1-I 3-2 Revision 9 eX Family FPGAs Revision Changes Page Advance v0.3 The Mechanical Drawings section has been removed from the data sheet. The mechanical drawings are now contained in a separate document, “Package Characteristics and Mechanical Drawings,” available on the Actel web site. A new section describing "Clock Resources"has been added. 1-3 A new table describing "I/O Features"has been added. 1-6 The "Pin Description"section has been updated and clarified. 1-30 The original Electrical Specifications table was separated into two tables (2.5V and Page 8 3.3/5.0V). In both tables, several different currents are specified for V and V . and 9 OH OL A new table listing 2.5V low power specifications and associated power graphs were page 9 added. Pin functions for eX256 TQ100 have been added to the "100-Pin TQFP"table. 2-3 A CS49 pin drawing and pin assignment table including eX64 and eX128 pin functions page 26 have been added. A CS128 pin drawing and pin assignment table including eX64, eX128, and eX256 pin pages functions have been added. 26-27 A CS180 pin drawing and pin assignment table for eX256 pin functions have been pages 27, added. 31 Advance v0.2 The following table note was added to the eX Timing Characteristics table for pages clarification: Clock skew improves as the clock network becomes more heavily loaded. 14-15 Revision 9 3-3 Datasheet Information Datasheet Categories Categories In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "eX Device Status" table on page II, is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Production This version contains information that is considered to be final. Export Administration Regulations (EAR) The product described in this datasheet is subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. 3-4 Revision 9 Microsemi Corporation (NASDAQ: MSCC) offers the industry’s most comprehensive portfolio of semiconductor technology. Committed to solving the most critical system challenges, Microsemi’s products include high-performance, high-reliability analog and RF devices, mixed signal integrated circuits, FPGAs and customizable SoCs, and complete subsystems. Microsemi serves leading system manufacturers around the world in the defense, security, aerospace, enterprise, commercial, and industrial markets. Learn more at www.microsemi.com. Microsemmi Corporate Headquarters 2381 Morse Avenue, Irvine, CA 92614 © 2011 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Phone: 949-221-7100·Fax: 949-756-0308 Corporation. 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