ACTEL Cortex-M3
Specifications
Bit Manipulation
Integrated Instructions & Bit Banding
Debug
Optional JTAG & Serial-Wire Debug Ports, Up to 8 Breakpoints and 4 Watchpoints.
Enhanced Instructions
Hardware Divide (2-12 Cycles), Single-Cycle (32x32) Multiply, Saturated Math Support.
Interrupt Priority Levels
8 to 256 priority levels
Interrupts
Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
ISA Support
Thumb/Thumb-2
Memory Protection
Optional 8 region MPU with sub regions and background region
Performance Efficiency
2.17 CoreMark/MHz - 1.25 DMIPS/MHz
Pipeline
3-stage
Sleep Modes
Sleep & Deep Sleep Signals, Optional Retention Mode with ARM Power Management Kit
Trace
Optional Instruction Trace (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)
Wake-up Interrupt Controller
Up to 240 Wake-up Interrupts, Integrated WFI and WFE Instructions and Sleep On Exit capability
Features
- Ability to extend power savings to other system components
- ARM7 levels of performance with thumb-level code density
- ARMv7-M architecture, optimized for microcontroller and low-cost applications
- Atomic bit manipulation with bit banding
- Atomic operation, cannot be interrupted by other bus activities
- Continuous storage of data requiring different byte lengths
- Data access in a single core access cycle
- Data watch point and trace unit (DWT) Implements hardware breakpoints and provides instruction execution statistics
- Dedicated space for vendor specific address ability
- Direct access to single bits of data
- Enhanced levels of performance, energy efficiency, and code density
- Flash patch and break point unit (FPB) that implements 6 program breakpoints and 2 literal data fetch breakpoints
- Hardware single-cycle multiply and hardware divide instructions
- Hierarchical structure with tightly integrated peripherals
- Integrated sleep modes
- Memory protection unit (MPU)-Optional component for separation of processing tasks and data protection, Up to 8 regions of protection; each of which can be divided into 8 sub-regions, Region sizes fro
- Mixed mode capability implies no need to inter-work between modes
- Pre-configured memory map
- Predefined addresses for code, memory, external devices, peripherals
- Sleep Now mode for immediate transfer to low-power state
- Sleep on Exit mode for entry into low-power state after the servicing of an interrupt
- Supported by a full range of development tools
- Trace port interface unit (TPIU) configured to support instrumentation trace macrocell (ITM) debug trace only
- Two 1 MB bit banding regions for memory and peripherals mapping to 32 MB alias regions
- Unaligned data storage and access
- Up to 4 gigabytes of addressable memory space
Frequently asked questions
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Why buy from GID?

Quality
We are industry veterans who take pride in our work

Protection
Avoid the dangers of risky trading in the gray market

Access
Our network of suppliers is ready and at your disposal

Savings
Maintain legacy systems to prevent costly downtime

Speed
Time is of the essence, and we are respectful of yours
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