CoreTimer Supported Device Families Product Summary Fusion IGLOO™ Intended Use IGLOOe Intended for Use in an Advanced Microcontroller Bus ® ProASIC 3L Architecture (AMBA)–Based Subsystem to Provide Timing Functionality ProASIC3 ProASIC3E Key Features Synthesis and Simulation Support Optimized for Use with CoreMP7 and Cortex-M1 ® Configurable 16-Bit or 32-Bit TimerSupported in the Actel Libero Integrated Design Environment (IDE) Runs from the Advanced Peripheral Bus (APB) Clock (PCLK) – No Additional Clock Required Prescale Provides Clock Division by up to 1,024 Verification and Compliance Continuous or One-Shot Mode Compliant with AMBA Interrupt Generation Contents Supplied in SysBASIC Core Bundle Benefits Introduction ............................................................... 2 Configurable Programmable Timer Functionality Connecting CoreTimer in CoreConsole ..................... 3 for AMBA-Based Systems CoreTimer Configurable Options .............................. 3 Automatically Stit ched in CoreConsole Programmer's Model ................................................. 3 Compatible with AMBA, CoreMP7, and Cortex-M1 Resource Requirements ............................................. 5 Ordering Information ................................................ 5 List of Changes ........................................................... 6 Datasheet Categories ................................................. 6 CoreTimer APB Clock Prescale Address Decoder Decrementing Counter Read Data Generation TIMINT Interrupt Generation Figure 1 • CoreTimer Block Diagram January 2008 v3.1 1 © 2008 Actel Corporation CoreTimer Continuous or One-Shot Timer mode is selected by the Introduction Timer Mode bit in the Timer Control Register. At any The CoreTimer module is an APB slave that provides point, the current counter value can be read from the access to an interrupt-generating, programmable Current Value Register. decrementing counter. Figure 1 on page 1 shows a top- The counter is enabled by a bit in the Timer Control level block diagram of CoreTimer. Register. At reset, the counter is disabled, the interrupt is cleared, and the Load Register is set to zero. The mode is set to Continuous, and the Prescale value is set to divide Functional Description the clock by two. The width of the decrementing counter in the CoreTimer A prescale unit is used to provide a clock enable pulse for module can be statically configured as either 16 or 32 the decrementing counter. The prescaler is driven by the bits. Programmable registers provide a means to APB clock (PCLK) and can be programmed via the Timer dynamically control the operation of the timer. If the Control Register to provide an enable pulse every 2, 4, 8, interrupt is enabled, an interrupt is generated when the 16, 32, 64, 128, 256, 512, or 1,024 periods of PCLK. decrementing counter reaches zero. There are two modes of operation available for Interrupt Generation and Clearing CoreTimer: Continuous mode and One-Shot Timer mode. An interrupt is generated when the counter reaches zero and is only cleared when the Interrupt Clear Register, Continuous Mode TimerIntClr, is written to. A register holds the value until This is the default mode. When zero is reached, the the interrupt is cleared. counter is reloaded with the start value, which is stored The interrupt can be masked by writing 0 to the in a programmable register, and continues to count Interrupt Enable bit in the Timer Control Register. Both down. If the interrupt is enabled, this mode can be used the raw interrupt status (prior to masking) and the final to generate an interrupt on a constant interval. interrupt status (after masking) can be read from status registers. One-Shot Timer Mode The counter decrements from its high value and halts on Clocking reaching zero. The timer must be reprogrammed to The counter in CoreTimer is clocked with PCLK, but a begin counting down again. This can be achieved by clock enable signal produced by the prescaler is used to either clearing the Timer Mode bit in the Timer Control enable the counter to operate from a lower effective Register or writing a new value to the Load Register. frequency than that at which PCLK is running. The interval between clock enable pulses can be adjusted Operation via the Prescale field in the Timer Control Register. It is possible to generate a clock enable pulse every 2, 4, 8, The timer is loaded by writing to the Load Register and 16, 32, 64, 128, 256, 512, or 1,024 periods of PCLK. then, if enabled, counts down to zero. When the counter is already running, writing to the Load Register will cause the counter to immediately restart at the new value. When zero is reached, an interrupt is generated if the interrupt is enabled. The interrupt can be cleared by writing to the Interrupt Clear Register. If One-Shot Timer mode is selected, the counter halts on reaching zero until One-Shot Timer mode is deselected or a new load value is written. Otherwise, after reaching zero, the timer reloads the count value from the Load Register and continues to decrement. In Continuous mode, the counter effectively generates a periodic interrupt. 2 v3.1 CoreTimer Connecting CoreTimer in CoreConsole Table 1 lists the ports present on the CoreTimer module and describes how to connect these in CoreConsole. Table 1CoreTimer Connections Connection CoreConsole Label Description Required Connections APB slave interface APBslave Connect this interface to any available slave slot on the APB. PCLK PCLK APB clock signal Normally connected to the HCLK output of MP7Bridge or Cortex-M1. PRESETn PRESETn Active low APB reset input Normally connected to the HRESETn output of MP7Bridge or Cortex-M1. Optional Connections Timer interrupt TIMINT Interrupt output for timer. This signal indicates that an interrupt has been generated by the counter having decremented to zero. The polarity of this signal is controlled by the Interrupt active level configurable option. This is normally connected to one of the interrupt source (ICINTSOURCEx) inputs of the Interrupt Controller. CoreTimer Configurable Options The configurable options for CoreTimer are outlined in Table 2. Table 2CoreTimer Configurable Options Configurable Option Default Setting Description Counter width 32 bits Sets the width of the counter in CoreTimer. Possible settings are "32 bit" and "16 bit." Interrupt active level Low Selects active low or active high TIMINT interrupt: Low = active low interrupt (default) High = active high interrupt Programmer's Model The CoreTimer registers are shown in Table 3. Table 3CoreTimer Registers Offset Type Width Reset ValueName Description 0x00 Read/Write 16 or 32 0x0000 or TimerLoad Load value 0x00000000 0x04 Read 16 or 32 0xFFFF or TimerValue Current value 0xFFFFFFFF 0x08 Read/Write 3 0x0 TimerControl Control register 0x0C Read/Write 4 0x0 TimerPrescale Clock prescale setting 0x10 Write – – TimerIntClr Interrupt clear 0x14 Read 1 0x0 TimerRIS Raw interrupt status 0x18 Read 1 0x0 TimerMIS Masked interrupt status v3.1 3 CoreTimer Load Register – TimerLoad Current Value Register – TimerValue This register contains the value from which the counter is This register gives the current value of the decrementing to decrement. When this register is written to, the counter. counter is loaded with the value written and begins to The Current Value Register is either 16 or 32 bits wide, decrement if the timer is enabled. depending on how CoreTimer is configured. The counter will be reloaded with the value in the Load Register when the current count reaches zero and Timer Control Register – TimerControl Continuous mode is enabled. Table 4 gives the bit assignments for the TimerControl The Load Register is either 16 or 32 bits wide, depending register. on how CoreTimer is configured. Table 4Bit Assignments for the TimerControl Register Bit(s) Name Type Function 31:3 – – Unused; reads zero. 2 Timer Mode Read/Write Selects timer operation mode: 0 = Continuous operation (default) 1 = One-shot count 1 Interrupt Enable Read/Write Interrupt enable bit: 0 = Timer interrupt disabled (default) 1 = Timer interrupt enabled 0 Timer Enable Read/Write Enable bit for timer: 0 = Timer disabled (default) 1 = Timer enabled Prescale Setting Register – TimerPrescale This register contains a single four-bit field that determines the effective clock rate for the timer counter, based on PCLK. Table 5 gives the bit assignments for the TimerPrescale register. Table 5Bit Assignments for the TimerPrescale Register Bits Name Type Function 31:4 – – Unused; reads zero. 3:0 Prescale Read/Write Prescale field. Determines effective clock rate for the counter based on PCLK: 0000 = divide by 2 (default) 0001 = divide by 4 0010 = divide by 8 0011 = divide by 16 0100 = divide by 32 0101 = divide by 64 0110 = divide by 128 0111 = divide by 256 1000 = divide by 512 1001 = divide by 1,024 Others = divide by 1,024 4 v3.1 CoreTimer Interrupt Clear Register – TimerIntClr Raw Interrupt Status Register – TimerRIS Any write to this register will clear (deassert) the TIMINT This register indicates the raw interrupt status from the interrupt output from the counter. Any data may be counter. This value is ANDed with the Timer Interrupt written. Enable bit from the Timer Control register to create the masked interrupt, which is passed to the interrupt output pin. Table 6 gives the bit assignments for the TimerRIS register. Table 6Bit Assignments for the TimerRIS Register Bit(s) Name Type Function 31:1 – – Unused; reads zero. 0 Raw Timer Interrupt Read Raw interrupt status from the counter: 0 = Raw interrupt not pending 1 = Raw Interrupt pending Interrupt Status Register – TimerMIS This register indicates the masked interrupt status from the counter. This value is the logical AND of the raw interrupt status with the Timer Interrupt Enable bit from the Timer Control Register and is the same value that is passed to the interrupt output pin. Table 7 gives the bit assignments for the TimerMIS register. Table 7Bit Assignments for the TimerMIS Register Bit(s) Name Type Function 31:1 – – Unused; reads zero. 0 Timer Interrupt Read Enabled interrupt status from the counter: 0 = Interrupt not pending 1 = Interrupt pending Resource Requirements The utilization for CoreTimer in a ProASIC3 device is as follows: Configured for 16-bit counter: 310 tiles Configured for 32-bit counter: 535 tiles Ordering Information CoreTimer is included in the SysBASIC core bundle supplied with the Actel CoreConsole IP Deployment Platform (IDP). The obfuscated RTL version of SysBASIC (SysBASIC-OC) is available for free with CoreConsole. The source RTL version of SysBASIC (SysBASIC-RM) can be ordered through your local Actel sales representative. CoreTimer cannot be ordered separately from the SysBASIC core bundle. v3.1 5 CoreTimer List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v3.1) Page v3.0 The "Supported Device Families" section was updated to include ProASIC3L. 1 The "Resource Requirements" section was updated to change ProASIC3E to ProASIC3. 5 v2.0 The "Key Features" section and "Benefits" section were updated to include Cortex-M1 1 information. The "Supported Device Families" section was updated to include IGLOO/e devices. 1 Table 1CoreTimer Connections was updated to include Cortex-M1 for PCLK and PRESETn. 3 Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of an advanced or production datasheet containing general product information. This brief summarizes specific device and family information for unreleased products. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. 6 v3.1 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. www.actel.com Actel Corporation Actel Europe Ltd. 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