CoreRemap Product Summary Contents Intended Use General Description ................................................... 1 • Intended for Use in a Processor-Based Subsystem Connecting CoreRemap in CoreConsole ................... 2 with Flash and RAM Memory Programmer’s Model ................................................. 2 Resource Requirements ............................................. 2 Ordering Information ................................................ 2 Key Features List of Changes ........................................................... 3 Supplied in SysBASIC Core Bundle Datasheet Categories ................................................. 3 Tiny Area Flexible – Software Programmable or Set Externally Optimized for use with CoreMP7 and Cortex™-M1 General Description This APB slave is a small control block that has a single- Benefits bit register which is intended for use in control aliasing Ideal for Debugging a Flash-Based Subsystem of memory resources at the bottom of the processor address space. Typically the nonvolatile Flash is located atAuto Stitch in CoreConsole slot 0 at the bottom of the memory map by default, but Compatible with AMBA, CoreMP7, and Cortex-M1 the SRAM may be made to appear at the base of the address space by setting Remap high (in which case slot 0 Supported Device Families is addressable as slot 1). The RemapDefault input determines the value of the Fusion Remap output following a reset. IGLOO™ The Remap output of the CoreRemap module is normally IGLOOe connected to the Remap input of the CoreAHB or ® ProASIC 3L CoreAHBLite. The RemapDefault input may be ProASIC3 connected to the top-level of the subsystem to provide a means of controlling the reset value of Remap. ProASIC3E Synthesis and Simulation Support ® Supported in the Actel Libero Integrated Design Environment (IDE) Verification and Compliance Compliant with AMBA January 2008 v2.1 1 © 2008 Actel Corporation CoreRemap Connecting CoreRemap in CoreConsole Table 1 lists the ports present on the CoreRemap and describes how to connect these in CoreConsole. Table 1 • System Control Block Connections Connection CoreConsole Label Description Required Connections APB Slave Interface APBslave Connect this interface to any available slave slot on the APB Bus. PCLK PCLK APB clock signal Normally connected to the HCLK output of CoreMP7Bridge or Cortex-M1 PRESETn PRESETn Active low APB reset input Normally connected to the HRESETn output of CoreMP7Bridge or Cortex-M1 Remap Remap This output is driven by an internal control register bit and is intended to be used for controlling memory aliasing. This signal should be connected to the Remap input of the AHB Controller (CoreAHB or CoreAHBLite). Optional Connections Default Setting for Remap RemapDefault This input determines the value of the Remap output following a reset. This signal may be connected to the subsystem top-level to allow external control of memory aliasing after reset. If no connection is made to this port, it will be tied low. Programmer’s Model CoreRemap contains a single register at offset 0x00 (and aliased throughout the slot) which is described in Table 2. Table 2System Control Register Bits Name Type Function 31:1 – – Reserved 0 Remap Read/Write Control bit which drives Remap output Resource Requirements The utilization for CoreRemap in a ProASIC3 device is 15 tiles. Ordering Information CoreRemap is included in the SysBASIC core bundle that is supplied with the Actel CoreConsole IP Deployment Platform tool. The obfuscated RTL version of SysBASIC (SysBASIC-OC) is available for free with CoreConsole. The source RTL version of SysBASIC (SysBASIC-RM) can be ordered through your local Actel sales representative. CoreRemap cannot be ordered separately from the SysBASIC core bundle. 2 v2.1 CoreRemap List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v2.1) Page v2.0 The "Supported Device Families" section was updated to include ProASIC3L. 1 The "Resource Requirements" section was updated to change ProASIC3E to ProASIC3. 2 Advanced v0.1 The "Product Summary" section was updated to include Cortex-M1 and IGLOO/e information. 1 Table 1System Control Block Connections was updated to include Cortex-M1 for PCLK and 2 PRESETn. Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of an advanced or production datasheet containing general product information. This brief summarizes specific device and family information for unreleased products. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. v2.1 3 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. www.actel.com Actel Corporation Actel Europe Ltd. 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