CoreAhbNvm Datasheet Intended Use Contents • Provides AHB Hardware Interface and CFI Software Interface to the Embedded Nonvolatile General Description ................................................... 1 Memory (NVM) Blocks within Fusion Devices Device Utilization and Performance ......................... 1 I/O Signal Descriptions ............................................... 2 Generic/Parameter Descriptions ................................ 2 Key Features Maximizing Performance for Large Memories ........ 3 Supplied in SysBASIC Core Bundle Supported CFI Commands ......................................... 5 Provides an Industry-Standard Software Interface ® Timing Diagrams ........................................................ 8 to Actel Fusion Flash Memory Ordering Information ................................................ 8 Implements a Subset of the Common Flash List of Changes ........................................................... 9 Memory Interface Specification Release 2.0 Datasheet Categories ................................................. 9 Implements Standard Slave AHB Bus Hardware Interface Supports Read, Automatic Write and Erase, and Status Operations General Description 32-Bit Interface, Allowing Byte, Half-Word, or Word Accesses to NVM CoreAhbNvm provides an AHB bus interface to the Low Tile Count (r esource utilization) embedded flash memory blocks within Fusion devices. The software, running on an AHB-based microprocessor, Ability to Logically Merg e Multiple Fusion NVM will be able to communicate to the embedded flash Blocks into One Large Area of NVM memory (read, write, and erase). This IP core is targeted NVM Spare Page Access to provide a functional subset of the Common Flash Interface (software interface only) with a design emphasis given to minimize design size. CoreAhbNvm Supported Families supports all devices in the Fusion family. Note that this datasheet focuses on the operation of the CoreAhbNvmFusion (AFS, M1AFS, M7AFS) and does not provide detail on the structure or the behavior of the Fusion flash memory. Refer to the Actel Fusion Family of Mixed-Signal FPGAs datasheet for Core Deliverables details on the Fusion flash memory. VHDL and Verilog Delivered as Plain Text or Obfuscated RTL via Actel CoreConsole IP Deployment Platform Device Utilization and Unit Test Delivered as CoreMP7 Bus Functional Performance Model (BFM) Scripts, and Example AHB-Based System Table 1 • CoreAhbNvm Device Utilization and Performance Core Verification Tiles Performance (MHz) User Can Easily Modify User Testbench Using 436 62 MHz (256, 512 k memory) Existing Format to Add Custom Tests 55 MHz (1 M memory) May 2008 Advanced v0.2 1 © 2008 Actel Corporation CoreAhbNvm Datasheet I/O Signal Descriptions The port signals for the CoreAhbNvm macro are given in Table 2. Table 2CoreAhbNvm Signal Descriptions Signal Direction Description HCLK Input Bus Clock. This clock times all bus transfers and all signal timings. HRESETn Input Reset. The bus reset signal is active LOW and is used to reset the system and the bus. This is the only active low AHB signal. HADDR[20:0] Input Address. Bit 20, when 1, denotes a spare page access. HWRITE Input Transfer direction. When high, this signal indicates a write transfer and when low a read transfer. HSIZE[2:0] Input Transfer size. Indicates the size of the transfer, which can be byte (8-bit), halfword (16-bit), or word (32-bit). 000 – Byte 001 – Half word 010 – Word HWDATA[31:0] Input 32-bit data from the master HREADYIN Input Ready signal from all other AHB slaves HSEL Input Combinatorial decode of HADDR, which indicates that this slave is currently selected. HRDATA[31:0] Output 32-bit data written back to the master HREADY Output Transfer done. When high, the HREADY signal indicates that a transfer has finished on the bus. This signal can be driven low to extend a transfer. HRESP[1:0] Output Transfer response, which has the following meanings: 00 – Okay 01 – Error 10 – Retry 11 – Split HTRANS[1:0] Input Type of transfer 00 – Idle 01 – Busy 10 – Non-sequential 11 – Sequential Generic/Parameter Descriptions CoreAhbNvm has one generic (VHDL) or one parameter (Verilog), called NVM_INSTANCES. This can take on the values shown in Table 3. If instantiated within CoreConsole, this generic/parameter is set by selecting a value from a pull-down box within the configuration window. Table 3Generic/Parameter Description NVM_INSTANCES NVM Size 1 256 kbytes 2 512 kbytes 41 Mbyte 2 Advanced v0.2 CoreAhbNvm Datasheet Maximizing Performance for Large Memories System performance degrades for NVM size greater than 256 kbytes. To maximize performance, constrain the design ® to 100 MHz within the Synplicity synthesis tool (Figure 1). Under Layout Options, Figure2 on page 4, select Advanced. Then choose High effort layout in the Advanced Layout Options, Figure 3 on page 4. Figure 1Synplicity Constraints Advanced v0.2 3 CoreAhbNvm Datasheet Figure 2Layout Options Figure 3Advanced Layout Options 4 Advanced v0.2 CoreAhbNvm Datasheet Supported CFI Commands CoreAhbNvm supports the Read, Automatic Erase, Automatic Write, and Status CFI Operations. The command descriptions are summarized in Table 4. Table 4Command Descriptions First Bus Cycle Second Bus Cycle No. of Bus 9 Command Cycles Operation Address Data Operation Address Data Notes Read Array 1 or ≥ 2 Write X FFh Read AA AD 1 Read Status 2 Write X 70h Read X SD Clear Status 1 Write X 50h Erase Page 2 Write PA 20h Write PA D0h 2 Single-Write 2 Write PA 40h Write AA AD 3 Multi-Write ≥ 2 Write PA E8h Write PA N 4, 5 Legend: X = any address within the device, QA = Query Address, QD = Query Data, IA = Identifier Address, ID = Identifier Data, AA = Array Address, AD = Array Data, SD = Status Data, PA = Any Address within the page Notes: 1. The Write portion of the Read Array command is only needed if not already in Read Array mode. 2. The Erase Page operation will fail if the page is locked. 3. The page portion of the address is ignored for the second bus cycle. 4. The page specified by AA is the page the data will be written to. The page portion of the address is ignored once the multi-write command has been sent (note that this means that writes will wraparound onto the same current page if the page address goes outside the PA specified with the first bus cycle). 5. N is the number of elements (bytes/words/double words) – 1 to be written to the write buffer. Expected count ranges are N = 00h to N = 7Fh (e.g., 1 to 128 bytes) in 8-bit mode, N = 00h to N = 003Fh in 16-bit mode, and N = 00h to N = 1Fh in 32-bit mode. Bus cycles 3 and higher are for writing data into the write buffer. The confirm command (D0h) is expected after exactly N + 1 Write cycles; any other command at that point in the sequence will prevent the transfer of the buffer to the array (the write will be aborted). 6. All new commands are ignored while the device is busy. Reads/Writes CoreAhbNvm Read operations, other than Read Array, mode and the Read Array command is not required to are always preceded by a Write command to set up the read the array after reset. read sequence. A preceding Write is only required for the Read Array operation when the device is not already Start in Read Array mode. The Fusion flash memory device contains a 16-byte read page buffer that enables fast Write Command data transfers. Read Array (0xFF) to any Address Accessing Spare Pages Read from Array Address Array Data will be Returned Assert the upper address bit, HADDR[20], to access a spare page. In this instance, the page address No Finished Reading (HADDR[11:7]) is ignored and the spare page for the Array Data? sector denoted by HADDR[17:12] is accessed. Yes Read Array Complete Read Array Command Figure 4Read Array Flow Diagram The algorithm for the Read command is shown in Figure 4. CoreAhbNvm comes out of reset in Read Array Advanced v0.2 5 CoreAhbNvm Datasheet Read Status Command The algorithm for the Read Status command is shown in S5, S4, or S1 to be set, they can only be reset by the Clear Figure 5. The status register shown in Table 5 may be Status command. read to determine the success of writing or page erase commands. After writing the Read Status command, all Start subsequent read operations output data from the status register until another valid command is written. When error conditions cause status register bits S5, S4, or S1 to Write Command Clear Status Register (0x50) to any Address be set, they can only be reset by the Clear Status command. Clear Status Register Complete Start Figure 6Clear Status Flow Diagram Write Command Erase Page Command Read Status Register (0x70) to any Address The algorithm for the Erase Page command is shown in Figure 7. The Erase Page requires two bus cycles to start: the command itself and a confirm command. Once the Read from any Address Status erase starts, it cannot be interrupted (any subsequent Register will be Returned as Data commands are ignored while the erase is in progress). CoreAhbNvm handles the required sequences. The user can determine when the erase is complete by monitoring No Finished Reading status bit S7 until ready status is indicated (note that the Status Register? status is updated automatically and the Read Status command sequence is not required). Once the Erase Page Yes command has completed, status bits S1, S4, and S5 should be checked to determine if any page erase error Read Status Register occurred. If any of the error status bits are set, they can Complete only be cleared by a Clear Status command. Figure 5Read Status Flow Diagram Table 5Status Register Start Status Bit Description Write Command Erase Page S7 Ready (real-time) (0x20) to Page Address to Erase S6 – S5 Program/Erase Error (sticky) Write Command Erase Confirm (0xD0) to Page Address to Erase S4 Write Error (sticky) S3-S2 – Read (poll) the Status Register S1 Read Error (sticky) S0 – = 0 Status Register Bit 7 Clear Status Command = 1 The algorithm for the Clear Status command is shown in = 1 Erase Failed with Status Register Figure 6. When error conditions cause status register bits Programming Error Bit 5 = 0 Erase Successful Completion Figure 7Erase Page Flow Diagram 6 Advanced v0.2 CoreAhbNvm Datasheet Single Write Command Multi-Write Command The algorithm for the Single Write command is shown in The algorithm for the Multi-Write command is shown in Figure 8. The Single Write is used to write a single byte, Figure 9 on page 8. The Multi-Write is used to write half-word, or word. It should be noted that the Single bytes, half-words, or words. A multi-write is initiated by Write still results in the entire page (in which the Single executing the Multi-Write command and waiting for the Write data is contained) being written into memory. write buffer to become available; that is, the status Therefore, the user should avoid using Single Writes indicates ready. Note that the status is updated where Multi-Writes are more appropriate (that is, when automatically and the Read Status command sequence is more than one location within a page is to be written). A not required. Once the write buffer is available, the single write is initiated by executing the Single Write second Write with a data value of N is executed. N is the command followed by a Write to the desired location number of elements (bytes/words/double words) – 1 to (note that all other commands are ignored once the be written to the write buffer—the expected ranges are Write is in progress). Once the Write command has N = 00h to N = 7Fh (e.g., 1 to 128 bytes) in 8-bit mode, completed (that is, the status no longer indicates busy— N = 00h to N = 003Fh in 16-bit mode, and N = 00h to note that the status is updated automatically and the N = 1Fh in 32-bit mode. Once N is written, the multiple Read Status command sequence is not required), status Writes to the desired locations within the page can then bit S4 should be checked to determine if any write error be made. Note that once the Multi-Write command has occurred. If any of the error status bits are set, they can been issued, the page addresses for the subsequent data only be cleared by a Clear Status command. writes are ignored (this means that Writes will wrap- around onto the same current page if the page address goes outside the page address specified with the first bus Start cycle). Once the last data value has been written, the confirm command (D0h) is expected after exactly N + 1 write cycles; any other command at that point in the Write Command sequence will prevent the transfer of the buffer to the Setup Write (0x40) array (the write will be aborted). Note that all other to any Address command sequences are ignored once the confirm command is received and the write to the array is started. Once the Multi-Write command has completed Write Data to Address Being Programmed (that is, the status no longer indicates busy – note that the status is updated automatically and the Read Status command sequence is not required), status bit S4 should be checked to determine if any write error occurred. If Read (poll) the Status Register any of the error status bits are set, they can only be cleared by a Clear Status command. = 0 Status Register Bit 7 = 1 = 1 Write Error Status Register Bit 4 = 0 Write Successful Completion Figure 8Single Write Flow Diagram Advanced v0.2 7 CoreAhbNvm Datasheet Timing Diagrams Start The timing diagrams for CoreAhbNvm are the normal AHB Read and Write timing diagrams available in the Write the Command ® AHB specification from ARM. Setup Write Buffer (0xE8) to the Page Address Ordering Information Read Status Register = 0 CoreAhbNvm is included in the SysBASIC core bundle = 0 (Buffer Not Ready) that is supplied with the Actel CoreConsole IP Status Status Deployment Platform tool. The obfuscated RTL version Register Bit 1 Register Bit 7 of SysBASIC (SysBASIC-OC) is available for free with CoreConsole. The source RTL version of SysBASIC = 1 (Buffer Ready) = 1 (SysBASIC-RM) can be ordered through your local Actel Write the Element Count (N) Write to Buffer Failed with sales representative. CoreAhbNvm cannot be ordered to the Page Address Protection Error separately from the SysBASIC core bundle. Write a Buffer Element to the Device Address Number of Elements No WrittenEqual to Element Count? Yes Yes Abort the Write to Buffer? No Write the Command Write a Command Other Buffer Program Confirm (0xD0) than Buffer Program to the Page Address Confirm to Any Address Write to Buffer Aborted Read (poll) the Status Register (Command Sequence Error) = 0 Status Register Bit 7 = 1 = 1 Write to Buffer Failed with Status Register Bit 4 Programming Error = 0 Write to Buffer Successful Figure 9Multi-Write Flow Diagram 8 Advanced v0.2 CoreAhbNvm Datasheet List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (Advanced v0.2) Page Advanced v0.1 The "Key Features" section was updated to include NVM Spare Page Access. 1 (April 2006) ® The "Supported Families" section was updated to remove ProASIC 3 (M7A3P) and ProASIC3E 1 (M7A3PE), which are not supported. Table 1 · CoreAhbNvm Device Utilization and Performance was updated. 1 The title of Table 2 · CoreAhbNvm Signal Descriptions, was changed from "CoreAhbNvm Port 2 Macro Signal Descriptions." The descriptions for the HADDR and HSIZE signals were revised. The description of the HRDATA signal was revised to change "date" to "data." The HTRANS signal was added. The "Maximizing Performance for Large Memories" section is new. 3 The "Accessing Spare Pages" section is new. 5 In the "Read Status Command" section, status register bit S3 was removed from the list of status 6 register bits that can be set by error conditions, and bit S1 was added. In the "Clear Status Command" section, status register bit S3 was removed from the list of status 6 register bits that can be set by error conditions, and S1 was added. Figure 7 · Erase Page Flow Diagram was updated. 6 In the "Single Write Command" section, the text was revised to state that status bit S4 should be 7 checked to determine if any write error occurred. Previously the text stated that status bits S4 and S5 should be checked. Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production." The definitions of these categories are as follows: Product Brief The Product brief is a summarized version of an advanced or production datasheet containing general product information. This brief summarizes specific device and family information for unreleased products. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. Advanced v0.2 9 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. www.actel.com Actel Corporation Actel Europe Ltd. Actel Japan Actel Hong Kong 2061 Stierlin Court River Court, Meadows Business Park EXOS Ebisu Building 4F Room 2107, China Resources Building Mountain View, CA Station Approach, Blackwater 1-24-14 Ebisu Shibuya-ku 26 Harbour Road 94043-4655 Camberley Surrey GU17 9AB Tokyo 150 Japan Wanchai, Hong Kong USA United Kingdom Phone +81.03.3445.7671 Phone +852 2185 6460 Phone 650.318.4200 Phone +44 (0) 1276 609 300 Fax +81.03.3445.7668 Fax +852 2185 6488 Fax 650.318.4600 Fax +44 (0) 1276 607 540 http://jp.actel.com www.actel.com.cn 51700079-1/5.08