Revision 9 IGLOOe Low Power Flash FPGAs with Flash*Freeze Technology • Bank-Selectable I/O Voltages—Up to 8 Banks per Chip Features and Benefits • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V/ 2.5V/1.8V/1.5V/1.2V, 3.3V PCI / 3.3V PCI-X, and Low Power LVCMOS 2.5 V / 5.0 V Input • 1.2 V to 1.5 V Core Voltage Support for Low Power • Differential I/O Standards: LVPECL, LVDS, B-LVDS, and • Supports Single-Voltage System Operation M-LVDS • Low-Power Active FPGA Operation • Voltage-Referenced I/O Standards: GTL+ 2.5V/3.3V, GTL • Flash*Freeze Technology Enables Ultra-Low Power 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Consumption while Maintaining FPGA Content Class I and II • Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-Low- • Wide Range Power Supply Voltage Support per JESD8-B, Power Flash*Freeze Mode Allowing I/Os to Operate from 2.7 V to 3.6 V High Capacity • Wide Range Power Supply Voltage Support per JESD8-12, • 600 k to 3 Million System Gates Allowing I/Os to Operate from 1.14 V to 1.575 V • I/O Registers on Input, Output, and Enable Paths • 108 to 504 kbits of True Dual-Port SRAM • Up to 620 User I/Os • Hot-Swappable and Cold-Sparing I/Os • Programmable Output Slew Rate and Drive Strength Reprogrammable Flash Technology • Programmable Input Delay • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS • Schmitt Trigger Option on Single-Ended Inputs Process • Weak Pull-Up/-Down • Live-at-Power-Up (LAPU) Level 0 Support • IEEE 1149.1 (JTAG) Boundary Scan Test ® • Single-Chip Solution • Pin-Compatible Packages across the IGLOO e Family • Retains Programmed Design when Powered Off Clock Conditioning Circuit (CCC) and PLL • 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance • Six CCC Blocks, Each with an Integrated PLL • Configurable Phase Shift, Multiply/Divide, Delay Capabilities, In-System Programming (ISP) and Security and External Feedback • ISP Using On-Chip 128-Bit Advanced Encryption Standard • Wide Input Frequency Range (1.5 MHz up to 250 MHz) (AES) Decryption via JTAG (IEEE 1532–compliant) ® Embedded Memory • FlashLock Designed to Secure FPGA Contents • 1 kbit of FlashROM User Nonvolatile Memory High-Performance Routing Hierarchy • SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM • Segmented, Hierarchical Routing and Clock Structure Blocks (×1, ×2, ×4, ×9, and ×18 organizations available) • High-Performance, Low-Skew Global Network • True Dual-Port SRAM (except ×18) • Architecture Supports Ultra-High Utilization ARM Processor Support in IGLOOe FPGAs Pro (Professional) I/O • M1 IGLOOe Devices—Cortex™-M1 Soft Processor Available • 700 Mbps DDR, LVDS-Capable I/Os with or without Debug •1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Table 1 • IGLOOe Product Family IGLOOe Devices AGLE600 AGLE3000 ARM-Enabled IGLOOe Devices M1AGLE3000 System Gates 600,000 3,000,000 VersaTiles (D-flip-flops) 13,824 75,264 Quiescent Current (typical) in Flash*Freeze Mode (µW) 49 137 504 RAM kbits (1,024 bits) 108 112 4,608-Bit Blocks 24 1 FlashROM Kbits (1,024 bits) 1 Yes Secure (AES) ISP Yes 6 CCCs with Integrated PLLs 6 1 VersaNet Globals 18 18 8 I/O Banks 8 Maximum User I/Os 270 620 Package Pins FBGA FG256, FG484 FG484, FG896 Notes: 1. Refer to the Cortex-M1 Handbook for more information. 2. Six chip (main) and twelve quadrant global networks are available. 3. For devices supporting lower densities, refer to the IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology datasheet. March 2012 I © 2012 Microsemi Corporation IGLOOe Low Power Flash FPGAs 1 I/Os Per Package IGLOOe Devices AGLE600 AGLE3000 ARM-Enabled IGLOOe Devices M1AGLE3000 I/O Types Single-Ended Differential Single-Ended Differential 1 1 Package I/O I/O Pairs I/O I/O Pairs FG256 165 79 – – FG484 270 135 341 168 FG896 – – 620 310 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the IGLOOe FPGA Fabric User’s Guide to ensure compliance with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For AGLE3000 devices, the usage of certain I/O standards is limited as follows: – SSTL3(I) and (II): up to 40 I/Os per north or south bank – LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank – SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank 4. FG256 and FG484 are footprint-compatible packages. 5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per minibank (group of I/Os). 6. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended user I/Os available is reduced by one. 7. "G" indicates RoHS-compliant packages. Refer to "IGLOOe Ordering Information" on page III for the location of the "G" in the part number. IGLOOe FPGAs Package Sizes Dimensions Package FG256 FG484 FG896 Length × Width (mm × mm) 17 × 17 23 × 23 31 × 31 Nominal Area (mm2) 289 529 961 Pitch (mm) 1 1 1 Height (mm) 1.6 2.23 2.23 IGLOOe Device Status IGLOOe Devices Status M1 IGLOOe Devices Status AGLE600 Production AGLE3000 Production M1AGLE3000 Production II Revision 9 IGLOOe Low Power Flash FPGAs IGLOOe Ordering Information _ AGLE3000 V2 FG G 896 Y I Application (Temperature Range) Blank = Commercial (0°C to +70°C Ambient Temperature) I = Industrial (–40°C to +85°C Ambient Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Security Feature Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS-Compliant Packaging Package Type = FG Fine Pitch Ball Grid Array (1.0 mm pitch) 2 = 1.2 V to 1.5 V 5 = 1.5 V only Part Number IGLOOe Devices = 600,000 System Gates AGLE600 AGLE3000 = 3,000,000 System Gates IGLOOe Devices with Cortex-M1 M1AGLE3000 = 3,000,000 System Gates Note: Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly. Revision 9 III IGLOOe Low Power Flash FPGAs Temperature Grade Offerings AGLE600 AGLE3000 Package M1AGLPE3000 FG256 C, I – FG484 C, I C, I FG896 – C, I Note: C = Commercial temperature range: 0°C to 70°C ambient temperature. I = Industrial temperature range: –40°C to 85°C ambient temperature. References made to IGLOOe devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with M1 (Cortex-M1). Contact your local Microsemi SoC Products Group representative for device availability: http://www.microsemi.com/soc/contact/default.aspx. IV Revision 9 IGLOOe Low Power Flash FPGAs Table of Contents IGLOOe Device Family Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 IGLOOe DC and Switching Characteristics General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-90 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93 Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-106 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-107 Pin Descriptions and Packaging Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 User-Defined Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Package Pin Assignments FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 FG896 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Revision 9 V 1 – IGLOOe Device Family Overview General Description The IGLOOe family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced features. The Flash*Freeze technology used in IGLOOe devices enables entering and exiting an ultra-low power mode while retaining SRAM and register data. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode. The Low Power Active capability (static idle) allows for ultra-low power consumption while the IGLOOe device is completely functional in the system. This allows the IGLOOe device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. Nonvolatile flash technology gives IGLOOe devices the advantage of being a secure, low power, single- chip solution that is live at power-up (LAPU). IGLOOe is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. IGLOOe devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on 6 integrated phase-locked loops (PLLs). IGLOOe devices have up to 3 million system gates, supported with up to 504 kbits of true dual-port SRAM and up to 620 user I/Os. M1 IGLOOe devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA fabric. It has a three-stage pipeline that offers a good balance between low power consumption and speed when implemented in an M1 IGLOOe device. The processor runs the ARMv6-M instruction set, has a configurable nested interrupt controller, and can be implemented with or without the debug block. Cortex- M1 is available for free from Microsemi for use in M1 IGLOOe FPGAs. The ARM-enabled devices have Microsemi ordering numbers that begin with M1AGLE and do not support AES decryption. Flash*Freeze Technology The IGLOOe device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra- low power Flash*Freeze mode. IGLOOe devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of IGLOOe V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total system power. When the IGLOOe device enters Flash*Freeze mode, the device automatically shuts off the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is retained. The availability of low power modes, combined with reprogrammability, a single-chip and single-voltage solution, and availability of small-footprint, high pin-count packages, make IGLOOe devices the best fit for portable electronics. Revision 9 1-1 IGLOOe Device Family Overview Flash Advantages Low Power Flash-based IGLOOe devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. IGLOOe devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. IGLOOe devices also have low dynamic power consumption to further maximize power savings; power is even further reduced by the use of a 1.2 V core voltage. Low dynamic power consumption, combined with low static power consumption and Flash*Freeze technology, gives the IGLOOe device the lowest total system power offered by any FPGA. Security The nonvolatile, flash-based IGLOOe devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. IGLOOe devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. IGLOOe devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of protection in the FPGA industry for programmed intellectual property and configuration data. In addition, all FlashROM data in IGLOOe devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOOe devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. IGLOOe devices with AES-based security provide a high level of protection for remote field updates over public networks such as the Internet, and are designed to ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed IGLOOe device cannot be read back, although secure design verification is possible. Security, built into the FPGA fabric, is an inherent component of the IGLOOe family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The IGLOOe family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with industry-standard security, making remote ISP possible. An IGLOOe device provides the best available security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOOe FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up Flash-based IGLOOe devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based IGLOOe devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOOe device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based IGLOOe devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. 1-2 Revision 9 IGLOOe Low Power Flash FPGAs Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM- based FPGAs, Flash-based IGLOOe devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The IGLOOe family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOOe family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets. Firm-Error Immunity Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of IGLOOe flash-based FPGAs. Once it is programmed, the flash cell configuration element of IGLOOe FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Advanced Flash Technology The IGLOOe family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. IGLOOe family FPGAs utilize design and process techniques to minimize power consumption in all modes of operation. Advanced Architecture The proprietary IGLOOe architecture provides granularity comparable to standard-cell ASICs. The IGLOOe device consists of five distinct and programmable architectural features (Figure 1-1 on page 4): • Flash*Freeze technology • FPGA VersaTiles • Dedicated FlashROM • Dedicated SRAM/FIFO memory • Extensive CCCs and PLLs • Pro I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the IGLOOe core tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile ® capability is unique to the Microsemi ProASIC family of third-generation-architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. Revision 9 1-3 IGLOOe Device Family Overview CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Pro I/Os VersaTile RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block ISP AES User Nonvolatile Flash*Freeze Charge Decryption* FlashRom Technology Pumps Figure 1-1 • IGLOOe Device Architecture Overview Flash*Freeze Technology The IGLOOe device has an ultra-low power static mode, called Flash*Freeze mode, which retains all SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be driven or can be toggling without impact on power consumption, and the device retains all core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode or can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL in this mode. Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power management of the device. The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode usage is not planned, which is advantageous because of the inherent low power static and dynamic capabilities of the IGLOOe device. Refer to Figure 1-2 for an illustration of entering/exiting Flash*Freeze mode. IGLOOe Flash*Freeze FPGA Mode Control Flash*Freeze Pin Figure 1-2 • IGLOOe Flash*Freeze Mode 1-4 Revision 9 IGLOOe Low Power Flash FPGAs VersaTiles PLUS® The IGLOOe core consists of VersaTiles, which have been enhanced beyond the ProASIC core tiles. The IGLOOe VersaTile supports the following: • All 3-input logic functions—LUT-3 equivalent • Latch with clear or set • D-flip-flop with clear or set • Enable D-flip-flop with clear or set Refer to Figure 1-3 for VersaTile configurations. Enable D-Flip-Flop with Clear or Set LUT-3 Equivalent D-Flip-Flop with Clear or Set Data Y X1 Data Y X2 CLK LUT-3 Y D-FF D-FF CLK X3 CLR Enable CLR Figure 1-3 • VersaTile Configurations User Nonvolatile FlashROM IGLOOe devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • Internet protocol addressing (wireless or fixed) • System calibration settings • Device serialization and/or inventory control • Subscription-based business models (for example, set-top boxes) • Secure key storage for secure communications algorithms • Asset management/tracking • Date stamping • Version management The FlashROM is written using the standard IGLOOe IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks, as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. ® The IGLOOe development software solutions, Libero Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. Revision 9 1-5 IGLOOe Device Family Overview SRAM and FIFO IGLOOe devices have embedded SRAM blocks along their north and south sides. Each variable-aspect- ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC IGLOOe devices provide designers with very flexible clock conditioning capabilities. Each member of the IGLOOe family contains six CCCs, each with an integrated PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC (center west side) has a PLL. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: • Wide input frequency range (f ) = 1.5 MHz up to 250 MHz IN_CCC • Output frequency range (f ) = 0.75 MHz up to 250 MHz OUT_CCC • 2 programmable delay types for clock skew minimization • Clock frequency synthesis Additional CCC specifications: • Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration. • Output duty cycle = 50% ± 1.5% or better • Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global network used • Maximum acquisition time is 300 µs • Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns • Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz / f OUT_CCC 1-6 Revision 9 IGLOOe Low Power Flash FPGAs Global Clocking IGLOOe devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. Pro I/Os with Advanced I/O Standards The IGLOOe family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). IGLOOe FPGAs support 19 different I/O standards, including single-ended, differential, and voltage-referenced. The I/Os are organized into banks, with eight banks per device (two per side). The configuration of these banks determines the I/O standards supported. Each I/O bank is subdivided into VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to use that reference voltage. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: • Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II) • Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II). IGLOOe banks support M-LVDS with 20 multi-drop points. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Wide Range I/O Support IGLOOe devices support JEDEC-defined wide range I/O operation. IGLOOe devices support both the JESD8-B specification, covering 3.0 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications. Specifying I/O States During Programming You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information. Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have limited display of Pin Numbers only. 1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during programming. 2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator window appears. 3. Click the Specify I/O States During Programming button to display the Specify I/O States During Programming dialog box. 4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header. Select the I/Os you wish to modify (Figure 1-4 on page 1-8). Revision 9 1-7 5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state settings: 1 – I/O is set to drive out logic High 0 – I/O is set to drive out logic Low Last Known State – I/O is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming Z -Tri-State: I/O is tristated Figure 1-4 • I/O States During Programming Window 6. Click OK to return to the FlashPoint – Programming File Generator window. Note: I/O States During programming are saved to the ADB and resulting programming files after completing programming file generation. 2 – IGLOOe DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 • Absolute Maximum Ratings Symbol Parameter Limits Units VCC DC core supply voltage –0.3 to 1.65 V VJTAG JTAG DC voltage –0.3 to 3.75 V VPUMP Programming voltage –0.3 to 3.75 V VCCPLL Analog power supply (PLL) –0.3 to 1.65 V 3 VCCI and VMV DC I/O buffer supply voltage –0.3 to 3.75 V VI I/O input voltage –0.3 V to 3.6 V (when I/O hot insertion mode is enabled) V –0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) 2 T Storage temperature –65 to +150 °C STG 2 T Junction temperature +125 °C J Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-3, and for recommended operating limits, refer to Table 2-2 on page 2-2. 3. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions" chapter in the IGLOOe FPGA Fabric User’s Guide for further information. Revision 9 2-1 IGLOOe DC and Switching Characteristics 1 Table 2-2 • Recommended Operating Conditions Symbol Parameter Commercial Industrial Units T Ambient Temperature 0 to +70 –40 to +85 °C A 2 T Junction Temperature 0 to + 85 –40 to +100 J 3 4 VCC 1.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V 1.2V–1.5V wide range DC 1.14 to 1.575 1.14 to 1.575 V 5, 6 core voltage VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V 6 VPUMP Programming voltage Programming Mode 3.15 to 3.45 3.15 to 3.45 V 7 Operation 0 to 3.45 0 to 3.45 V 8 4 VCCPLL Analog power supply (PLL) 1.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V 1.2V–1.5V DC core supply 1.14 to 1.26 1.14 to 1.26 V 5 voltage 5 VCCI and 1.2 V DC supply voltage 1.14 to 1.26 1.14 to 1.26 V 9 VMV 1.2V wide range DC supply 1.14 to 1.575 1.14 to 1.575 5 voltage 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V 2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V 10 3.0 V DC supply voltage 2.7 to 3.6 2.7 to 3.6 3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V Notes: 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi recommends that the user follow best design practices using Microsemi’s timing and power simulation tools. 3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-20 on page 2-20. VCCI should be at the same voltage within a given I/O bank. 4. For IGLOOe V5 devices 5. For IGLOOe V2 devices only, operating at VCCI ≥ VCC 6. All IGLOOe devices (V5 and V2) must be programmed with the VCC core voltage at 1.5 V. Applications using the V2 devices powered by a 1.2 V supply must switch the core supply to 1.5 V for in-system programming. 7. VPUMP can be left floating during operation (not programming mode). 8. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions" chapter in the IGLOOe FPGA Fabric User’s Guide for further information. 9. VMV pins must be connected to the corresponding VCCI pins. See the" Pin Descriptions" chapter in the IGLOOe FPGA Fabric User’s Guide for further information. 10. 3.3 V wide range is compliant to the JDEC8b specification and supports 3.0 V VCCI operation. 2-2 Revision 9 IGLOOe Low Power Flash FPGAs 1 Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature Programming Program Retention Maximum Storage Maximum Operating Junction 2 2 Product Grade Cycles (biased/unbiased) Temperature T (°C) Temperature T (°C) STG J Commercial 500 20 years 110 100 Industrial 500 20 years 110 100 Notes: 1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits. 1, 3 Table 2-4 • Overshoot and Undershoot Limits Average VCCI–GND Overshoot or Undershoot Duration Maximum Overshoot/ 2 2 VCCI as a Percentage of Clock Cycle Undershoot 2.7 V or less 10% 1.4 V 5% 1.49 V 3 V 10% 1.1 V 5% 1.19 V 3.3 V 10% 0.79 V 5% 0.88 V 3.6 V 10% 0.45 V 5% 0.54 V Notes: 1. Based on reliability requirements at junction temperature at 85°C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 3. This table does not provide PCI overshoot/undershoot limits. I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every IGLOOe device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5. There are five regions to consider during power-up. IGLOOe I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure2-1 on page2-4 and Figure 2-2 on page 2-5). 2. VCCI > VCC – 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: • During programming, I/Os become tristated and weakly pulled up to VCCI. Revision 9 2-3 IGLOOe DC and Switching Characteristics • JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. PLL Behavior at Brownout Condition Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 and Figure 2- 2 on page 2-5 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the IGLOOe FPGA Fabric User’s Guide for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation. VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 5: I/O buffers are ON Region 4: I/O Region 4: I/O Region 1: I/O Buffers are OFF and power supplies are within buf buffers are ON. fers are ON. specification. I/Os are functional I/Os are functional I/Os meet the entire datasheet (except dif (except differential ferential inputs) and timer specifications for but slower because VCCI speed, VIH / VIL, VOH / VOL, is below specification. For the etc. same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. VCC = 1.425 V Region 2: I/O buffers are ON. Region 3: I/O buffers are ON. I/Os are functional (except differential inputs) I/Os are functional; I/O DC but slower because VCCI / VCC are below specifications are met, specification. For the same reason, input but I/Os are slower because buffers do not meet VIH / VIL levels, and the VCC is below specification. output buffers do not meet VOH / VOL levels. Activation trip point: V = 0.85 V ± 0.25 V a Deactivation trip point: Region 1: I/O buffers are OFF V = 0.75 V ± 0.25 V d VCCI Activation trip point: Min VCCI datasheet specification V = 0.9 V ± 0.3 V voltage at a selected I/O a Deactivation trip point: standard; i.e., 1.425 V or 1.7 V V = 0.8 V ± 0.3 V or 2.3 V or 3.0 V d Figure 2-1 • V5 – I/O State as a Function of VCCI and VCC Voltage Levels 2-4 Revision 9 IGLOOe Low Power Flash FPGAs VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) V CC VCC = 1.575 V Region 5: I/O buffers are ON Region 4: I/O Region 4: I/O Region 1: I/O Buffers are OFF and power supplies are within buf buffers are ON. fers are ON. specification. I/Os are functional I/Os are functional I/Os meet the entire datasheet (except dif (except differential inputs) ferential and timer specifications for but slower because VCCI is speed, VIH / VIL , VOH / VOL , etc. below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. VCC = 1.14 V Region 2: I/O buffers are ON. Region 3: I/O buffers are ON. I/Os are functional (except differential inputs) I/Os are functional; I/O DC but slower because VCCI/VCC are below specifications are met, specification. For the same reason, input but I/Os are slower because buffers do not meet VIH/VIL levels, and the VCC is below specification. output buffers do not meet VOH/VOL levels. Activation trip point: V = 0.85 V ± 0.2 V a Deactivation trip point: Region 1: I/O buffers are OFF V = 0.75 V ± 0.2 V d VCCI Activation trip point: Min VCCI datasheet specification voltage at a selected I/O V = 0.9 V ± 0.15 V a standard; i.e., 1.14 V,1.425 V, 1.7 V, Deactivation trip point: 2.3 V, or 3.0 V V = 0.8 V ± 0.15 V d Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels Thermal Characteristics Introduction The temperature variable in Microsemi Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. EQ 1 can be used to calculate junction temperature. T = Junction Temperature = ΔT + T J A EQ 1 where: T = Ambient Temperature A ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θ * P ja θ = Junction-to-ambient of the package. θ numbers are located in Table 2-5. ja ja P = Power dissipation Revision 9 2-5 IGLOOe DC and Switching Characteristics Package Thermal Characteristics The device junction-to-case thermal resistivity is θ and the junction-to-ambient air thermal resistivity is jc θ . The thermal characteristics for θ are shown for two air flow rates. The absolute maximum junction ja ja temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation allowed for an 896-pin FBGA package at commercial temperature and in still air. Max. junction temp. (°C)– Max. ambient temp. (°C) 100°C7 – 0°C Maximum Power Allowed = ---- ----------------- ----------------- ----------------- ----------------- ---------------- ----------------- ----------------- ----- ------- - = -- ----------------- ---------------- - = 2.206 W θ (°C/W) 13.6°C/W ja EQ 2 Table 2-5 • Package Thermal Resistivities θ ja Package Type Pin Count θ Still Air 200 ft./min. 500 ft./min. Units jc Plastic Quad Flat Package (PQFP) 208 8.0 26.1 22.5 20.8 C/W Plastic Quad Flat Package (PQFP) with 208 3.8 16.2 13.3 11.9 C/W embedded heat spreader Fine Pitch Ball Grid Array (FBGA) 256 3.8 26.9 22.8 21.5 C/W 484 3.2 20.5 17.0 15.9 C/W 676 3.2 16.4 13.0 12.0 C/W 896 2.4 13.6 10.4 9.4 C/W Temperature and Voltage Derating Factors Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to T = 70°C,VCC = 1.425 V) J For IGLOOe V2 or V5 devices, 1.5 V DC Core Supply Voltage Junction Temperature (°C) Array Voltage VCC (V) –40°C 0°C 25°C 70°C 85°C 100°C 1.425 0.945 0.965 0.978 1.000 1.008 1.013 1.500 0.876 0.893 0.906 0.927 0.934 0.940 1.575 0.824 0.840 0.852 0.872 0.879 0.884 Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to T = 70°C, VCC = 1.14 V) J For IGLOOe V2, 1.2 V DC Core Supply Voltage Junction Temperature (°C) Array Voltage VCC (V) –40°C 0°C 25°C 70°C 85°C 100°C 1.14 0.968 0.978 0.991 1.000 1.006 1.010 1.20 0.864 0.873 0.885 0.893 0.898 0.902 1.26 0.793 0.803 0.813 0.821 0.826 0.829 2-6 Revision 9 IGLOOe Low Power Flash FPGAs Calculating Power Dissipation Quiescent Supply Current Quiescent supply current (IDD) calculation depends on multiple factors, including operating voltages (VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power modes usage. Microsemi recommends using the PowerCalculator and SmartPower software estimation tools to evaluate the projected static and active power based on the user design, power mode usage, operating voltage, and temperature. Table 2-8 • Quiescent Supply Current (IDD), IGLOOe Flash*Freeze Mode* Core Voltage AGLE600 AGLE3000 Units Typical (25°C) 1.2 V 34 95 µA 1.5 V 72 310 µA Note: *IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7). Table 2-9 • Quiescent Supply Current (IDD), IGLOOe Sleep Mode (VCC = 0 V)* Core Voltage AGLE600 AGLE3000 Units VCCI/VJTAG = 1.2 V (per bank) 1.2 V 1.7 1.7 µA Typical (25°C) VCCI/VJTAG = 1.5 V (per bank) 1.2 V / 1.5 V 1.8 1.8 µA Typical (25°C) VCCI/VJTAG = 1.8 V (per bank) 1.2 V / 1.5 V 1.9 1.9 µA Typical (25°C) VCCI/VJTAG = 2.5 V (per bank) 1.2 V / 1.5 V 2.2 2.2 µA Typical (25°C) VCCI/VJTAG= 3.3 V (per bank) 1.2 V / 1.5 V 2.5 2.5 µA Typical (25°C) Note: *IDD includes VCC, VPUMP, and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7). Table 2-10 • Quiescent Supply Current (IDD), IGLOOe Shutdown Mode (VCC, VCCI = 0 V)* Core Voltage AGLE600 AGLE3000 Units Typical (25°C) 1.2 V / 1.5 V 0 0 µA Note: *IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7). Revision 9 2-7 IGLOOe DC and Switching Characteristics Table 2-11 • Quiescent Supply Current, No IGLOOe Flash*Freeze Mode* Core Voltage AGLE600 AGLE3000 Units 2 I Current CCA Typical (25°C) 1.2 V 28 89 µA 1.5 V 82 320 µA 3, 4 or I Current I CCI JTAG VCCI/VJTAG = 1.2 V (per bank) 1.2 V 1.7 1.7 µA Typical (25°C) VCCI/VJTAG = 1.5 V (per bank) 1.2 V / 1.5 V 1.8 1.8 µA Typical (25°C) VCCI/VJTAG = 1.8 V (per bank) 1.2 V / 1.5 V 1.9 1.9 µA Typical (25°C) VCCI/VJTAG = 2.5 V (per bank) 1.2 V / 1.5 V 2.2 2.2 µA Typical (25°C) VCCI/VJTAG= 3.3 V (per bank) 1.2 V / 1.5 V 2.5 2.5 µA Typical (25°C) Notes: 1. To calculate total device IDD, multiply the number of banks used in ICCI and add ICCA contribution. 2. Includes VCC, VCCPLL, and VPUMP currents. 3. Per VCCI or VJTAG bank 4. Values do not include I/O static contribution (PDC6 and PDC7). 2-8 Revision 9 IGLOOe Low Power Flash FPGAs Power per I/O Pin Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings VCCI Static Power Dynamic Power 1 2 (V) PDC6 (mW) PAC9 (µW/MHz) Single-Ended 3.3 V LVTTL/LVCMOS 3.3 – 16.34 3.3 V LVTTL/LVCMOS – Schmitt trigger 3.3 – 24.49 3 3.3 V LVCMOS Wide Range 3.3 – 16.34 3 3.3 V LVCMOS Wide Range – Schmitt trigger 3.3 – 24.49 2.5 V LVCMOS 2.5 – 4.71 2.5 V LVCMOS 2.5 – 6.13 1.8 V LVCMOS 1.8 – 1.66 1.8 V LVCMOS – Schmitt trigger 1.8 – 1.78 1.5 V LVCMOS (JESD8-11) 1.5 – 1.01 1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 0.97 4 1.2 V LVCMOS 1.2 – 0.60 4 1.2 V LVCMOS – Schmitt trigger 1.2 – 0.53 4 1.2 V LVCMOS Wide Range 1.2 – 0.60 4 1.2 V LVCMOS Wide Range – Schmitt trigger 1.2 – 0.53 3.3 V PCI 3.3 – 17.76 3.3 V PCI – Schmitt trigger 3.3 – 19.10 3.3 V PCI-X 3.3 – 17.76 3.3 V PCI-X – Schmitt trigger 3.3 – 19.10 Voltage-Referenced 3.3 V GTL 3.3 2.90 7.14 2.5 V GTL 2.5 2.13 3.54 3.3 V GTL+ 3.3 2.81 2.91 2.5 V GTL+ 2.5 2.57 2.61 HSTL (I) 1.5 0.17 0.79 HSTL (II) 1.5 0.17 .079 SSTL2 (I) 2.5 1.38 3.26 SSTL2 (II) 2.5 1.38 3.26 SSTL3 (I) 3.3 3.21 7.97 SSTL3 (II) 3.3 3.21 7.97 Differential LVDS 2.5 2.26 0.89 LVPECL 3.3 5.71 1.94 Notes: 1. PDC6 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCCI. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. 4. Applicable for IGLOOe V2 devices only. Revision 9 2-9 IGLOOe DC and Switching Characteristics 1 Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings C VCCI Static Power Dynamic Power LOAD 2 3 (pF) (V) PDC7 (mW) PAC10 (µW/MHz) Single-Ended 3.3 V LVTTL/LVCMOS 5 3.3 – 148.00 4 3.3 V LVCMOS Wide Range 5 3.3 – 148.00 2.5 V LVCMOS 5 2.5 – 83.23 1.8 V LVCMOS 5 1.8 – 54.58 1.5 V LVCMOS (JESD8-11) 5 1.5 – 37.05 1.2 V LVCMOS (JESD8-11) 5 1.2 – 17.94 1.2 V LVCMOS (JESD8-11) – Wide 17.94 Range 3.3 V PCI 10 3.3 – 204.61 3.3 V PCI-X 10 3.3 – 204.61 Voltage-Referenced 3.3 V GTL 10 3.3 – 24.08 2.5 V GTL 10 2.5 – 13.52 3.3 V GTL+ 10 3.3 – 24.10 2.5 V GTL+ 10 2.5 – 13.54 HSTL (I) 20 1.5 7.08 26.22 HSTL (II) 20 1.5 13.88 27.18 SSTL2 (I) 30 2.5 16.69 105.56 SSTL2 (II) 30 2.5 25.91 116.60 SSTL3 (I) 30 3.3 26.02 114.67 SSTL3 (II) 30 3.3 42.21 131.69 Differential LVDS – 2.5 7.70 89.62 LVPECL – 3.3 19.42 167.86 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI. 4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. 2-10 Revision 9 IGLOOe Low Power Flash FPGAs Power Consumption of Various Internal Resources Table 2-14 • Different Components Contributing to the Dynamic Power Consumption in IGLOOe Devices For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage Device-Specific Dynamic Contributions (µW/MHz) Parameter Definition AGLE600 AGLE3000 PAC1 Clock contribution of a Global Rib 19.7 12.77 PAC2 Clock contribution of a Global Spine 4.16 1.85 PAC3 Clock contribution of a VersaTile row 0.88 PAC4 Clock contribution of a VersaTile used as a sequential module 0.11 PAC5 First contribution of a VersaTile used as a sequential module 0.057 PAC6 Second contribution of a VersaTile used as a sequential module 0.207 PAC7 Contribution of a VersaTile used as a combinatorial module 0.207 PAC8 Average contribution of a routing net 0.7 PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-12 on page 2-9. PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-13 on page 2-10. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.70 Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power calculator or SmartPower in Libero Integrated Design Environment (IDE) software. Table 2-15 • Different Components Contributing to the Static Power Consumption in IGLOO Devices For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage Device Specific Static Power (mW) Parameter Definition AGLE600 AGLE3000 PDC1 Array static power in Active mode See Table 2-11 on page 2-8. PDC2 Array static power in Static (Idle) mode See Table 2-10 on page 2-7. PDC3 Array static power in Flash*Freeze mode See Table 2-8 on page 2-7. PDC4 Static PLL contribution 1.84 PDC5 Bank quiescent power (VCCI-dependent) See Table 2-11 on page 2-8. PDC6 I/O input pin static power (standard-dependent) See Table 2-12 on page 2-9. PDC7 I/O output pin static power (standard-dependent) See Table 2-13 on page 2-10. Revision 9 2-11 IGLOOe DC and Switching Characteristics Table 2-16 • Different Components Contributing to the Dynamic Power Consumption in IGLOOe Devices For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage Device-Specific Dynamic Contributions (µW/MHz) Parameter Definition AGLE600 AGLE3000 PAC1 Clock contribution of a Global Rib 12.61 8.17 PAC2 Clock contribution of a Global Spine 2.66 1.18 PAC3 Clock contribution of a VersaTile row 0.56 PAC4 Clock contribution of a VersaTile used as a sequential module 0.071 PAC5 First contribution of a VersaTile used as a sequential module 0.045 PAC6 Second contribution of a VersaTile used as a sequential module 0.186 PAC7 Contribution of a VersaTile used as a combinatorial module 0.109 PAC8 Average contribution of a routing net 0.449 PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-8 on page 2-7. PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-9 on page 2-7 and Table 2-10 on page 2-7. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic PLL contribution 2.10 Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power calculator or SmartPower in Libero IDE software. Table 2-17 • Different Components Contributing to the Static Power Consumption in IGLOO Devices For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage Device Specific Static Power (mW) Parameter Definition AGLE600 AGLE3000 PDC1 Array static power in Active mode See Table 2-11 on page 2-8. PDC2 Array static power in Static (Idle) mode See Table 2-10 on page 2-7. PDC3 Array static power in Flash*Freeze mode See Table 2-8 on page 2-7. PDC4 Static PLL contribution 0.90 PDC5 Bank quiescent power (VCCI-dependent) See Table 2-11 on page 2-8. PDC6 I/O input pin static power (standard-dependent) See Table 2-12 on page 2-9. PDC7 I/O output pin static power (standard-dependent) See Table 2-13 on page 2-10. 2-12 Revision 9 IGLOOe Low Power Flash FPGAs Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software. The power calculation methodology described below uses the following variables: • The number of PLLs as well as the number and the frequency of each output clock generated • The number of combinatorial and sequential cells used in the design • The internal clock frequencies • The number and the standard of I/O pins used in the design • The number of RAM blocks used in the design • Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table2-18 on page 2-15. • Enable rates of output buffers—guidelines are provided for typical applications in Table 2-19 on page 2-15. • Read rate and write rate to the memory—guidelines are provided for typical applications in Table 2-19 on page 2-15. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—P TOTAL P = P + P TOTAL STAT DYN P is the total static power consumption. STAT P is the total dynamic power consumption. DYN Total Static Power Consumption—P STAT P = (PDC1 or PDC2 or PDC3) + N * PDC5 + N * PDC6 + N * P STAT BANKS INPUTS OUTPUTS DC7 N is the number of I/O input buffers used in the design. INPUTS N is the number of I/O output buffers used in the design. OUTPUTS N is the number of I/O banks powered in the design. BANKS Total Dynamic Power Consumption—P DYN P = P + P + P + P + P + P + P + P DYN CLOCK S-CELL C-CELL NET INPUTS OUTPUTS MEMORY PLL Global Clock Contribution—P CLOCK P = (PAC1 + N * PAC2 + N * PAC3 + N * PAC4) * F CLOCK SPINE ROW S-CELL CLK N is the number of global spines used in the user design—guidelines are provided in SPINE the "Spine Architecture" section of the Global Resources chapter in the IGLOOe FPGA Fabric User's Guide. N is the number of VersaTile rows used in the design—guidelines are provided in the ROW "Spine Architecture" section of the Global Resources chapter in the IGLOOe FPGA Fabric User's Guide. F is the global clock signal frequency. CLK N is the number of VersaTiles used as sequential modules in the design. S-CELL PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution—P S-CELL P = N * (PAC5 + α / 2 * PAC6) * F S-CELL S-CELL 1 CLK N is the number of VersaTiles used as sequential modules in the design. When a S-CELL multi-tile sequential cell is used, it should be accounted for as 1. α is the toggle rate of VersaTile outputs—guidelines are provided in Table2-18 on 1 page 2-15. F is the global clock signal frequency. CLK Revision 9 2-13 IGLOOe DC and Switching Characteristics Combinatorial Cells Contribution—P C-CELL P = N * α / 2 * PAC7 * F C-CELL C-CELL 1 CLK N is the number of VersaTiles used as combinatorial modules in the design. C-CELL α is the toggle rate of VersaTile outputs—guidelines are provided in Table2-18 on 1 page 2-15. F is the global clock signal frequency. CLK Routing Net Contribution—P NET P = (N + N ) * α / 2 * PAC8 * F NET S-CELL C-CELL 1 CLK N is the number of VersaTiles used as sequential modules in the design. S-CELL N is the number of VersaTiles used as combinatorial modules in the design. C-CELL α is the toggle rate of VersaTile outputs—guidelines are provided in Table2-18 on 1 page 2-15. F is the global clock signal frequency. CLK I/O Input Buffer Contribution—P INPUTS P = N * α / 2 * PAC9 * F INPUTS INPUTS 2 CLK N is the number of I/O input buffers used in the design. INPUTS α is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-15. 2 F is the global clock signal frequency. CLK I/O Output Buffer Contribution—P OUTPUTS P = N * α / 2 * β * PAC10 * F OUTPUTS OUTPUTS 2 1 CLK N is the number of I/O output buffers used in the design. OUTPUTS α is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-15. 2 β is the I/O buffer enable rate—guidelines are provided in Table 2-19 on page 2-15. 1 F is the global clock signal frequency. CLK RAM Contribution—P MEMORY P = PAC11 * N * F * β + PAC12 * N * F * β MEMORY BLOCKS READ-CLOCK 2 BLOCK WRITE-CLOCK 3 N is the number of RAM blocks used in the design. BLOCKS F is the memory read clock frequency. READ-CLOCK β is the RAM enable rate for read operations—guidelines are provided in Table 2-19 on 2 page 2-15. F is the memory write clock frequency. WRITE-CLOCK β is the RAM enable rate for write operations—guidelines are provided in Table 2-19 on 3 page 2-15. PLL Contribution—P PLL P = PDC4 + PAC13 * F PLL CLKOUT 1 F is the output clock frequency. CLKOUT 1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (P * F product) to the total PLL contribution. AC13 CLKOUT 2-14 Revision 9 IGLOOe Low Power Flash FPGAs Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: • The average toggle rate of a shift register is 100% as all flip-flop outputs toggle at half of the clock frequency. • The average toggle rate of an 8-bit counter is 25%: – Bit 0 (LSB) = 100% – Bit 1 = 50% – Bit 2 = 25% –… – Bit 7 (MSB) = 0.78125% – Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-18 • Toggle Rate Guidelines Recommended for Power Calculation Component Definition Guideline α Toggle rate of VersaTile outputs 10% 1 α I/O buffer toggle rate 10% 2 Table 2-19 • Enable Rate Guidelines Recommended for Power Calculation Component Definition Guideline β I/O output buffer enable rate 100% 1 β RAM enable rate for read operations 12.5% 2 β RAM enable rate for write operations 12.5% 3 Revision 9 2-15 IGLOOe DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Combinational Cell Y Y LVPECL t = 1.19 ns t = 1.04 ns PD PD t = 1.75 ns DP I/O Module (Non-Registered) Combinational Cell Y LVTTL/LVCMOS 3.3 V Output drive strength = 12 mA t = 3.13 ns t = 1.77 ns DP High slew rate PD I/O Module Combinational Cell (Non-Registered) Y I/O Module LVTTL/LVCMOS 3.3 V (Registered) Output drive strength = 24 mA t = 2.76 ns t = 1.45 ns DP High slew rate PY t = 1.33 ns PD LVPECL DQ I/O Module (Non-Registered) Combinational Cell Y LVCMOS 1.5V Output drive strength = 12 mA t = 0.43 ns ICLKQ t = 3.30 ns DP High slew t = 0.47 ns t = 0.85 ns ISUD PD Input LVTTL/LVCMOS 3.3 V Clock I/O Module (Registered) Register Cell Register Cell Combinational Cell t = 1.10 ns PY Y DQ DQ DQ GTL+ 3.3V I/O Module t = 0.90 ns PD (Non-Registered) t = 1.85 ns DP t = 0.90 ns t = 0.90 ns t = 1.02 ns LVDS, CLKQ CLKQ OCLKQ t = 0.82 ns t = 0.82 ns t = 0.52 ns BLVDS, SUD SUD OSUD M-LVDS Input LVTTL/LVCMOS 3.3 V Input LVTTL/LVCMOS 3.3 V Clock t = 1.62 ns Clock PY t = 1.10 ns t = 1.10 ns PY PY Figure 2-3 • Timing Model Operating Conditions: Std. Speed, Commercial Temperature Range (T = 70°C), Worst-Case J VCC = 1.425 V, Applicable to 1.5 V DC Core Voltage, V2 and V5 devices 2-16 Revision 9 IGLOOe Low Power Flash FPGAs t t PY DIN D Q PAD DIN Y CLK To Array I/O Interface t = MAX(t (R), t (F)) PY PY PY t = MAX(t (R), t (F)) DIN DIN DIN VIH Vtrip Vtrip PAD VIL VCC 50% 50% Y t t GND PY PY (R) (F) t t PYS PYS (R) (F) V CC 50% 50% DIN GND t t DOUT DOUT (R) (F) Figure 2-4 • Input Buffer Timing Model and Delays (example) Revision 9 2-17 IGLOOe DC and Switching Characteristics t t DOUT DP D Q PAD DOUT CLK Std D Load From Array t = MAX(t (R), t (F)) DP DP DP I/O Interface t = MAX(t (R), t (F)) DOUT DOUT DOUT t t DOUT DOUT VCC (R) (F) 50% 50% D 0 V VCC 50% 50% DOUT 0 V VOH Vtrip Vtrip V OL PAD t t DP DP (R) (F) Figure 2-5 • Output Buffer Model and Delays (example) 2-18 Revision 9 IGLOOe Low Power Flash FPGAs t EOUT D Q CLK , t , t , t , t , t t E ZL ZH HZ LZ ZLS ZHS EOUT D Q PAD DOUT CLK D t = MAX(t (r), t (f)) I/O Interface EOUT EOUT EOUT VCC D VCC 50% 50% E t EOUT (F) t EOUT (R) VCC 50% 50% 50% 50% t LZ EOUT t ZH t t ZL HZ VCCI 90% VCCI PAD Vtrip Vtrip VOL 10% V CCI VCC D VCC 50% 50% E t t EOUT (F) EOUT (R) VCC 50% 50% EOUT 50% t ZHS t ZLS VOH PAD Vtrip Vtrip VOL Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example) Revision 9 2-19 IGLOOe DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions 1 1 Equivalent VIL VIH VOL VOH IOL IOH Software Default I/O Drive Drive Slew Min. Max. Min. Max. Max. Min. 2 Standard Strength Strength Rate V V V V V VmAmA 3.3 V 12 mA 12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12 LVTTL / 3.3 V LVCMOS 3.3 V 100 µA 12 mA High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1 LVCMOS Wide 3 Range 2.5 V 12 mA 12 mA High –0.3 0.7 1.7 3.6 0.7 1.7 12 12 LVCMOS 1.8 V 12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 12 12 LVCMOS 1.5 V 12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12 LVCMOS 1.2 V 2 mA 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 5 LVCMOS 1.2 V 100 µA 2 mA High –0.3 0.3 * VCCI 0.7 * VCCI 3.6 0.1 VCCI – 0.1 0.1 0.1 LVCMOS Wide 4,5 Range 3.3 V PCI Per PCI Specification 3.3 V PCI-X Per PCI-X Specification 6 6 3.3 V GTL 25 mA 25 mA High –0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25 6 6 2.5 V GTL 25 mA 25 mA High –0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25 3.3 V GTL+ 35 mA 35 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 51 51 2.5 V GTL+ 33 mA 33 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 40 40 HSTL (I) 8 mA 8 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 8 8 Notes: 1. Currents are measured at 85°C junction temperature. 2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-12 specification. 4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 5. Output drive strength is below JEDEC specification. 6. Output Slew Rates can be extracted from IBIS Models, http://www.microsemi.com/soc/download/ibis/default.aspx. 2-20 Revision 9 IGLOOe Low Power Flash FPGAs Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels (continued) Applicable to Commercial and Industrial Conditions 1 1 Equivalent VIL VIH VOL VOH IOL IOH Software Default I/O Drive Drive Slew Min. Max. Min. Max. Max. Min. 2 Standard Strength Strength Rate V V V V V VmAmA 6 6 HSTL (II) 15 mA 15 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 15 15 SSTL2 (I) 15 mA 15 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.54 VCCI – 0.62 15 15 SSTL2 (II) 18 mA 18 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.35 VCCI – 0.43 18 18 SSTL3 (I) 14 mA 14 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.7 VCCI – 1.1 14 14 SSTL3 (II) 21 mA 21 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.5 VCCI – 0.9 21 21 Notes: 1. Currents are measured at 85°C junction temperature. 2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-12 specification. 4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 5. Output drive strength is below JEDEC specification. 6. Output Slew Rates can be extracted from IBIS Models, http://www.microsemi.com/soc/download/ibis/default.aspx. Revision 9 2-21 IGLOOe DC and Switching Characteristics Table 2-21 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions 1 2 Commercial Industrial 3 4 3 4 IIL IIH IIL IIH DC I/O Standards µA µA µA µA 3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15 3.3 V LVCMOS Wide Range 10 10 15 15 2.5 V LVCMOS 10 10 15 15 1.8 V LVCMOS 10 10 15 15 1.5 V LVCMOS 10 10 15 15 5 1.2 V LVCMOS 10 10 15 15 5 1.2 V LVCOMS Wide Range 10 10 15 15 3.3 V PCI 10 10 15 15 3.3 V PCI-X 10 10 15 15 3.3 V GTL 10 10 15 15 2.5 V GTL 10 10 15 15 3.3 V GTL+ 10 10 15 15 2.5 V GTL+ 10 10 15 15 HSTL (I) 10 10 15 15 HSTL (II) 10 10 15 15 SSTL2 (I) 10 10 15 15 SSTL2 (II) 10 10 15 15 SSTL3 (I) 10 10 15 15 SSTL3 (II) 10 10 15 15 Notes: 1. Commercial range (0°C < T < 70°C) A 2. Industrial range (–40°C < T < 85°C) A 3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 5. Applicable to V2 devices operating at VCCI ≥ VCC. 2-22 Revision 9 IGLOOe Low Power Flash FPGAs Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-22 • Summary of AC Measuring Points Input Reference Board Termination Measuring Trip Standard Voltage (VREF_TYP) Voltage (VTT_REF) Point (Vtrip) 3.3 V LVTTL / 3.3 V LVCMOS – – 1.4 V 3.3 V LVCMOS Wide Range – – 1.4 V 2.5 V LVCMOS – – 1.2 V 1.8 V LVCMOS – – 0.90 V 1.5 V LVCMOS – – 0.75 V 1.2 V LVCMOS* – – 0.6 V 1.2 V LVCMOS – Wide Range* – – 0.6 V 3.3 V PCI – – 0.285 * VCCI (RR) – – 0.615 * VCCI (FF)) 3.3 V PCI-X – – 0.285 * VCCI (RR) – – 0.615 * VCCI (FF) 3.3 V GTL 0.8 V 1.2 V VREF 2.5 V GTL 0.8 V 1.2 V VREF 3.3 V GTL+ 1.0 V 1.5 V VREF 2.5 V GTL+ 1.0 V 1.5 V VREF HSTL (I) 0.75 V 0.75 V VREF HSTL (II) 0.75 V 0.75 V VREF SSTL2 (I) 1.25 V 1.25 V VREF SSTL2 (II) 1.25 V 1.25 V VREF SSTL3 (I) 1.5 V 1.485 V VREF SSTL3 (II) 1.5 V 1.485 V VREF LVDS – – Cross point LVPECL – – Cross point Note: *Applicable to V2 devices ONLY operating in the 1.2 V core range. Revision 9 2-23 IGLOOe DC and Switching Characteristics Table 2-23 • I/O AC Parameter Definitions Parameter Definition t Data to Pad delay through the Output Buffer DP t Pad to Data delay through the Input Buffer with Schmitt trigger disabled PY t Data to Output Buffer delay through the I/O interface DOUT t Enable to Output Buffer Tristate Control delay through the I/O interface EOUT t Input Buffer to Data delay through the I/O interface DIN t Pad to Data delay through the Input Buffer with Schmitt trigger enabled PYS t Enable to Pad delay through the Output Buffer—HIGH to Z HZ t Enable to Pad delay through the Output Buffer—Z to HIGH ZH t Enable to Pad delay through the Output Buffer—LOW to Z LZ t Enable to Pad delay through the Output Buffer—Z to LOW ZL t Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH ZHS t Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW ZLS 2-24 Revision 9 IGLOOe Low Power Flash FPGAs Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings Std. Speed Grade, Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCI (per standard) I/O Standard 3.3 V LVTTL / 12 12 High 5 – 0.972.120.181.081.34 0.66 2.17 1.69 2.71 3.08 5.76 5.28 ns 3.3 V LVCMOS 3.3 V LVCMOS 100 µA 12 High 5 – 0.972.960.181.421.840.662.982.283.864.366.585.87 ns 1, 2 Wide Range 2.5 V LVCMOS 12 12 High 5 – .097 2.15 0.18 1.31 1.41 0.66 2.20 1.85 2.78 2.98 5.80 5.45 ns 1.8 V LVCMOS 12 12 High 5 – 0.97 2.37 0.18 1.27 1.59 0.66 2.42 2.03 3.07 3.57 6.02 5.62 ns 1.5 V LVCMOS 12 12 High 5 – 0.97 2.69 0.18 1.47 1.77 0.66 2.75 2.30 3.24 3.67 6.35 5.89 ns 3 3.3 V PCI Per – High 10 25 0.97 2.38 0.18 0.96 1.42 0.66 2.43 1.80 2.72 3.08 6.03 5.39 ns PCI spec 3 3.3 V PCI-X Per – High 10 25 0.97 2.38 0.19 0.92 1.34 0.66 2.43 1.80 2.72 3.08 6.03 5.39 ns PCI-X spec 3.3 V GTL 25 – High 10 25 0.97 1.78 0.19 2.35 – 0.66 1.80 1.78 – – 5.39 5.38 ns 2.5 V GTL 25 – High 10 25 0.97 1.85 0.19 1.98 – 0.66 1.89 1.82 – – 5.49 5.42 ns 3.3 V GTL+ 35 – High 10 25 0.97 1.80 0.19 1.32 – 0.66 1.84 1.77 – – 5.44 5.36 ns 2.5 V GTL+ 33 – High 10 25 0.97 1.92 0.19 1.26 – 0.66 1.96 1.80 – – 5.56 5.40 ns HSTL (I) 8 – High 20 50 0.97 2.67 0.18 1.72 – 0.66 2.72 2.67 – – 6.32 6.26 ns HSTL (II) 15 – High 20 25 0.97 2.55 0.18 1.72 – 0.66 2.60 2.34 – – 6.20 5.93 ns SSTL2 (I) 15 – High 30 50 0.97 1.86 0.19 1.12 – 0.66 1.90 1.68 – – 5.50 5.28 ns SSTL2 (II) 18 – High 30 25 0.97 1.89 0.19 1.12 – 0.66 1.93 1.62 – – 5.53 5.22 ns SSTL3 (I) 14 – High 30 50 0.97 2.00 0.19 1.06 – 0.66 2.04 1.67 – – 5.64 5.27 ns SSTL3 (II) 21 – High 30 25 0.97 1.81 0.19 1.06 – 0.66 1.85 1.55 – – 5.45 5.14 ns LVDS 24 – High – – 0.97 1.73 0.19 1.62 ––––––– – ns LVPECL 24 – High – – 0.97 1.65 0.18 1.42 ––––––– – ns Notes: 1. All LVCMOS 3.3V software macros support LVCMOS 3.3V wide range as specified in the JESD8-B specification.Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-48 for connectivity. This resistor is not required during normal operation. 2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 3. Resistance is used to measure I/O propagation delays as defined in PCI Specifications. 4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Revision 9 2-25 Drive Strength (mA) Equivalent Software Default 4 Drive Strength Option (mA) Slew Rate Capacitive Load (pF) External Resistor (Ω) t (ns) DOUT t (ns) DP t (ns) DIN t (ns) PY t (ns) PYS t (ns) EOUT t (ns) ZL t (ns) ZH t (ns) LZ t (ns) HZ t (ns) ZLS t (ns) ZHS Units IGLOOe DC and Switching Characteristics Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings Std. Speed Grade, Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, J Worst-Case VCCI (per standard) I/O Standard 3.3 V LVTTL / 12 12 High 5 – 1.55 2.47 0.26 1.31 1.58 1.10 2.51 2.04 3.28 3.97 8.29 7.82 ns 3.3 V LVCMOS 3.3 V LVCMOS 100 µA 12 High 35 – 1.55 3.40 0.26 1.66 2.14 1.10 3.40 2.68 4.55 5.49 9.19 8.46 ns 1,2 Wide Range 2.5 V LVCMOS 12 12 High 5 – 1.55 2.51 0.26 1.55 1.77 1.10 2.54 2.22 3.36 3.85 8.33 8.00 ns 1.8 V LVCMOS 12 12 High 5 – 1.55 2.75 0.26 1.53 1.96 1.10 2.78 2.40 3.68 4.56 8.57 8.19 ns 1.5 V LVCMOS 12 12 High 5 – 1.55 3.10 0.26 1.72 2.16 1.10 3.15 2.70 3.86 4.68 8.93 8.49 ns 1.2 V LVCMOS 2 2 High 5 – 1.55 4.06 0.26 2.09 2.95 1.10 3.92 3.46 4.01 3.79 9.71 9.24 ns 1.2 V LVCMOS 100 µA 2 High 5 – 1.55 4.06 0.26 2.09 2.95 1.10 3.92 3.46 4.01 3.79 9.71 9.24 ns 2,3 Wide Range 4 3.3 V PCI Per PCI – High 10 25 1.55 2.76 0.26 1.19 1.63 1.10 2.79 2.16 3.29 3.97 8.58 7.94 ns spec 4 3.3 V PCI-X Per – High 10 25 1.55 2.76 0.25 1.22 1.58 1.10 2.79 2.16 3.29 3.97 8.58 7.94 ns PCI-X spec 3.3 V GTL 25 – High 10 25 1.55 2.08 0.25 2.76 – 1.10 2.09 2.08 – – 7.88 7.87 ns 2.5 V GTL 25 – High 10 25 1.55 2.17 0.25 2.35 – 1.10 2.20 2.13 – – 7.99 7.91 ns 3.3 V GTL+ 35 – High 10 25 1.55 2.12 0.25 1.62 – 1.10 2.14 2.07 – – 7.93 7.85 ns 2.5 V GTL+ 33 – High 10 25 1.55 2.25 0.25 1.55 – 1.10 2.27 2.10 – – 8.06 7.89 ns HSTL (I) 8 – High 20 50 1.55 3.09 0.25 1.95 – 1.10 3.11 3.09 – – 8.90 8.88 ns HSTL (II) 15 – High 20 25 1.55 2.94 0.25 1.95 – 1.10 2.98 2.74 – – 8.77 8.53 ns SSTL2 (I) 15 – High 30 50 1.55 2.18 0.25 1.40 – 1.10 2.21 2.03 – – 7.99 7.82 ns SSTL2 (II) 18 – High 30 25 1.55 2.21 0.25 1.40 – 1.10 2.24 1.97 – – 8.03 7.76 ns SSTL3 (I) 14 – High 30 50 1.55 2.33 0.25 1.33 – 1.10 2.36 2.02 – – 8.15 7.81 ns SSTL3 (II) 21 – High 30 25 1.55 2.13 0.25 1.33 – 1.10 2.16 1.89 – – 7.94 7.67 ns LVDS 24 – High – – 1.55 2.26 0.25 1.95 – –– –– –– – ns LVPECL 24 – High – – 1.55 2.17 0.25 1.70 – –– –– –– – ns Notes: 1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. 2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-48 for connectivity. This resistor is not required during normal operation. 5. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2-26 Revision 9 Drive Strength (mA) Equivalent Software Default 5 Drive Strength Option (mA) Slew Rate Capacitive Load (pF) External Resistor (Ω) t (ns) DOUT t (ns) DP t (ns) DIN t (ns) PY t (ns) PYS t (ns) EOUT t (ns) ZL t (ns) ZH t (ns) LZ t (ns) HZ t (ns) ZLS t (ns) ZHS Units IGLOOe Low Power Flash FPGAs Detailed I/O DC Characteristics Table 2-26 • Input Capacitance Symbol Definition Conditions Min. Max. Units C Input capacitance VIN = 0, f = 1.0 MHz 8 pF IN C Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF INCLK 1 Table 2-27 • I/O Output Buffer Maximum Resistances 2 3 Standard Drive Strength R (Ω) R (Ω) PULL-DOWN PULL-UP 3.3 V LVTTL / 3.3 V LVCMOS 4 mA 100 300 8 mA 50 150 12 mA 25 75 16 mA 17 50 24 mA 11 33 3.3 V LVCMOS Wide Range 100 µA TBD TBD 2.5 V LVCMOS 4 mA 100 200 8 mA 50 100 12 mA 25 50 16 mA 20 40 24 mA 11 22 1.8 V LVCMOS 2 mA 200 225 4 mA 100 112 6 mA 50 56 8 mA 50 56 12 mA 20 22 16 mA 20 22 1.5 V LVCMOS 2 mA 200 224 4 mA 100 112 6 mA 67 75 8 mA 33 37 12 mA 33 37 4 1.2 V LVCMOS 2 mA TBD TBD 4 1.2 V LVCMOS Wide Range 100 µA TBD TBD 3.3 V PCI/PCI-X Per PCI/PCI-X 25 75 specification 3.3 V GTL 25 mA 11 – Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website at http://www.microsemi.com/soc/techdocs/models/ibis.html. 2. R = (VOLspec) / IOLspec (PULL-DOWN-MAX) 3. R = (VCCImax – VOHspec) / IOHspec (PULL-UP-MAX) 4. Applicable to IGLOOe V2 devices operating in the 1.2 V core range ONLY. Revision 9 2-27 IGLOOe DC and Switching Characteristics 1 Table 2-27 • I/O Output Buffer Maximum Resistances (continued) 2 3 Standard Drive Strength R (Ω) R (Ω) PULL-DOWN PULL-UP 2.5 V GTL 25 mA 14 – 3.3 V GTL+ 35 mA 12 – 2.5 V GTL+ 33 mA 15 – HSTL (I) 8 mA 50 50 HSTL (II) 15 mA 25 25 SSTL2 (I) 15 mA 27 31 SSTL2 (II) 18 mA 13 15 SSTL3 (I) 14 mA 44 69 SSTL3 (II) 21 mA 18 32 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website at http://www.microsemi.com/soc/techdocs/models/ibis.html. 2. R = (VOLspec) / IOLspec (PULL-DOWN-MAX) 3. R = (VCCImax – VOHspec) / IOHspec (PULL-UP-MAX) 4. Applicable to IGLOOe V2 devices operating in the 1.2 V core range ONLY. Table 2-28 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values 1 2 R R( (WEAK PULL-UP) (WEAK PULL-DOWN) (Ω) (Ω) VCCI Minimum Maximum Minimum Maximum 3.3 V 10 k 45 k 10 k 45 k 3.3 V (wide range I/Os) 10 k 45 k 10 k 45 k 2.5 V 11 k 55 k 12 k 74 k 1.8 V 18 k 70 k 17 k 110 k 1.5 V 19 k 90 k 19 k 140 k 1.2 V 25 k 110 k 25 k 150 k 1.2 V (wide range I/Os) 19 k 110 k 19 k 150 k Notes: 1. R = (VCCImax – VOHspec) / I (WEAK PULL-UP-MAX) (WEAK PULL-UP-MIN) 2. R = (VOLspec) / I (WEAK PULLDOWN-MAX) (WEAK PULLDOWN-MIN) 2-28 Revision 9 IGLOOe Low Power Flash FPGAs Table 2-29 • I/O Short Currents IOSH/IOSL Drive Strength IOSH (mA)* IOSL (mA)* 3.3 V LVTTL / 3.3 V LVCMOS 4 mA 25 27 8 mA 51 54 12 mA 103 109 16 mA 132 127 24 mA 268 181 3.3 V LVCMOS Wide Range 100 µA TBD TBD 2.5 V LVCMOS 4 mA 16 18 8 mA 32 37 12 mA 65 74 16 mA 83 87 24 mA 169 124 1.8 V LVCMOS 2 mA 9 11 4 mA 17 22 6 mA 35 44 8 mA 45 51 12 mA 91 74 16 mA 91 74 1.5 V LVCMOS 2 mA 13 16 4 mA 25 33 6 mA 32 39 8 mA 66 55 12 mA 66 55 1.2 V LVCMOS 2 mA TBD TBD 1.2 V LVCMOS Wide Range 100 µA TBD TBD 3.3 V PCI/PCIX Per PCI/PCI-X Per PCI Curves Specification 3.3 V GTL 25 mA 268 181 2.5 V GTL 25 mA 169 124 3.3 V GTL+ 35 mA 268 181 2.5 V GTL+ 33 mA 169 124 HSTL (I) 8 mA 32 39 HSTL (II) 15 mA 66 55 SSTL2 (I) 15 mA 83 87 SSTL2 (II) 18 mA 169 124 SSTL3 (I) 14 mA 51 54 SSTL3 (II) 21 mA 103 109 Note: T = 100°C J Revision 9 2-29 IGLOOe DC and Switching Characteristics The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of analysis. For example, at 100°C, the short current condition would have to be sustained for more than six months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-30 • Duration of Short Circuit Event before Failure Temperature Time before Failure –40°C > 20 years 0°C > 20 years 25°C > 20 years 70°C 5 years 85°C 2 years 100°C 6 months Table 2-31 • Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers Input Buffer Configuration Hysteresis Value (typ.) 3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 240 mV 2.5 V LVCMOS (Schmitt trigger mode) 140 mV 1.8 V LVCMOS (Schmitt trigger mode) 80 mV 1.5 V LVCMOS (Schmitt trigger mode) 60 mV 1.2 V LVCMOS (Schmitt trigger mode) 40 mV Table 2-32 • I/O Input Rise Time, Fall Time, and Related I/O Reliability* Input Rise/Fall Time Input Buffer (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS (Schmitt trigger No requirement 10 ns* 20 years disabled) (100°C) LVTTL/LVCMOS (Schmitt trigger No requirement No requirement, but input noise 20 years enabled) voltage cannot exceed Schmitt (100°C) hysteresis. HSTL/SSTL/GTL No requirement 10 ns* 10 years (100°C) LVDS/B-LVDS/M-LVDS/LVPECL No requirement 10 ns* 10 years (100°C) Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. 2-30 Revision 9 IGLOOe Low Power Flash FPGAs Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic is a general purpose standard (EIA/JESD) for 3.3V applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is supported as part of the 3.3 V LVTTL support. Table 2-33 • Minimum and Maximum DC Input and Output Levels 3.3 V LVTTL / 1 2 3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Min. Max. Min. Max. Max. Min. Max. Max. 3 3 4 4 Drive Strength V V V V V VmAmA mA mA µA µA 4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10 16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 132 127 10 10 24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 268 181 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R to VCCI for t / t / t LZ ZL ZLS R = 1 k Test Point R to GND for t / t / t HZ ZH ZHS Test Point Datapath 35 pF Enable Path 5 pF for t / t / t / t ZH ZHS ZL ZLS 5 pF for t / t HZ LZ Figure 2-7 • AC Loading Table 2-34 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) C (pF) LOAD 03.3 1.4 – 5 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Revision 9 2-31 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-35 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V J Speed Unit Drive Strength Grade t t t t t t t t t t t t s DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 4 mA Std. 0.97 4.90 0.18 1.08 1.34 0.66 5.00 3.99 2.27 2.16 8.60 7.59 ns 8 mA Std. 0.97 4.05 0.18 1.08 1.34 0.66 4.13 3.45 2.53 2.65 7.73 7.05 ns 12 mA Std. 0.97 3.44 0.18 1.08 1.34 0.66 3.51 3.05 2.71 2.95 7.11 6.64 ns 16 mA Std. 0.97 3.27 0.18 1.08 1.34 0.66 3.34 2.96 2.74 3.04 6.93 6.55 ns 24 mA Std. 0.97 3.18 0.18 1.08 1.34 0.66 3.24 2.97 2.79 3.36 6.84 6.56 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Commercial-Case Conditions: T J Drive Strength Speed Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 4 mA Std. 0.97 2.85 0.18 1.08 1.34 0.66 2.92 2.27 2.27 2.27 6.51 5.87 ns 8 mA Std. 0.97 2.39 0.18 1.08 1.34 0.66 2.44 1.88 2.53 2.76 6.03 5.47 ns 12 mA Std. 0.97 2.12 0.18 1.08 1.34 0.66 2.17 1.69 2.71 3.08 5.76 5.28 ns 16 mA Std. 0.97 2.08 0.18 1.08 1.34 0.66 2.12 1.65 2.75 3.17 5.72 5.25 ns 24 mA Std. 0.97 2.10 0.18 1.08 1.34 0.66 2.14 1.60 2.80 3.49 5.74 5.20 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2-32 Revision 9 IGLOOe Low Power Flash FPGAs 1.2 V DC Core Voltage Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V J Drive Strength Speed Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 4 mA Std. 1.55 5.54 0.26 1.31 1.58 1.10 5.63 4.53 2.79 2.87 11.42 10.32 ns 8 mA Std. 1.55 4.60 0.26 1.31 1.58 1.10 4.67 3.94 3.09 3.45 10.45 9.73 ns 12 mA Std. 1.55 3.93 0.26 1.31 1.58 1.10 3.99 3.51 3.28 3.82 9.77 9.29 ns 16 mA Std. 1.55 3.74 0.26 1.31 1.58 1.10 3.79 3.41 3.32 3.92 9.58 9.20 ns 24 mA Std. 1.55 3.64 0.26 1.31 1.58 1.10 3.69 3.42 3.38 4.30 9.48 9.21 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 4 mA Std. 1.55 3.26 0.26 1.31 1.58 1.10 3.33 2.67 2.79 3.01 9.12 8.46 ns 8 mA Std. 1.55 2.77 0.26 1.31 1.58 1.10 2.80 2.24 3.09 3.59 8.59 8.03 ns 12 mA Std. 1.55 2.47 0.26 1.31 1.58 1.10 2.51 2.04 3.28 3.97 8.29 7.82 ns 16 mA Std. 1.55 2.42 0.26 1.31 1.58 1.10 2.46 2.00 3.33 4.08 8.24 7.79 ns 24 mA Std. 1.55 2.45 0.26 1.31 1.58 1.10 2.48 1.95 3.38 4.46 8.26 7.73 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Revision 9 2-33 IGLOOe DC and Switching Characteristics 3.3 V LVCMOS Wide Range Table 2-39 • Minimum and Maximum DC Input and Output Levels 1 2 3.3 V LVCMOS Wide Range VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Equivalent Software Default Drive Drive Strength Min. Max. Min. Max Max. Min. Max. Max. 3 4 4 5 5 Strength Option (V) (V) (V) (V) (V) (V) µA µA (mA) (mA) µA µA 100 µA 2 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10 100 µA 4 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10 100 µA 6 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10 100 µA 8 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10 100 µA 12 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10 100 µA 16 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10 100 µA 24 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI . Input current is larger when operating outside recommended ranges. 3. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 4. Currents are measured at 85°C junction temperature. 5. All LVCMOS 3.3 V software macros supports LVCMOS 3.3 V wide range as specified in the JDEC8a specification. 6. Software default selection highlighted in gray. Table 2-40 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) C (pF) LOAD 03.3 1.4 – 5 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2-34 Revision 9 IGLOOe Low Power Flash FPGAs Timing Characteristics 1.5 V DC Core Voltage Table 2-41 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V J Equivalent Software Default Drive Drive Strength Speed 1 Strength Option Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 100 µA 4 mA Std. 0.97 7.26 0.18 1.42 1.84 0.66 7.28 5.78 3.18 2.93 10.88 9.38 ns 100 µA 8 mA Std. 0.97 5.94 0.18 1.42 1.84 0.66 5.96 4.96 3.59 3.69 9.56 8.56 ns 100 µA 12 mA Std. 0.97 5.00 0.18 1.42 1.84 0.66 5.02 4.34 3.86 4.16 8.62 7.94 ns 100 µA 16 mA Std. 0.97 4.73 0.18 1.42 1.84 0.66 4.75 4.21 3.92 4.29 8.35 7.81 ns 100 µA 24 mA Std. 0.97 4.59 0.18 1.42 1.84 0.66 4.61 4.23 3.99 4.78 8.21 7.82 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-42 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V J Equivalent Software Default Drive Drive Strength Speed 1 Strength Option Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 100 µA 4 mA Std. 0.97 4.10 0.18 1.42 1.84 0.66 4.12 3.17 3.18 3.11 7.71 6.77 ns 100 µA 8 mA Std. 0.97 3.37 0.18 1.42 1.84 0.66 3.39 2.57 3.59 3.87 6.99 6.16 ns 100 µA 12 mA Std. 0.97 2.96 0.18 1.42 1.84 0.66 2.98 2.28 3.86 4.36 6.58 5.87 ns 100 µA 16 mA Std. 0.97 2.90 0.18 1.42 1.84 0.66 2.92 2.22 3.93 4.49 6.51 5.82 ns 100 µA 24 mA Std. 0.97 2.92 0.18 1.42 1.84 0.66 2.94 2.15 4.00 4.99 6.54 5.75 ns Notes: 1. The minimum drive strength for any or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 3. Software default selection highlighted in gray. Revision 9 2-35 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-43 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V J Equivalent Software Default Drive Drive Strength Speed 1 Strength Option Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 100 µA 4 mA Std. 1.55 8.14 0.26 1.66 2.14 1.10 8.14 6.46 3.80 3.79 13.93 12.25 ns 100 µA 8 mA Std. 1.55 6.68 0.26 1.66 2.14 1.10 6.68 5.57 4.25 4.69 12.47 11.36 ns 100 µA 12 mA Std. 1.55 5.65 0.26 1.66 2.14 1.10 5.65 4.91 4.55 5.25 11.44 10.69 ns 100 µA 16 mA Std. 1.55 5.36 0.26 1.66 2.14 1.10 5.36 4.76 4.61 5.41 11.14 10.55 ns 100 µA 24 mA Std. 1.55 5.20 0.26 1.66 2.14 1.10 5.20 4.78 4.69 6.00 10.99 10.56 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Table 2-44 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Strength Speed 1 Strength Option Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 100 µA 4 mA Std. 1.55 4.65 0.26 1.66 2.14 110 4.65 3.64 3.80 4.00 10.44 9.43 ns 100 µA 8 mA Std. 1.55 3.85 0.26 1.66 2.14 1.10 3.85 2.99 4.25 4.91 9.64 8.77 ns 100 µA 12 mA Std. 1.55 3.40 0.26 1.66 2.14 1.10 3.40 2.68 4.55 5.49 9.19 8.46 ns 100 µA 16 mA Std. 1.55 3.33 0.26 1.66 2.14 1.10 3.33 2.62 4.62 5.65 9.11 8.41 ns 100 µA 24 mA Std. 1.55 3.36 0.26 1.66 2.14 1.10 3.36 2.54 4.71 6.24 9.15 8.32 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 3. Software default selection highlighted in gray. 2-36 Revision 9 IGLOOe Low Power Flash FPGAs 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. Table 2-45 • Minimum and Maximum DC Input and Output Levels 1 2 2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Min. Max. Min. Max. Max. Min. Max. Max. 3 3 4 4 Strength V V V V V VmAmA mA mA µA µA 4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10 8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10 12 mA –0.3 0.7 1.7 3.6 0.7 1.7 12 12 65 74 10 10 16 mA –0.3 0.7 1.7 3.6 0.7 1.7 16 16 83 87 10 10 24 mA –0.3 0.7 1.7 3.6 0.7 1.7 24 24 169 124 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R to VCCI for t / t / t LZ ZL ZLS R = 1 k Test Point R to GND for t / t / t HZ ZH ZHS Test Point Datapath 35 pF Enable Path 5 pF for t / t / t / t ZH ZHS ZL ZLS 5 pF for t / t HZ LZ Figure 2-8 • AC Loading Table 2-46 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) C (pF) LOAD 02.5 1.2 – 5 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Revision 9 2-37 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-47 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V J Speed Unit Drive Strength Grade t t t t t t t t t t t t s DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 4 mA Std. 0.97 5.55 0.18 1.31 1.41 0.66 5.66 4.75 2.28 1.96 9.26 8.34 ns 8 mA Std. 0.97 4.58 0.18 1.31 1.41 0.66 4.67 4.07 2.58 2.53 8.27 7.66 ns 12 mA Std. 0.97 3.89 0.18 1.31 1.41 0.66 3.97 3.58 2.78 2.91 7.56 7.17 ns 16 mA Std. 0.97 3.68 0.18 1.31 1.41 0.66 3.75 3.47 2.82 3.01 7.35 7.06 ns 24 mA Std. 0.97 3.59 0.18 1.31 1.41 0.66 3.66 3.48 2.88 3.37 7.26 7.08 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-48 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Commercial-Case Conditions: T J Speed Unit Drive Strength Grade t t t t t t t t t t t t s DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 4 mA Std. 0.97 2.94 0.18 1.31 1.41 0.66 3.00 2.68 2.28 2.03 6.60 6.27 ns 8 mA Std. 0.97 2.45 0.18 1.31 1.41 0.66 2.50 2.12 2.58 2.62 6.10 5.72 ns 12 mA Std. 0.97 2.15 0.18 1.31 1.41 0.66 2.20 1.85 2.78 2.98 5.80 5.45 ns 16 mA Std. 0.97 2.10 0.18 1.31 1.41 0.66 2.15 1.80 2.82 3.08 5.75 5.40 ns 24 mA Std. 0.97 2.11 0.18 1.31 1.41 0.66 2.16 1.74 2.88 3.47 5.75 5.33 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2-38 Revision 9 IGLOOe Low Power Flash FPGAs 1.2 V DC Core Voltage Table 2-49 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V J Speed Drive Strength Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 4 mA Std. 1.55 6.25 0.26 1.55 1.77 1.10 6.36 5.34 2.81 2.63 12.14 11.13 ns 8 mA Std. 1.55 5.18 0.26 1.55 1.77 1.10 5.26 4.61 3.13 3.32 11.05 10.39 ns 12 mA Std. 1.55 4.42 0.26 1.55 1.77 1.10 4.49 4.08 3.36 3.76 10.28 9.86 ns 16 mA Std. 1.55 4.19 0.26 1.55 1.77 1.10 4.25 3.96 3.40 3.89 10.04 9.75 ns 24 mA Std. 1.55 4.09 0.26 1.55 1.76 1.10 4.15 3.97 3.47 4.32 9.94 9.76 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Table 2-50 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Commercial-Case Conditions: T J Speed Drive Strength Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 4 mA Std. 1.55 3.38 0.26 1.55 1.77 1.10 3.42 3.11 2.81 2.72 9.21 8.89 ns 8 mA Std. 1.55 2.83 0.26 1.55 1.77 1.10 2.87 2.51 3.13 3.42 8.66 8.30 ns 12 mA Std. 1.55 2.51 0.26 1.55 1.77 1.10 2.54 2.22 3.36 3.85 8.33 8.00 ns 16 mA Std. 1.55 2.45 0.26 1.55 1.77 1.10 2.48 2.16 3.40 3.97 8.27 7.95 ns 24 mA Std. 1.55 2.46 0.26 1.55 1.77 1.10 2.49 2.09 3.47 4.44 8.28 7.88 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Revision 9 2-39 IGLOOe DC and Switching Characteristics 1.8 V LVCMOS Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-51 • Minimum and Maximum DC Input and Output Levels 1.8 V 1 2 LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Min. Max. Min. Max. Max. Min. Max. Max. 3 3 4 4 Strength V V V V V VmAmA mA mA µA µA 2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 9 11 10 10 4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 17 22 10 10 6 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 6 6 35 44 10 10 8 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 8 8 45 51 10 10 12 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 12 12 91 74 10 10 16 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 16 16 91 74 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R to VCCI for t / t / t LZ ZL ZLS R = 1 k Test Point R to GND for t / t / t HZ ZH ZHS Test Point Datapath 35 pF Enable Path 5 pF for t / t / t / t ZH ZHS ZL ZLS 5 pF for t / t HZ LZ Figure 2-9 • AC Loading Table 2-52 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) C (pF) LOAD 01.8 0.9 – 5 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2-40 Revision 9 IGLOOe Low Power Flash FPGAs Timing Characteristics 1.5 V DC Core Voltage Table 2-53 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Speed Drive Strength Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 2 mA Std. 0.97 7.33 0.18 1.27 1.59 0.66 7.47 6.18 2.34 1.18 11.07 9.77 ns 4 mA Std. 0.97 6.07 0.18 1.27 1.59 0.66 6.20 5.25 2.69 2.42 9.79 8.84 ns 6 mA Std. 0.97 5.18 0.18 1.27 1.59 0.66 5.29 4.61 2.93 2.88 8.88 8.21 ns 8 mA Std. 0.97 4.88 0.18 1.27 1.59 0.66 4.98 4.48 2.99 3.01 8.58 8.08 ns 12 mA Std. 0.97 4.80 0.18 1.27 1.59 0.66 4.89 4.49 3.07 3.47 8.49 8.09 ns 16 mA Std. 0.97 4.80 0.18 1.27 1.59 0.66 4.89 4.49 3.07 3.47 8.49 8.09 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-54 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Commercial-Case Conditions: T J Speed Drive Strength Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 2 mA Std. 0.97 3.43 0.18 1.27 1.59 0.66 3.51 3.39 2.33 1.19 7.10 6.98 ns 4 mA Std. 0.97 2.83 0.18 1.27 1.59 0.66 2.89 2.59 2.69 2.49 6.48 6.18 ns 6 mA Std. 0.97 2.45 0.18 1.27 1.59 0.66 2.51 2.19 2.93 2.95 6.10 5.79 ns 8 mA Std. 0.97 2.38 0.18 1.27 1.59 0.66 2.43 2.12 2.98 3.08 6.03 5.71 ns 12 mA Std. 0.97 2.37 0.18 1.27 1.59 0.66 2.42 2.03 3.07 3.57 6.02 5.62 ns 16 mA Std. 0.97 2.37 0.18 1.27 1.59 0.66 2.42 2.03 3.07 3.57 6.02 5.62 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Revision 9 2-41 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-55 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Speed Drive Strength Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 2 mA Std. 1.55 8.21 0.26 1.53 1.96 1.10 8.35 6.88 2.87 1.70 14.14 12.67 ns 4 mA Std. 1.55 6.83 0.26 1.53 1.96 1.10 6.94 5.88 3.27 3.18 12.73 11.67 ns 6 mA Std. 1.55 5.85 0.26 1.53 1.96 1.10 5.94 5.19 3.53 3.37 11.73 10.98 ns 8 mA Std. 1.55 5.52 0.26 1.53 1.96 1.10 5.61 5.06 3.59 3.88 11.39 10.84 ns 12 mA Std. 1.55 5.42 0.26 1.53 1.96 1.10 5.51 5.06 3.68 4.44 11.30 10.85 ns 16 mA Std. 1.55 5.42 0.26 1.53 1.96 1.10 5.51 5.06 3.68 4.44 11.30 10.85 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Table 2-56 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Commercial-Case Conditions: T J Speed Drive Strength Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 2 mA Std. 1.55 3.82 0.26 1.53 1.96 1.10 3.98 3.87 2.86 1.72 9.76 9.66 ns 4 mA Std. 1.55 3.25 0.26 1.53 1.96 1.10 3.30 3.01 3.26 3.26 9.08 8.79 ns 6 mA Std. 1.55 2.84 0.26 1.53 1.96 1.10 2.88 2.58 3.53 3.81 8.66 8.37 ns 8 mA Std. 1.55 2.76 0.26 1.53 1.96 1.10 2.80 2.50 3.58 3.97 8.58 8.29 ns 12 mA Std. 1.55 2.75 0.26 1.53 1.96 1.10 2.78 2.40 3.68 4.56 8.57 8.19 ns 16 mA Std. 1.55 2.75 0.26 1.53 1.96 1.10 2.78 2.40 3.68 4.56 8.57 8.19 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2-42 Revision 9 IGLOOe Low Power Flash FPGAs 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-57 • Minimum and Maximum DC Input and Output Levels 1.5 V 1 2 LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Min. Max. Min. Max. Max. Min. Max. Max. 3 3 4 4 Strength V V V V V VmAmA mA mA µA µA 2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10 4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 25 33 10 10 6 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 6 6 32 39 10 10 8 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 8 8 66 55 10 10 12 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12 66 55 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R to VCCI for t / t / t LZ ZL ZLS R = 1 k Test Point R to GND for t / t / t HZ ZH ZHS Test Point Datapath 35 pF Enable Path 5 pF for t / t / t / t ZH ZHS ZL ZLS 5 pF for t / t HZ LZ Figure 2-10 • AC Loading Table 2-58 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) C (pF) LOAD 0 1.5 0.75 – 5 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Revision 9 2-43 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-59 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V J Speed Drive Strength Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 2 mA Std. 0.97 7.61 0.18 1.47 1.77 0.66 7.76 6.33 2.81 2.34 11.36 9.92 ns 4 mA Std. 0.97 6.54 0.18 1.47 1.77 0.66 6.67 5.56 3.09 2.88 10.26 9.16 ns 6 mA Std. 0.97 6.15 0.18 1.47 1.77 0.66 6.27 5.42 3.15 3.02 9.87 9.02 ns 8 mA Std. 0.97 6.07 0.18 1.47 1.77 0.66 6.20 5.42 2.64 3.56 9.79 9.02 ns 12 mA Std. 0.97 6.07 0.18 1.47 1.77 0.66 6.20 5.42 2.64 3.56 9.79 9.02 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-60 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Commercial-Case Conditions: T J Speed Drive Strength Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 2 mA Std. 0.97 3.25 0.18 1.47 1.77 0.66 3.32 3.00 2.80 2.43 6.92 6.59 ns 4 mA Std. 0.97 2.81 0.18 1.47 1.77 0.66 2.87 2.51 3.08 2.97 6.46 6.10 ns 6 mA Std. 0.97 2.72 0.18 1.47 1.77 0.66 2.78 2.41 3.14 3.12 6.37 6.01 ns 8 mA Std. 0.97 2.69 0.18 1.47 1.77 0.66 2.75 2.30 3.24 3.67 6.35 5.89 ns 12 mA Std. 0.97 2.69 0.18 1.47 1.77 0.66 2.75 2.30 3.24 3.67 6.35 5.89 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2-44 Revision 9 IGLOOe Low Power Flash FPGAs 1.2 V DC Core Voltage Table 2-61 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V J Speed Drive Strength Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 2 mA Std. 1.55 8.53 0.26 1.72 2.16 1.10 8.67 7.05 3.39 3.09 14.46 12.83 ns 4 mA Std. 1.55 7.34 0.26 1.72 2.16 1.10 7.46 6.22 3.70 3.73 13.25 12.01 ns 6 mA Std. 1.55 6.91 0.26 1.72 2.16 1.10 7.03 6.07 3.77 3.90 12.82 11.85 ns 8 mA Std. 1.55 6.83 0.26 1.72 2.16 1.10 6.94 6.07 2.91 4.54 12.73 11.86 ns 12 mA Std. 1.55 6.83 0.26 1.72 2.16 1.10 6.94 6.07 2.91 4.54 12.73 11.86 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Table 2-62 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Commercial-Case Conditions: T J Speed Drive Strength Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 2 mA Std. 1.55 3.72 0.26 1.72 2.16 1.10 3.78 3.45 3.38 3.19 9.56 9.24 ns 4 mA Std. 1.55 3.23 0.26 1.72 2.16 1.10 3.27 2.92 3.69 3.83 9.06 8.71 ns 6 mA Std. 1.55 3.13 0.26 1.72 2.16 1.10 3.18 2.82 3.76 4.01 8.96 8.61 ns 8 mA Std. 1.55 3.10 0.26 1.72 2.16 1.10 3.15 2.70 3.86 4.68 8.93 8.49 ns 12 mA Std. 1.55 3.10 0.26 1.72 2.16 1.10 3.15 2.70 3.86 4.68 8.93 8.49 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Revision 9 2-45 IGLOOe DC and Switching Characteristics 1.2 V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-63 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.2 V 1 2 3 LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Min. Max. Min. Max. Max. Min. Max. Max. 4 4 5 5 Strength V V V V V VmAmA mA mA µA µA 2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 TBD TBD 10 10 Notes: 1. Applicable to V2 devices ONLY. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 4. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 5. Currents are measured at 85°C junction temperature. 6. Software default selection highlighted in gray. R to VCCI for t / t / t LZ ZL ZLS R = 1 k R to GND for t / t / t Test Point HZ ZH ZHS Test Point Datapath 5 pF Enable Path 5 pF for t / t / t / t ZH ZHS ZL ZLS 5 pF for t / t HZ LZ Figure 2-11 • AC Loading Table 2-64 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) C (pF) LOAD 01.2 0.6 – 5 Note: *Measuring point = Vtrip See Table 2-22 on page 2-23 for a complete table of trip points. . 2-46 Revision 9 IGLOOe Low Power Flash FPGAs Timing Characteristics 1.2 V DC Core Voltage Table 2-65 • 1.2 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V J Speed Drive Strength Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 2 mA Std. 1.55 9.92 0.26 2.09 2.95 1.10 9.53 7.48 4.02 3.67 15.31 13.26 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Table 2-66 • 1.2 LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V J Speed Drive Strength Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS 2 mA Std. 1.55 4.06 0.26 2.09 2.95 1.10 3.92 3.46 4.01 3.79 9.71 9.24 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 1.2 V LVCMOS Wide Range Table 2-67 • Minimum and Maximum DC Input and Output Levels 1.2 V LVCMOS 1 2 3 Wide Range VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Equivalent Software Default Drive Drive Strength Min. Max. Min. Max Max. Min. Max. Max. 4 5 5 6 6 Strength Option (V) (V) (V) (V) (V) (V) µA µA (mA) (mA) µA µA 100 µA 2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 100 100 TBD TBD 10 10 Notes: 1. Applicable to V2 devices ONLY. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 4. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 5. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 6. Currents are measured at 85°C junction temperature. 7. Software default selection highlighted in gray. Timing Characteristics Refer to LVCMOS 1.2 V (normal range) "Timing Characteristics" on page 2-47 for worst-case timing. Revision 9 2-47 IGLOOe DC and Switching Characteristics 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-68 • Minimum and Maximum DC Input and Output Levels 1 2 3.3 V PCI/PCI-X VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Min. Max. Min., Max. Max. Min. Max. Max. 3 3 4 4 Drive Strength V V V V V VmAmA mA mA µA µA Per PCI Per PCI curves 10 10 specification Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI . Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable path characterization are described in Figure 2-12. R to VCCI for t / t / t R to VCCI for t (F) LZ ZL ZLS DP R = 25 R = 1 k R to GND for t (R) R to GND for t / t / t DP HZ ZH ZHS Test Point Test Point Datapath Enable Path 10 pF for t / t / t / t ZH ZHS ZL ZLS 10 pF for t / t HZ LZ Figure 2-12 • AC Loading AC loadings are defined per PCI/PCI-X specifications for the datapath; Microsemi loading for tristate is described in Table 2-69. Table 2-69 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) C (pF) LOAD 0 3.3 0.285 * VCCI for t –10 DP(R) 0.615 * VCCI for t DP(F) Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2-48 Revision 9 IGLOOe Low Power Flash FPGAs Timing Characteristics 1.5 V DC Core Voltage Table 2-70 • 3.3 V PCI/PCI-X – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V J Speed Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS Std. 0.97 2.38 0.18 0.96 1.42 0.66 2.43 1.80 2.72 3.08 6.03 5.39 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-71 • 3.3 V PCI/PCI-X – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V J Speed Grade t t t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ ZLS ZHS Std. 1.55 2.76 0.26 1.19 1.63 1.10 2.79 2.16 3.29 3.97 8.58 7.94 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Revision 9 2-49 IGLOOe DC and Switching Characteristics Voltage-Referenced I/O Characteristics 3.3 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V. Table 2-72 • Minimum and Maximum DC Input and Output Levels 1 2 3.3 V GTL VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Min. Max. Min. Max. Max Min. Max. Max. 3 3 4 4 Strength V V V V V VmAmA mA mA µA µA 5 25 mA –0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25 268 181 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Output drive strength is below JEDEC specification. VTT GTL 25 Test Point 10 pF Figure 2-13 • AC Loading Table 2-73 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C (pF) LOAD VREF – 0.05 VREF + 0.05 0.8 0.8 1.2 10 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2-50 Revision 9 IGLOOe Low Power Flash FPGAs Timing Characteristics 1.5 V DC Core Voltage Table 2-74 • 3.3 V GTL – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCI = 3.0 V VREF = 0.8 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 0.98 1.83 0.19 2.41 0.67 1.84 1.83 5.47 5.46 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-75 • 3.3 V GTL – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, J Worst-Case VCCI = 3.0 V VREF = 0.8 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 1.55 2.09 0.26 2.75 1.10 2.10 2.09 7.91 7.89 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Revision 9 2-51 IGLOOe DC and Switching Characteristics 2.5 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Table 2-76 • Minimum and Maximum DC Input and Output Levels 1 2 2.5 GTL VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Min. Max. Min. Max. Max. Min. Max. Max. 3 3 4 4 Strength V V V V V VmAmA mA mA µA µA 5 25 mA –0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25 169 124 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Output drive strength is below JEDEC specification. VTT GTL 25 Test Point 10 pF Figure 2-14 • AC Loading Table 2-77 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C (pF) LOAD VREF – 0.05 VREF + 0.05 0.8 0.8 1.2 10 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Timing Characteristics 1.5 V DC Core Voltage Table 2-78 • 2.5 V GTL – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCI = 3.0 V VREF = 0.8 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 0.98 1.90 0.19 2.04 0.67 1.94 1.87 5.57 5.50 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-79 • 2.5 V GTL – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, J Worst-Case VCCI = 3.0 V VREF = 0.8 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 1.55 2.16 0.26 2.35 1.10 2.20 2.13 8.01 7.94 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2-52 Revision 9 IGLOOe Low Power Flash FPGAs 3.3 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V Table 2-80 • Minimum and Maximum DC Input and Output Levels 1 2 3.3 V GTL+ VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Min. Max. Min. Max. Max. Min. Max. Max. 3 3 4 4 Strength V V V V V VmAmA mA mA µA µA 35 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 35 35 268 181 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. V TT GTL+ 25 Test Point 10 pF Figure 2-15 • AC Loading Table 2-81 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C (pF) LOAD VREF – 0.1 VREF + 0.1 1.0 1.0 1.5 10 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Timing Characteristics 1.5 V DC Core Voltage Table 2-82 • 3.3 V GTL+ – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCI = 3.0 V VREF = 1.0 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 0.98 1.85 0.19 1.35 0.67 1.88 1.81 5.51 5.44 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-83 • 3.3 V GTL+ – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, J Worst-Case VCCI = 3.0 V VREF = 1.0 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 1.55 2.11 0.26 1.61 1.10 2.15 2.07 7.95 7.88 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Revision 9 2-53 IGLOOe DC and Switching Characteristics 2.5 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Table 2-84 • Minimum and Maximum DC Input and Output Levels 1 2 2.5 V GTL+ VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Min. Max. Min. Max. Max. Min. Max. Max. 3 3 4 4 Strength V V V V V VmAmA mA mA µA µA 33 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 33 33 169 124 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. V TT GTL+ 25 Test Point 10 pF Figure 2-16 • AC Loading Table 2-85 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C (pF) LOAD VREF – 0.1 VREF + 0.1 1.0 1.0 1.5 10 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Timing Characteristics 1.5 V DC Core Voltage Table 2-86 • 2.5 V GTL+ – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCI = 2.3 V VREF = 1.0 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 0.98 1.97 0.19 1.29 0.67 2.00 1.84 5.63 5.47 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-87 • 2.5 V GTL+ – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, J Worst-Case VCCI = 2.3 V VREF = 1.0 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 1.55 2.23 0.26 1.55 1.10 2.28 2.11 8.08 7.91 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2-54 Revision 9 IGLOOe Low Power Flash FPGAs HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-88 • Minimum and Maximum DC Input and Output Levels HSTL Class 1 2 I VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Min. Max. Min. Max. Max. Min. Max. Max. 3 3 4 4 Strength V V V V V VmAmA mA mA µA µA 8 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 8 8 32 39 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. V TT HSTL Class I 50 Test Point 20 pF Figure 2-17 • AC Loading Table 2-89 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C (pF) LOAD VREF – 0.1 VREF + 0.1 0.75 0.75 0.75 20 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Timing Characteristics 1.5 V DC Core Voltage Table 2-90 • HSTL Class I – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCI = 1.4 V VREF = 0.75 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 0.98 2.74 0.19 1.77 0.67 2.79 2.73 6.42 6.36 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-91 • HSTL Class I – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, J Worst-Case VCCI = 1.4 V VREF = 0.75 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 1.55 3.10 0.26 1.94 1.10 3.12 3.10 8.93 8.91 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Revision 9 2-55 IGLOOe DC and Switching Characteristics HSTL Class II High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-92 • Minimum and Maximum DC Input and Output Levels HSTL 1 2 Class II VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Min. Max. Min. Max. Max. Min. Max. Max. 3 3 4 4 Strength V V V V V VmAmA mA mA µA µA 5 15 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 15 15 66 55 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Output drive strength is below JEDEC specification. V TT HSTL Class II 25 Test Point 20 pF Figure 2-18 • AC Loading Table 2-93 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C (pF) LOAD VREF – 0.1 VREF + 0.1 0.75 0.75 0.75 20 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Timing Characteristics 1.5 V DC Core Voltage Table 2-94 • HSTL Class II – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCI = 1.4 V VREF = 0.75 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 0.98 2.62 0.19 1.77 0.67 2.66 2.40 6.29 6.03 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-95 • HSTL Class II – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, J Worst-Case VCCI = 1.4 V VREF = 0.75 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 1.55 2.93 0.26 1.94 1.10 2.98 2.75 8.79 8.55 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2-56 Revision 9 IGLOOe Low Power Flash FPGAs SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-96 • Minimum and Maximum DC Input and Output Levels SSTL2 1 2 Class I VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Min. Max. Min. Max. Max. Min. Max. Max. 3 3 4 4 Strength V V V V V VmAmA mA mA µA µA 15 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.54 VCCI – 0.62 15 15 83 87 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. V TT SSTL2 Class I 50 Test Point 25 30 pF Figure 2-19 • AC Loading Table 2-97 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C (pF) LOAD VREF – 0.2 VREF + 0.2 1.25 1.25 1.25 30 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Timing Characteristics 1.5 V DC Core Voltage Table 2-98 • SSTL 2 Class I – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCI = 2.3 V VREF = 1.25 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 0.98 1.91 0.19 1.15 0.67 1.94 1.72 5.57 5.35 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-99 • SSTL 2 Class I – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, J Worst-Case VCCI = 2.3 V VREF = 1.25 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 1.55 2.17 0.26 1.39 1.10 2.21 2.04 8.02 7.84 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Revision 9 2-57 IGLOOe DC and Switching Characteristics SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-100 • Minimum and Maximum DC Input and Output Levels SSTL2 1 2 Class II VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Min. Max. Min. Max. Max. Min. Max. Max. 3 3 4 4 Strength V V V V V VmAmA mA mA µA µA 18 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.35 VCCI – 0.43 18 18 169 124 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. V TT SSTL2 Class II 25 Test Point 25 30 pF Figure 2-20 • AC Loading Table 2-101 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C (pF) LOAD VREF – 0.2 VREF + 0.2 1.25 1.25 1.25 30 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Timing Characteristics 1.5 V DC Core Voltage Table 2-102 • SSTL 2 Class II – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCI = 2.3 V VREF = 1.25 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 0.98 1.94 0.19 1.15 0.67 1.97 1.66 5.60 5.29 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-103 • SSTL 2 Class II – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, J Worst-Case VCCI = 2.3 V VREF = 1.25 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 1.55 2.20 0.26 1.39 1.10 2.24 1.97 8.05 7.78 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2-58 Revision 9 IGLOOe Low Power Flash FPGAs SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-104 • Minimum and Maximum DC Input and Output Levels 1 2 SSTL3 Class I VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Min. Max. Min. Max. Max. Min. Max. Max. 3 3 4 4 Strength V V V V V VmAmA mA mA µA µA 14 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.7 VCCI – 1.1 14 14 51 54 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. V TT SSTL3 Class I 50 Test Point 25 30 pF Figure 2-21 • AC Loading Table 2-105 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C (pF) LOAD VREF – 0.2 VREF + 0.2 1.5 1.5 1.485 30 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Timing Characteristics 1.5 V DC Core Voltage Table 2-106 • SSTL 3 Class I – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCI = 3.0 V VREF = 1.5 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 0.98 2.05 0.19 1.09 0.67 2.09 1.71 5.72 5.34 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-107 • SSTL 3 Class I – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, J Worst-Case VCCI = 3.0 V VREF = 1.5 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 1.55 2.32 0.26 1.32 1.10 2.37 2.02 8.17 7.83 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Revision 9 2-59 IGLOOe DC and Switching Characteristics SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-108 • Minimum and Maximum DC Input and Output Levels 1 2 SSTL3 Class II VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Min. Max. Min. Max. Max. Min. Max. Max. 3 3 4 4 Drive Strength V V V V V VmAmA mA mA µA µA 21 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.5 VCCI – 0.9 21 21 103 109 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. V TT SSTL3 Class II 25 Test Point 25 30 pF Figure 2-22 • AC Loading Table 2-109 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C (pF) LOAD VREF – 0.2 VREF + 0.2 1.5 1.5 1.485 30 Note: Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Timing Characteristics 1.5 V DC Core Voltage Table 2-110 • SSTL 3 Class II – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 1.5 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 0.98 1.86 0.19 1.09 0.67 1.89 1.58 5.52 5.21 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-111 • SSTL 3 Class II – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, J Worst-Case VCCI = 3.0 V VREF = 1.5 V Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 1.55 2.12 0.26 1.32 1.10 2.16 1.89 7.97 7.70 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2-60 Revision 9 IGLOOe Low Power Flash FPGAs Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by the Microsemi Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and DDR. However, there is no support for bidirectional I/Os or tristates with the LVPECL standards. LVDS Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit be carried through two signal lines, so two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-23. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different. Along with LVDS I/O, IGLOOe also supports Bus LVDS structure and Multipoint LVDS (M-LVDS) configuration (up to 40 nodes). Bourns Part Number: CAT16-LV4F12 FPGA FPGA OUTBUF_LVDS P P 165 Ω Z = 50 Ω 0 INBUF_LVDS + 140 Ω 100 Ω – Z = 50 Ω 165 Ω 0 N N Figure 2-23 • LVDS Circuit Diagram and Board-Level Implementation Revision 9 2-61 IGLOOe DC and Switching Characteristics Table 2-112 • Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Typ. Max. Units VCCI Supply Voltage 2.375 2.5 2.625 V VOL Output Low Voltage 0.9 1.075 1.25 V VOH Output High Voltage 1.25 1.425 1.6 V 1 IOL Output Lower Current 0.65 0.91 1.16 mA 1 IOH Output High Current 0.65 0.91 1.16 mA VI Input Voltage 0 2.925 V 2,3 IIH Input High Leakage Current 10 µA 2,4 IIL Input Low Leakage Current 10 µA VODIFF Differential Output Voltage 250 350 450 mV VOCM Output Common Mode Voltage 1.125 1.25 1.375 V VICM Input Common Mode Voltage 0.05 1.25 2.35 V VIDIFF Input Differential Voltage 100 350 mV Notes: 1. IOL/IOH is defined by VODIFF/(resistor network). 2. Currents are measured at 85°C junction temperature. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 4. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. Table 2-113 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) 1.075 1.325 Cross point – Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Timing Characteristics 1.5 V DC Core Voltage Table 2-114 • LVDS – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V J Speed Grade t t t t Units DOUT DP DIN PY Std. 0.98 1.77 0.19 1.62 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-115 • LVDS – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V J Speed Grade t t t t Units DOUT DP DIN PY Std. 1.55 2.19 0.26 1.88 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2-62 Revision 9 IGLOOe Low Power Flash FPGAs B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-24. The input and output buffer delays are available in the LVDS section in Table 2-114 on page 2-62 and Table 2-115 on page 2-62. Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: R =60 Ω and S R =70 Ω, given Z =50 Ω (2") and Z =50 Ω (~1.5"). T 0 stub Receiver Transceiver Driver Receiver Transceiver EN EN D EN EN EN BIBUF_LVDS R T R T + - + - + - + - + - R R R R R R R R R R S S S S S S S S S S Z Z Z Z Z Z Z Z ... stub stub stub stub stub stub stub stub Z Z Z Z Z Z 0 0 0 0 0 0 R R T Z Z Z Z Z Z T 0 0 0 0 0 0 Figure 2-24 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-25. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation because the output standard specifications are different. Bourns Part Number: CAT16-PC4F12 FPGA FPGA P P OUTBUF_LVPECL 100 Ω Z = 50 Ω 0 INBUF_LVPECL + 187 W 100 Ω – Z = 50 Ω 100 Ω 0 N N Figure 2-25 • LVPECL Circuit Diagram and Board-Level Implementation Revision 9 2-63 IGLOOe DC and Switching Characteristics Table 2-116 • Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Max. Min. Max. Min. Max. Units VCCI Supply Voltage 3.0 3.3 3.6 V VOL Output Low Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V VOH Output High Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V VIL, VIH Input Low, Input High Voltages 0 3.3 0 3.6 0 3.9 V V Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V ODIFF V Output Common Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V OCM V Input Common Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V ICM V Input Differential Voltage 300 300 300 mV IDIFF Table 2-117 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) 1.64 1.94 Cross point – Note: *Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Timing Characteristics 1.5 V DC Core Voltage Table 2-118 • LVPECL – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V J Speed Grade t t t t Units DOUT DP DIN PY Std. 0.98 1.75 0.19 1.45 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-119 • LVPECL – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V J Speed Grade t t t t Units DOUT DP DIN PY Std. 1.55 2.16 0.26 1.70 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2-64 Revision 9 TRIBUF INBUF INBUF INBUF CLKBUF Pad Out IGLOOe Low Power Flash FPGAs I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset L D DOUT Data_out PRE Y F PRE E Core Data DQ DQ Array C DFN1E1P1 G DFN1E1P1 E E Enable EOUT B H I CLK A PRE J DQ DFN1E1P1 K Data Input I/O Register with: E Active High Enable Active High Preset Positive-Edge Triggered Data Output Register and Enable Output Register with: Active High Enable Active High Preset CLKBUF INBUF INBUF Postive-Edge Triggered Figure 2-26 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Revision 9 2-65 CLK Enable D_Enable IGLOOe DC and Switching Characteristics Table 2-120 • Parameter Definition and Measuring Nodes Measuring Nodes Parameter Name Parameter Definition (from, to)* t Clock-to-Q of the Output Data Register H, DOUT OCLKQ t Data Setup Time for the Output Data Register F, H OSUD t Data Hold Time for the Output Data Register F, H OHD t Enable Setup Time for the Output Data Register G, H OSUE t Enable Hold Time for the Output Data Register G, H OHE t Asynchronous Preset-to-Q of the Output Data Register L, DOUT OPRE2Q t Asynchronous Preset Removal Time for the Output Data Register L, H OREMPRE t Asynchronous Preset Recovery Time for the Output Data Register L, H ORECPRE t Clock-to-Q of the Output Enable Register H, EOUT OECLKQ t Data Setup Time for the Output Enable Register J, H OESUD t Data Hold Time for the Output Enable Register J, H OEHD t Enable Setup Time for the Output Enable Register K, H OESUE t Enable Hold Time for the Output Enable Register K, H OEHE t Asynchronous Preset-to-Q of the Output Enable Register I, EOUT OEPRE2Q t Asynchronous Preset Removal Time for the Output Enable Register I, H OEREMPRE t Asynchronous Preset Recovery Time for the Output Enable Register I, H OERECPRE t Clock-to-Q of the Input Data Register A, E ICLKQ t Data Setup Time for the Input Data Register C, A ISUD t Data Hold Time for the Input Data Register C, A IHD t Enable Setup Time for the Input Data Register B, A ISUE t Enable Hold Time for the Input Data Register B, A IHE t Asynchronous Preset-to-Q of the Input Data Register D, E IPRE2Q t Asynchronous Preset Removal Time for the Input Data Register D, A IREMPRE t Asynchronous Preset Recovery Time for the Input Data Register D, A IRECPRE Note: See Figure 2-26 on page 2-65 for more information. 2-66 Revision 9 TRIBUF INBUF INBUF CLKBUF INBUF Pad Out IGLOOe Low Power Flash FPGAs Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear DOUT FF Data_out Y Core DQ DQ Data Array CC EE DFN1E1C1 DFN1E1C1 GG EOUT E E Enable CLR BB CLR LL HH CLK AA JJ DQ CLR DD DFN1E1C1 KK E Data Input I/O Register with CLR Active High Enable Active High Clear Positive-Edge Triggered Data Output Register and Enable Output Register with Active High Enable Active High Clear INBUF INBUF CLKBUF Positive-Edge Triggered Figure 2-27 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Revision 9 2-67 Enable D_Enable CLK IGLOOe DC and Switching Characteristics Table 2-121 • Parameter Definition and Measuring Nodes Measuring Nodes Parameter Name Parameter Definition (from, to)* t Clock-to-Q of the Output Data Register HH, DOUT OCLKQ t Data Setup Time for the Output Data Register FF, HH OSUD t Data Hold Time for the Output Data Register FF, HH OHD t Enable Setup Time for the Output Data Register GG, HH OSUE t Enable Hold Time for the Output Data Register GG, HH OHE t Asynchronous Clear-to-Q of the Output Data Register LL, DOUT OCLR2Q t Asynchronous Clear Removal Time for the Output Data Register LL, HH OREMCLR t Asynchronous Clear Recovery Time for the Output Data Register LL, HH ORECCLR t Clock-to-Q of the Output Enable Register HH, EOUT OECLKQ t Data Setup Time for the Output Enable Register JJ, HH OESUD t Data Hold Time for the Output Enable Register JJ, HH OEHD t Enable Setup Time for the Output Enable Register KK, HH OESUE t Enable Hold Time for the Output Enable Register KK, HH OEHE t Asynchronous Clear-to-Q of the Output Enable Register II, EOUT OECLR2Q t Asynchronous Clear Removal Time for the Output Enable Register II, HH OEREMCLR t Asynchronous Clear Recovery Time for the Output Enable Register II, HH OERECCLR t Clock-to-Q of the Input Data Register AA, EE ICLKQ t Data Setup Time for the Input Data Register CC, AA ISUD t Data Hold Time for the Input Data Register CC, AA IHD t Enable Setup Time for the Input Data Register BB, AA ISUE t Enable Hold Time for the Input Data Register BB, AA IHE t Asynchronous Clear-to-Q of the Input Data Register DD, EE ICLR2Q t Asynchronous Clear Removal Time for the Input Data Register DD, AA IREMCLR t Asynchronous Clear Recovery Time for the Input Data Register DD, AA IRECCLR Note: *See Figure 2-27 on page 2-67 for more information. 2-68 Revision 9 IGLOOe Low Power Flash FPGAs Input Register t t ICKMPWH ICKMPWL 50% 50% 50% 50% 50% 50% 50% CLK t IHD t ISUD 1 50% 0 50% Data t t t Enable 50% IRECPRE IREMPRE IWPRE t IHE 50% 50% 50% t ISUE Preset t t t IWCLR IRECCLR IREMCLR 50% 50% 50% Clear t IPRE2Q 50% 50% 50% Out_1 t ICLR2Q t ICLKQ Figure 2-28 • Input Register Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-122 • Input Data Register Propagation Delays Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V J Parameter Description Std. Units t Clock-to-Q of the Input Data Register 0.42 ns ICLKQ t Data Setup Time for the Input Data Register 0.47 ns ISUD t Data Hold Time for the Input Data Register 0.00 ns IHD t Enable Setup Time for the Input Data Register 0.67 ns ISUE t Enable Hold Time for the Input Data Register 0.00 ns IHE t Asynchronous Clear-to-Q of the Input Data Register 0.79 ns ICLR2Q t Asynchronous Preset-to-Q of the Input Data Register 0.79 ns IPRE2Q t Asynchronous Clear Removal Time for the Input Data Register 0.00 ns IREMCLR t Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns IRECCLR t Asynchronous Preset Removal Time for the Input Data Register 0.00 ns IREMPRE t Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns IRECPRE t Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns IWCLR t Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns IWPRE t Clock Minimum Pulse Width HIGH for the Input Data Register 0.31 ns ICKMPWH t Clock Minimum Pulse Width LOW for the Input Data Register 0.28 ns ICKMPWL Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Revision 9 2-69 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-123 • Input Data Register Propagation Delays Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V J Parameter Description Std. Units t Clock-to-Q of the Input Data Register 0.68 ns ICLKQ t Data Setup Time for the Input Data Register 0.97 ns ISUD t Data Hold Time for the Input Data Register 0.00 ns IHD t Enable Setup Time for the Input Data Register 1.02 ns ISUE t Enable Hold Time for the Input Data Register 0.00 ns IHE t Asynchronous Clear-to-Q of the Input Data Register 1.19 ns ICLR2Q t Asynchronous Preset-to-Q of the Input Data Register 1.19 ns IPRE2Q t Asynchronous Clear Removal Time for the Input Data Register 0.00 ns IREMCLR t Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns IRECCLR t Asynchronous Preset Removal Time for the Input Data Register 0.00 ns IREMPRE t Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns IRECPRE t Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns IWCLR t Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns IWPRE t Clock Minimum Pulse Width HIGH for the Input Data Register 0.31 ns ICKMPWH t Clock Minimum Pulse Width LOW for the Input Data Register 0.28 ns ICKMPWL Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2-70 Revision 9 IGLOOe Low Power Flash FPGAs Output Register t t OCKMPWH OCKMPWL 50% 50% 50% 50% 50% 50% 50% CLK t t OSUD OHD 1 50% 0 50% Data_out t OREMPRE Enable 50% t t OWPRE ORECPRE t OHE 50% 50% 50% t Preset OSUE t t OREMCLR t ORECCLR OWCLR 50% 50% 50% Clear t OPRE2Q 50% 50% 50% DOUT t OCLR2Q t OCLKQ Figure 2-29 • Output Register Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-124 • Output Data Register Propagation Delays Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V J Parameter Description Std. Units t Clock-to-Q of the Output Data Register 1.00 ns OCLKQ t Data Setup Time for the Output Data Register 0.51 ns OSUD t Data Hold Time for the Output Data Register 0.00 ns OHD t Enable Setup Time for the Output Data Register 0.70 ns OSUE t Enable Hold Time for the Output Data Register 0.00 ns OHE t Asynchronous Clear-to-Q of the Output Data Register 1.34 ns OCLR2Q t Asynchronous Preset-to-Q of the Output Data Register 1.34 ns OPRE2Q t Asynchronous Clear Removal Time for the Output Data Register 0.00 ns OREMCLR t Asynchronous Clear Recovery Time for the Output Data Register 0.24 ns ORECCLR t Asynchronous Preset Removal Time for the Output Data Register 0.00 ns OREMPRE t Asynchronous Preset Recovery Time for the Output Data Register 0.24 ns ORECPRE t Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 ns OWCLR t Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 ns OWPRE t Clock Minimum Pulse Width HIGH for the Output Data Register 0.31 ns OCKMPWH t Clock Minimum Pulse Width LOW for the Output Data Register 0.28 ns OCKMPWL Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Revision 9 2-71 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-125 • Output Data Register Propagation Delays Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V J Parameter Description Std. Units t Clock-to-Q of the Output Data Register 1.52 ns OCLKQ t Data Setup Time for the Output Data Register 1.15 ns OSUD t Data Hold Time for the Output Data Register 0.00 ns OHD t Enable Setup Time for the Output Data Register 1.11 ns OSUE t Enable Hold Time for the Output Data Register 0.00 ns OHE t Asynchronous Clear-to-Q of the Output Data Register 1.96 ns OCLR2Q t Asynchronous Preset-to-Q of the Output Data Register 1.96 ns OPRE2Q t Asynchronous Clear Removal Time for the Output Data Register 0.00 ns OREMCLR t Asynchronous Clear Recovery Time for the Output Data Register 0.24 ns ORECCLR t Asynchronous Preset Removal Time for the Output Data Register 0.00 ns OREMPRE t Asynchronous Preset Recovery Time for the Output Data Register 0.24 ns ORECPRE t Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 ns OWCLR t Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 ns OWPRE t Clock Minimum Pulse Width HIGH for the Output Data Register 0.31 ns OCKMPWH t Clock Minimum Pulse Width LOW for the Output Data Register 0.28 ns OCKMPWL Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2-72 Revision 9 IGLOOe Low Power Flash FPGAs Output Enable Register t t OECKMPWH OECKMPWL 50% 50% 50% 50% 50% 50% 50% CLK t t OESUD OEHD 1 50% 0 50% D_Enable 50% Enable t t OEWPRE OEREMPRE t OERECPRE 50% 50% 50% t t OESUEOEHE Preset t t t OEWCLR OERECCLR OEREMCLR 50% 50% 50% Clear t t OECLR2Q OEPRE2Q 50% 50% 50% EOUT t OECLKQ Figure 2-30 • Output Enable Register Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-126 • Output Enable Register Propagation Delays Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V J Parameter Description Std. Units t Clock-to-Q of the Output Enable Register 0.75 ns OECLKQ t Data Setup Time for the Output Enable Register 0.51 ns OESUD t Data Hold Time for the Output Enable Register 0.00 ns OEHD t Enable Setup Time for the Output Enable Register 0.73 ns OESUE t Enable Hold Time for the Output Enable Register 0.00 ns OEHE t Asynchronous Clear-to-Q of the Output Enable Register 1.13 ns OECLR2Q t Asynchronous Preset-to-Q of the Output Enable Register 1.13 ns OEPRE2Q t Asynchronous Clear Removal Time for the Output Enable Register 0.00 ns OEREMCLR t Asynchronous Clear Recovery Time for the Output Enable Register 0.24 ns OERECCLR t Asynchronous Preset Removal Time for the Output Enable Register 0.00 ns OEREMPRE t Asynchronous Preset Recovery Time for the Output Enable Register 0.24 ns OERECPRE t Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 ns OEWCLR t Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 ns OEWPRE t Clock Minimum Pulse Width HIGH for the Output Enable Register 0.31 ns OECKMPWH t Clock Minimum Pulse Width LOW for the Output Enable Register 0.28 ns OECKMPWL Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Revision 9 2-73 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-127 • Output Enable Register Propagation Delays Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V J Parameter Description Std. Units t Clock-to-Q of the Output Enable Register 1.10 ns OECLKQ t Data Setup Time for the Output Enable Register 1.15 ns OESUD t Data Hold Time for the Output Enable Register 0.00 ns OEHD t Enable Setup Time for the Output Enable Register 1.22 ns OESUE t Enable Hold Time for the Output Enable Register 0.00 ns OEHE t Asynchronous Clear-to-Q of the Output Enable Register 1.65 ns OECLR2Q t Asynchronous Preset-to-Q of the Output Enable Register 1.65 ns OEPRE2Q t Asynchronous Clear Removal Time for the Output Enable Register 0.00 ns OEREMCLR t Asynchronous Clear Recovery Time for the Output Enable Register 0.24 ns OERECCLR t Asynchronous Preset Removal Time for the Output Enable Register 0.00 ns OEREMPRE t Asynchronous Preset Recovery Time for the Output Enable Register 0.24 ns OERECPRE t Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 ns OEWCLR t Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 ns OEWPRE t Clock Minimum Pulse Width HIGH for the Output Enable Register 0.31 ns OECKMPWH t Clock Minimum Pulse Width LOW for the Output Enable Register 0.28 ns OECKMPWL Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2-74 Revision 9 IGLOOe Low Power Flash FPGAs DDR Module Specifications Input DDR Module Input DDR INBUF A D Out_QF Data (to core) FF1 B E Out_QR CLK (to core) CLKBUF FF2 C CLR INBUF DDR_IN Figure 2-31 • Input DDR Timing Model Table 2-128 • Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) t Clock-to-Out Out_QR B, D DDRICLKQ1 t Clock-to-Out Out_QF B, E DDRICLKQ2 t Data Setup Time of DDR input A, B DDRISUD t Data Hold Time of DDR input A, B DDRIHD t Clear-to-Out Out_QR C, D DDRICLR2Q1 t Clear-to-Out Out_QF C, E DDRICLR2Q2 t Clear Removal C, B DDRIREMCLR t Clear Recovery C, B DDRIRECCLR Revision 9 2-75 IGLOOe DC and Switching Characteristics CLK t t DDRISUD DDRIHD Data 12 3 4 5 6 7 8 9 t DDRIRECCLR CLR t DDRIREMCLR t DDRICLKQ1 t DDRICLR2Q1 Out_QF 2 4 6 t DDRICLKQ2 t DDRICLR2Q2 Out_QR 7 3 5 Figure 2-32 • Input DDR Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-129 • Input DDR Propagation Delays Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V J Parameter Description Std. Units t Clock-to-Out Out_QR for Input DDR 0.48 ns DDRICLKQ1 t Clock-to-Out Out_QF for Input DDR 0.65 ns DDRICLKQ2 t Data Setup for Input DDR (negedge) 0.50 ns DDRISUD1 t Data Setup for Input DDR (posedge) 0.40 ns DDRISUD2 t Data Hold for Input DDR (negedge) 0.00 ns DDRIHD1 t Data Hold for Input DDR (posedge) 0.00 ns DDRIHD2 t Asynchronous Clear to Out Out_QR for Input DDR 0.82 ns DDRICLR2Q1 t Asynchronous Clear-to-Out Out_QF for Input DDR 0.98 ns DDRICLR2Q2 t Asynchronous Clear Removal Time for Input DDR 0.00 ns DDRIREMCLR t Asynchronous Clear Recovery Time for Input DDR 0.23 ns DDRIRECCLR t Asynchronous Clear Minimum Pulse Width for Input DDR 0.19 ns DDRIWCLR t Clock Minimum Pulse Width HIGH for Input DDR 0.31 ns DDRICKMPWH t Clock Minimum Pulse Width LOW for Input DDR 0.28 ns DDRICKMPWL F Maximum Frequency for Input DDR MHz DDRIMAX Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2-76 Revision 9 IGLOOe Low Power Flash FPGAs 1.2 V DC Core Voltage Table 2-130 • Input DDR Propagation Delays Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V J Parameter Description Std. Units t Clock-to-Out Out_QR for Input DDR 0.76 ns DDRICLKQ1 t Clock-to-Out Out_QF for Input DDR 0.94 ns DDRICLKQ2 t Data Setup for Input DDR (negedge) 0.93 ns DDRISUD1 t Data Setup for Input DDR (posedge) 0.84 ns DDRISUD2 t Data Hold for Input DDR (negedge) 0.00 ns DDRIHD1 t Data Hold for Input DDR (posedge) 0.00 ns DDRIHD2 t Asynchronous Clear to Out Out_QR for Input DDR 1.23 ns DDRICLR2Q1 t Asynchronous Clear-to-Out Out_QF for Input DDR 1.42 ns DDRICLR2Q2 t Asynchronous Clear Removal Time for Input DDR 0.00 ns DDRIREMCLR t Asynchronous Clear Recovery Time for Input DDR 0.24 ns DDRIRECCLR t Asynchronous Clear Minimum Pulse Width for Input DDR 0.19 ns DDRIWCLR t Clock Minimum Pulse Width HIGH for Input DDR 0.31 ns DDRICKMPWH t Clock Minimum Pulse Width LOW for Input DDR 0.28 ns DDRICKMPWL F Maximum Frequency for Input DDR MHz DDRIMAX Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Revision 9 2-77 IGLOOe DC and Switching Characteristics Output DDR Module Output DDR A Data_F X (from core) FF1 Out B 0 CLK X E CLKBUF C X X OUTBUF D 1 Data_R X (from core) FF2 B X CLR INBUF C X DDR_OUT Figure 2-33 • Output DDR Timing Model Table 2-131 • Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) t Clock-to-Out B, E DDROCLKQ t Asynchronous Clear-to-Out C, E DDROCLR2Q t Clear Removal C, B DDROREMCLR t Clear Recovery C, B DDRORECCLR t Data Setup Data_F A, B DDROSUD1 t Data Setup Data_R D, B DDROSUD2 t Data Hold Data_F A, B DDROHD1 t Data Hold Data_R D, B DDROHD2 2-78 Revision 9 IGLOOe Low Power Flash FPGAs CLK t t DDROHD2 DDROSUD2 45 Data_F 1 2 3 t t DDROHD1 DDROREMCLR Data_R 6 7 8 910 11 t DDRORECCLR t CLR DDROREMCLR t t DDROCLKQ DDROCLR2Q Out 71 28 3 9 40 Figure 2-34 • Output DDR Timing Diagram Revision 9 2-79 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-132 • Output DDR Propagation Delays Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V J Parameter Description Std. Units t Clock-to-Out of DDR for Output DDR 1.07 ns DDROCLKQ t Data_F Data Setup for Output DDR 0.67 ns DDROSUD1 t Data_R Data Setup for Output DDR 0.67 ns DDROSUD2 t Data_F Data Hold for Output DDR 0.00 ns DDROHD1 t Data_R Data Hold for Output DDR 0.00 ns DDROHD2 t Asynchronous Clear-to-Out for Output DDR 1.38 ns DDROCLR2Q t Asynchronous Clear Removal Time for Output DDR 0.00 ns DDROREMCLR t Asynchronous Clear Recovery Time for Output DDR 0.23 ns DDRORECCLR t Asynchronous Clear Minimum Pulse Width for Output DDR 0.19 ns DDROWCLR1 t Clock Minimum Pulse Width HIGH for the Output DDR 0.31 ns DDROCKMPWH t Clock Minimum Pulse Width LOW for the Output DDR 0.28 ns DDROCKMPWL F Maximum Frequency for the Output DDR MHz DDOMAX Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-133 • Output DDR Propagation Delays Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V J Parameter Description Std. Units t Clock-to-Out of DDR for Output DDR 1.60 ns DDROCLKQ t Data_F Data Setup for Output DDR 1.09 ns DDROSUD1 t Data_R Data Setup for Output DDR 1.16 ns DDROSUD2 t Data_F Data Hold for Output DDR 0.00 ns DDROHD1 t Data_R Data Hold for Output DDR 0.00 ns DDROHD2 t Asynchronous Clear-to-Out for Output DDR 1.99 ns DDROCLR2Q t Asynchronous Clear Removal Time for Output DDR 0.00 ns DDROREMCLR t Asynchronous Clear Recovery Time for Output DDR 0.24 ns DDRORECCLR t Asynchronous Clear Minimum Pulse Width for Output DDR 0.19 ns DDROWCLR1 t Clock Minimum Pulse Width HIGH for the Output DDR 0.31 ns DDROCKMPWH t Clock Minimum Pulse Width LOW for the Output DDR 0.28 ns DDROCKMPWL F Maximum Frequency for the Output DDR MHz DDOMAX Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2-80 Revision 9 IGLOOe Low Power Flash FPGAs VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The IGLOOe library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide. AY INV A A Y NOR2 OR2 Y B B A A AND2 Y Y NAND2 B B A A B Y XOR3 XOR2 Y B C A A MAJ3 0 Y A MUX2 BY B B NAND3 1 C C S Figure 2-35 • Sample of Combinatorial Cells Revision 9 2-81 IGLOOe DC and Switching Characteristics t PD Fanout = 4 A Net Y NAND2 or Any Length = 1 VersaTile Combinatorial Logic B t = MAX(t , t , PD PD(RR) PD(RF) t , t ) where edges are PD(FF) PD(FR) A applicable for a particular Net combinatorial cell Y NAND2 or Any Length = 1 VersaTile Combinatorial B Logic A Net Y NAND2 or Any Length = 1 VersaTile Combinatorial B Logic A Net Y NAND2 or Any Length = 1 VersaTile Combinatorial B Logic VCC 50% 50% A, B, C GND VCC 50% 50% OUT GND t t PD PD (FF) (RR) VCC t PD OUT (FR) 50% 50% t PD GND (RF) Figure 2-36 • Timing Model and Waveforms 2-82 Revision 9 IGLOOe Low Power Flash FPGAs Timing Characteristics 1.5 V DC Core Voltage Table 2-134 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V J Combinatorial Cell Equation Parameter Std. Units INV Y = !A t 0.80 ns PD AND2 Y = A · B t 0.84 ns PD NAND2 Y = !(A · B) t 0.90 ns PD OR2 Y = A + B t 1.19 ns PD NOR2 Y = !(A + B) t 1.10 ns PD XOR2 Y = A ⊕ Bt 1.37 ns PD MAJ3 Y = MAJ(A, B, C) t 1.33 ns PD XOR3 Y = A ⊕ B ⊕ Ct 1.79 ns PD MUX2 Y = A !S + B S t 1.48 ns PD AND3 Y = A · B · C t 1.21 ns PD Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-135 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V J Combinatorial Cell Equation Parameter Std. Units INV Y = !A t 1.35 ns PD AND2 Y = A · B t 1.42 ns PD NAND2 Y = !(A · B) t 1.58 ns PD OR2 Y = A + B t 2.10 ns PD NOR2 Y = !(A + B) t 1.94 ns PD XOR2 Y = A ⊕ Bt 2.33 ns PD MAJ3 Y = MAJ(A, B, C) t 2.34 ns PD XOR3 Y = A ⊕ B ⊕ Ct 3.05 ns PD MUX2 Y = A !S + B S t 2.64 ns PD AND3 Y = A · B · C t 2.10 ns PD Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Revision 9 2-83 IGLOOe DC and Switching Characteristics VersaTile Specifications as a Sequential Module The IGLOOe library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide. Data Out Data Out DQ D Q En DFN1 DFN1E1 CLK CLK PRE Data Out Data Out Q D DQ En DFN1C1 DFI1E1P1 CLK CLK CLR Figure 2-37 • Sample of Sequential Cells 2-84 Revision 9 IGLOOe Low Power Flash FPGAs t t CKMPWH CKMPWL 50% 50% 50% 50% 50% 50% 50% CLK t HD t SUD Data 50% 0 50% EN 50% t t WPRE RECPRE t REMPRE t HE 50% 50% 50% t PRE SUE t t t REMCLR RECCLR WCLR 50% 50% 50% CLR t PRE2Q t CLR2Q 50% 50% 50% Out t CLKQ Figure 2-38 • Timing Model and Waveforms Timing Characteristics 1.5 V DC Core Voltage Table 2-136 • Register Delays Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V J Parameter Description Std. Units t Clock-to-Q of the Core Register 0.89 ns CLKQ t Data Setup Time for the Core Register 0.81 ns SUD t Data Hold Time for the Core Register 0.00 ns HD t Enable Setup Time for the Core Register 0.73 ns SUE t Enable Hold Time for the Core Register 0.00 ns HE t Asynchronous Clear-to-Q of the Core Register 0.60 ns CLR2Q t Asynchronous Preset-to-Q of the Core Register 0.62 ns PRE2Q t Asynchronous Clear Removal Time for the Core Register 0.00 ns REMCLR t Asynchronous Clear Recovery Time for the Core Register 0.24 ns RECCLR t Asynchronous Preset Removal Time for the Core Register 0.00 ns REMPRE t Asynchronous Preset Recovery Time for the Core Register 0.23 ns RECPRE t Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 ns WCLR t Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 ns WPRE t Clock Minimum Pulse Width HIGH for the Core Register 0.56 ns CKMPWH t Clock Minimum Pulse Width LOW for the Core Register 0.56 ns CKMPWL Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Revision 9 2-85 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-137 • Register Delays = 70°C, Worst-Case VCC = 1.14 V Commercial-Case Conditions: T J Parameter Description Std. Units t Clock-to-Q of the Core Register 1.61 ns CLKQ t Data Setup Time for the Core Register 1.17 ns SUD t Data Hold Time for the Core Register 0.00 ns HD t Enable Setup Time for the Core Register 1.29 ns SUE t Enable Hold Time for the Core Register 0.00 ns HE t Asynchronous Clear-to-Q of the Core Register 0.87 ns CLR2Q t Asynchronous Preset-to-Q of the Core Register 0.89 ns PRE2Q t Asynchronous Clear Removal Time for the Core Register 0.00 ns REMCLR t Asynchronous Clear Recovery Time for the Core Register 0.24 ns RECCLR t Asynchronous Preset Removal Time for the Core Register 0.00 ns REMPRE t Asynchronous Preset Recovery Time for the Core Register 0.24 ns RECPRE t Asynchronous Clear Minimum Pulse Width for the Core Register 0.46 ns WCLR t Asynchronous Preset Minimum Pulse Width for the Core Register 0.46 ns WPRE t Clock Minimum Pulse Width HIGH for the Core Register 0.95 ns CKMPWH t Clock Minimum Pulse Width LOW for the Core Register 0.95 ns CKMPWL Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2-86 Revision 9 IGLOOe Low Power Flash FPGAs Global Resource Characteristics AGLE600 Clock Tree Topology Clock delays are device-specific. Figure 2-39 is an example of a global tree used for clock routing. The global tree presented in Figure 2-39 is driven by a CCC located on the west side of the AGLE600 device. It is used to drive all D-flip-flops in the device. Central Global Rib CCC VersaTile Rows Global Spine Figure 2-39 • Example of Global Tree Use in an AGLE600 Device for Clock Routing Revision 9 2-87 IGLOOe DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-90. Table 2-138 and Table 2-140 present minimum and maximum global clock delays within the device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics 1.5 V DC Core Voltage Table 2-138 • AGLE600 Global Resource Commercial-Case Conditions: T = 70°C, VCC = 1.425 V J Std. 1 2 Parameter Description Min. Max. Units t Input LOW Delay for Global Clock 1.48 1.82 ns RCKL t Input HIGH Delay for Global Clock 1.52 1.94 ns RCKH t Minimum Pulse Width HIGH for Global Clock ns RCKMPWH t Minimum Pulse Width LOW for Global Clock ns RCKMPWL t Maximum Skew for Global Clock 0.42 ns RCKSW F Maximum Frequency for Global Clock MHz RMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-139 • AGLE3000 Global Resource Commercial-Case Conditions: T = 70°C, VCC = 1.425 V J Std. 1 2 Parameter Description Min. Max. Units t Input LOW Delay for Global Clock 2.00 2.34 ns RCKL t Input HIGH Delay for Global Clock 2.09 2.51 ns RCKH Minimum Pulse Width HIGH for Global Clock ns t RCKMPWH t Minimum Pulse Width LOW for Global Clock ns RCKMPWL t Maximum Skew for Global Clock 0.42 ns RCKSW Maximum Frequency for Global Clock MHz F RMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2-88 Revision 9 IGLOOe Low Power Flash FPGAs 1.2 V DC Core Voltage Table 2-140 • AGLE600 Global Resource Commercial-Case Conditions: T = 70°C, VCC = 1.14 V J Std. 1 2 Parameter Description Min. Max. Units t Input LOW Delay for Global Clock 2.22 2.67 ns RCKL t Input HIGH Delay for Global Clock 2.32 2.93 ns RCKH t Minimum Pulse Width HIGH for Global Clock ns RCKMPWH t Minimum Pulse Width LOW for Global Clock ns RCKMPWL t Maximum Skew for Global Clock 0.61 ns RCKSW F Maximum Frequency for Global Clock MHz RMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Table 2-141 • AGLE3000 Global Resource Commercial-Case Conditions: T = 70°C, VCC = 1.14 V J Std. 1 2 Parameter Description Min. Max. Units t Input LOW Delay for Global Clock 2.83 3.27 ns RCKL t Input HIGH Delay for Global Clock 3.00 3.61 ns RCKH t Minimum Pulse Width HIGH for Global Clock ns RCKMPWH Minimum Pulse Width LOW for Global Clock ns t RCKMPWL t Maximum Skew for Global Clock 0.61 ns RCKSW F Maximum Frequency for Global Clock MHz RMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Revision 9 2-89 IGLOOe DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-142 • IGLOOe CCC/PLL Specification For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage Parameter Min. Typ. Max. Units Clock Conditioning Circuitry Input Frequency f 1.5 250MHz IN_CCC Clock Conditioning Circuitry Output Frequency f 0.75 250MHz OUT_CCC 1 Serial Clock (SCLK) for Dynamic PLL 100 MHz 2, 3 4 Delay Increments in Programmable Delay Blocks 360 ps Number of Programmable Values in Each Programmable Delay 32 ns Block Input Cycle-to-Cycle Jitter (peak magnitude) 1 CCC Output Peak-to-Peak Period Jitter F Max Peak-to-Peak Period Jitter CCC_OUT 1 Global External 3 Global Network FB Used Networks Used Used 0.75 MHz to 24 MHz 0.50% 0.75% 0.70% 24 MHz to 100 MHz 1.00% 1.50% 1.20% 100 MHz to 250 MHz 2.50% 3.75% 2.75% Acquisition Time LockControl = 0 300 µs LockControl = 1 6.0 ms Tracking Jitter LockControl = 0 2.5 ns LockControl = 1 1.5 ns Output Duty Cycle 48.5 51.5 % 2, 3, 5 Delay Range in Block: Programmable Delay 1 1.25 15.65 ns 2, 3, 5 Delay Range in Block: Programmable Delay 2 0.469 15.65 ns 2, 3 Delay Range in Block: Fixed Delay 3.5 ns Notes: 1. Maximum value obtained for a Std. speed grade device in Worst Case Commercial Conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-6 for deratings. 3. T = 25°C, VCC = 1.5 V J 4. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to SmartGen online help for more information. 5. For definitions of Type 1 and Type 2, refer to the PLL Block Diagram in the "Clock Conditioning Circuits in IGLOO and ProASIC3 Devices" chapter of the IGLOOe FPGA Fabric User’s Guide. 6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. 2-90 Revision 9 IGLOOe Low Power Flash FPGAs Table 2-143 • IGLOOe CCC/PLL Specification For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage Parameter Min. Typ. Max. Units Clock Conditioning Circuitry Input Frequency f 1.5 160MHz IN_CCC Clock Conditioning Circuitry Output Frequency f 0.75 160 MHz OUT_CCC 1 Serial Clock (SCLK) for Dynamic PLL 60 MHz 2, 3 4 Delay Increments in Programmable Delay Blocks 580 ps Number of Programmable Values in Each Programmable Delay 32 Block Input Cycle-to-Cycle Jitter (peak magnitude) 0.25 ns CCC Output Peak-to-Peak Period Jitter F Max Peak-to-Peak Period Jitter CCC_OUT 1 Global External 3 Global Network FB Used Networks Used Used 0.75 MHz to 24 MHz 0.50% 0.75% 0.70% 24 MHz to 100 MHz 1.00% 1.50% 1.20% 100 MHz to 160 MHz 2.50% 3.75% 2.75% Acquisition Time LockControl = 0 300 µs LockControl = 1 6.0 ms 5 Tracking Jitter LockControl = 0 4 ns LockControl = 1 3 ns Output Duty Cycle 48.5 51.5 % 2, 3 Delay Range in Block: Programmable Delay 1 2.3 20.86ns 2, 3 Delay Range in Block: Programmable Delay 2 0.863 20.86ns 2, 3 Delay Range in Block: Fixed Delay 5.7 ns Notes: 1. Maximum value obtained for a Std. speed grade device in Worst Case Commercial Conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-6 for deratings. 3. T = 25°C, VCC = 1.5 V J 4. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to SmartGen online help for more information. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter. Revision 9 2-91 IGLOOe DC and Switching Characteristics Output Signal T T period_max period_min Note: Peak-to-peak jitter measurements are defined by T = T – T . peak-to-peak period_max period_min Figure 2-40 • Peak-to-Peak Jitter Definition 2-92 Revision 9 IGLOOe Low Power Flash FPGAs Embedded SRAM and FIFO Characteristics SRAM RAM4K9 RAM512X18 RADDR8 RD17 ADDRA11 DOUTA8 RADDR7 RD16 DOUTA7 ADDRA10 ADDRA0 DOUTA0 RADDR0 RD0 DINA8 DINA7 RW1 DINA0 RW0 WIDTHA1 WIDTHA0 PIPE PIPEA WMODEA BLKA REN WENA RCLK CLKA ADDRB11 DOUTB8 WADDR8 ADDRB10 DOUTB7 WADDR7 ADDRB0 DOUTB0 WADDR0 WD17 WD16 DINB8 DINB7 WD0 DINB0 WW1 WW0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WEN WENB CLKB WCLK RESET RESET Figure 2-41 • RAM Models Revision 9 2-93 IGLOOe DC and Switching Characteristics Timing Waveforms t CYC t t CKH CKL CLK t t AS AH A A A [R|W]ADDR 0 1 2 t BKS t BKH BLK t t ENS ENH WEN t CKQ1 D D D D DOUT|RD n 0 1 2 t DOH1 Figure 2-42 • RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512X18. t CYC t t CKH CKL CLK t t AH AS A A A [R|W]ADDR 0 1 2 t BKS t BKH BLK t t ENS ENH WEN t CKQ2 D DOUT|RD D D n 0 1 t DOH2 Figure 2-43 • RAM Read for Pipelined Output. Applicable to Both RAM4K9 and RAM512X18. 2-94 Revision 9 IGLOOe Low Power Flash FPGAs t CYC t t CKH CKL CLK t t AS AH A A A [R|W]ADDR 0 1 2 t BKS t BKH BLK t t ENS ENH WEN t t DS DH DI DI DIN|WD 0 1 D D DOUT|RD n 2 Figure 2-44 • RAM Write, Output Retained. Applicable to both RAM4K9 and RAM512X18. t CYC t t CKH CKL CLK t t AS AH A A A ADDR 0 1 2 t BKS t BKH BLK t ENS WEN t t DS DH DI DI DI DIN 0 1 2 DOUT D DI DI n 0 1 (pass-through) DOUT D DI DI n 0 1 (pipelined) Figure 2-45 • RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 Only. Revision 9 2-95 IGLOOe DC and Switching Characteristics t CYC t t CKH CKL CLK RESET t RSTBQ D DOUT|RD D m n Figure 2-46 • RAM Reset 2-96 Revision 9 IGLOOe Low Power Flash FPGAs Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-144 • RAM4K9 Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V J Parameter Description Std. Units t Address Setup Time 0.83 ns AS t Address Hold Time 0.16 ns AH t REN, WEN Setup Time 0.81 ns ENS t REN, WEN Hold Time 0.16 ns ENH t BLK Setup Time 1.65 ns BKS t BLK Hold Time 0.16 ns BKH t Input Data (DIN) Setup Time 0.71 ns DS t Input Data (DIN) Hold Time 0.36 ns DH t Clock HIGH to New Data Valid on DOUT (output retained, WMODE = 0) 3.53 ns CKQ1 Clock HIGH to New Data Valid on DOUT (flow-through, WMODE = 1) 3.06 ns t Clock HIGH to New Data Valid on DOUT (pipelined) 1.81 ns CKQ2 1 t Address collision clk-to-clk delay for reliable write after write on same 0.23 ns C2CWWL address; applicable to closing edge 1 t Address collision clk-to-clk delay for reliable read access after write on 0.35 ns C2CRWH same address; applicable to opening edge 1 t Address collision clk-to-clk delay for reliable write access after read on 0.41 ns C2CWRH same address; applicable to opening edge t RESET Low to Data Out Low on DOUT (flow-through) 2.06 ns RSTBQ RESET Low to Data Out Low on DOUT (pipelined) 2.06 ns t RESET Removal 0.61 ns REMRSTB t RESET Recovery 3.21 ns RECRSTB t RESET Minimum Pulse Width 0.68 ns MPWRSTB t Clock Cycle Time 6.24 ns CYC F Maximum Frequency 160 MHz MAX Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Revision 9 2-97 IGLOOe DC and Switching Characteristics Table 2-145 • RAM512X18 Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.425 V J Parameter Description Std. Units t Address Setup Time 0.83 ns AS t Address Hold Time 0.16 ns AH t REN, WEN Setup Time 0.73 ns ENS t REN, WEN Hold Time 0.08 ns ENH t Input Data (WD) Setup Time 0.71 ns DS t Input Data (WD) Hold Time 0.36 ns DH t Clock HIGH to New Data Valid on RD (output retained, WMODE = 0) 4.21 ns CKQ1 t Clock HIGH to New Data Valid on RD (pipelined) 1.71 ns CKQ2 1 t Address collision clk-to-clk delay for reliable read access after write on 0.35 ns C2CRWH same address; applicable to opening edge 1 t Address collision clk-to-clk delay for reliable write access after read on 0.42 ns C2CWRH same address; applicable to opening edge t RESET Low to Data Out Low on RD (flow-through) 2.06 ns RSTBQ RESET Low to Data Out Low on RD (pipelined) 2.06 ns t RESET Removal 0.61 ns REMRSTB t RESET Recovery 3.21 ns RECRSTB t RESET Minimum Pulse Width 0.68 ns MPWRSTB t Clock Cycle Time 6.24 ns CYC F Maximum Frequency 160 MHz MAX Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2-98 Revision 9 IGLOOe Low Power Flash FPGAs Applies to 1.2 V DC Core Voltage Table 2-146 • RAM4K9 = 70°C, Worst-Case VCC = 1.14 V Commercial-Case Conditions: T J Parameter Description Std. Units t Address Setup Time 1.53 ns AS t Address Hold Time 0.29 ns AH t REN, WEN Setup Time 1.50 ns ENS t REN, WEN Hold Time 0.29 ns ENH t BLK Setup Time 3.05 ns BKS t BLK Hold Time 0.29 ns BKH t Input Data (DIN) Setup Time 1.33 ns DS t Input Data (DIN) Hold Time 0.66 ns DH t Clock High to New Data Valid on DOUT (output retained, WMODE = 0) 6.61 ns CKQ1 Clock High to New Data Valid on DOUT (flow-through, WMODE = 1) 5.72 ns t Clock High to New Data Valid on DOUT (pipelined) 3.38 ns CKQ2 1 t Address collision clk-to-clk delay for reliable write after write on same 0.30 ns C2CWWL address; applicable to closing edge 1 t Address collision clk-to-clk delay for reliable read access after write on 0.89 ns C2CRWH same address; applicable to opening edge 1 t Address collision clk-to-clk delay for reliable write access after read on 1.01 ns C2CWRH same address; applicable to opening edge t RESET Low to Data Out Low on DOUT (pass-through) 3.86 ns RSTBQ RESET Low to Data Out Low on DOUT (pipelined) 3.86 ns t RESET Removal 1.12 ns REMRSTB t RESET Recovery 5.93 ns RECRSTB t RESET Minimum Pulse Width 1.18 ns MPWRSTB t Clock Cycle Time 10.90 ns CYC F Maximum Frequency 92 MHz MAX Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Revision 9 2-99 IGLOOe DC and Switching Characteristics Table 2-147 • RAM512X18 Commercial-Case Conditions: T = 70°C, Worst-Case VCC = 1.14 V J Parameter Description Std. Units t Address Setup Time 1.53 ns AS t Address Hold Time 0.29 ns AH t REN, WEN Setup Time 1.36 ns ENS t REN, WEN Hold Time 0.15 ns ENH t Input Data (WD) Setup Time 1.33 ns DS t Input Data (WD) Hold Time 0.66 ns DH t Clock High to New Data Valid on RD (output retained) 7.88 ns CKQ1 t Clock High to New Data Valid on RD (pipelined) 3.20 ns CKQ2 1 t Address collision clk-to-clk delay for reliable read access after write on 0.87 ns C2CRWH same address; applicable to opening edge 1 t Address collision clk-to-clk delay for reliable write access after read on 1.04 ns C2CWRH same address; applicable to opening edge t RESET Low to Data Out Low on RD (flow-through) 3.86 ns RSTBQ RESET Low to Data Out Low on RD (pipelined) 3.86 ns t RESET Removal 1.12 ns REMRSTB t RESET Recovery 5.93 ns RECRSTB t RESET Minimum Pulse Width 1.18 ns MPWRSTB t Clock Cycle Time 10.90 ns CYC F Maximum Frequency 92 MHz MAX Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2-100 Revision 9 IGLOOe Low Power Flash FPGAs FIFO FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 RD0 WW0 ESTOP FULL FSTOP AFULL EMPTY AEVAL11 AEMPTY AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE RESET Figure 2-47 • FIFO Model Revision 9 2-101 IGLOOe DC and Switching Characteristics Timing Waveforms RCLK/ WCLK t t MPWRSTB RSTCK RESET t RSTFG EMPTY t RSTAF AEMPTY t RSTFG FULL t RSTAF AFULL WA/RA MATCH (A ) (Address Counter) 0 Figure 2-48 • FIFO Reset t CYC RCLK t RCKEF EMPTY t CKAF AEMPTY WA/RA NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY) (Address Counter) Figure 2-49 • FIFO EMPTY Flag and AEMPTY Flag Assertion 2-102 Revision 9 IGLOOe Low Power Flash FPGAs t CYC WCLK t WCKFF FULL t CKAF AFULL WA/RA NO MATCH NO MATCH Dist = AFF_TH MATCH (FULL) (Address Counter) Figure 2-50 • FIFO FULL Flag and AFULL Flag Assertion WCLK MATCH WA/RA NO MATCH NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1 (Address Counter) (EMPTY) 1st Rising 2nd Rising Edge Edge After 1st After 1st Write Write RCLK t RCKEF EMPTY t CKAF AEMPTY Figure 2-51 • FIFO EMPTY Flag and AEMPTY Flag Deassertion RCLK WA/RA MATCH (FULL) Dist = AFF_TH – 1 NO MATCH NO MATCH NO MATCH NO MATCH (Address Counter) 1st Rising 1st Rising Edge Edge After 1st After 2nd Read WCLK Read t WCKF FULL t CKAF AFULL Figure 2-52 • FIFO FULL Flag and AFULL Flag Deassertion Revision 9 2-103 IGLOOe DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-148 • FIFO Commercial-Case Conditions: T = 70°C, VCC = 1.425 V J Parameter Description Std. Units t REN, WEN Setup Time 1.99 ns ENS t REN, WEN Hold Time 0.16 ns ENH t BLK Setup Time 0.30 ns BKS t BLK Hold Time 0.00 ns BKH t Input Data (WD) Setup Time 0.76 ns DS t Input Data (WD) Hold Time 0.25 ns DH t Clock HIGH to New Data Valid on RD (pass-through) 3.33 ns CKQ1 t Clock HIGH to New Data Valid on RD (pipelined) 1.80 ns CKQ2 t RCLK HIGH to Empty Flag Valid 3.53 ns RCKEF t WCLK HIGH to Full Flag Valid 3.35 ns WCKFF t Clock HIGH to Almost Empty/Full Flag Valid 12.85 ns CKAF t RESET LOW to Empty/Full Flag Valid 3.48 ns RSTFG t RESET LOW to Almost Empty/Full Flag Valid 12.72 ns RSTAF t RESET LOW to Data Out LOW on RD (pass-through) 2.02 ns RSTBQ RESET LOW to Data Out LOW on RD (pipelined) 2.02 ns t RESET Removal 0.61 ns REMRSTB t RESET Recovery 3.21 ns RECRSTB t RESET Minimum Pulse Width 0.68 ns MPWRSTB t Clock Cycle Time 6.24 ns CYC F Maximum Frequency 160 MHz MAX Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2-104 Revision 9 IGLOOe Low Power Flash FPGAs Applies to 1.2 V DC Core Voltage Table 2-149 • FIFO = 70°C, VCC = 1.14 V Commercial-Case Conditions: T J Parameter Description Std. Units t REN, WEN Setup Time 4.13 ns ENS t REN, WEN Hold Time 0.31 ns ENH t BLK Setup Time 0.47 ns BKS t BLK Hold Time 0.00 ns BKH t Input Data (WD) Setup Time 1.56 ns DS t Input Data (WD) Hold Time 0.49 ns DH t Clock HIGH to New Data Valid on RD (pass-through) 6.80 ns CKQ1 t Clock HIGH to New Data Valid on RD (pipelined) 3.62 ns CKQ2 t RCLK HIGH to Empty Flag Valid 7.23 ns RCKEF t WCLK HIGH to Full Flag Valid 6.85 ns WCKFF t Clock HIGH to Almost Empty/Full Flag Valid 26.61 ns CKAF t RESET LOW to Empty/Full Flag Valid 7.12 ns RSTFG t RESET LOW to Almost Empty/Full Flag Valid 26.33 ns RSTAF t RESET LOW to Data Out LOW on RD (pass-through) 4.09 ns RSTBQ RESET LOW to Data Out LOW on RD (pipelined) 4.09 ns t RESET Removal 1.23 ns REMRSTB t RESET Recovery 6.58 ns RECRSTB t RESET Minimum Pulse Width 1.18 ns MPWRSTB t Clock Cycle Time 10.90 ns CYC F Maximum Frequency 92 MHz MAX Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Revision 9 2-105 IGLOOe DC and Switching Characteristics Embedded FlashROM Characteristics t t t SU SU SU CLK t t t HOLD HOLD HOLD Address A A 0 1 t t t CKQ2 CKQ2 CKQ2 D D D Data 0 0 1 Figure 2-53 • Timing Diagram Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-150 • Embedded FlashROM Access Time Commercial-Case Conditions: T = 70°C, VCC = 1.425 V J Parameter Description Std. Units t Address Setup Time 0.58 ns SU t Address Hold Time 0.00 ns HOLD t Clock-to-Out 34.14 ns CK2Q F Maximum Clock Frequency 15 MHz MAX Applies to 1.2 V DC Core Voltage Table 2-151 • Embedded FlashROM Access Time Commercial-Case Conditions: T = 70°C, VCC = 1.14 V J Parameter Description Std. Units t Address Setup Time 0.59 ns SU t Address Hold Time 0.00 ns HOLD t Clock-to-Out 52.90 ns CK2Q F Maximum Clock Frequency 10 MHz MAX 2-106 Revision 9 IGLOOe Low Power Flash FPGAs JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-16 for more details. Timing Characteristics Applies to 1.2 V DC Core Voltage Table 2-152 • JTAG 1532 Commercial-Case Conditions: T = 70°C, VCC = 1.14 V J Parameter Description Std. Units t Test Data Input Setup Time 1.50 ns DISU t Test Data Input Hold Time 3.00 ns DIHD t Test Mode Select Setup Time 1.50 ns TMSSU t Test Mode Select Hold Time 3.00 ns TMDHD t Clock to Q (data out) 11.00 ns TCK2Q t Reset to Q (data out) 30.00 ns RSTB2Q F TCK Maximum Frequency 9.00 MHz TCKMAX t ResetB Removal Time 1.18 ns TRSTREM t ResetB Recovery Time 0.00 ns TRSTREC t ResetB Minimum Pulse TBD ns TRSTMPW Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Applies to 1.5 V DC Core Voltage Table 2-153 • JTAG 1532 Commercial-Case Conditions: T = 70°C, VCC = 1.425 V J Parameter Description Std. Units t Test Data Input Setup Time 1.00 ns DISU t Test Data Input Hold Time 2.00 ns DIHD t Test Mode Select Setup Time 1.00 ns TMSSU t Test Mode Select Hold Time 2.00 ns TMDHD t Clock to Q (data out) 8.00 ns TCK2Q t Reset to Q (data out) 25.00 ns RSTB2Q F TCK Maximum Frequency 15.00 MHz TCKMAX t ResetB Removal Time 0.58 ns TRSTREM t ResetB Recovery Time 0.00 ns TRSTREC t ResetB Minimum Pulse TBD ns TRSTMPW Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Revision 9 2-107 IGLOOe DC and Switching Characteristics 2-108 Revision 9 3 – Pin Descriptions and Packaging Supply Pins GND Ground Ground supply voltage to the core, I/O outputs, and I/O logic. GNDQ Ground (quiet) Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise originated from the output buffer ground domain. This minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always be connected to GND on the board. VCC Core Supply Voltage Supply voltage to the FPGA core, nominally 1.5 V for IGLOOe V5 devices, and 1.2 V or 1.5 V for IGLOOe V2 devices. VCC is required for powering the JTAG state machine in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device. For IGLOOe V2 devices, VCC can be switched dynamically from 1.2 V to 1.5 V or vice versa. This allows in-system programming (ISP) when VCC is at 1.5 V and the benefit of low power operation when VCC is at 1.2 V. VCCIBx I/O Supply Voltage Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to eight I/O banks on IGLOOe devices plus a dedicated VJTAG bank. Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to GND. VMVx I/O Supply Voltage (quiet) Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the VMV plane is decoupled from the simultaneous switching noise originating from the output buffer VCCI domain. This minimizes the noise transfer within the package and improves input signal integrity. Each bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.). VCCPLA/B/C/D/E/F PLL Supply Voltage Supply voltage to analog PLL, nominally 1.5 V or 1.2 V, depending on the device. • 1.5 V for IGLOOe devices • 1.2 V or 1.5 V for IGLOOe V2 devices When the PLLs are not used, the place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the PLLs. Refer to the PLL Power Supply Decoupling section in the "Clock Conditioning Circuits in Low Power Flash FPGAs and Mixed Signal FPGAs" chapter in the IGLOOe FPGA Fabric User’s Guide for a complete board solution for the PLL analog power supply and ground. There are six VCCPLX pins on IGLOOe devices. Revision 9 3-1 Pin Descriptions and Packaging VCOMPLA/B/C/D/E/F PLL Ground Ground to analog PLL power supplies. When the PLLs are not used, the place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. There are six VCOMPL pins (PLL ground) on IGLOOe devices. VJTAG JTAG Supply Voltage Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals will not be able to transition the device, even in bypass mode. Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. VPUMP Programming Supply Voltage IGLOOe devices support single-voltage ISP of the configuration flash and FlashROM. For programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming power supply voltage (VPUMP) range is listed in the datasheet. When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible. Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. User-Defined Supply Pins VREF I/O Voltage Reference Reference voltage for I/O minibanks. VREF pins are configured by the user from regular I/Os, and any I/O in a bank, except JTAG I/Os, can be designated the voltage reference I/O. Only certain I/O standards require a voltage reference—HSTL (I) and (II), SSTL2 (I) and (II), SSTL3 (I) and (II), and GTL/GTL+. One VREF pin can support the number of I/Os available in its minibank. 3-2 Revision 9 IGLOOe Low Power Flash FPGAs User Pins I/O User Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected. During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC supplies continuously powered up, when the device transitions from programming to operating mode, the I/Os are instantly configured to the desired user configuration. Unused I/Os are configured as follows: • Output buffer is disabled (with tristate value of high impedance) • Input buffer is disabled (with tristate value of high impedance) • Weak pull-up is programmed GL Globals GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power Flash Devices and Mixed Signal FPGAs" chapter of the IGLOOe FPGA Fabric User’s Guide. All inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. The inputs to the global network are multiplexed, and only one input can be used as a global input. Refer to the I/O Structure section of the IGLOOe FPGA Fabric User’s Guide for an explanation of the naming of global pins. FF Flash*Freeze Mode Activation Pin Flash*Freeze mode is available on IGLOOe devices. The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The FF pin is active low, has the same characteristics as a single-ended I/O, and must meet the maximum rise and fall times. When Flash*Freeze mode is not used in the design, the FF pin is available as a regular I/O. The FF pin can be configured as a Schmitt trigger input. When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted. The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin should be treated as a sensitive asynchronous signal. When defining pin placement and board layout, simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be considered. Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both Flash*Freeze mode and normal operation mode. No user intervention is required. Revision 9 3-3 Pin Descriptions and Packaging Table 3-1 shows the Flash*Freeze pin location on the available packages. The Flash*Freeze pin location is independent of device (except for a PQ208 package), allowing migration to larger or smaller IGLOO devices while maintaining the same pin location on the board. Refer to the "Flash*Freeze Technology and Low Power Modes" chapter of the IGLOOe FPGA Fabric User’s Guide for more information on I/O states during Flash*Freeze mode. Table 3-1 • Flash*Freeze Pin Locations for IGLOOe Devices Package Flash*Freeze Pin FG256 T3 FG484 W6 FG896 AH4 JTAG Pins Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. TCK Test Clock Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull- up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state. Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ will satisfy the requirements. Refer to Table 3-2 for more information. Table 3-2 • Recommended Tie-Off Values for the TCK and TRST Pins 1,2 VJTAG Tie-Off Resistance VJTAG at 3.3 V 200 Ω to 1 kΩ VJTAG at 2.5 V 200 Ω to 1 kΩ VJTAG at 1.8 V 500 Ω to 1 kΩ VJTAG at 1.5 V 500 Ω to 1 kΩ Notes: 1. The TCK pin can be pulled-up or pulled-down. 2. The TRST pin is pulled-down. 3. Equivalent parallel resistance if more than one device is on the JTAG chain 3-4 Revision 9 IGLOOe Low Power Flash FPGAs Table 3-3 • TRST and TCK Pull-Down Recommendations VJTAG Tie-Off Resistance* VJTAG at 3.3 V 200 Ω to 1 kΩ VJTAG at 2.5 V 200 Ω to 1 kΩ VJTAG at 1.8 V 500 Ω to 1 kΩ VJTAG at 1.5 V 500 Ω to 1 kΩ Note: Equivalent parallel resistance if more than one device is on the JTAG chain TDI Test Data Input Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin. TDO Test Data Output Serial output for JTAG boundary scan, ISP, and UJTAG usage. TMS Test Mode Select The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin. TRST Boundary Scan Reset Pin The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull- down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor values must be chosen from Table 3-2 and must satisfy the parallel resistance value requirement. The values in Table 3-2 correspond to the resistor recommended when a single device is used, and the equivalent parallel resistor when multiple devices are connected via a JTAG chain. In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA pin. Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ will satisfy the requirements. Special Function Pins NC No Connect This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. DC Do Not Connect This pin should not be connected to any signals on the PCB. These pins should be left unconnected. Packaging Semiconductor technology is constantly shrinking in size while growing in capability and functional integration. To enable next-generation silicon technologies, semiconductor packages have also evolved to provide improved performance and flexibility. Microsemi consistently delivers packages that provide the necessary mechanical and environmental protection to ensure consistent reliability and performance. Microsemi IC packaging technology efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition, Microsemi offers a variety of packages designed to meet your most demanding application and economic requirements for today's embedded and mobile systems. Revision 9 3-5 Pin Descriptions and Packaging Related Documents User’s Guides IGLOOe FPGA Fabric User’s Guide http://www.microsemi.com/soc/documents/IGLOOe_UG.pdf Packaging Documents The following documents provide packaging information and device selection for low power flash devices. Product Catalog http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf Lists devices currently recommended for new designs and the packages available for each member of the family. Use this document or the datasheet tables to determine the best package for your design, and which package drawing to use. Package Mechanical Drawings http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf This document contains the package mechanical drawings for all packages currently or previously supplied by Microsemi. Use the bookmarks to navigate to the package mechanical drawings. Additional packaging materials: http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 3-6 Revision 9 4 – Package Pin Assignments FG256 A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Revision 9 4-1 Package Pin Assignments FG256 FG256 FG256 Pin Number AGLE600 Function Pin Number AGLE600 Function Pin Number AGLE600 Function A1 GND C5 GAC0/IO02NDB0V0 E9 IO21NDB1V0 A2 GAA0/IO00NDB0V0 C6 GAC1/IO02PDB0V0 E10 VCCIB1 A3 GAA1/IO00PDB0V0 C7 IO15NDB0V2 E11 VCCIB1 A4 GAB0/IO01NDB0V0 C8 IO15PDB0V2 E12 VMV1 A5 IO05PDB0V0 C9 IO20PDB1V0 E13 GBC2/IO38PDB2V0 A6 IO10PDB0V1 C10 IO25NDB1V0 E14 IO37NDB2V0 A7 IO12PDB0V2 C11 IO27PDB1V0 E15 IO41NDB2V0 A8 IO16NDB0V2 C12 GBC0/IO33NDB1V1 E16 IO41PDB2V0 A9 IO23NDB1V0 C13 VCCPLB F1 IO124PDB7V0 A10 IO23PDB1V0 C14 VMV2 F2 IO125PDB7V0 A11 IO28NDB1V1 C15 IO36NDB2V0 F3 IO126PDB7V0 A12 IO28PDB1V1 C16 IO42PDB2V0 F4 IO130NDB7V1 A13 GBB1/IO34PDB1V1 D1 IO128PDB7V1 F5 VCCIB7 A14 GBA0/IO35NDB1V1 D2 IO129PDB7V1 F6 GND A15 GBA1/IO35PDB1V1 D3 GAC2/IO132PDB7V1 F7 VCC A16 GND D4 VCOMPLA F8 VCC B1 GAB2/IO133PDB7V1 D5 GNDQ F9 VCC B2 GAA2/IO134PDB7V1 D6 IO09NDB0V1 F10 VCC B3 GNDQ D7 IO09PDB0V1 F11 GND B4 GAB1/IO01PDB0V0 D8 IO13PDB0V2 F12 VCCIB2 B5 IO05NDB0V0 D9 IO21PDB1V0 F13 IO38NDB2V0 B6 IO10NDB0V1 D10 IO25PDB1V0 F14 IO40NDB2V0 B7 IO12NDB0V2 D11 IO27NDB1V0 F15 IO40PDB2V0 B8 IO16PDB0V2 D12 GNDQ F16 IO45PSB2V1 B9 IO20NDB1V0 D13 VCOMPLB G1 IO124NDB7V0 B10 IO24NDB1V0 D14 GBB2/IO37PDB2V0 G2 IO125NDB7V0 B11 IO24PDB1V0 D15 IO39PDB2V0 G3 IO126NDB7V0 B12 GBC1/IO33PDB1V1 D16 IO39NDB2V0 G4 GFC1/IO120PPB7V0 B13 GBB0/IO34NDB1V1 E1 IO128NDB7V1 G5 VCCIB7 B14 GNDQ E2 IO129NDB7V1 G6 VCC B15 GBA2/IO36PDB2V0 E3 IO132NDB7V1 G7 GND B16 IO42NDB2V0 E4 IO130PDB7V1 G8 GND C1 IO133NDB7V1 E5 VMV0 G9 GND C2 IO134NDB7V1 E6 VCCIB0 G10 GND C3 VMV7 E7 VCCIB0 G11 VCC C4 VCCPLA E8 IO13NDB0V2 G12 VCCIB2 4-2 Revision 9 IGLOOe Low Power Flash FPGAs FG256 FG256 FG256 Pin Number AGLE600 Function Pin Number AGLE600 Function Pin Number AGLE600 Function G13 GCC1/IO50PPB2V1 K1 GFC2/IO115PSB6V1 M5 VMV5 G14 IO44NDB2V1 K2 IO113PPB6V1 M6 VCCIB5 G15 IO44PDB2V1 K3 IO112PDB6V1 M7 VCCIB5 G16 IO49NSB2V1 K4 IO112NDB6V1 M8 IO84NDB5V0 H1 GFB0/IO119NPB7V0 K5 VCCIB6 M9 IO84PDB5V0 H2 GFA0/IO118NDB6V1 K6 VCC M10 VCCIB4 H3 GFB1/IO119PPB7V0 K7 GND M11 VCCIB4 H4 VCOMPLF K8 GND M12 VMV3 H5 GFC0/IO120NPB7V0 K9 GND M13 VCCPLD H6 VCC K10 GND M14 GDB1/IO66PPB3V1 H7 GND K11 VCC M15 GDC1/IO65PDB3V1 H8 GND K12 VCCIB3 M16 IO61NDB3V1 H9 GND K13 IO54NPB3V0 N1 IO105PDB6V0 H10 GND K14 IO57NPB3V0 N2 IO105NDB6V0 H11 VCC K15 IO55NPB3V0 N3 GEC1/IO104PPB6V0 H12 GCC0/IO50NPB2V1 K16 IO57PPB3V0 N4 VCOMPLE H13 GCB1/IO51PPB2V1 L1 IO113NPB6V1 N5 GNDQ H14 GCA0/IO52NPB3V0 L2 IO109PPB6V0 N6 GEA2/IO101PPB5V2 H15 VCOMPLC L3 IO108PDB6V0 N7 IO92NDB5V1 H16 GCB0/IO51NPB2V1 L4 IO108NDB6V0 N8 IO90NDB5V1 J1 GFA2/IO117PSB6V1 L5 VCCIB6 N9 IO82NDB5V0 J2 GFA1/IO118PDB6V1 L6 GND N10 IO74NDB4V1 J3 VCCPLF L7 VCC N11 IO74PDB4V1 J4 IO116NDB6V1 L8 VCC N12 GNDQ J5 GFB2/IO116PDB6V1 L9 VCC N13 VCOMPLD J6 VCC L10 VCC N14 VJTAG J7 GND L11 GND N15 GDC0/IO65NDB3V1 J8 GND L12 VCCIB3 N16 GDA1/IO67PDB3V1 J9 GND L13 GDB0/IO66NPB3V1 P1 GEB1/IO103PDB6V0 J10 GND L14 IO60NDB3V1 P2 GEB0/IO103NDB6V0 J11 VCC L15 IO60PDB3V1 P3 VMV6 J12 GCB2/IO54PPB3V0 L16 IO61PDB3V1 P4 VCCPLE J13 GCA1/IO52PPB3V0 M1 IO109NPB6V0 P5 IO101NPB5V2 J14 GCC2/IO55PPB3V0 M2 IO106NDB6V0 P6 IO95PPB5V1 J15 VCCPLC M3 IO106PDB6V0 P7 IO92PDB5V1 J16 GCA2/IO53PSB3V0 M4 GEC0/IO104NPB6V0 P8 IO90PDB5V1 Revision 9 4-3 Package Pin Assignments FG256 FG256 Pin Number AGLE600 Function Pin Number AGLE600 Function P9 IO82PDB5V0 T12 GDC2/IO70PDB4V0 P10 IO76NDB4V1 T13 IO68NDB4V0 P11 IO76PDB4V1 T14 GDA2/IO68PDB4V0 P12 VMV4 T15 TMS P13 TCK T16 GND P14 VPUMP P15 TRST P16 GDA0/IO67NDB3V1 R1 GEA1/IO102PDB6V0 R2 GEA0/IO102NDB6V0 R3 GNDQ R4 GEC2/IO99PDB5V2 R5 IO95NPB5V1 R6 IO91NDB5V1 R7 IO91PDB5V1 R8 IO83NDB5V0 R9 IO83PDB5V0 R10 IO77NDB4V1 R11 IO77PDB4V1 R12 IO69NDB4V0 R13 GDB2/IO69PDB4V0 R14 TDI R15 GNDQ R16 TDO T1 GND T2 IO100NDB5V2 T3 FF/GEB2/IO100PDB5 V2 T4 IO99NDB5V2 T5 IO88NDB5V0 T6 IO88PDB5V0 T7 IO89NSB5V0 T8 IO80NSB4V1 T9 IO81NDB4V1 T10 IO81PDB4V1 T11 IO70NDB4V0 4-4 Revision 9 IGLOOe Low Power Flash FPGAs FG484 A1 Ball Pad Corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Revision 9 4-5 Package Pin Assignments FG484 FG484 FG484 Pin Pin Pin Number AGLE600 Function Number AGLE600 Function Number AGLE600 Function A1 GND AA14 NC B5 IO03PDB0V0 A2 GND AA15 NC B6 IO07NDB0V1 A3 VCCIB0 AA16 IO71NDB4V0 B7 IO07PDB0V1 A4 IO06NDB0V1 AA17 IO71PDB4V0 B8 IO11NDB0V1 A5 IO06PDB0V1 AA18 NC B9 IO17NDB0V2 A6 IO08NDB0V1 AA19 NC B10 IO14PDB0V2 A7 IO08PDB0V1 AA20 NC B11 IO19PDB0V2 A8 IO11PDB0V1 AA21 VCCIB3 B12 IO22NDB1V0 A9 IO17PDB0V2 AA22 GND B13 IO26NDB1V0 A10 IO18NDB0V2 AB1 GND B14 NC A11 IO18PDB0V2 AB2 GND B15 NC A12 IO22PDB1V0 AB3 VCCIB5 B16 IO30NDB1V1 A13 IO26PDB1V0 AB4 IO97NDB5V2 B17 IO30PDB1V1 A14 IO29NDB1V1 AB5 IO97PDB5V2 B18 IO32PDB1V1 A15 IO29PDB1V1 AB6 IO93NDB5V1 B19 NC A16 IO31NDB1V1 AB7 IO93PDB5V1 B20 NC A17 IO31PDB1V1 AB8 IO87NDB5V0 B21 VCCIB2 A18 IO32NDB1V1 AB9 IO87PDB5V0 B22 GND A19 NC AB10 NC C1 VCCIB7 A20 VCCIB1 AB11 NC C2 NC A21 GND AB12 IO75NDB4V1 C3 NC A22 GND AB13 IO75PDB4V1 C4 NC AA1 GND AB14 IO72NDB4V0 C5 GND AA2 VCCIB6 AB15 IO72PDB4V0 C6 IO04NDB0V0 AA3 NC AB16 IO73NDB4V0 C7 IO04PDB0V0 AA4 IO98PDB5V2 AB17 IO73PDB4V0 C8 VCC AA5 IO96NDB5V2 AB18 NC C9 VCC AA6 IO96PDB5V2 AB19 NC C10 IO14NDB0V2 AA7 IO86NDB5V0 AB20 VCCIB4 C11 IO19NDB0V2 AA8 IO86PDB5V0 AB21 GND C12 NC AA9 IO85PDB5V0 AB22 GND C13 NC AA10 IO85NDB5V0 B1 GND C14 VCC AA11 IO78PPB4V1 B2 VCCIB7 C15 VCC AA12 IO79NDB4V1 B3 NC C16 NC AA13 IO79PDB4V1 B4 IO03NDB0V0 C17 NC 4-6 Revision 9 IGLOOe Low Power Flash FPGAs FG484 FG484 FG484 Pin Pin Pin Number AGLE600 Function Number AGLE600 Function Number AGLE600 Function C18 GND E9 IO10NDB0V1 F22 NC C19 NC E10 IO12NDB0V2 G1 IO127NDB7V1 C20 NC E11 IO16PDB0V2 G2 IO127PDB7V1 C21 NC E12 IO20NDB1V0 G3 NC C22 VCCIB2 E13 IO24NDB1V0 G4 IO128PDB7V1 D1 NC E14 IO24PDB1V0 G5 IO129PDB7V1 D2 NC E15 GBC1/IO33PDB1V1 G6 GAC2/IO132PDB7V1 D3 NC E16 GBB0/IO34NDB1V1 G7 VCOMPLA D4 GND E17 GNDQ G8 GNDQ D5 GAA0/IO00NDB0V0 E18 GBA2/IO36PDB2V0 G9 IO09NDB0V1 D6 GAA1/IO00PDB0V0 E19 IO42NDB2V0 G10 IO09PDB0V1 D7 GAB0/IO01NDB0V0 E20 GND G11 IO13PDB0V2 D8 IO05PDB0V0 E21 NC G12 IO21PDB1V0 D9 IO10PDB0V1 E22 NC G13 IO25PDB1V0 D10 IO12PDB0V2 F1 NC G14 IO27NDB1V0 D11 IO16NDB0V2 F2 IO131NDB7V1 G15 GNDQ D12 IO23NDB1V0 F3 IO131PDB7V1 G16 VCOMPLB D13 IO23PDB1V0 F4 IO133NDB7V1 G17 GBB2/IO37PDB2V0 D14 IO28NDB1V1 F5 IO134NDB7V1 G18 IO39PDB2V0 D15 IO28PDB1V1 F6 VMV7 G19 IO39NDB2V0 D16 GBB1/IO34PDB1V1 F7 VCCPLA G20 IO43PDB2V0 D17 GBA0/IO35NDB1V1 F8 GAC0/IO02NDB0V0 G21 IO43NDB2V0 D18 GBA1/IO35PDB1V1 F9 GAC1/IO02PDB0V0 G22 NC D19 GND F10 IO15NDB0V2 H1 NC D20 NC F11 IO15PDB0V2 H2 NC D21 NC F12 IO20PDB1V0 H3 VCC D22 NC F13 IO25NDB1V0 H4 IO128NDB7V1 E1 NC F14 IO27PDB1V0 H5 IO129NDB7V1 E2 NC F15 GBC0/IO33NDB1V1 H6 IO132NDB7V1 E3 GND F16 VCCPLB H7 IO130PDB7V1 E4 GAB2/IO133PDB7V1 F17 VMV2 H8 VMV0 E5 GAA2/IO134PDB7V1 F18 IO36NDB2V0 H9 VCCIB0 E6 GNDQ F19 IO42PDB2V0 H10 VCCIB0 E7 GAB1/IO01PDB0V0 F20 NC H11 IO13NDB0V2 E8 IO05NDB0V0 F21 NC H12 IO21NDB1V0 Revision 9 4-7 Package Pin Assignments FG484 FG484 FG484 Pin Pin Pin Number AGLE600 Function Number AGLE600 Function Number AGLE600 Function H13 VCCIB1 K4 IO124NDB7V0 L17 GCA0/IO52NPB3V0 H14 VCCIB1 K5 IO125NDB7V0 L18 VCOMPLC H15 VMV1 K6 IO126NDB7V0 L19 GCB0/IO51NPB2V1 H16 GBC2/IO38PDB2V0 K7 GFC1/IO120PPB7V0 L20 IO49PPB2V1 H17 IO37NDB2V0 K8 VCCIB7 L21 IO47NDB2V1 H18 IO41NDB2V0 K9 VCC L22 IO47PDB2V1 H19 IO41PDB2V0 K10 GND M1 NC H20 VCC K11 GND M2 IO114NPB6V1 H21 NC K12 GND M3 IO117NDB6V1 H22 NC K13 GND M4 GFA2/IO117PDB6V1 J1 IO123NDB7V0 K14 VCC M5 GFA1/IO118PDB6V1 J2 IO123PDB7V0 K15 VCCIB2 M6 VCCPLF J3 NC K16 GCC1/IO50PPB2V1 M7 IO116NDB6V1 J4 IO124PDB7V0 K17 IO44NDB2V1 M8 GFB2/IO116PDB6V1 J5 IO125PDB7V0 K18 IO44PDB2V1 M9 VCC J6 IO126PDB7V0 K19 IO49NPB2V1 M10 GND J7 IO130NDB7V1 K20 IO45NPB2V1 M11 GND J8 VCCIB7 K21 IO48NDB2V1 M12 GND J9 GND K22 IO46NDB2V1 M13 GND J10 VCC L1 NC M14 VCC J11 VCC L2 IO122PDB7V0 M15 GCB2/IO54PPB3V0 J12 VCC L3 IO122NDB7V0 M16 GCA1/IO52PPB3V0 J13 VCC L4 GFB0/IO119NPB7V0 M17 GCC2/IO55PPB3V0 J14 GND L5 GFA0/IO118NDB6V1 M18 VCCPLC J15 VCCIB2 L6 GFB1/IO119PPB7V0 M19 GCA2/IO53PDB3V0 J16 IO38NDB2V0 L7 VCOMPLF M20 IO53NDB3V0 J17 IO40NDB2V0 L8 GFC0/IO120NPB7V0 M21 IO56PDB3V0 J18 IO40PDB2V0 L9 VCC M22 NC J19 IO45PPB2V1 L10 GND N1 IO114PPB6V1 J20 NC L11 GND N2 IO111NDB6V1 J21 IO48PDB2V1 L12 GND N3 NC J22 IO46PDB2V1 L13 GND N4 GFC2/IO115PPB6V1 K1 IO121NDB7V0 L14 VCC N5 IO113PPB6V1 K2 IO121PDB7V0 L15 GCC0/IO50NPB2V1 N6 IO112PDB6V1 K3 NC L16 GCB1/IO51PPB2V1 N7 IO112NDB6V1 4-8 Revision 9 IGLOOe Low Power Flash FPGAs FG484 FG484 FG484 Pin Pin Pin Number AGLE600 Function Number AGLE600 Function Number AGLE600 Function N8 VCCIB6 P21 IO59PDB3V0 T12 IO82NDB5V0 N9 VCC P22 IO58NDB3V0 T13 IO74NDB4V1 N10 GND R1 NC T14 IO74PDB4V1 N11 GND R2 IO110PDB6V0 T15 GNDQ N12 GND R3 VCC T16 VCOMPLD N13 GND R4 IO109NPB6V0 T17 VJTAG N14 VCC R5 IO106NDB6V0 T18 GDC0/IO65NDB3V1 N15 VCCIB3 R6 IO106PDB6V0 T19 GDA1/IO67PDB3V1 N16 IO54NPB3V0 R7 GEC0/IO104NPB6V0 T20 NC N17 IO57NPB3V0 R8 VMV5 T21 IO64PDB3V1 N18 IO55NPB3V0 R9 VCCIB5 T22 IO62NDB3V1 N19 IO57PPB3V0 R10 VCCIB5 U1 NC N20 NC R11 IO84NDB5V0 U2 IO107PDB6V0 N21 IO56NDB3V0 R12 IO84PDB5V0 U3 IO107NDB6V0 N22 IO58PDB3V0 R13 VCCIB4 U4 GEB1/IO103PDB6V0 P1 NC R14 VCCIB4 U5 GEB0/IO103NDB6V0 P2 IO111PDB6V1 R15 VMV3 U6 VMV6 P3 IO115NPB6V1 R16 VCCPLD U7 VCCPLE P4 IO113NPB6V1 R17 GDB1/IO66PPB3V1 U8 IO101NPB5V2 P5 IO109PPB6V0 R18 GDC1/IO65PDB3V1 U9 IO95PPB5V1 P6 IO108PDB6V0 R19 IO61NDB3V1 U10 IO92PDB5V1 P7 IO108NDB6V0 R20 VCC U11 IO90PDB5V1 P8 VCCIB6 R21 IO59NDB3V0 U12 IO82PDB5V0 P9 GND R22 IO62PDB3V1 U13 IO76NDB4V1 P10 VCC T1 NC U14 IO76PDB4V1 P11 VCC T2 IO110NDB6V0 U15 VMV4 P12 VCC T3 NC U16 TCK P13 VCC T4 IO105PDB6V0 U17 VPUMP P14 GND T5 IO105NDB6V0 U18 TRST P15 VCCIB3 T6 GEC1/IO104PPB6V0 U19 GDA0/IO67NDB3V1 P16 GDB0/IO66NPB3V1 T7 VCOMPLE U20 NC P17 IO60NDB3V1 T8 GNDQ U21 IO64NDB3V1 P18 IO60PDB3V1 T9 GEA2/IO101PPB5V2 U22 IO63PDB3V1 P19 IO61PDB3V1 T10 IO92NDB5V1 V1 NC P20 NC T11 IO90NDB5V1 V2 NC Revision 9 4-9 Package Pin Assignments FG484 FG484 Pin Pin Number AGLE600 Function Number AGLE600 Function V3 GND W16 IO68NDB4V0 V4 GEA1/IO102PDB6V0 W17 GDA2/IO68PDB4V0 V5 GEA0/IO102NDB6V0 W18 TMS V6 GNDQ W19 GND V7 GEC2/IO99PDB5V2 W20 NC V8 IO95NPB5V1 W21 NC V9 IO91NDB5V1 W22 NC V10 IO91PDB5V1 Y1 VCCIB6 V11 IO83NDB5V0 Y2 NC V12 IO83PDB5V0 Y3 NC V13 IO77NDB4V1 Y4 IO98NDB5V2 V14 IO77PDB4V1 Y5 GND V15 IO69NDB4V0 Y6 IO94NDB5V1 V16 GDB2/IO69PDB4V0 Y7 IO94PDB5V1 V17 TDI Y8 VCC V18 GNDQ Y9 VCC V19 TDO Y10 IO89PDB5V0 V20 GND Y11 IO80PDB4V1 V21 NC Y12 IO78NPB4V1 V22 IO63NDB3V1 Y13 NC W1 NC Y14 VCC W2 NC Y15 VCC W3 NC Y16 NC W4 GND Y17 NC W5 IO100NDB5V2 Y18 GND W6 FF/GEB2/IO100PDB5V2 Y19 NC W7 IO99NDB5V2 Y20 NC W8 IO88NDB5V0 Y21 NC W9 IO88PDB5V0 Y22 VCCIB3 W10 IO89NDB5V0 W11 IO80NDB4V1 W12 IO81NDB4V1 W13 IO81PDB4V1 W14 IO70NDB4V0 W15 GDC2/IO70PDB4V0 4-10 Revision 9 IGLOOe Low Power Flash FPGAs FG484 FG484 FG484 Pin Pin Pin Number AGLE3000 Function Number AGLE3000 Function Number AGLE3000 Function A1 GND AA14 IO170NDB4V2 B5 IO08PDB0V0 A2 GND AA15 IO170PDB4V2 B6 IO14NDB0V1 A3 VCCIB0 AA16 IO166NDB4V1 B7 IO14PDB0V1 A4 IO10NDB0V1 AA17 IO166PDB4V1 B8 IO18NDB0V2 A5 IO10PDB0V1 AA18 IO160NDB4V0 B9 IO24NDB0V2 A6 IO16NDB0V1 AA19 IO160PDB4V0 B10 IO34PDB0V4 A7 IO16PDB0V1 AA20 IO158NPB4V0 B11 IO40PDB0V4 A8 IO18PDB0V2 AA21 VCCIB3 B12 IO46NDB1V0 A9 IO24PDB0V2 AA22 GND B13 IO54NDB1V1 A10 IO28NDB0V3 AB1 GND B14 IO62NDB1V2 A11 IO28PDB0V3 AB2 GND B15 IO62PDB1V2 A12 IO46PDB1V0 AB3 VCCIB5 B16 IO68NDB1V3 A13 IO54PDB1V1 AB4 IO216NDB5V2 B17 IO68PDB1V3 A14 IO56NDB1V1 AB5 IO216PDB5V2 B18 IO72PDB1V3 A15 IO56PDB1V1 AB6 IO210NDB5V2 B19 IO74PDB1V4 A16 IO64NDB1V2 AB7 IO210PDB5V2 B20 IO76NPB1V4 A17 IO64PDB1V2 AB8 IO208NDB5V1 B21 VCCIB2 A18 IO72NDB1V3 AB9 IO208PDB5V1 B22 GND A19 IO74NDB1V4 AB10 IO197NDB5V0 C1 VCCIB7 A20 VCCIB1 AB11 IO197PDB5V0 C2 IO303PDB7V3 A21 GND AB12 IO174NDB4V2 C3 IO305PDB7V3 A22 GND AB13 IO174PDB4V2 C4 IO06NPB0V0 AA1 GND AB14 IO172NDB4V2 C5 GND AA2 VCCIB6 AB15 IO172PDB4V2 C6 IO12NDB0V1 AA3 IO228PDB5V4 AB16 IO168NDB4V1 C7 IO12PDB0V1 AA4 IO224PDB5V3 AB17 IO168PDB4V1 C8 VCC AA5 IO218NDB5V3 AB18 IO162NDB4V1 C9 VCC AA6 IO218PDB5V3 AB19 IO162PDB4V1 C10 IO34NDB0V4 AA7 IO212NDB5V2 AB20 VCCIB4 C11 IO40NDB0V4 AA8 IO212PDB5V2 AB21 GND C12 IO48NDB1V0 AA9 IO198PDB5V0 AB22 GND C13 IO48PDB1V0 AA10 IO198NDB5V0 B1 GND C14 VCC AA11 IO188PPB4V4 B2 VCCIB7 C15 VCC AA12 IO180NDB4V3 B3 IO06PPB0V0 C16 IO70NDB1V3 AA13 IO180PDB4V3 B4 IO08NDB0V0 C17 IO70PDB1V3 Revision 9 4-11 Package Pin Assignments FG484 FG484 FG484 Pin Pin Pin Number AGLE3000 Function Number AGLE3000 Function Number AGLE3000 Function C18 GND E9 IO22NDB0V2 F22 IO98NDB2V2 C19 IO76PPB1V4 E10 IO30NDB0V3 G1 IO289NDB7V1 C20 IO88NDB2V0 E11 IO38PDB0V4 G2 IO289PDB7V1 C21 IO94PPB2V1 E12 IO44NDB1V0 G3 IO291PPB7V2 C22 VCCIB2 E13 IO58NDB1V2 G4 IO295PDB7V2 D1 IO293PDB7V2 E14 IO58PDB1V2 G5 IO297PDB7V2 D2 IO303NDB7V3 E15 GBC1/IO79PDB1V4 G6 GAC2/IO307PDB7V4 D3 IO305NDB7V3 E16 GBB0/IO80NDB1V4 G7 VCOMPLA D4 GND E17 GNDQ G8 GNDQ D5 GAA0/IO00NDB0V0 E18 GBA2/IO82PDB2V0 G9 IO26NDB0V3 D6 GAA1/IO00PDB0V0 E19 IO86NDB2V0 G10 IO26PDB0V3 D7 GAB0/IO01NDB0V0 E20 GND G11 IO36PDB0V4 D8 IO20PDB0V2 E21 IO90NDB2V1 G12 IO42PDB1V0 D9 IO22PDB0V2 E22 IO98PDB2V2 G13 IO50PDB1V1 D10 IO30PDB0V3 F1 IO299NPB7V3 G14 IO60NDB1V2 D11 IO38NDB0V4 F2 IO301NDB7V3 G15 GNDQ D12 IO52NDB1V1 F3 IO301PDB7V3 G16 VCOMPLB D13 IO52PDB1V1 F4 IO308NDB7V4 G17 GBB2/IO83PDB2V0 D14 IO66NDB1V3 F5 IO309NDB7V4 G18 IO92PDB2V1 D15 IO66PDB1V3 F6 VMV7 G19 IO92NDB2V1 D16 GBB1/IO80PDB1V4 F7 VCCPLA G20 IO102PDB2V2 D17 GBA0/IO81NDB1V4 F8 GAC0/IO02NDB0V0 G21 IO102NDB2V2 D18 GBA1/IO81PDB1V4 F9 GAC1/IO02PDB0V0 G22 IO105NDB2V2 D19 GND F10 IO32NDB0V3 H1 IO286PSB7V1 D20 IO88PDB2V0 F11 IO32PDB0V3 H2 IO291NPB7V2 D21 IO90PDB2V1 F12 IO44PDB1V0 H3 VCC D22 IO94NPB2V1 F13 IO50NDB1V1 H4 IO295NDB7V2 E1 IO293NDB7V2 F14 IO60PDB1V2 H5 IO297NDB7V2 E2 IO299PPB7V3 F15 GBC0/IO79NDB1V4 H6 IO307NDB7V4 E3 GND F16 VCCPLB H7 IO287PDB7V1 E4 GAB2/IO308PDB7V4 F17 VMV2 H8 VMV0 E5 GAA2/IO309PDB7V4 F18 IO82NDB2V0 H9 VCCIB0 E6 GNDQ F19 IO86PDB2V0 H10 VCCIB0 E7 GAB1/IO01PDB0V0 F20 IO96PDB2V1 H11 IO36NDB0V4 E8 IO20NDB0V2 F21 IO96NDB2V1 H12 IO42NDB1V0 4-12 Revision 9 IGLOOe Low Power Flash FPGAs FG484 FG484 FG484 Pin Pin Pin Number AGLE3000 Function Number AGLE3000 Function Number AGLE3000 Function H13 VCCIB1 K4 IO279NDB7V0 L17 GCA0/IO114NPB3V0 H14 VCCIB1 K5 IO283NDB7V1 L18 VCOMPLC H15 VMV1 K6 IO281NDB7V0 L19 GCB0/IO113NPB2V3 H16 GBC2/IO84PDB2V0 K7 GFC1/IO275PPB7V0 L20 IO110PPB2V3 H17 IO83NDB2V0 K8 VCCIB7 L21 IO111NDB2V3 H18 IO100NDB2V2 K9 VCC L22 IO111PDB2V3 H19 IO100PDB2V2 K10 GND M1 GNDQ H20 VCC K11 GND M2 IO255NPB6V2 H21 VMV2 K12 GND M3 IO272NDB6V4 H22 IO105PDB2V2 K13 GND M4 GFA2/IO272PDB6V4 J1 IO285NDB7V1 K14 VCC M5 GFA1/IO273PDB6V4 J2 IO285PDB7V1 K15 VCCIB2 M6 VCCPLF J3 VMV7 K16 GCC1/IO112PPB2V3 M7 IO271NDB6V4 J4 IO279PDB7V0 K17 IO108NDB2V3 M8 GFB2/IO271PDB6V4 J5 IO283PDB7V1 K18 IO108PDB2V3 M9 VCC J6 IO281PDB7V0 K19 IO110NPB2V3 M10 GND J7 IO287NDB7V1 K20 IO106NPB2V3 M11 GND J8 VCCIB7 K21 IO109NDB2V3 M12 GND J9 GND K22 IO107NDB2V3 M13 GND J10 VCC L1 IO257PSB6V2 M14 VCC J11 VCC L2 IO276PDB7V0 M15 GCB2/IO116PPB3V0 J12 VCC L3 IO276NDB7V0 M16 GCA1/IO114PPB3V0 J13 VCC L4 GFB0/IO274NPB7V0 M17 GCC2/IO117PPB3V0 J14 GND L5 GFA0/IO273NDB6V4 M18 VCCPLC J15 VCCIB2 L6 GFB1/IO274PPB7V0 M19 GCA2/IO115PDB3V0 J16 IO84NDB2V0 L7 VCOMPLF M20 IO115NDB3V0 J17 IO104NDB2V2 L8 GFC0/IO275NPB7V0 M21 IO126PDB3V1 J18 IO104PDB2V2 L9 VCC M22 IO124PSB3V1 J19 IO106PPB2V3 L10 GND N1 IO255PPB6V2 J20 GNDQ L11 GND N2 IO253NDB6V2 J21 IO109PDB2V3 L12 GND N3 VMV6 J22 IO107PDB2V3 L13 GND N4 GFC2/IO270PPB6V4 K1 IO277NDB7V0 L14 VCC N5 IO261PPB6V3 K2 IO277PDB7V0 L15 GCC0/IO112NPB2V3 N6 IO263PDB6V3 K3 GNDQ L16 GCB1/IO113PPB2V3 N7 IO263NDB6V3 Revision 9 4-13 Package Pin Assignments FG484 FG484 FG484 Pin Pin Pin Number AGLE3000 Function Number AGLE3000 Function Number AGLE3000 Function N8 VCCIB6 P21 IO130PDB3V2 T12 IO194NDB5V0 N9 VCC P22 IO128NDB3V1 T13 IO186NDB4V4 N10 GND R1 IO247NDB6V1 T14 IO186PDB4V4 N11 GND R2 IO245PDB6V1 T15 GNDQ N12 GND R3 VCC T16 VCOMPLD N13 GND R4 IO249NPB6V1 T17 VJTAG N14 VCC R5 IO251NDB6V2 T18 GDC0/IO151NDB3V4 N15 VCCIB3 R6 IO251PDB6V2 T19 GDA1/IO153PDB3V4 N16 IO116NPB3V0 R7 GEC0/IO236NPB6V0 T20 IO144PDB3V3 N17 IO132NPB3V2 R8 VMV5 T21 IO140PDB3V3 N18 IO117NPB3V0 R9 VCCIB5 T22 IO134NDB3V2 N19 IO132PPB3V2 R10 VCCIB5 U1 IO240PPB6V0 N20 GNDQ R11 IO196NDB5V0 U2 IO238PDB6V0 N21 IO126NDB3V1 R12 IO196PDB5V0 U3 IO238NDB6V0 N22 IO128PDB3V1 R13 VCCIB4 U4 GEB1/IO235PDB6V0 P1 IO247PDB6V1 R14 VCCIB4 U5 GEB0/IO235NDB6V0 P2 IO253PDB6V2 R15 VMV3 U6 VMV6 P3 IO270NPB6V4 R16 VCCPLD U7 VCCPLE P4 IO261NPB6V3 R17 GDB1/IO152PPB3V4 U8 IO233NPB5V4 P5 IO249PPB6V1 R18 GDC1/IO151PDB3V4 U9 IO222PPB5V3 P6 IO259PDB6V3 R19 IO138NDB3V3 U10 IO206PDB5V1 P7 IO259NDB6V3 R20 VCC U11 IO202PDB5V1 P8 VCCIB6 R21 IO130NDB3V2 U12 IO194PDB5V0 P9 GND R22 IO134PDB3V2 U13 IO176NDB4V2 P10 VCC T1 IO243PPB6V1 U14 IO176PDB4V2 P11 VCC T2 IO245NDB6V1 U15 VMV4 P12 VCC T3 IO243NPB6V1 U16 TCK P13 VCC T4 IO241PDB6V0 U17 VPUMP P14 GND T5 IO241NDB6V0 U18 TRST P15 VCCIB3 T6 GEC1/IO236PPB6V0 U19 GDA0/IO153NDB3V4 P16 GDB0/IO152NPB3V4 T7 VCOMPLE U20 IO144NDB3V3 P17 IO136NDB3V2 T8 GNDQ U21 IO140NDB3V3 P18 IO136PDB3V2 T9 GEA2/IO233PPB5V4 U22 IO142PDB3V3 P19 IO138PDB3V3 T10 IO206NDB5V1 V1 IO239PDB6V0 P20 VMV3 T11 IO202NDB5V1 V2 IO240NPB6V0 4-14 Revision 9 IGLOOe Low Power Flash FPGAs FG484 FG484 Pin Pin Number AGLE3000 Function Number AGLE3000 Function V3 GND W15 GDC2/IO156PDB4V0 V4 GEA1/IO234PDB6V0 W16 IO154NDB4V0 V5 GEA0/IO234NDB6V0 W17 GDA2/IO154PDB4V0 V6 GNDQ W18 TMS V7 GEC2/IO231PDB5V4 W19 GND V8 IO222NPB5V3 W20 IO150NDB3V4 V9 IO204NDB5V1 W21 IO146NDB3V4 V10 IO204PDB5V1 W22 IO148PPB3V4 V11 IO195NDB5V0 Y1 VCCIB6 V12 IO195PDB5V0 Y2 IO237NDB6V0 V13 IO178NDB4V3 Y3 IO228NDB5V4 V14 IO178PDB4V3 Y4 IO224NDB5V3 V15 IO155NDB4V0 Y5 GND V16 GDB2/IO155PDB4V0 Y6 IO220NDB5V3 V17 TDI Y7 IO220PDB5V3 V18 GNDQ Y8 VCC V19 TDO Y9 VCC V20 GND Y10 IO200PDB5V0 V21 IO146PDB3V4 Y11 IO192PDB4V4 V22 IO142NDB3V3 Y12 IO188NPB4V4 W1 IO239NDB6V0 Y13 IO187PSB4V4 W2 IO237PDB6V0 Y14 VCC W3 IO230PSB5V4 Y15 VCC W4 GND Y16 IO164NDB4V1 W5 IO232NDB5V4 Y17 IO164PDB4V1 W6 FF/GEB2/IO232PDB5 Y18 GND V4 Y19 IO158PPB4V0 W7 IO231NDB5V4 Y20 IO150PDB3V4 W8 IO214NDB5V2 Y21 IO148NPB3V4 W9 IO214PDB5V2 Y22 VCCIB3 W10 IO200NDB5V0 W11 IO192NDB4V4 W12 IO184NDB4V3 W13 IO184PDB4V3 W14 IO156NDB4V0 Revision 9 4-15 Package Pin Assignments FG896 A1 Ball Pad Corner 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 4-16 Revision 9 IGLOOe Low Power Flash FPGAs FG896 FG896 FG896 AGLE3000 AGLE3000 AGLE3000 Pin Number Function Pin Number Function Pin Number Function A2 GND AA8 IO245NDB6V1 AB13 IO206PDB5V1 A3 GND AA9 GEB1/IO235PPB6V0 AB14 IO198NDB5V0 A4 IO14NPB0V1 AA10 VCC AB15 IO198PDB5V0 A5 GND AA11 IO226PPB5V4 AB16 IO192NDB4V4 A6 IO07NPB0V0 AA12 VCCIB5 AB17 IO192PDB4V4 A7 GND AA13 VCCIB5 AB18 IO178NDB4V3 A8 IO09NDB0V1 AA14 VCCIB5 AB19 IO178PDB4V3 A9 IO17NDB0V2 AA15 VCCIB5 AB20 IO174NDB4V2 A10 IO17PDB0V2 AA16 VCCIB4 AB21 IO162NPB4V1 A11 IO21NDB0V2 AA17 VCCIB4 AB22 VCC A12 IO21PDB0V2 AA18 VCCIB4 AB23 VCCPLD A13 IO33NDB0V4 AA19 VCCIB4 AB24 VCCIB3 A14 IO33PDB0V4 AA20 IO174PDB4V2 AB25 IO150PDB3V4 A15 IO35NDB0V4 AA21 VCC AB26 IO148PDB3V4 A16 IO35PDB0V4 AA22 IO142NPB3V3 AB27 IO147NDB3V4 A17 IO41NDB1V0 AA23 IO144NDB3V3 AB28 IO145PDB3V3 A18 IO43NDB1V0 AA24 IO144PDB3V3 AB29 IO143PDB3V3 A19 IO43PDB1V0 AA25 IO146NDB3V4 AB30 IO137PDB3V2 A20 IO45NDB1V0 AA26 IO146PDB3V4 AC1 IO254PDB6V2 A21 IO45PDB1V0 AA27 IO147PDB3V4 AC2 IO254NDB6V2 A22 IO57NDB1V2 AA28 IO139NDB3V3 AC3 IO240PDB6V0 A23 IO57PDB1V2 AA29 IO139PDB3V3 AC4 GEC1/IO236PDB6V0 A24 GND AA30 IO133NDB3V2 AC5 IO237PDB6V0 A25 IO69PPB1V3 AB1 IO256NDB6V2 AC6 IO237NDB6V0 A26 GND AB2 IO244PDB6V1 AC7 VCOMPLE A27 GBC1/IO79PPB1V4 AB3 IO244NDB6V1 AC8 GND A28 GND AB4 IO241PDB6V0 AC9 IO226NPB5V4 A29 GND AB5 IO241NDB6V0 AC10 IO222NDB5V3 AA1 IO256PDB6V2 AB6 IO243NPB6V1 AC11 IO216NPB5V2 AA2 IO248PDB6V1 AB7 VCCIB6 AC12 IO210NPB5V2 AA3 IO248NDB6V1 AB8 VCCPLE AC13 IO204NDB5V1 AA4 IO246NDB6V1 AB9 VCC AC14 IO204PDB5V1 AA5 GEA1/IO234PDB6V0 AB10 IO222PDB5V3 AC15 IO194NDB5V0 AA6 GEA0/IO234NDB6V0 AB11 IO218PPB5V3 AC16 IO188NDB4V4 AA7 IO243PPB6V1 AB12 IO206NDB5V1 AC17 IO188PDB4V4 Revision 9 4-17 Package Pin Assignments FG896 FG896 FG896 AGLE3000 AGLE3000 AGLE3000 Pin Number Function Pin Number Function Pin Number Function AC18 IO182PPB4V3 AD22 VCCIB4 AE26 GDB0/IO152NDB3V4 AC19 IO170NPB4V2 AD23 TCK AE27 GDB1/IO152PDB3V4 AC20 IO164NDB4V1 AD24 VCC AE28 VMV3 AC21 IO164PDB4V1 AD25 TRST AE28 VMV3 AC22 IO162PPB4V1 AD26 VCCIB3 AE29 VCC AC23 GND AD27 GDA0/IO153NDB3V4 AE30 IO149PDB3V4 AC24 VCOMPLD AD28 GDC0/IO151NDB3V4 AF1 GND AC25 IO150NDB3V4 AD29 GDC1/IO151PDB3V4 AF2 IO238PPB6V0 AC26 IO148NDB3V4 AD30 GND AF3 VCCIB6 AC27 GDA1/IO153PDB3V4 AE1 IO242PPB6V1 AF4 IO220NPB5V3 AC28 IO145NDB3V3 AE2 VCC AF5 VCC AC29 IO143NDB3V3 AE3 IO239PDB6V0 AF6 IO228NDB5V4 AC30 IO137NDB3V2 AE4 IO239NDB6V0 AF7 VCCIB5 AD1 GND AE5 VMV6 AF8 IO230PDB5V4 AD2 IO242NPB6V1 AE5 VMV6 AF9 IO229NDB5V4 AD3 IO240NDB6V0 AE6 GND AF10 IO229PDB5V4 AD4 GEC0/IO236NDB6V0 AE7 GNDQ AF11 IO214PPB5V2 AD5 VCCIB6 AE8 IO230NDB5V4 AF12 IO208NDB5V1 AD6 GNDQ AE9 IO224NPB5V3 AF13 IO208PDB5V1 AD6 GNDQ AE10 IO214NPB5V2 AF14 IO200PDB5V0 AD7 VCC AE11 IO212NDB5V2 AF15 IO196NDB5V0 AD8 VMV5 AE12 IO212PDB5V2 AF16 IO186NDB4V4 AD9 VCCIB5 AE13 IO202NPB5V1 AF17 IO186PDB4V4 AD10 IO224PPB5V3 AE14 IO200NDB5V0 AF18 IO180NDB4V3 AD11 IO218NPB5V3 AE15 IO196PDB5V0 AF19 IO180PDB4V3 AD12 IO216PPB5V2 AE16 IO190NDB4V4 AF20 IO168NDB4V1 AD13 IO210PPB5V2 AE17 IO184PDB4V3 AF21 IO168PDB4V1 AD14 IO202PPB5V1 AE18 IO184NDB4V3 AF22 IO160NDB4V0 AD15 IO194PDB5V0 AE19 IO172PDB4V2 AF23 IO158NPB4V0 AD16 IO190PDB4V4 AE20 IO172NDB4V2 AF24 VCCIB4 AD17 IO182NPB4V3 AE21 IO166NDB4V1 AF25 IO154NPB4V0 AD18 IO176NDB4V2 AE22 IO160PDB4V0 AF26 VCC AD19 IO176PDB4V2 AE23 GNDQ AF27 TDO AD20 IO170PPB4V2 AE24 VMV4 AF28 VCCIB3 AD21 IO166PDB4V1 AE25 GND AF29 GNDQ 4-18 Revision 9 IGLOOe Low Power Flash FPGAs FG896 FG896 FG896 AGLE3000 AGLE3000 AGLE3000 Pin Number Function Pin Number Function Pin Number Function AF29 GNDQ AH4 FF/GEB2/IO232PPB5 AJ8 IO213NDB5V2 V4 AF30 GND AJ9 IO213PDB5V2 AH5 VCCIB5 AG1 IO238NPB6V0 AJ10 IO209NDB5V1 AH6 IO219NDB5V3 AG2 VCC AJ11 IO209PDB5V1 AH7 IO219PDB5V3 AG3 IO232NPB5V4 AJ12 IO203NDB5V1 AH8 IO227NDB5V4 AG4 GND AJ13 IO203PDB5V1 AH9 IO227PDB5V4 AG5 IO220PPB5V3 AJ14 IO197NDB5V0 AH10 IO225PPB5V3 AG6 IO228PDB5V4 AJ15 IO195PDB5V0 AH11 IO223PPB5V3 AG7 IO231NDB5V4 AJ16 IO183NDB4V3 AH12 IO211NDB5V2 AG8 GEC2/IO231PDB5V4 AJ17 IO183PDB4V3 AH13 IO211PDB5V2 AG9 IO225NPB5V3 AJ18 IO179NPB4V3 AH14 IO205PPB5V1 AG10 IO223NPB5V3 AJ19 IO177PDB4V2 AH15 IO195NDB5V0 AG11 IO221PDB5V3 AJ20 IO173NDB4V2 AH16 IO185NDB4V3 AG12 IO221NDB5V3 AJ21 IO173PDB4V2 AH17 IO185PDB4V3 AG13 IO205NPB5V1 AJ22 IO163NDB4V1 AH18 IO181PDB4V3 AG14 IO199NDB5V0 AJ23 IO163PDB4V1 AH19 IO177NDB4V2 AG15 IO199PDB5V0 AJ24 IO167NPB4V1 AH20 IO171NPB4V2 AG16 IO187NDB4V4 AJ25 VCC AH21 IO165PPB4V1 AG17 IO187PDB4V4 AJ26 IO156NPB4V0 AH22 IO161PPB4V0 AG18 IO181NDB4V3 AJ27 VCC AH23 IO157NDB4V0 AG19 IO171PPB4V2 AJ28 TMS AH24 IO157PDB4V0 AG20 IO165NPB4V1 AJ29 GND AH25 IO155NDB4V0 AG21 IO161NPB4V0 AJ30 GND AH26 VCCIB4 AG22 IO159NDB4V0 AK2 GND AH27 TDI AG23 IO159PDB4V0 AK3 GND AH28 VCC AG24 IO158PPB4V0 AK4 IO217PPB5V2 AH29 VPUMP AG25 GDB2/IO155PDB4V0 AK5 GND AH30 GND AG26 GDA2/IO154PPB4V0 AK6 IO215PPB5V2 AJ1 GND AG27 GND AK7 GND AJ2 GND AG28 VJTAG AK8 IO207NDB5V1 AJ3 GEA2/IO233PPB5V4 AG29 VCC AK9 IO207PDB5V1 AJ4 VCC AG30 IO149NDB3V4 AK10 IO201NDB5V0 AJ5 IO217NPB5V2 AH1 GND AK11 IO201PDB5V0 AJ6 VCC AH2 IO233NPB5V4 AK12 IO193NDB4V4 AJ7 IO215NPB5V2 AH3 VCC AK13 IO193PDB4V4 Revision 9 4-19 Package Pin Assignments FG896 FG896 FG896 AGLE3000 AGLE3000 AGLE3000 Pin Number Function Pin Number Function Pin Number Function AK14 IO197PDB5V0 B20 IO53PDB1V1 C25 IO75PDB1V4 AK15 IO191NDB4V4 B21 IO53NDB1V1 C26 VCCIB1 AK16 IO191PDB4V4 B22 IO61NDB1V2 C27 IO64PPB1V2 AK17 IO189NDB4V4 B23 IO61PDB1V2 C28 VCC AK18 IO189PDB4V4 B24 IO69NPB1V3 C29 GBA1/IO81PPB1V4 AK19 IO179PPB4V3 B25 VCC C30 GND AK20 IO175NDB4V2 B26 GBC0/IO79NPB1V4 D1 IO303PPB7V3 AK21 IO175PDB4V2 B27 VCC D2 VCC AK22 IO169NDB4V1 B28 IO64NPB1V2 D3 IO305NPB7V3 AK23 IO169PDB4V1 B29 GND D4 GND AK24 GND B30 GND D5 GAA1/IO00PPB0V0 AK25 IO167PPB4V1 C1 GND D6 GAC1/IO02PDB0V0 AK26 GND C2 IO309NPB7V4 D7 IO06NPB0V0 AK27 GDC2/IO156PPB4V0 C3 VCC D8 GAB0/IO01NDB0V0 AK28 GND C4 GAA0/IO00NPB0V0 D9 IO05NDB0V0 AK29 GND C5 VCCIB0 D10 IO11NDB0V1 B1 GND C6 IO03PDB0V0 D11 IO11PDB0V1 B2 GND C7 IO03NDB0V0 D12 IO23NDB0V2 B3 GAA2/IO309PPB7V4 C8 GAB1/IO01PDB0V0 D13 IO23PDB0V2 B4 VCC C9 IO05PDB0V0 D14 IO27PDB0V3 B5 IO14PPB0V1 C10 IO15NPB0V1 D15 IO40PDB0V4 B6 VCC C11 IO25NDB0V3 D16 IO47NDB1V0 B7 IO07PPB0V0 C12 IO25PDB0V3 D17 IO47PDB1V0 B8 IO09PDB0V1 C13 IO31NPB0V3 D18 IO55NPB1V1 B9 IO15PPB0V1 C14 IO27NDB0V3 D19 IO65NDB1V3 B10 IO19NDB0V2 C15 IO39NDB0V4 D20 IO65PDB1V3 B11 IO19PDB0V2 C16 IO39PDB0V4 D21 IO71NDB1V3 B12 IO29NDB0V3 C17 IO55PPB1V1 D22 IO71PDB1V3 B13 IO29PDB0V3 C18 IO51PDB1V1 D23 IO73NDB1V4 B14 IO31PPB0V3 C19 IO59NDB1V2 D24 IO73PDB1V4 B15 IO37NDB0V4 C20 IO63NDB1V2 D25 IO74NDB1V4 B16 IO37PDB0V4 C21 IO63PDB1V2 D26 GBB0/IO80NPB1V4 B17 IO41PDB1V0 C22 IO67NDB1V3 D27 GND B18 IO51NDB1V1 C23 IO67PDB1V3 D28 GBA0/IO81NPB1V4 B19 IO59PDB1V2 C24 IO75NDB1V4 D29 VCC 4-20 Revision 9 IGLOOe Low Power Flash FPGAs FG896 FG896 FG896 AGLE3000 AGLE3000 AGLE3000 Pin Number Function Pin Number Function Pin Number Function D30 GBA2/IO82PPB2V0 F5 VMV7 G7 VCC E1 GND F5 VMV7 G8 VMV0 E2 IO303NPB7V3 F6 GND G9 VCCIB0 E3 VCCIB7 F7 GNDQ G10 IO10NDB0V1 E4 IO305PPB7V3 F8 IO12NDB0V1 G11 IO16NDB0V1 E5 VCC F9 IO12PDB0V1 G12 IO22PDB0V2 E6 GAC0/IO02NDB0V0 F10 IO10PDB0V1 G13 IO26PPB0V3 E7 VCCIB0 F11 IO16PDB0V1 G14 IO38NPB0V4 E8 IO06PPB0V0 F12 IO22NDB0V2 G15 IO36NDB0V4 E9 IO24NDB0V2 F13 IO30NDB0V3 G16 IO46NDB1V0 E10 IO24PDB0V2 F14 IO30PDB0V3 G17 IO46PDB1V0 E11 IO13NDB0V1 F15 IO36PDB0V4 G18 IO56NDB1V1 E12 IO13PDB0V1 F16 IO48NDB1V0 G19 IO56PDB1V1 E13 IO34NDB0V4 F17 IO48PDB1V0 G20 IO66NDB1V3 E14 IO34PDB0V4 F18 IO50NDB1V1 G21 IO66PDB1V3 E15 IO40NDB0V4 F19 IO58NDB1V2 G22 VCCIB1 E16 IO49NDB1V1 F20 IO60PDB1V2 G23 VMV1 E17 IO49PDB1V1 F21 IO77NDB1V4 G24 VCC E18 IO50PDB1V1 F22 IO72NDB1V3 G25 GNDQ E19 IO58PDB1V2 F23 IO72PDB1V3 G25 GNDQ E20 IO60NDB1V2 F24 GNDQ G26 VCCIB2 E21 IO77PDB1V4 F25 GND G27 IO86NDB2V0 E22 IO68NDB1V3 F26 VMV2 G28 IO92NDB2V1 E23 IO68PDB1V3 F26 VMV2 G29 IO100PPB2V2 E24 VCCIB1 F27 IO86PDB2V0 G30 GND E25 IO74PDB1V4 F28 IO92PDB2V1 H1 IO294PDB7V2 E26 VCC F29 VCC H2 IO294NDB7V2 E27 GBB1/IO80PPB1V4 F30 IO100NPB2V2 H3 IO300NDB7V3 E28 VCCIB2 G1 GND H4 IO300PDB7V3 E29 IO82NPB2V0 G2 IO296NPB7V2 H5 IO295PDB7V2 E30 GND G3 IO306NDB7V4 H6 IO299PDB7V3 F1 IO296PPB7V2 G4 IO297NDB7V2 H7 VCOMPLA F2 VCC G5 VCCIB7 H8 GND F3 IO306PDB7V4 G6 GNDQ H9 IO08NDB0V0 F4 IO297PDB7V2 G6 GNDQ H10 IO08PDB0V0 Revision 9 4-21 Package Pin Assignments FG896 FG896 FG896 AGLE3000 AGLE3000 AGLE3000 Pin Number Function Pin Number Function Pin Number Function H11 IO18PDB0V2 J16 IO42PDB1V0 K21 VCC H12 IO26NPB0V3 J17 IO44NDB1V0 K22 IO78PPB1V4 H13 IO28NDB0V3 J18 IO44PDB1V0 K23 IO88NDB2V0 H14 IO28PDB0V3 J19 IO54NDB1V1 K24 IO88PDB2V0 H15 IO38PPB0V4 J20 IO54PDB1V1 K25 IO94PDB2V1 H16 IO42NDB1V0 J21 IO76NPB1V4 K26 IO94NDB2V1 H17 IO52NDB1V1 J22 VCC K27 IO85PDB2V0 H18 IO52PDB1V1 J23 VCCPLB K28 IO85NDB2V0 H19 IO62NDB1V2 J24 VCCIB2 K29 IO93PDB2V1 H20 IO62PDB1V2 J25 IO90PDB2V1 K30 IO93NDB2V1 H21 IO70NDB1V3 J26 IO90NDB2V1 L1 IO286NDB7V1 H22 IO70PDB1V3 J27 GBB2/IO83PDB2V0 L2 IO286PDB7V1 H23 GND J28 IO83NDB2V0 L3 IO298NDB7V3 H24 VCOMPLB J29 IO91PDB2V1 L4 IO298PDB7V3 H25 GBC2/IO84PDB2V0 J30 IO91NDB2V1 L5 IO283PDB7V1 H26 IO84NDB2V0 K1 IO288NDB7V1 L6 IO291NDB7V2 H27 IO96PDB2V1 K2 IO288PDB7V1 L7 IO291PDB7V2 H28 IO96NDB2V1 K3 IO304NDB7V3 L8 IO293PDB7V2 H29 IO89PDB2V0 K4 IO304PDB7V3 L9 IO293NDB7V2 H30 IO89NDB2V0 K5 GAB2/IO308PDB7V4 L10 IO307NPB7V4 J1 IO290NDB7V2 K6 IO308NDB7V4 L11 VCC J2 IO290PDB7V2 K7 IO301PDB7V3 L12 VCC J3 IO302NDB7V3 K8 IO301NDB7V3 L13 VCC J4 IO302PDB7V3 K9 GAC2/IO307PPB7V4 L14 VCC J5 IO295NDB7V2 K10 VCC L15 VCC J6 IO299NDB7V3 K11 IO04PPB0V0 L16 VCC J7 VCCIB7 K12 VCCIB0 L17 VCC J8 VCCPLA K13 VCCIB0 L18 VCC J9 VCC K14 VCCIB0 L19 VCC J10 IO04NPB0V0 K15 VCCIB0 L20 VCC J11 IO18NDB0V2 K16 VCCIB1 L21 IO78NPB1V4 J12 IO20NDB0V2 K17 VCCIB1 L22 IO104NPB2V2 J13 IO20PDB0V2 K18 VCCIB1 L23 IO98NDB2V2 J14 IO32NDB0V3 K19 VCCIB1 L24 IO98PDB2V2 J15 IO32PDB0V3 K20 IO76PPB1V4 L25 IO87PDB2V0 4-22 Revision 9 IGLOOe Low Power Flash FPGAs FG896 FG896 FG896 AGLE3000 AGLE3000 AGLE3000 Pin Number Function Pin Number Function Pin Number Function L26 IO87NDB2V0 N1 IO276PDB7V0 P6 GFC1/IO275PDB7V0 L27 IO97PDB2V1 N2 IO278PDB7V0 P7 GFC0/IO275NDB7V0 L28 IO101PDB2V2 N3 IO280PDB7V0 P8 IO277PDB7V0 L29 IO103PDB2V2 N4 IO284PDB7V1 P9 IO277NDB7V0 L30 IO119NDB3V0 N5 IO279PDB7V0 P10 VCCIB7 M1 IO282NDB7V1 N6 IO285NDB7V1 P11 VCC M2 IO282PDB7V1 N7 IO287NDB7V1 P12 GND M3 IO292NDB7V2 N8 IO281NDB7V0 P13 GND M4 IO292PDB7V2 N9 IO281PDB7V0 P14 GND M5 IO283NDB7V1 N10 VCCIB7 P15 GND M6 IO285PDB7V1 N11 VCC P16 GND M7 IO287PDB7V1 N12 GND P17 GND M8 IO289PDB7V1 N13 GND P18 GND M9 IO289NDB7V1 N14 GND P19 GND M10 VCCIB7 N15 GND P20 VCC M11 VCC N16 GND P21 VCCIB2 M12 GND N17 GND P22 GCC1/IO112PDB2V3 M13 GND N18 GND P23 IO110PDB2V3 M14 GND N19 GND P24 IO110NDB2V3 M15 GND N20 VCC P25 IO109PPB2V3 M16 GND N21 VCCIB2 P26 IO111NPB2V3 M17 GND N22 IO106NDB2V3 P27 IO105PDB2V2 M18 GND N23 IO106PDB2V3 P28 IO105NDB2V2 M19 GND N24 IO108PDB2V3 P29 GCC2/IO117PDB3V0 M20 VCC N25 IO108NDB2V3 P30 IO117NDB3V0 M21 VCCIB2 N26 IO95NDB2V1 R1 GFC2/IO270PDB6V4 M22 NC N27 IO99NDB2V2 R2 GFB1/IO274PPB7V0 M23 IO104PPB2V2 N28 IO99PDB2V2 R3 VCOMPLF M24 IO102PDB2V2 N29 IO107PDB2V3 R4 GFA0/IO273NDB6V4 M25 IO102NDB2V2 N30 IO107NDB2V3 R5 GFB0/IO274NPB7V0 M26 IO95PDB2V1 P1 IO276NDB7V0 R6 IO271NDB6V4 M27 IO97NDB2V1 P2 IO278NDB7V0 R7 GFB2/IO271PDB6V4 M28 IO101NDB2V2 P3 IO280NDB7V0 R8 IO269PDB6V4 M29 IO103NDB2V2 P4 IO284NDB7V1 R9 IO269NDB6V4 M30 IO119PDB3V0 P5 IO279NDB7V0 R10 VCCIB7 Revision 9 4-23 Package Pin Assignments FG896 FG896 FG896 AGLE3000 AGLE3000 AGLE3000 Pin Number Function Pin Number Function Pin Number Function R11 VCC T16 GND U21 VCCIB3 R12 GND T17 GND U22 IO120PDB3V0 R13 GND T18 GND U23 IO128PDB3V1 R14 GND T19 GND U24 IO124PDB3V1 R15 GND T20 VCC U25 IO124NDB3V1 R16 GND T21 VCCIB3 U26 IO126PDB3V1 R17 GND T22 IO109NPB2V3 U27 IO129PDB3V1 R18 GND T23 IO116NDB3V0 U28 IO127PDB3V1 R19 GND T24 IO118NDB3V0 U29 IO125PDB3V1 R20 VCC T25 IO122NPB3V1 U30 IO121NDB3V0 R21 VCCIB2 T26 GCA1/IO114PPB3V0 V1 IO268NDB6V4 R22 GCC0/IO112NDB2V3 T27 GCB0/IO113NPB2V3 V2 IO262PDB6V3 R23 GCB2/IO116PDB3V0 T28 GCA2/IO115PPB3V0 V3 IO260PDB6V3 R24 IO118PDB3V0 T29 VCCPLC V4 IO252PDB6V2 R25 IO111PPB2V3 T30 IO121PDB3V0 V5 IO257NPB6V2 R26 IO122PPB3V1 U1 IO268PDB6V4 V6 IO261NPB6V3 R27 GCA0/IO114NPB3V0 U2 IO264NDB6V3 V7 IO255PDB6V2 R28 VCOMPLC U3 IO264PDB6V3 V8 IO259PDB6V3 R29 GCB1/IO113PPB2V3 U4 IO258PDB6V3 V9 IO259NDB6V3 R30 IO115NPB3V0 U5 IO258NDB6V3 V10 VCCIB6 T1 IO270NDB6V4 U6 IO257PPB6V2 V11 VCC T2 VCCPLF U7 IO261PPB6V3 V12 GND T3 GFA2/IO272PPB6V4 U8 IO265NDB6V3 V13 GND T4 GFA1/IO273PDB6V4 U9 IO263NDB6V3 V14 GND T5 IO272NPB6V4 U10 VCCIB6 V15 GND T6 IO267NDB6V4 U11 VCC V16 GND T7 IO267PDB6V4 U12 GND V17 GND T8 IO265PDB6V3 U13 GND V18 GND T9 IO263PDB6V3 U14 GND V19 GND T10 VCCIB6 U15 GND V20 VCC T11 VCC U16 GND V21 VCCIB3 T12 GND U17 GND V22 IO120NDB3V0 T13 GND U18 GND V23 IO128NDB3V1 T14 GND U19 GND V24 IO132PDB3V2 T15 GND U20 VCC V25 IO130PPB3V2 4-24 Revision 9 IGLOOe Low Power Flash FPGAs FG896 FG896 AGLE3000 AGLE3000 Pin Number Function Pin Number Function V26 IO126NDB3V1 Y1 IO266PDB6V4 V27 IO129NDB3V1 Y2 IO250PDB6V2 V28 IO127NDB3V1 Y3 IO250NDB6V2 V29 IO125NDB3V1 Y4 IO246PDB6V1 V30 IO123PDB3V1 Y5 IO247NDB6V1 W1 IO266NDB6V4 Y6 IO247PDB6V1 W2 IO262NDB6V3 Y7 IO249NPB6V1 W3 IO260NDB6V3 Y8 IO245PDB6V1 W4 IO252NDB6V2 Y9 IO253NDB6V2 W5 IO251NDB6V2 Y10 GEB0/IO235NPB6V0 W6 IO251PDB6V2 Y11 VCC W7 IO255NDB6V2 Y12 VCC W8 IO249PPB6V1 Y13 VCC W9 IO253PDB6V2 Y14 VCC W10 VCCIB6 Y15 VCC W11 VCC Y16 VCC W12 GND Y17 VCC W13 GND Y18 VCC W14 GND Y19 VCC W15 GND Y20 VCC W16 GND Y21 IO142PPB3V3 W17 GND Y22 IO134NDB3V2 W18 GND Y23 IO138NDB3V3 W19 GND Y24 IO140NDB3V3 W20 VCC Y25 IO140PDB3V3 W21 VCCIB3 Y26 IO136PPB3V2 W22 IO134PDB3V2 Y27 IO141NDB3V3 W23 IO138PDB3V3 Y28 IO135NDB3V2 W24 IO132NDB3V2 Y29 IO131NDB3V2 W25 IO136NPB3V2 Y30 IO133PDB3V2 W26 IO130NPB3V2 W27 IO141PDB3V3 W28 IO135PDB3V2 W29 IO131PDB3V2 W30 IO123NDB3V1 Revision 9 4-25 5 – Datasheet Information List of Changes The following table lists critical changes that were made in each revision of the IGLOOe datasheet. Revision Changes Page Revision 9 The "In-System Programming (ISP) and Security" section and "Security" section I, 1-2 (March 2012) were revised to clarify that although no existing security measures can give an absolute guarantee, Microsemi FPGAs implement the best security available in the industry (SAR 34665). The Y security option and Licensed DPA Logo were added to the "IGLOOe III Ordering Information" section. The trademarked Licensed DPA Logo identifies that a product is covered by a DPA counter-measures license from Cryptography Research (SAR 34725). The following sentence was removed from the "Advanced Architecture" section: 1-3 "In addition, extensive on-chip programming circuitry allows for rapid, single- voltage (3.3V) programming of IGLOOe devices via an IEEE 1532 JTAG interface" (SAR 34685). The "Specifying I/O States During Programming" section is new (SAR 34696). 1-7 Values for VCCPLL at 1.5 V DC core supply voltage were revised from "1.4 to 2-2 1.6 V" to "1.425 to 1.575 V" in Table 2-2 • Recommended Operating Conditions 1 (SAR 32292). The reference to guidelines for global spines and VersaTile rows, given in the 2-13 "Global Clock Contribution—PCLOCK" section, was corrected to the "Spine Architecture" section of the Global Resources chapter in the IGLOOe FPGA Fabric User's Guide (SAR 34731). The example in the paragraph above Table 2-30 • Duration of Short Circuit Event 2-30 before Failure was revised to change the maximum temperature from 110°C to 100°C, with an example of six months instead of three months (SAR 32287). The notes regarding drive strength in the "Summary of I/O Timing Characteristics 2-23, – Default I/O Software Settings" section, "3.3 V LVCMOS Wide Range" section 2-34, 2-47 and "1.2 V LVCMOS Wide Range" section tables were revised for clarification. They now state that the minimum drive strength for the default software configuration when run in wide range is ±100 µA. The drive strength displayed in software is supported in normal range only. For a detailed I/V curve, refer to the IBIS models (SAR 34766). The AC Loading figures in the "Single-Ended I/O Characteristics" section were 2-31 updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O Software Settings" section (SAR 34886). The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 2-37 34793): "It uses a 5 V–tolerant input buffer and push-pull output buffer." Table 2-142 • IGLOOe CCC/PLL Specification and Table 2-143 • IGLOOe 2-90, 2-91 CCC/PLL Specification were updated. A note was added to both tables indicating that when the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available (SAR 34818). Revision 9 5-1 Datasheet Information Revision Changes Page Revision 9 The following figures were deleted. Reference was made to a new application (continued) note, Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based cSoCs and FPGAs, which covers these cases in detail (SAR 34869). Figure 2-46 • Write Access after Write onto Same Address Figure 2-47 • Read Access after Write onto Same Address Figure 2-48 • Write Access after Read onto Same Address 2-94, The port names in the SRAM "Timing Waveforms", SRAM "Timing 2-97, Characteristics" tables, Figure 2-48 • FIFO Reset, and the FIFO "Timing 2-102, Characteristics" tables were revised to ensure consistency with the software 2-104 names (SAR 35749). The "Pin Descriptions and Packaging" chapter is new (SAR 34768). 3-1 Package names used in the "Package Pin Assignments" section were revised to 4-1 match standards given in Package Mechanical Drawings (SAR 34769) July 2010 The versioning system for datasheets has been changed. Datasheets are N/A assigned a revision number that increments each time the datasheet is revised. The "IGLOOe Device Status" table on page II indicates the status for each device in the device family. 5-2 Revision 9 IGLOOe Low Power Flash FPGAs Revision Changes Page Revision 8 (Nov 2009) The version changed to v2.0 for IGLOOe datasheet chapters, indicating the N/A datasheet contains information based on final characterization. Product Brief v2.0 The "Pro (Professional) I/O" section was revised to add "Hot-swappable and cold- I sparing I/Os." The "Reprogrammable Flash Technology" section was revised to add "250 MHz I (1.5 V systems) and 160 MHz (1.2 V systems) System Performance." Definitions of hot-swap and cold-sparing were added to the "Pro I/Os with 1-7 Advanced I/O Standards" section. DC and Switching 3.3 V LVCMOS and 1.2 V LVCMOS Wide Range support was added to the N/A Characteristics v2.0 datasheet. This affects all tables that contained 3.3 V LVCMOS and 1.2 V LVCMOS data. IIL and IIH input leakage current information was added to all "Minimum and N/A Maximum DC Input and Output Levels" tables. Values for 1.2 V wide range DC core supply voltage were added to Table 2-2 • 2-2 Recommended Operating Conditions 1. Table notes regarding 3.3 V wide range and the core voltage required for programming were added to the table. The data in Table 2-6 • Temperature and Voltage Derating Factors for Timing 2-6 Delays (1.5 V DC core supply voltage) and Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (1.2 V DC core supply voltage) was revised. 3.3 V LVCMOS wide range data was included in Table 2-12 • Summary of I/O 2-9, 2-10 Input Buffer Power (per pin) – Default I/O Software Settings and Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1. Table notes were added in connection with this data. The temperature was revised from 110ºC to 100ºC in Table 2-30 • Duration of 2-30, 2-30 Short Circuit Event before Failure and Table 2-32 • I/O Input Rise Time, Fall Time, and Related I/O Reliability*. The tables in the "Overview of I/O Performance" section and "Detailed I/O DC 2-20, 2-27 Characteristics" sectionwere revised to include 3.3 V LVCMOS and 1.2 V LVCMOS wide range. Most tables were updated in the following sections, revising existing values and 2-31, adding information for 3.3 V and 1.2 V wide range: 2-50, 2-61 "Single-Ended I/O Characteristics" "Voltage-Referenced I/O Characteristics" "Differential I/O Characteristics" The value for "Delay range in block: fixed delay" was revised in Table 2-142 • 2-90, 2-91 IGLOOe CCC/PLL Specification and Table 2-143 • IGLOOe CCC/PLL Specification. The timing characteristics tables for RAM4K9 and RAM512X18 were updated, 2-97 – including renaming of the address collision parameters. 2-100 Revision 7 (Apr 2009) The –F speed grade is no longer offered for IGLOOe devices and was removed III, IV from the documentation. The speed grade column and note regarding –F speed Product Brief v1.4 grade were removed from "IGLOOe Ordering Information". The "Speed Grade DC and Switching and Temperature Grade Matrix" section was removed. Characteristics Advance v0.4 Revision 9 5-3 Datasheet Information Revision Changes Page Revision 6 (Feb 2009) The "Pro (Professional) I/O" section was revised to add two bullets regarding I wide range power supply voltage support. Product Brief v1.3 3.0 V was added to the list of supported voltages in the "Pro I/Os with Advanced 1-7 I/O Standards" section. The "Wide Range I/O Support" section is new. Revision 5 (Oct 2008) The Quiescent Current values in Table 1 • IGLOOe Product Family table were I updated. Product Brief v1.2 Revision 4 (Jul 2008) As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core N/A voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to Product Brief v1.1 1.5 V. DC and Switching Characteristics Advance v0.3 Revision 3 (Jun 2008) Tables have been updated to reflect default values in the software. The default N/A I/O capacitance is 5 pF. Tables have been updated to include the LVCMOS 1.2 V DC and Switching I/O set. Characteristics Advance v0.2 DDR Tables have two additional data points added to reflect both edges for Input DDR setup and hold time. The power data table has been updated to match SmartPower data rather then simulation values. Table 2-143 • IGLOOe CCC/PLL Specification was updated to add VMV to the 2-91 VCCI parameter row and remove the word "output" from the parameter description for VCCI. Table note 3 was added. Table 2-2 • Recommended Operating Conditions 1 was updated to include the T 2-2 J parameter. Table note 9 is new. In Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating 2-3 Temperature1, the maximum operating junction temperature was changed from 110° to 100°. VMV was removed from Table 2-4 • Overshoot and Undershoot Limits 1, 3. The 2-3 title of the table was revised to remove "as measured on quiet I/Os." Table note 2 was revised to remove "estimated SSO density over cycles." Table note 3 was deleted. The "PLL Behavior at Brownout Condition" section is new. 2-4 Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage 2-5 Levels is new. EQ 2 was updated. The temperature was changed to 100°C, and therefore the 2-6 end result changed. The table notes for Table 2-8 • Quiescent Supply Current (IDD), IGLOOe 2-7 Flash*Freeze Mode*, Table 2-9 • Quiescent Supply Current (IDD), IGLOOe Sleep Mode (VCC = 0 V)*, and Table 2-10 • Quiescent Supply Current (IDD), IGLOOe Shutdown Mode (VCC, VCCI = 0 V)* were updated to remove VMV and include PDC6 and PDC7. VCCI and VJTAG were removed from the statement about IDD in the table note for Table 2-10 • Quiescent Supply Current (IDD), IGLOOe Shutdown Mode (VCC, VCCI = 0 V)*. Note 2 of Table 2-11 • Quiescent Supply Current, No IGLOOe Flash*Freeze 2-8 Mode* was updated to include VCCPLL. Note 4 was updated to include PDC6 and PDC7. Table note 3 was added to Table 2-12 • Summary of I/O Input Buffer Power (per 2-9 pin) – Default I/O Software Settings and referenced for 1.2 V LVCMOS. 5-4 Revision 9 IGLOOe Low Power Flash FPGAs Revision Changes Page Revision 3 (cont’d) Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software 2-10 Settings1 was updated to change PDC3 to PDC7. The table notes were updated to reflect that power was measured on VCCI Table note 4 is new. . Table 2-15 • Different Components Contributing to the Static Power Consumption 2-11, 2-12 in IGLOO Devices and Table 2-17 • Different Components Contributing to the Static Power Consumption in IGLOO Devices were updated to add PDC6 and PDC7, and to change the definition for PDC5 to bank quiescent power. A table subtitle was added for Table 2-17 • Different Components Contributing to 2-12 the Static Power Consumption in IGLOO Devices. The "Total Static Power Consumption—PSTAT" section was updated to revise the 2-13 calculation of P , including PDC6 and PDC7. STAT Footnote 1 was updated to include information about P . The PLL 2-14 AC13 Contribution equation was changed from: P = P + P * FCLKOUT to PLL AC13 AC14 PPLL = P + P * F DC4 AC13 CLKOUT. The "Timing Model" was updated to be consistent with the revised timing 2-16 numbers. In Table 2-21 • Summary of Maximum and Minimum DC Input Levels, T was 2-22 J changed to T in notes 1 and 2. A Table 2-21 • Summary of Maximum and Minimum DC Input Levels was updated 2-22 to included a hysteresis value for 1.2 V LVCMOS (Schmitt trigger mode). All AC Loading figures for single-ended I/O standards were changed from N/A Datapaths at 35 pF to 5 pF. The "1.2 V LVCMOS (JESD8-12A)" section is new. 2-46 Revision 2 (Jun 2008) The product brief section of the datasheet was divided into two sections and N/A given a version number, starting at v1.0. The first section of the document Product Brief v1.0 includes features, benefits, ordering information, and temperature and speed grade offerings. The second section is a device family overview. Revision 2 (cont’d) The naming conventions changed for the following pins in the "FG484" for the 4-6 A3GLE600: Packaging v1.1 Pin Number New Function Name J19 IO45PPB2V1 K20 IO45NPB2V1 M2 IO114NPB6V1 N1 IO114PPB6V1 N4 GFC2/IO115PPB6V1 P3 IO115NPB6V1 Revision 1 (Mar 2008) The "Low Power" section was updated to change "1.2 V and 1.5 V Core Voltage" I to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 25 µW)" was removed Product Brief rev. 1 from "Low Power Active FPGA Operation." 1.2_V was added to the list of core and I/O voltages in the "Pro (Professional) I/O" I, 1-7 and "Pro I/Os with Advanced I/O Standards" section sections. Revision 0 (Jan 2008) This document was previously in datasheet Advance v0.4. As a result of moving N/A to the handbook format, Actel has restarted the version numbers. The new version number is 51700096-001-0. Revision 9 5-5 Datasheet Information Revision Changes Page Advance v0.4 The Table 1 • IGLOOe Product Family table was updated to change the maximum I (December 2007) number of user I/Os for AGLE3000. The "IGLOOe FPGAs Package Sizes Dimensions" table table is new. Package II 1 dimensions were removed from the "I/Os Per Package " table. The number of I/Os was updated for FG896. A note regarding marking information was added to the "IGLOOe Ordering III Information" table. Table 2-4 • IGLOOe CCC/PLL Specification and Table 2-5 • IGLOOe CCC/PLL 2-18, Specification were updated. 2-19 The "During Flash*Freeze Mode" section was updated to include information 2-60 about the output of the I/O to the FPGA core. Figure 2-38 • Flash*Freeze Mode Type 1 – Timing Diagram was updated to 2-56 modify the LSICC signal. Table 2-32 • Flash*Freeze Pin Location in IGLOOe Family Packages (device- 2-64 independent) was updated for the FG896 package. Figure 2-40 • Flash*Freeze Mode Type 2 – Timing Diagram was updated to 2-58 modify the LSICC Signal. Information regarding calculation of the quiescent supply current was added to 3-6 the "Quiescent Supply Current" section. Table 3-8 • Quiescent Supply Current (IDD), IGLOOe Flash*Freeze Mode† was 3-6 updated. Table 3-9 • Quiescent Supply Current (IDD), IGLOOe Sleep Mode (VCC = 0 V)† 3-6 was updated. Table 3-11 • Quiescent Supply Current, No IGLOOe Flash*Freeze Mode1 was 3-6 updated. Table 3-99 • Minimum and Maximum DC Input and Output Levels was updated. 3-51 Table 3-136 • JTAG 1532 and Table 3-135 • JTAG 1532 were updated. 3-95 The "484-Pin FBGA" table for AGLE3000 is new. 4-11 The "896-Pin FBGA" package and table for AGLE3000 is new. 4-16 Advance v0.3 Cortex-M1 device information was added to the Table 1 • IGLOOe Product Family I, II, III, IV (September 2007) table, the "I/Os Per Package1" table, "IGLOOe Ordering Information", and "Temperature Grade Offerings". Advance v0.2 The words "ambient temperature" were added to the temperature range in the III, IV "IGLOOe Ordering Information", "Temperature Grade Offerings", and "Speed Grade and Temperature Grade Matrix" sections. The T parameter in Table 3-2 • Recommended Operating Conditions was 3-2 J changed to T , ambient temperature, and table notes 6–8 were added. A 5-6 Revision 9 IGLOOe Low Power Flash FPGAs Datasheet Categories Categories In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "IGLOOe Device Status" table, is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Production This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Safety Critical, Life Support, and High-Reliability Applications Policy The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of the SoC Products Group’s products is available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information. Revision 9 5-7 Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA © 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Within the USA: +1 (949) 380-6100 Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 51700096-9/3.12