Revision 8 SmartFusion Customizable System-on-Chip (cSoC) – Programmable Embedded FIFO Control Logic Microcontroller Subsystem (MSS) • Secure ISP with 128-Bit AES via JTAG ® • Hard 100 MHz 32-Bit ARM Cortex™-M3 ® • FlashLock to Secure FPGA Contents – 1.25 DMIPS/MHz Throughput from Zero Wait State • Five Clock Conditioning Circuits (CCCs) with up to 2 Memory Integrated Analog PLLs – Memory Protection Unit (MPU) – Phase Shift, Multiply/Divide, and Delay Capabilities – Single Cycle Multiplication, Hardware Divide – Frequency: Input 1.5–350 MHz, Output 0.75 to – JTAG Debug (4 wires), Serial Wire Debug (SWD, 2 350 MHz wires), and Single Wire Viewer (SWV) Interfaces • Internal Memory Programmable Analog – Embedded Nonvolatile Flash Memory (eNVM), 128 Analog Front-End (AFE) Kbytes to 512 Kbytes • Up to Three 12-Bit SAR ADCs – Embedded High-Speed SRAM (eSRAM), 16 Kbytes – 500 Ksps in 12-Bit Mode to 64 Kbytes, Implemented in 2 Physical Blocks to Enable Simultaneous Access from 2 Different – 550 Ksps in 10-Bit Mode Masters – 600 Ksps in 8-Bit Mode • Multi-Layer AHB Communications Matrix • Internal 2.56 V Reference or Optional External – Provides up to 16 Gbps of On-Chip Memory Reference 1 Bandwidth, Allowing Multi-Master Schemes • One First-Order ΣΔ DAC (sigma-delta) per ADC 2 • 10/100 Ethernet MAC with RMII Interface – 8-Bit, 16-Bit, or 24-Bit 500 Ksps Update Rate • Programmable External Memory Controller, Which • Up to 5 High-Performance Analog Signal Conditioning Supports: Blocks (SCB) per Device, Each Including: – Asynchronous Memories – Two High-Voltage Bipolar Voltage Monitors (with 4 – NOR Flash, SRAM, PSRAM input ranges from ±2.5 V to –11.5/+14 V) with 1% Accuracy – Synchronous SRAMs 2 – High Gain Current Monitor, Differential Gain = 50, up •Two I C Peripherals to 14 V Common Mode • Two 16550 Compatible UARTs – Temperature Monitor (Resolution = ¼°C in 12-Bit • Two SPI Peripherals Mode; Accurate from –55°C to 150°C) • Two 32-Bit Timers • Up to Ten High-Speed Voltage Comparators • 32-Bit Watchdog Timer (t =15ns) pd • 8-Channel DMA Controller to Offload the Cortex-M3 from Data Transactions Analog Compute Engine (ACE) • Offloads Cortex-M3–Based MSS from Analog • Clock Sources Initialization and Processing of ADC, DAC, and SCBs – 32 KHz to 20 MHz Main Oscillator • Sample Sequence Engine for ADC and DAC Parameter – Battery-Backed 32 KHz Low Power Oscillator with Set-Up Real-Time Counter (RTC) • Post-Processing Engine for Functions such as Low- – 100 MHz Embedded RC Oscillator; 1% Accurate Pass Filtering and Linear Transformation – Embedded Analog PLL with 4 Output Phases (0, 90, ® 180, 270) • Easily Configured via GUI in Libero Integrated Design (IDE) Software High-Performance FPGA ® I/Os and Operating Voltage • Based on proven ProASIC 3 FPGA Fabric • FPGA I/Os • Low Power, Firm-Error Immune 130-nm, 7-Layer Metal, Flash-Based CMOS Process – LVDS, PCI, PCI-X, up to 24 mA IOH/IOL • Nonvolatile, Live at Power-Up, Retains Program When – Up to 350 MHz Powered Off • MSS I/Os • 350 MHz System Performance – Schmitt Trigger, up to 6 mA IOH, 8 mA IOL • Embedded SRAMs and FIFOs – Up to 180 MHz – Variable Aspect Ratio 4,608-Bit SRAM Blocks • Single 3.3 V Power Supply with On-Chip 1.5 V Regulator – x1, x2, x4, x9, and x18 Organizations • External 1.5V Is Allowed by Bypassing Regulator – True Dual-Port SRAM (excluding x18) (digital VCC = 1.5 V for FPGA and MSS, analog VCC = 3.3 V and 1.5 V) 1 Theoretical maximum 2 A2F200 and larger devices March 2012 I © 2012 Microsemi Corporation SmartFusion Customizable System-on-Chip (cSoC) SmartFusion cSoC Family Product Table A2F060 A2F200 A2F500 FPGA Fabric TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484 System Gates 60,000 200,000 500,000 Tiles (D-flip-flops) 1,536 4,608 11,520 RAM Blocks (4,608 bits) 8 8 24 A2F060 A2F200 A2F500 Microcontroller Subsystem (MSS) TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484 Flash (Kbytes) 128 256 512 SRAM (Kbytes) 16 64 64 Cortex-M3 processor with MPU Yes Yes Yes 10/100 Ethernet MAC No Yes Yes External Memory Controller (EMC) 26-/16-bit address/data 26-bit address,16-bit data – 26-/16-bit address/data DMA 8 Ch 8 Ch 8 Ch 2 IC2 2 2 SPI 1 2 1 2 1 2 16550 UART 2 2 2 32-Bit Timer 2 2 2 1 PLL 1 12 1 2 32 KHz Low Power Oscillator 1 1 1 100 MHz On-Chip RC Oscillator 1 1 1 Main Oscillator (32 KHz to 20 MHz) 1 1 1 A2F060 A2F200 A2F500 Programmable Analog TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484 ADCs (8-/10-/12-bit SAR) 1 2 2 3 DACs (8-/16-/24-bit sigma-delta) 1 2 2 3 Signal Conditioning Blocks (SCBs) 1 4 2 5 Comparator* 2 8 8 10 Current Monitors* 1 4 4 5 Temperature Monitors* 1 4 4 5 Bipolar High Voltage Monitors* 2 8 8 10 Note: *These functions share I/O pins and may not all be available at the same time. See the "Analog Front-End Overview" section in the SmartFusion Programmable Analog User’s Guide for details. II Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Package I/Os: MSS + FPGA I/Os Device A2F060 A2F200 A2F500 Package TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484 Direct Analog Inputs 11 11 11 8 8 8 8 8 8 8 12 1 Shared Analog Inputs 4 4 4 16 16 16 16 16 16 16 20 Total Analog Inputs 15 15 15 24 24 24 24 24 24 24 32 Total Analog Outputs 1111 2 2 2 122 3 2,3 4 4 4 MSS I/Os 21 28 26 22 31 25 41 22 31 25 41 5 FPGA I/Os 33 68 66 66 78 66 94 66 78 66 128 Total I/Os 70 112 108 113 135 117 161 113 135 117 204 Notes: 1. These pins are shared between direct analog inputs to the ADCs and voltage/current/temperature monitors. 2. 16 MSS I/Os are multiplexed and can be used as FPGA I/Os, if not needed for MSS. These I/Os support Schmitt triggers and support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V) standards. 3. 9 MSS I/Os are primarily for 10/100 Ethernet MAC and are also multiplexed and can be used as FPGA I/Os if Ethernet MAC is not used in a design. These I/Os support Schmitt triggers and support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V standards. 4. 10/100 Ethernet MAC is not available on A2F060. 5. EMC is not available on the A2F500 PQ208 package. Table 1 • SmartFusion cSoC Package Sizes Dimensions Package TQ144 PQ208 CS288 FG256 FG484 Length × Width (mm\mm) 20 × 20 28 × 28 17 × 17 23 × 23 2 Nominal Area (mm ) 400 784 289 529 Pitch (mm) 0.5 0.5 1.0 1.0 Height (mm) 1.40 3.40 1.60 2.23 SmartFusion cSoC Device Status Device Status A2F060 Preliminary: CS288, FG256, TQ144 A2F200 Production: CS288, FG256, FG484, PQ208 A2F500 Production: CS288, FG256, FG484, PQ208 Revision 8 III SmartFusion Customizable System-on-Chip (cSoC) SmartFusion cSoC Block Diagram ™ PPB Supervisor Cortex -M3 SysReg PLL OSC RC + JTAG NVIC SysTick Microcontroller Subsystem ENVM WDT 32 KHz RTC Programmable Analog 3 V 3 V SWD MPU – ESRAM FPGA Fabric SD I APB SPI 1 APB SPI 2 AHB Bus Matrix UART 1 EFROM Timer1 UART 2 10/100 2 IAP PDMA APB EMC 2 I C 1 Timer2 I C 2 EMAC SCB Analog Compute Temp. Volt Mon. Engine (ABPS) Mon. DAC Curr. ADC Comparator (SDD) Mon. Sample Sequencing Engine VersaTiles ........ SCB Volt Mon. Temp. DAC ADC Mon. (ABPS) (SDD) Post Processing Engine Curr. Comparator SRAM SRAM SRAM ........ SRAM SRAM SRAM Mon. Legend: SDD – Sigma-delta DAC SCB – Signal conditioning block PDMA – Peripheral DMA IAP – In-application programming ABPS – Active bipolar prescaler WDT – Watchdog Timer SWD – Serial Wire Debug IV Revision 8 .... ............ ............ Bank 1 Bank 2 SmartFusion Customizable System-on-Chip (cSoC) SmartFusion cSoC System Architecture Bank 0 Embedded FlashROM ISP AES Decryption Charge Pumps (eFROM) Embedded NVM (eNVM) Cortex-M3 Microcontroller Subsystem (MSS) Embedded SRAM (eSRAM) SCB SCB ADC and DAC ADC and DAC SCB SCB Bank 3 Osc. CCC PLL/CCC MSS FPGA Analog Note: Architecture for A2F200 Revision 8 V Bank 4 Bank 5 SmartFusion Customizable System-on-Chip (cSoC) Product Ordering Codes _ A2F200 M3 F 1 FG G 484 Y I Application (junction temperature range) Blank = Commercial (0 to +85°C) I = Industrial (–40 to +100°C) ES = Engineering Silicon (room temperature only) Security Feature* Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Package Lead Count 208 256 288 484 Lead-Free Packaging Options Blank = Standard Packaging G = RoHS-Compliant (green) Packaging Package Type = TQ Thin Quad Flat Pack (0.5 mm pitch) = PQ Plastic Quad Flat Pack (0.5 mm pitch) = CS Chip Scale Package (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) Speed Grade Blank = 80 MHz MSS Speed; FPGA Fabric at Standard Speed –1 = 100 MHz MSS Speed; FPGA Fabric 15% Faster than Standard eNVM Size = A 8 Kbytes = B 16 Kbytes = C 32 Kbytes = D 64 Kbytes = E 128 Kbytes = F 256 Kbytes = G 512 Kbytes CPU Type M3 = Cortex-M3 Part Number SmartFusion Devices A2F060 = 60,000 System Gates A2F200 = 200,000 System Gates A2F500 = 500,000 System Gates Note: *Most devices in the SmartFusion cSoC family can be ordered with the Y suffix. Devices with a package size greater or equal to 5x5 mm are supported. Contact your local Microsemi SoC Products Group sales representative for more information. Temperature Grade Offerings SmartFusion cSoC A2F060 A2F200 A2F500 TQ144 C, I – – PQ208 – C, I C, I CS288 C, I C, I C, I FG256 C, I C, I C, I FG484 – C, I C, I Notes: 1. C = Commercial Temperature Range: 0°C to 85°C Junction 2. I = Industrial Temperature Range: –40°C to 100°C Junction VI Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Table of Contents SmartFusion Family Overview Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SmartFusion DC and Switching Characteristics General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 Main and Lower Power Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 FPGA Fabric SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65 Embedded Nonvolatile Memory Block (eNVM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74 Embedded FlashROM (eFROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75 Programmable Analog Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76 Serial Peripheral Interface (SPI) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88 2 Inter-Integrated Circuit (I C) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-90 SmartFusion Development Tools Types of Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 SmartFusion Ecosystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Middleware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 SmartFusion Programming In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 In-Application Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Typical Programming and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Pin Descriptions Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 User-Defined Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Global I/O Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Microcontroller Subsystem (MSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Analog Front-End (AFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Analog Front-End Pin-Level Function Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 TQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 CS288 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 Revision 8 Table of Contents Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 Microsemi SoC Products Group Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . 6-11 Revision 8 1 – SmartFusion Family Overview Introduction ® The SmartFusion family of cSoCs builds on the technology first introduced with the Fusion mixed signal FPGAs. SmartFusion cSoCs are made possible by integrating FPGA technology with programmable high-performance analog and hardened ARM Cortex-M3 microcontroller blocks on a flash semiconductor process. The SmartFusion cSoC takes its name from the fact that these three discrete technologies are integrated on a single chip, enabling the lowest cost of ownership and smallest footprint solution to you. General Description Microcontroller Subsystem (MSS) The MSS is composed of a 100 MHz Cortex-M3 processor and integrated peripherals, which are interconnected via a multi-layer AHB bus matrix (ABM). This matrix allows the Cortex-M3 processor, FPGA fabric master, Ethernet message authentication controller (MAC), when available, and peripheral DMA (PDMA) controller to act as masters to the integrated peripherals, FPGA fabric, embedded nonvolatile memory (eNVM), embedded synchronous RAM (eSRAM), external memory controller (EMC), and analog compute engine (ACE) blocks. SmartFusion cSoCs of different densities offer various sets of integrated peripherals. Available 2 peripherals include SPI, I C, and UART serial ports, embedded FlashROM (EFROM), 10/100 Ethernet MAC, timers, phase-locked loops (PLLs), oscillators, real-time counters (RTC), and peripheral DMA controller (PDMA). Programmable Analog Analog Front-End (AFE) SmartFusion cSoCs offer an enhanced analog front-end compared to Fusion devices. The successive approximation register analog-to-digital converters (SAR ADC) are similar to those found on Fusion devices. SmartFusion cSoC also adds first order sigma-delta digital-to-analog converters (SDD DAC). SmartFusion cSoCs can handle multiple analog signals simultaneously with its signal conditioning blocks (SCBs). SCBs are made of a combination of active bipolar prescalers (ABPS), comparators, current monitors and temperature monitors. ABPS modules allow larger bipolar voltages to be fed to the ADC. Current monitors take the voltage across an external sense resistor and convert it to a voltage suitable for the ADC input range. Similarly, the temperature monitor reads the current through an external PN- junction (diode or transistor) and converts it internally for the ADC. The SCB also includes comparators to monitor fast signal thresholds without using the ADC. The output of the comparators can be fed to the analog compute engine or the ADC. Analog Compute Engine (ACE) The mixed signal blocks found in SmartFusion cSoCs are controlled and connected to the rest of the system via a dedicated processor called the analog compute engine (ACE). The role of the ACE is to offload control of the analog blocks from the Cortex-M3, thus offering faster throughput or better power consumption compared to a system where the main processor is in charge of monitoring the analog resources. The ACE is built to handle sampling, sequencing, and post-processing of the ADCs, DACs, and SCBs. Revision 8 1-1 SmartFusion Family Overview ProASIC3 FPGA Fabric ® The SmartFusion cSoC family, based on the proven, low power, firm-error immune ProASIC 3 flash FPGA architecture, benefits from the advantages only flash-based devices offer: Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, high performance, and ease of use. Flash- based SmartFusion cSoCs are live at power-up and do not need to be loaded from an external boot PROM at each power-up. On-board security mechanisms prevent access to the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system programming (ISP) to support future design iterations and critical field upgrades, with confidence that valuable IP cannot be compromised or copied. Secure ISP can be performed using the industry standard AES algorithm with MAC data authentication on the device. Low Power Flash-based SmartFusion cSoCs exhibit power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. With SmartFusion cSoCs, there is no power-on current and no high current transition, both of which are common with SRAM-based FPGAs. SmartFusion cSoCs also have low dynamic power consumption and support very low power time- keeping mode, offering further power savings. Security As the nonvolatile, flash-based SmartFusion cSoC family requires no boot PROM, there is no vulnerable ® external bitstream. SmartFusion cSoCs incorporate FlashLock , which provides a unique combination of reprogrammability and design security without external overhead, advantages that only a device with nonvolatile flash programming can offer. SmartFusion cSoCs utilize a 128-bit flash-based key lock and a separate AES key to provide security for programmed IP and configuration data. The FlashROM data in Fusion devices can also be encrypted prior to loading. Additionally, the flash memory blocks can be programmed during runtime using the AES- 128 block cipher encryption standard (FIPS Publication 192). SmartFusion cSoCs with AES-based security are designed to provide protection for remote field updates over public networks, such as the Internet, and help to ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. As an additional security measure, the FPGA configuration data of a programmed Fusion device cannot be read back, although secure design verification is possible. During design, the user controls and defines both internal and external access to the flash memory blocks. Security, built into the FPGA fabric, is an inherent component of the SmartFusion cSoC family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. SmartFusion cSoCs, with FlashLock and AES security, are unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with industry standard security measures, making remote ISP feasible. A SmartFusion cSoC provides the highest security available for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based SmartFusion cSoCs do not require system configuration components such as electrically erasable programmable read-only memories (EEPROMs) or microcontrollers to load device configuration data during power-up. This reduces bill-of-materials costs and PCB area, and increases system security and reliability. Live at Power-Up Flash-based SmartFusion cSoCs are live at power-up (LAPU). LAPU SmartFusion cSoCs greatly simplify total system design and reduce total system cost by eliminating the need for complex programmable logic devices (CPLDs). SmartFusion LAPU clocking (PLLs) replace off-chip clocking resources. In addition, glitches and brownouts in system power will not corrupt the SmartFusion flash configuration. Unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables reduction or complete removal of expensive voltage monitor and brownout 1-2 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) detection devices from the PCB design. Flash-based SmartFusion cSoCs simplify total system design and reduce cost and design risk, while increasing system reliability. Immunity to Firm Errors Firm errors occur most commonly when high-energy neutrons, generated in the atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O configuration behavior in an unpredictable way. Another source of radiation-induced firm errors is alpha particles. For alpha radiation to cause a soft or firm error, its source must be in very close proximity to the affected circuit. The alpha source must be in the package molding compound or in the die itself. While low-alpha molding compounds are being used increasingly, this helps reduce but does not entirely eliminate alpha-induced firm errors. Firm errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not occur in SmartFusion cSoCs. Once it is programmed, the flash cell configuration element of SmartFusion cSoCs cannot be altered by high energy neutrons and is therefore immune to errors from them. Recoverable (or soft) errors occur in the user data SRAMs of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Specifying I/O States During Programming You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information. Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have limited display of Pin Numbers only. 1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during programming. 2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator window appears. 3. Click the Specify I/O States During Programming button to display the Specify I/O States During Programming dialog box. 4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header. Select the I/Os you wish to modify (Figure 1-1 on page 1-4). 5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state settings: 1 – I/O is set to drive out logic High 0 – I/O is set to drive out logic Low Last Known State – I/O is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming Z -Tri-State: I/O is tristated Revision 8 1-3 SmartFusion Family Overview Figure 1-1 • I/O States During Programming Window 6. Click OK to return to the FlashPoint – Programming File Generator window. Note: I/O States During programming are saved to the ADB and resulting programming files after completing programming file generation. 1-4 Revision 8 2 – SmartFusion DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond the operating conditions listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-3 on page 2-3 is not implied. Table 2-1 • Absolute Maximum Ratings Symbol Parameter Limits Units VCC DC core supply voltage –0.3 to 1.65 V VJTAG JTAG DC voltage –0.3 to 3.75 V VPP Programming voltage –0.3 to 3.75 V VCCPLLx Analog power supply (PLL) –0.3 to 1.65 V VCCFPGAIOBx DC FPGA I/O buffer supply voltage –0.3 to 3.75 V VCCMSSIOBx DC MSS I/O buffer supply voltage –0.3 to 3.75 V VI I/O input voltage –0.3 V to 3.6 V V (when I/O hot insertion mode is enabled) –0.3 V to (VCCxxxxIOBx + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot- insertion mode is disabled) VCC33A Analog clean 3.3 V supply to the analog –0.3 to 3.75 V circuitry VCC33ADCx Analog 3.3 V supply to ADC –0.3 to 3.75 V VCC33AP Analog clean 3.3 V supply to the charge pump –0.3 to 3.75 V VCC33SDDx Analog 3.3 V supply to the sigma-delta DAC –0.3 to 3.75 V VAREFx Voltage reference for ADC 1.0 to 3.75 V VCCRCOSC Analog supply to the integrated RC oscillator –0.3 to 3.75 V VDDBAT External battery supply –0.3 to 3.75 V VCCMAINXTAL Analog supply to the main crystal oscillator –0.3 to 3.75 V VCCLPXTAL Analog supply to the low power 32 kHz crystal –0.3 to 3.75 V oscillator VCCENVM Embedded nonvolatile memory supply –0.3 to 1.65 V VCCESRAM Embedded SRAM supply –0.3 to 1.65 V VCC15A Analog 1.5 V supply to the analog circuitry –0.3 to 1.65 V VCC15ADCx Analog 1.5 V supply to the ADC –0.3 to 1.65 V 1 T Storage temperature –65 to +150 °C STG 1 T Junction temperature 125 °C J Notes: 1. For flash programming and retention maximum limits, refer to Table 2-4 on page 2-4. For recommended operating conditions, refer to Table 2-3 on page 2-3. 2. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-5 on page 2-4. Revision 8 2-1 SmartFusion DC and Switching Characteristics Table 2-2 • Analog Maximum Ratings Parameter Conditions Min. Max. Units ABPS[n] pad voltage (relative to ground) GDEC[1:0] = 00 (±15.36 V range) Absolute maximum –11.5 14.4 V Recommended –11 14 V GDEC[1:0] = 01 (±10.24 V range) –11.5 12 V GDEC[1:0] = 10 (±5.12 V range) –6 6 V GDEC[1:0] = 11 (±2.56 V range) –3 3 V CM[n] pad voltage relative to ground) CMB_DI_ON = 0 (ADC isolated) COMP_EN = 0 (comparator off, for the associated even-numbered comparator) Absolute maximum –0.3 14.4 V Recommended –0.3 14 V CMB_DI_ON = 0 (ADC isolated) –0.3 3 V COMP_EN = 1 (comparator on) TMB_DI_ON = 1 (direct ADC in) –0.3 3 V TM[n] pad voltage (relative to ground) TMB_DI_ON = 0 (ADC isolated) –0.3 3 V COMP_EN = 1(comparator on) TMB_DI_ON = 1 (direct ADC in) –0.3 3 V ADC[n] pad voltage (relative to ground) –0.3 3.6 V 2-2 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Table 2-3 • Recommended Operating Conditions 1 Symbol Parameter Commercial Industrial Units T Junction temperature 0 to +85 –40 to +100 °C J 2 VCC 1.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V VJTAG JTAG DC voltage 1.425 to 3.6 1.425 to 3.6 V VPP Programming voltage Programming mode 3.15 to 3.45 3.15 to 3.45 V 3 Operation 0 to 3.6 0 to 3.6 V VCCPLLx Analog power supply (PLL) 1.425 to 1.575 1.425 to 1.575 V VCCFPGAIOBx/ 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V 4 VCCMSSIOBx 1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V 2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V 3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V 5 VCC33A Analog clean 3.3 V supply to the analog circuitry 3.15 to 3.45 3.15 to 3.45 V 5 VCC33ADCx Analog 3.3 V supply to ADC 3.15 to 3.45 3.15 to 3.45 V 5 VCC33AP Analog clean 3.3 V supply to the charge pump 3.15 to 3.45 3.15 to 3.45 V 5 VCC33SDDx Analog 3.3 V supply to sigma-delta DAC 3.15 to 3.45 3.15 to 3.45 V VAREFx Voltage reference for ADC 2.527 to 3.3 2.527 to 3.3 V VCCRCOSC Analog supply to the integrated RC oscillator 3.15 to 3.45 3.15 to 3.45 V VDDBAT External battery supply 2.7 to 3.63 2.7 to 3.63 V 5 VCCMAINXTAL Analog supply to the main crystal oscillator 3.15 to 3.45 3.15 to 3.45 V 5 VCCLPXTAL Analog supply to the low power 32 KHz crystal 3.15 to 3.45 3.15 to 3.45 V oscillator VCCENVM Embedded nonvolatile memory supply 1.425 to 1.575 1.425 to 1.575 V VCCESRAM Embedded SRAM supply 1.425 to 1.575 1.425 to 1.575 V 2 VCC15A Analog 1.5 V supply to the analog circuitry 1.425 to 1.575 1.425 to 1.575 V 2 VCC15ADCx Analog 1.5 V supply to the ADC 1.425 to 1.575 1.425 to 1.575 V Notes: 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC, VCC15A, and VCC15ADCx. 3. VPP can be left floating during operation (not programming mode). 4. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-19 on page 2-23. VCCxxxxIOBx should be at the same voltage within a given I/O bank. 5. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A, VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL. Revision 8 2-3 SmartFusion DC and Switching Characteristics Table 2-4 • FPGA and Embedded Flash Programming, Storage and Operating Limits Grade Programming Product Grade Storage Temperature Element Cycles Retention Commercial Min. T = 0°C FPGA/FlashROM 500 20 years J Min. T = 85°C Embedded Flash < 1,000 20 years J < 10,000 10 years < 15,000 5 years Industrial Min. T = –40°C FPGA/FlashROM 500 20 years J Min. T = 100°C Embedded Flash < 1,000 20 years J < 10,000 10 years < 15,000 5 years 1 Table 2-5 • Overshoot and Undershoot Limits Average VCCxxxxIOBx–GND Overshoot or Undershoot Maximum Overshoot/ 2 2 VCCxxxxIOBx Duration as a Percentage of Clock Cycle Undershoot 2.7 V or less 10% 1.4 V 5% 1.49 V 3 V 10% 1.1 V 5% 1.19 V 3.3 V 10% 0.79 V 5% 0.88 V 3.6 V 10% 0.45 V 5% 0.54 V Notes: 1. Based on reliability requirements at 85°C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 3. This table does not provide PCI overshoot/undershoot limits. Power Supply Sequencing Requirement SmartFusion cSoCs have an on-chip 1.5 V regulator, but usage of an external 1.5 V supply is also allowed while the on-chip regulator is disabled. In that case, the 3.3 V supplies (VCC33A, etc.) should be powered before 1.5 V (VCC, etc.) supplies. The 1.5 V supplies should be enabled only after 3.3 V supplies reach a value higher than 2.7 V. I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every SmartFusion cSoC. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-6. There are five regions to consider during power-up. SmartFusion I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCxxxxIOBx are above the minimum specified trip points (Figure 2-1 on page 2-6). 2. VCCxxxxIOBx > VCC – 0.75 V (typical) 3. Chip is in the SoC Mode. 2-4 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) VCCxxxxIOBx Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCxxxxIOBx ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: • During programming, I/Os become tristated and weakly pulled up to VCCxxxxIOBx. • JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. PLL Behavior at Brownout Condition The Microsemi SoC Products Group recommends using monotonic power supplies or voltage regulators to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLx exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-6 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation Revision 8 2-5 SmartFusion DC and Switching Characteristics VCC = VCCxxxxIOBx + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 5: I/O buffers are ON Region 4: I/O Region 1: I/O Buffers are OFF and power supplies are within buffers are ON. specification. I/Os are functional I/Os meet the entire datasheet (except differential and timer specifications for but slower because speed, VIH / VIL , VOH / VOL , etc. VCCxxxxIOBx below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. VCC = 1.425 V Region 2: I/O buffers are ON. Region 3: I/O buffers are ON. I/Os are functional (except differential inputs) I/Os are functional; I/O DC but slower because VCCxxxxIOBx / V are specifications are met, CC below specification. For the same reason, input but I/Os are slower because the VCC is below specification. buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Activation trip point: V = 0.85 V ± 0.25 V a Deactivation trip point: Region 1: I/O buffers are OFF V = 0.75 V ± 0.25 V d VCCxxxxIOBx Activation trip point: Min VCCxxxxIOBx datasheet specification V = 0.9 V ± 0.3 V voltage at a selected I/O a Deactivation trip point: standard; i.e., 1.425 V or 1.7 V V = 0.8 V ± 0.3 V or 2.3 V or 3.0 V d Figure 2-1 • I/O State as a Function of VCCxxxxIOBx and VCC Voltage Levels 2-6 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Thermal Characteristics Introduction The temperature variable in the SoC Products Group Designer software refers to the junction temperature, not the ambient, case, or board temperatures. This is an important distinction because dynamic and static power consumption will cause the chip's junction temperature to be higher than the ambient, case, or board temperatures. EQ 1 through EQ 3 give the relationship between thermal resistance, temperature gradient, and power. T – θ J A ------------------ θ = JA P EQ 1 T – T J B ------------------- θ = JB P EQ 2 T – T J C ------------------- θ = JC P EQ 3 where θ = Junction-to-air thermal resistance JA θ = Junction-to-board thermal resistance JB θ = Junction-to-case thermal resistance JC T = Junction temperature J T = Ambient temperature A T = Board temperature (measured 1.0 mm away from the B package edge) T = Case temperature C P = Total power dissipated by the device Table 2-6 • Package Thermal Resistance Die Size θ JA Product (mm) Still Air 1.0 m/s 2.5 m/s θ θ Units JC JB A2F200M3F-FG256 X = 4.0; Y = 5.6 33.7 30.0 28.3 9.3 24.8 °C/W A2F200M3F-FG484 X = 5.10; Y = 7.3 21.8 18.2 16.7 7.7 16.8 °C/W Revision 8 2-7 SmartFusion DC and Switching Characteristics Theta-JA Junction-to-ambient thermal resistance (θ ) is determined under standard conditions specified by JA JEDEC (JESD-51), but it has little relevance in actual performance of the product. It should be used with caution but is useful for comparing the thermal performance of one package to another. A sample calculation showing the maximum power dissipation allowed for the A2F200-FG484 package under forced convection of 1.0 m/s and 75°C ambient temperature is as follows: T – T J(MAX) A(MAX) --------------------------------------------- Maximum Power Allowed = θ JA EQ 4 where θ = 19.00°C/W (taken from Table 2-6 on page 2-7). JA T = 75.00°C A 100.00°C – 75.00°C Maximum Power Allowed == ---------------------------------------------------- 1.3 W 19.00°C/W EQ 5 The power consumption of a device can be calculated using the Microsemi SoC Products Group power calculator. The device's power consumption must be lower than the calculated maximum power dissipation by the package. If the power consumption is higher than the device's maximum allowable power dissipation, a heat sink can be attached on top of the case, or the airflow inside the system must be increased. Theta-JB Junction-to-board thermal resistance (θ ) measures the ability of the package to dissipate heat from the JB surface of the chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance from junction to board uses an isothermal ring cold plate zone concept. The ring cold plate is simply a means to generate an isothermal boundary condition at the perimeter. The cold plate is mounted on a JEDEC standard board with a minimum distance of 5.0 mm away from the package edge. Theta-JC Junction-to-case thermal resistance (θ ) measures the ability of a device to dissipate heat from the JC surface of the chip to the top or bottom surface of the package. It is applicable for packages used with external heat sinks. Constant temperature is applied to the surface in consideration and acts as a boundary condition. This only applies to situations where all or nearly all of the heat is dissipated through the surface in consideration. Calculation for Heat Sink For example, in a design implemented in an A2F200-FG484 package with 2.5 m/s airflow, the power consumption value using the power calculator is 3.00 W. The user-dependent T and T are given as a j follows: T = 100.00°C J T = 70.00°C A From the datasheet: θ = 17.00°C/W JA θ = 8.28°C/W JC 2-8 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) T – T J A 100°C – 70°C ------------------- ------------------------------------ P == = 1.76 W θ 17.00 W JA EQ 6 The 1.76 W power is less than the required 3.00 W. The design therefore requires a heat sink, or the airflow where the device is mounted should be increased. The design's total junction-to-air thermal resistance requirement can be estimated by EQ 7: T – T J A 100°C – 70°C ------------------- ------------------------------------ θ == = 10.00°C/W JA(total) P 3.00 W EQ 7 Determining the heat sink's thermal performance proceeds as follows: θ = θ ++ θ θ JA(TOTAL) JC CS SA EQ 8 where θ = 0.37°C/W JA = Thermal resistance of the interface material between the case and the heat sink, usually provided by the thermal interface manufacturer θ = Thermal resistance of the heat sink in °C/W SA θ = θ – θ – θ SA JA(TOTAL) JC CS EQ 9 θ == 13.33°C/W – 8.28°C/W – 0.37°C/W 5.01°C/W SA A heat sink with a thermal resistance of 5.01°C/W or better should be used. Thermal resistance of heat sinks is a function of airflow. The heat sink performance can be significantly improved with increased airflow. Carefully estimating thermal resistance is important in the long-term reliability of an FPGA. Design engineers should always correlate the power consumption of the device with the maximum allowable power dissipation of the package selected for that device. Note: The junction-to-air and junction-to-board thermal resistances are based on JEDEC standard (JESD-51) and assumptions made in building the model. It may not be realized in actual application and therefore should be used with a degree of caution. Junction-to-case thermal resistance assumes that all power is dissipated through the case. Temperature and Voltage Derating Factors Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to T = 85°C, worst-case VCC = 1.425 V) J Array Junction Temperature (°C) Voltage VCC (V) –40°C 0°C 25°C 70°C 85°C 100°C 1.425 0.86 0.91 0.93 0.98 1.00 1.02 1.500 0.81 0.86 0.88 0.93 0.95 0.96 1.575 0.78 0.83 0.85 0.90 0.91 0.93 Revision 8 2-9 SmartFusion DC and Switching Characteristics Calculating Power Dissipation Quiescent Supply Current Table 2-8 • Power Supplies Configuration Modes and Power Supplies Time Keeping mode 0 V 0 V 0 V 3.3 V 0 V 0 V 0 V Off Enable Disable Standby mode On* 3.3 V 1.5 V N/A 3.3 V N/A N/A Reset Enable Disable SoC mode On* 3.3 V 1.5 V N/A 3.3 V N/A N/A On Enable Enable Note: *On means proper voltage is applied. Refer to Table 2-3 on page 2-3 for recommended operating conditions. Table 2-9 • Quiescent Supply Current Characteristics A2F060 A2F200 A2F500 1.5 V 3.3 V 1.5 V 3.3 V 1.5 V 3.3 V Parameter Modes Domain Domain Domain Domain Domain Domain IDC1 SoC mode 3 mA 2 mA 7 mA 4 mA 16.5 mA 4 mA IDC2 Standby mode 3 mA 2 mA 7 mA 4 mA 16.5 mA 4 mA IDC3 Time Keeping mode N/A 10 µA N/A 10 µA N/A 10 µA Power per I/O Pin Table 2-10 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Static Power Dynamic Power PAC9 VCCFPGAIOBx (V) PDC7 (mW) (µW/MHz) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 17.55 2.5 V LVCMOS 2.5 – 5.97 1.8 V LVCMOS 1.8 – 2.88 1.5 V LVCMOS (JESD8-11) 1.5 – 2.33 3.3 V PCI 3.3 – 19.21 3.3 V PCI-X 3.3 – 19.21 Differential LVDS 2.5 2.26 0.82 LVPECL 3.3 5.72 1.16 2-10 Revision 8 VCCxxxxIOBx VCCFPGAIOBx VCCMSSIOBx VCC33A / VCC33ADCx VCC33AP / VCC33SDDx VCCMAINXTAL / VCCLPXTAL VCC / VCC15A / VCC15ADCx VCCPLLx, VCCENVM, VCCESRAM VDDBAT VCCRCOSC VJTAG VPP eNVM (reset/off) LPXTAL (enable/disable) MAINXTAL (enable/disable) SmartFusion Customizable System-on-Chip (cSoC) Table 2-11 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to MSS I/O Banks Static Power Dynamic Power VCCMSSIOBx (V) PDC7 (mW) PAC9 (µW/MHz) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 17.21 3.3 V LVCMOS / 3.3 V LVCMOS – Schmitt trigger 3.3 – 20.00 2.5 V LVCMOS 2.5 – 5.55 2.5 V LVCMOS – Schmitt trigger 2.5 – 7.03 1.8 V LVCMOS 1.8 – 2.61 1.8 V LVCMOS – Schmitt trigger 1.8 – 2.72 1.5 V LVCMOS (JESD8-11) 1.5 – 1.98 1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 1.93 * Table 2-12 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins VCCFPGAIOBx Static Power Dynamic Power C (pF) (V) PDC8 (mW) PAC10 (µW/MHz) LOAD Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 475.66 2.5 V LVCMOS 35 2.5 – 270.50 1.8 V LVCMOS 35 1.8 – 152.17 1.5 V LVCMOS (JESD8-11) 35 1.5 – 104.44 3.3 V PCI 10 3.3 – 202.69 3.3 V PCI-X 10 3.3 – 202.69 Differential LVDS – 2.5 7.74 88.26 LVPECL – 3.3 19.54 164.99 Note: *Dynamic power consumption is given for standard load and software default drive strength and output slew. Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Applicable to MSS I/O Banks Static Power Dynamic Power 2 3 C (pF) VCCMSSIOBx (V) PDC8 (mW) PAC10 (µW/MHz) LOAD Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 10 3.3 – 155.65 2.5 V LVCMOS 10 2.5 – 88.23 1.8 V LVCMOS 10 1.8 – 45.03 1.5 V LVCMOS (JESD8-11) 10 1.5 – 31.01 Revision 8 2-11 SmartFusion DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-14 • Different Components Contributing to Dynamic Power Consumption in SmartFusion cSoCs Power Supply Device Parameter Definition Name Domain A2F060 A2F200 A2F500 Units PAC1 Clock contribution of a Global Rib VCC 1.5 V 3.39 3.40 5.05 µW/MHz PAC2 Clock contribution of a Global Spine VCC 1.5 V 1.14 1.83 2.50 µW/MHz PAC3 Clock contribution of a VersaTile VCC 1.5 V 1.15 1.15 1.15 µW/MHz row PAC4 Clock contribution of a VersaTile VCC 1.5 V 0.12 0.12 0.12 µW/MHz used as a sequential module PAC5 First contribution of a VersaTile VCC 1.5 V 0.07 0.07 0.07 µW/MHz used as a sequential module PAC6 Second contribution of a VersaTile VCC 1.5 V 0.29 0.29 0.29 µW/MHz used as a sequential module PAC7 Contribution of a VersaTile used as VCC 1.5 V 0.29 0.29 0.29 µW/MHz a combinatorial module PAC8 Average contribution of a routing net VCC 1.5 V 1.04 0.79 0.79 µW/MHz PAC9 Contribution of an I/O input pin VCCxxxxIOBx/VCC See Table 2-10 and Table 2-11 on page 2-11 (standard dependent) PAC10 Contribution of an I/O output pin VCCxxxxIOBx/VCC See Table 2-12 and Table 2-13 on page 2-11 (standard dependent) PAC11 Average contribution of a RAM VCC 1.5 V 25.00 µW/MHz block during a read operation PAC12 Average contribution of a RAM VCC 1.5 V 30.00 µW/MHz block during a write operation PAC13 Dynamic Contribution for PLL VCC 1.5 V 2.60 µW/MHz PAC15 Contribution of NVM block during a VCC 1.5 V 358.00 µW/MHz read operation (F < 33MHz) PAC16 1st contribution of NVM block during VCC 1.5 V 12.88 mW a read operation (F > 33MHz) PAC17 2nd contribution of NVM block VCC 1.5 V 4.80 µW/MHz during a read operation (F > 33MHz) PAC18 Main Crystal Oscillator contribution VCCMAINXTAL 3.3 V 1.98 mW PAC19a RC Oscillator contribution VCCRCOSC 3.3 V 3.30 mW PAC19b RC Oscillator contribution VCC 1.5 V 3.00 mW PAC20a Analog Block Dynamic Power VCC33ADCx 3.3 V 8.25 mW Contribution of the ADC PAC20b Analog Block Dynamic Power VCC15ADCx 1.5 V 3.00 mW Contribution of the ADC PAC21 Low Power Crystal Oscillator VCCLPXTAL 3.3 V 33.00 µW contribution PAC22 MSS Dynamic Power Contribution – VCC 1.5 V 67.50 mW 1 Running Drysthone at 100MHz PAC23 Temperature Monitor Power See Table 2-94 on –1.23 mW Contribution page 2-77 2-12 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Table 2-14 • Different Components Contributing to Dynamic Power Consumption in SmartFusion cSoCs Power Supply Device Parameter Definition Name Domain A2F060 A2F200 A2F500 Units PAC24 Current Monitor Power Contribution See Table 2-93 on –1.03 mW page 2-76 PAC25 ABPS Power Contribution See Table 2-97 on –0.70 mW page 2-81 PAC26 Sigma-Delta DAC Power See Table 2-99 on –0.58 mW 2 Contribution page 2-84 PAC27 Comparator Power Contribution See Table 2-98 on –1.02 mW page 2-83 PAC28 Voltage Regulator Power See Table 2-100 on –36.30 mW 3 Contribution page 2-86 Notes: 1. For a different use of MSS peripherals and resources, refer to SmartPower. 2. Assumes Input = Half Scale Operation mode. 3. Assumes 100 mA load on 1.5 V domain. Table 2-15 • Different Components Contributing to the Static Power Consumption in SmartFusion cSoCs Power Supply Device Parameter Definition Name Domain A2F060 A2F200 A2F200 Units PDC1 Core static power contribution in VCC 1.5 V 11.10 23.70 37.95 mW SoC mode PDC2 Device static power contribution in See Table 2-8 on – 11.10 23.70 37.95 mW Standby Mode page 2-10 PDC3 Device static power contribution in See Table 2-8 on 3.3 V 33.00 33.00 33.00 µW Time Keeping mode page 2-10 PDC7 Static contribution per input pin VCCxxxxIOBx/VCC See Table 2-10 and Table 2-11 on page 2-11. (standard dependent contribution) PDC8 Static contribution per output pin VCCxxxxIOBx/VCC See Table 2-12 and Table 2-13 on page 2-11. (standard dependent contribution) PDC9 Static contribution per PLL VCC 1.5 V 2.55 2.55 2.55 mW Table 2-16 • eNVM Dynamic Power Consumption Parameter Description Condition Min. Typ. Max. Units eNVM System eNVM array operating power Idle 795 µA Read operation See Table 2-14 on page 2-12. Erase 900 µA Write 900 µA PNVMCTRL eNVM controller operating power 20 µW/MHz Revision 8 2-13 SmartFusion DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software. The power calculation methodology described below uses the following variables: • The number of PLLs/CCCs as well as the number and the frequency of each output clock generated • The number of combinatorial and sequential cells used in the design • The internal clock frequencies • The number and the standard of I/O pins used in the design • The number of RAM blocks used in the design • The number of eNVM blocks used in the design • The analog block used in the design, including the temperature monitor, current monitor, ABPS, sigma-delta DAC, comparator, low power crystal oscillator, RC oscillator and the main crystal oscillator • Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table2-17 on page 2-18. • Enable rates of output buffers—guidelines are provided for typical applications in Table 2-18 on page 2-18. • Read rate and write rate to the memory—guidelines are provided for typical applications in Table 2-18 on page 2-18. • Read rate to the eNVM blocks The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—P TOTAL SoC Mode, Standby Mode, and Time Keeping Mode. P = P + P TOTAL STAT DYN P is the total static power consumption. STAT P is the total dynamic power consumption. DYN Total Static Power Consumption—P STAT SoC Mode P = P + (N * P ) + (N * P ) + (N * P ) STAT DC1 INPUTS DC7 OUTPUTS DC8 PLLS DC9 N is the number of I/O input buffers used in the design. INPUTS N is the number of I/O output buffers used in the design. OUTPUTS N is the number of PLLs available in the device. PLLS Standby Mode P = P STAT DC2 Time Keeping Mode P = P STAT DC3 Total Dynamic Power Consumption—P DYN SoC Mode P = P + P + P + P + P + P + P + P + P + DYN CLOCK S-CELL C-CELL NET INPUTS OUTPUTS MEMORY PLL eNVM + P + P + P + P P XTL-OSC RC-OSC AB LPXTAL-OSC MSS 2-14 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Standby Mode = P + P P DYN RC-OSC LPXTAL-OSC Time Keeping Mode P = P DYN LPXTAL-OSC Global Clock Dynamic Contribution—P CLOCK SoC Mode P = (P + N * P + N * PAC3 + N * P ) * F CLOCK AC1 SPINE AC2 ROW S-CELL AC4 CLK N is the number of global spines used in the user design—guidelines are provided in the SPINE "Device Architecture" chapter of the SmartFusion FPGA Fabric User's Guide. N is the number of VersaTile rows used in the design—guidelines are provided in the "Device ROW Architecture" chapter of the SmartFusion FPGA Fabric User's Guide. F is the global clock signal frequency. CLK N is the number of VersaTiles used as sequential modules in the design. S-CELL Standby Mode and Time Keeping Mode P = 0 W CLOCK Sequential Cells Dynamic Contribution—P S-CELL SoC Mode = N * (P + (α / 2) * P ) * F P S-CELL S-CELL AC5 1 AC6 CLK N is the number of VersaTiles used as sequential modules in the design. When a multi-tile S-CELL sequential cell is used, it should be accounted for as 1. α is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-17 on page 2-18. 1 F is the global clock signal frequency. CLK Standby Mode and Time Keeping Mode P = 0 W S-CELL Combinatorial Cells Dynamic Contribution—P C-CELL SoC Mode P = N * (α / 2) * P * F C-CELL C-CELL 1 AC7 CLK N is the number of VersaTiles used as combinatorial modules in the design. C-CELL α is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-17 on page 2-18. 1 F is the global clock signal frequency. CLK Standby Mode and Time Keeping Mode P = 0 W C-CELL Routing Net Dynamic Contribution—P NET SoC Mode = (N + N ) * (α / 2) * P * F P NET S-CELL C-CELL 1 AC8 CLK N is the number VersaTiles used as sequential modules in the design. S-CELL N is the number of VersaTiles used as combinatorial modules in the design. C-CELL α is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-17 on page 2-18. 1 F is the frequency of the clock driving the logic including these nets. CLK Revision 8 2-15 SmartFusion DC and Switching Characteristics Standby Mode and Time Keeping Mode = 0 W P NET I/O Input Buffer Dynamic Contribution—P INPUTS SoC Mode = N * (α / 2) * P * F P INPUTS INPUTS 2 AC9 CLK Where: N is the number of I/O input buffers used in the design. INPUTS α is the I/O buffer toggle rate—guidelines are provided in Table 2-17 on page 2-18. 2 F is the global clock signal frequency. CLK Standby Mode and Time Keeping Mode P = 0 W INPUTS I/O Output Buffer Dynamic Contribution—P OUTPUTS SoC Mode P = N * (α / 2) * β * P * F OUTPUTS OUTPUTS 2 1 AC10 CLK Where: N is the number of I/O output buffers used in the design. OUTPUTS α is the I/O buffer toggle rate—guidelines are provided in Table 2-17 on page 2-18. 2 β is the I/O buffer enable rate—guidelines are provided in Table 2-18 on page 2-18. 1 F is the global clock signal frequency. CLK Standby Mode and Time Keeping Mode P = 0 W OUTPUTS FPGA Fabric SRAM Dynamic Contribution—P MEMORY SoC Mode P = (N * P * β * F ) + (N * P * β * F ) MEMORY BLOCKS AC11 2 READ-CLOCK BLOCKS AC12 3 WRITE-CLOCK Where: N is the number of RAM blocks used in the design. BLOCKS F is the memory read clock frequency. READ-CLOCK β is the RAM enable rate for read operations—guidelines are provided in Table2-18 on 2 page 2-18. β the RAM enable rate for write operations—guidelines are provided in Table 2-18 on page 2-18. 3 F is the memory write clock frequency. WRITE-CLOCK Standby Mode and Time Keeping Mode P = 0 W MEMORY PLL/CCC Dynamic Contribution—P PLL SoC Mode P = P * F PLL AC13 CLKOUT F is the input clock frequency. CLKIN 1 F is the output clock frequency. CLKOUT Standby Mode and Time Keeping Mode 1.The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula output clock by adding its corresponding contribution (P * F product) to the total PLL AC14 CLKOUT contribution. 2-16 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) P = 0 W PLL Embedded Nonvolatile Memory Dynamic Contribution—P eNVM SoC Mode The eNVM dynamic power consumption is a piecewise linear function of frequency. P = N * β * P * F when F ≤ 33 MHz, eNVM eNVM-BLOCKS 4 AC15 READ-eNVM READ-eNVM P = N * β *(P + P * F ) when F > 33 MHz eNVM eNVM-BLOCKS 4 AC16 AC17 READ-eNVM READ-eNVM Where: N is the number of eNVM blocks used in the design. eNVM-BLOCKS β is the eNVM enable rate for read operations. Default is 0 (eNVM mainly in idle state). 4 F is the eNVM read clock frequency. READ-eNVM Standby Mode and Time Keeping Mode P = 0 W eNVM Main Crystal Oscillator Dynamic Contribution—P XTL-OSC SoC Mode = P P XTL-OSC AC18 Standby Mode P = 0 W XTL-OSC Time Keeping Mode P = 0 W XTL-OSC Low Power Oscillator Crystal Dynamic Contribution—P LPXTAL-OSC Operating, Standby, and Time Keeping Mode P = P LPXTAL-OSC AC21 RC Oscillator Dynamic Contribution—P RC-OSC SoC Mode P = P P RC-OSC AC19A + AC19B Standby Mode and Time Keeping Mode = 0 W P RC-OSC Analog System Dynamic Contribution—P AB SoC Mode = P * N + P * N + P * N + P * N + P * N + P * N P AB AC23 TM AC24 CM AC25 ABPS AC26 SDD AC27 COMP ADC ADC + P VR Where: N is the number of current monitor blocks CM N is the number of temperature monitor blocks TM N is the number of sigma-delta DAC blocks SDD N is the number of ABPS blocks ABPS N is the number of ADC blocks ADC N is the number of comparator blocks COMP P = P VR AC28 P = P + P ADC AC20A AC20B Revision 8 2-17 SmartFusion DC and Switching Characteristics Microcontroller Subsystem Dynamic Contribution—P MSS SoC Mode = P P MSS AC22 Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that the net switches at half the clock frequency. Below are some examples: • The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the clock frequency. • The average toggle rate of an 8-bit counter is 25%: – Bit 0 (LSB) = 100% – Bit 1 = 50% – Bit 2 = 25% –… – Bit 7 (MSB) = 0.78125% – Average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8. Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When non-tristate output buffers are used, the enable rate should be 100%. Table 2-17 • Toggle Rate Guidelines Recommended for Power Calculation Component Definition Guideline α Toggle rate of VersaTile outputs 10% 1 α I/O buffer toggle rate 10% 2 Table 2-18 • Enable Rate Guidelines Recommended for Power Calculation Component Definition Guideline β I/O output buffer enable rate Toggle rate of the logic driving the 1 output buffer β FPGA fabric SRAM enable rate for read 12.5% 2 operations β FPGA fabric SRAM enable rate for write 12.5% 3 operations β eNVM enable rate for read operations < 5% 4 2-18 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Combinational Cell LVPECL (applicable to Y Y FPGA /O bank, EMC pin) t = 0.57 ns t = 0.49 ns PD PD t = 1.53 ns DP I/O Module (Non-Registered) Combinational Cell Y Output drive strength = 12 mA LVTTL High slew rate t = 2.81 ns (FPGA I/O Bank, EMC pin) DP t = 0.89 ns PD I/O Module Combinational Cell (Non-Registered) I/O Module Y (Registered) Output drive strength = 8 mA LVTTL t = 1.46 ns High slew rate PY t = 3.87 ns (FPGA I/O Bank, EMC pin) DP LVPECL t = 0.51 ns PD I/O Module DQ (Applicable (Non-Registered) to FPGA Combinational Cell I/O Bank, Y EMC pin) LVCMOS 1.5 VOutput drive strength = 4 mA High slew rate t = 0.24 ns ICLKQ t = 4.13 ns (FPGA I/O Bank, EMC pin) t = 0.48 ns DP t = 0.27 ns PD ISUD Input LVTTL Clock I/O Module Register Cell Register Cell (Registered) Combinational Cell t = 0.81 ns (FPGA I/O Bank, EMC pin) PY Y DQ DQ DQ LVTTL 3.3 V Output drive I/O Module strength = 12 mA High slew rate t = 0.48 ns PD (Non-Registered) t = 2.81 ns DP (FPGA I/O Bank, EMC pin) t = 0.56 ns CLKQ t = 0.60 ns t = 0.56 ns OCLKQ CLKQ LVDS, t = 0.44 ns SUD t = 0.44 ns t = 0.32 ns SUD OSUD BLVDS, M-LVDS Input LVTTL Input LVTTL Clock Clock (Applicable for t = 1.55 ns PY FPGA I/O Bank, EMC pin) t = 0.81 ns t = 0.81 ns PY PY (FPGA I/O Bank, EMC pin) (FPGA I/O Bank, EMC pin) Figure 2-2 • Timing Model Operating Conditions: –1 Speed, Commercial Temperature Range (T = 85°C), J Worst Case VCC = 1.425 V Revision 8 2-19 SmartFusion DC and Switching Characteristics t t PY DIN D Q PAD DIN Y CLK To Array I/O Interface t = MAX(t (R), t (F)) PY PY PY t = MAX(t (R), t (F)) DIN DIN DIN VIH V V trip trip VIL PAD VCC 50% 50% Y GND t t PY PY (R) (F) VCC 50% 50% DIN t GND t DOUT DOUT (R) (F) Figure 2-3 • Input Buffer Timing Model and Delays (example) 2-20 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) t t DOUT DP D Q PAD DOUT CLK Std D Load From Array t = MAX(t (R), t (F)) DP DP DP I/O Interface t = MAX(t (R), t (F)) DOUT DOUT DOUT t t DOUT DOUT VCC (R) (F) 50% 50% D 0 V VCC 50% 50% DOUT 0 V VOH V V trip trip VOL PAD t t DP DP (R) (F) Figure 2-4 • Output Buffer Model and Delays (example) Revision 8 2-21 SmartFusion DC and Switching Characteristics t EOUT D Q CLK t , t , t , t , t , t E ZL ZH HZ LZ ZLS ZHS EOUT D Q PAD DOUT CLK D t = MAX(t (r), t (f)) I/O Interface EOUT EOUT EOUT VCC D VCC 50% 50% E t EOUT (F) t EOUT (R) VCC 50% 50% 50% 50% t LZ EOUT t ZH t ZL t VCCxxxxIOBx HZ 90% VCCxxxxIOBx PAD V V trip trip VOL 10% VCCxxxxIOBx VCC D VCC 50% 50% E t t EOUT (R) EOUT (F) VCC 50% 50% EOUT 50% t ZHS t VOH ZLS PAD V V trip trip VOL Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example) 2-22 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-19 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial Conditions—Software Default Settings Applicable to FPGA I/O Banks 1 1 VIL VIH VOL VOH I I OL OH Drive Slew Min. Max. Min. Max. Max. Min. V V V V V VmAmA I/O Standard Strgth. Rate 3.3VLVTTL/ 12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12 3.3 V LVCMOS 2.5 V LVCMOS 12 mA High –0.3 0.7 1.7 3.6 0.7 1.7 12 12 1.8 V LVCMOS 12 mA High –0.3 0.35 * 0.65* 3.6 0.45 VCCxxxxIOBx 12 12 VCCxxxxIOBx VCCxxxxIOBx – 0.45 1.5 V LVCMOS 12 mA High –0.3 0.35 * 0.65* 3.6 0.25 * 0.75* 12 12 VCCxxxxIOBx VCCxxxxIOBx VCCxxxxIOBx VCCxxxxIOBx 3.3 V PCI Per PCI specifications 3.3 V PCI-X Per PCI-X specifications Notes: 1. Currents are measured at 85°C junction temperature. 2. Output slew rate can be extracted by the IBIS Models. Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial Conditions—Software Default Settings Applicable to MSS I/O Banks 1 1 VIL VIH VOL VOH I I OL OH Drive Slew Min. Max. Min. Max. Max. Min. I/O Standard Strgth. Rate V V V V V VmAmA 3.3VLVTTL/ 8 mA High –0.3 0.8 2 3.6 0.4 2.4 8 8 3.3 V LVCMOS 2.5 V LVCMOS 8 mA High –0.3 0.7 1.7 3.6 0.7 1.7 8 8 1.8 V LVCMOS 4 mA High –0.3 0.35* 0.65* 3.6 0.45 VCCxxxxIOBx 44 VCCxxxxIOBx VCCxxxxIOBx – 0.45 1.5 V LVCMOS 2 mA High –0.3 0.35* 0.65* 3.6 0.25* 0.75* 22 VCCxxxxIOBx VCCxxxxIOBx VCCxxxxIOBx VCCxxxxIOBx Notes: 1. Currents are measured at 85°C junction temperature. 2. Output slew rate can be extracted by the IBIS Models. Revision 8 2-23 SmartFusion DC and Switching Characteristics Table 2-21 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial Conditions in all I/O Bank Types Commercial I I IL IH DC I/O Standards µA µA 3.3 V LVTTL / 3.3 V LVCMOS 15 15 2.5 V LVCMOS 15 15 1.8 V LVCMOS 15 15 1.5 V LVCMOS 15 15 3.3 V PCI 15 15 3.3 V PCI-X 15 15 Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-22 • Summary of AC Measuring Points Applicable to All I/O Bank Types Standard Measuring Trip Point (V ) trip 3.3 V LVTTL / 3.3 V LVCMOS 1.4 V 2.5 V LVCMOS 1.2 V 1.8 V LVCMOS 0.90 V 1.5 V LVCMOS 0.75 V 3.3 V PCI 0.285 * VCCxxxxIOBx (RR) 0.615 * VCCxxxxIOBx (FF) 3.3 V PCI-X 0.285 * VCCxxxxIOBx (RR) 0.615 * VCCxxxxIOBx (FF) LVDS Cross point LVPECL Cross point Table 2-23 • I/O AC Parameter Definitions Parameter Parameter Definition t Data to pad delay through the output buffer DP t Pad to data delay through the input buffer PY t Data to output buffer delay through the I/O interface DOUT t Enable to output buffer tristate control delay through the I/O interface EOUT t Input buffer to data delay through the I/O interface DIN t Enable to pad delay through the output buffer—High to Z HZ t Enable to pad delay through the output buffer—Z to High ZH t Enable to pad delay through the output buffer—Low to Z LZ t Enable to pad delay through the output buffer—Z to Low ZL t Enable to pad delay through the output buffer with delayed enable—Z to High ZHS t Enable to pad delay through the output buffer with delayed enable—Z to Low ZLS 2-24 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Worst Commercial-Case Conditions: T = 85°C, Worst Case VCC = 1.425 V, J Worst-Case VCCxxxxIOBx (per standard) Applicable to FPGA I/O Banks, Assigned to EMC I/O Pins I/O Standard 3.3VLVTTL/ 12 mA High 35 – 0.50 2.81 0.03 0.81 0.32 2.86 2.23 2.55 2.82 4.58 3.94 ns 3.3 V LVCMOS 2.5 V LVCMOS 12 mA High 35 – 0.50 2.73 0.03 1.03 0.32 2.88 2.69 2.62 2.70 4.60 4.41 ns 1.8 V LVCMOS 12 mA High 35 – 0.50 2.81 0.03 0.95 0.32 2.87 2.38 2.92 3.18 4.58 4.10 ns 1.5 V LVCMOS 12 mA High 35 – 0.50 3.24 0.03 1.12 0.32 3.30 2.79 3.10 3.27 5.02 4.50 ns 1 3.3 V PCI Per PCI spec High 10 25 0.50 2.11 0.03 0.68 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns 1 3.3 V PCI-X Per PCI-X High 10 25 0.50 2.11 0.03 0.64 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns spec LVDS 24 mA High – – 0.50 1.53 0.03 1.55 – – – – – – – ns LVPECL 24 mA High – – 0.50 1.46 0.03 1.46 – – – – – – – ns Notes: 1. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-39 for connectivity. This resistor is not required during normal operation. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Worst Commercial-Case Conditions: T = 85°C, Worst Case VCC = 1.425 V, J Worst-Case VCCxxxxIOBx (per standard) Applicable to MSS I/O Banks I/O Standard 3.3 V LVTTL / 8 mA High 10 – 0.18 1.92 0.07 0.78 1.09 0.18 1.96 1.55 1.83 2.04 ns 3.3 V LVCMOS 2.5 V LVCMOS 8 mA High 10 – 0.18 1.96 0.07 0.99 1.16 0.18 2.00 1.82 1.82 1.93 ns 1.8 V LVCMOS 4 mA High 10 – 0.18 2.31 0.07 0.91 1.37 0.18 2.35 2.27 1.84 1.87 ns 1.5 V LVCMOS 2 mA High 10 – 0.18 2.70 0.07 1.07 1.55 0.18 2.75 2.67 1.87 1.85 ns Notes: 1. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-39 for connectivity. This resistor is not required during normal operation. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Revision 8 2-25 Drive Strength Drive Strength Slew Rate Slew Rate Capacitive Load (pF) Capacitive Load (pF) External Resistor External Resistor (Ω) t (ns) DOUT t (ns) DOUT t (ns) DP t (ns) DP t (ns) DIN t (ns) DIN t (ns) t (ns) PY PY t (ns) EOUT t (ns) PYS t (ns) ZL t (ns) EOUT t (ns) ZH t (ns) ZL t (ns) LZ t (ns) ZH t (ns) HZ t (ns) LZ t (ns) ZLS t (ns) HZ t (ns) ZHS Units Units SmartFusion DC and Switching Characteristics Detailed I/O DC Characteristics Table 2-26 • Input Capacitance Symbol Definition Conditions Min. Max. Units C Input capacitance V = 0, f = 1.0 MHz 8 pF IN IN C Input capacitance on the clock pin V = 0, f = 1.0 MHz 8 pF INCLK IN 1 Table 2-27 • I/O Output Buffer Maximum Resistances Applicable to FPGA I/O Banks R R PULL-DOWN PULL-UP 2 3 Standard Drive Strength (Ω) (Ω) 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 12 mA 25 75 16 mA 17 50 24 mA 11 33 2.5 V LVCMOS 2 mA 100 200 4 mA 100 200 6 mA 50 100 8 mA 50 100 12 mA 25 50 16 mA 20 40 24 mA 11 22 1.8 V LVCMOS 2 mA 200 225 4 mA 100 112 6 mA 50 56 8 mA 50 56 12 mA 20 22 16 mA 20 22 1.5 V LVCMOS 2 mA 200 224 4 mA 100 112 6 mA 67 75 8 mA 33 37 12 mA 33 37 3.3 V PCI/PCI-X Per PCI/PCI-X specification 25 75 Notes: 1. These maximum values are provided for information only. Minimum output buffer resistance values depend on VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website at http://www.microsemi.com/soc/download/ibis/default.aspx (also generated by the SoC Products Group Libero IDE toolset). 2. R = (V ) / I (PULL-DOWN-MAX) OLspec OLspec 3. R = (V – V ) / I (PULL-UP-MAX) CCImax OHspec OHspec 2-26 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) 1 Table 2-28 • I/O Output Buffer Maximum Resistances Applicable to MSS I/O Banks R R PULL-DOWN PULL-UP 2 3 Standard Drive Strength (Ω) (Ω) 3.3 V LVTTL / 3.3 V LVCMOS 8mA 50 150 2.5 V LVCMOS 8 mA 50 100 1.8 V LVCMOS 4 mA 100 112 1.5 V LVCMOS 2 mA 200 224 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the SoC Products Group website at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R = (V ) / I (PULL-DOWN-MAX) OLspec OLspec 3. R = (V – V ) / I (PULL-UP-MAX) CCImax OHspec OHspec Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values 1 2 R R (WEAK PULL-UP) (WEAK PULL-DOWN) (Ω) (Ω) VCCxxxxIOBx Min. Max. Min. Max. 3.3 V 10 k 45 k 10 k 45 k 2.5 V 11 k 55 k 12 k 74 k 1.8 V 18 k 70 k 17 k 110 k 1.5 V 19 k 90 k 19 k 140 k Notes: 1. R = (V ) / I (WEAK PULL-DOWN-MAX) OLspec (WEAK PULL-DOWN-MIN) 2. R = (V – V ) / I (WEAK PULL-UP-MAX) CCImax OHspec (WEAK PULL-UP-MIN) Revision 8 2-27 SmartFusion DC and Switching Characteristics Table 2-30 • I/O Short Currents I /I OSH OSL Applicable to FPGA I/O Banks * * Drive Strength I (mA) I (mA) OSL OSH 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25 4 mA 27 25 6 mA 54 51 8 mA 54 51 12 mA 109 103 16 mA 127 132 24 mA 181 268 2.5 V LVCMOS 2 mA 18 16 4 mA 18 16 6 mA 37 32 8 mA 37 32 12 mA 74 65 16 mA 87 83 24 mA 124 169 1.8 V LVCMOS 2 mA 11 9 4 mA 22 17 6 mA 44 35 8 mA 51 45 12 mA 74 91 16 mA 74 91 1.5 V LVCMOS 2 mA 16 13 4 mA 33 25 6 mA 39 32 8 mA 55 66 12 mA 55 66 3.3 V PCI/PCI-X Per PCI/PCI-X specification 109 103 Note: *T = 85°C. J Table 2-31 • I/O Short Currents I /I OSH OSL Applicable to MSS I/O Banks Drive Strength I (mA)* I (mA)* OSL OSH 3.3 V LVTTL / 3.3 V LVCMOS 8 mA 54 51 2.5 V LVCMOS 8 mA 37 32 1.8 V LVCMOS 4 mA 22 17 1.5 V LVCMOS 2 mA 16 13 Note: *T = 85°C J 2-28 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) The length of time an I/O can withstand I /I events depends on the junction temperature. The OSH OSL reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 100°C, the short current condition would have to be sustained for more than 2200 operation hours to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-32 • Duration of Short Circuit Event before Failure Temperature Time before Failure –40°C > 20 years 0°C > 20 years 25°C > 20 years 70°C 5 years 85°C 2 years 100°C 6 months Table 2-33 • Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (typical) for Schmitt Mode Input Buffers Input Buffer Configuration Hysteresis Value (typical) 3.3 V LVTTL / LVCMOS / PCI / PCI-X (Schmitt trigger mode) 240 mV 2.5 V LVCMOS (Schmitt trigger mode) 140 mV 1.8 V LVCMOS (Schmitt trigger mode) 80 mV 1.5 V LVCMOS (Schmitt trigger mode) 60 mV Table 2-34 • I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS No requirement 10 ns * 20 years (100°C) LVDS/B-LVDS/ No requirement 10 ns * 10 years (100°C) M-LVDS/LVPECL Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microsemi SoC Products Group recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. Revision 8 2-29 SmartFusion DC and Switching Characteristics Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-35 • Minimum and Maximum DC Input and Output Levels Applicable to FPGA I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS VIL VIH VOL VOH I I I I I I OL OH OSL OSH IL IH Min. Max. Min. Max. Max. Min. Max. Max. 1 1 2 2 Drive Strength V V V V V VmAmA mA mA µA µA 2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 15 15 4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 15 15 6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 15 15 8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 15 15 12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 15 15 16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 15 15 24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-36 • Minimum and Maximum DC Input and Output Levels Applicable to MSS I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS VIL VIH VOL VOH I I I I I I OL OH OSL OSH IL IH Min. Max. Min. Max. Max. Min. Max. Max. 1 1 2 2 Drive Strength V V V V V VmAmA mA mA µA µA 8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 15 15 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. R to VCCxxxxIOBx for t / t / t LZ ZL ZLS R = 1 K Test Point R to GND for t / t / t HZ ZH ZHS Test Point 35 pF 35 pF for t / t / t / t Datapath ZH ZHS ZL ZLS Enable Path 35 pF for t / t HZ LZ Figure 2-6 • AC Loading Table 2-37 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) V (typ.) (V) C (pF) REF LOAD 0 3.3 1.4 – 35 Note: *Measuring point = V See Table 2-22 on page 2-24 for a complete table of trip points. trip. 2-30 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Timing Characteristics Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew = 85°C, Worst-Case VCC = 1.425 V, Worst Commercial-Case Conditions: T J Worst-Case VCCxxxxIOBx = 3.0 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Drive Speed t t t t t t t t t t Units Strength Grade t DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS 4 mA Std. 0.60 7.20 0.04 0.97 0.39 7.34 6.18 2.52 2.46 9.39 8.23 ns –1 0.50 6.00 0.03 0.81 0.32 6.11 5.15 2.10 2.05 7.83 6.86 ns 8 mA Std. 0.60 4.64 0.04 0.97 0.39 4.73 3.84 2.85 3.02 6.79 5.90 ns –1 0.50 3.87 0.03 0.81 0.32 3.94 3.20 2.37 2.52 5.65 4.91 ns 12 mA Std. 0.60 3.37 0.04 0.97 0.39 3.43 2.67 3.07 3.39 5.49 4.73 ns –1 0.50 2.81 0.03 0.81 0.32 2.86 2.23 2.55 2.82 4.58 3.94 ns 16 mA Std. 0.60 3.18 0.04 0.97 0.39 3.24 2.43 3.11 3.48 5.30 4.49 ns –1 0.50 2.65 0.03 0.81 0.32 2.70 2.03 2.59 2.90 4.42 3.74 ns 24 mA Std. 0.60 2.93 0.04 0.97 0.39 2.99 2.03 3.17 3.83 5.05 4.09 ns –1 0.50 2.45 0.03 0.81 0.32 2.49 1.69 2.64 3.19 4.21 3.41 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Table 2-39 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCxxxxIOBx = 3.0 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Drive Speed Strength Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS 4 mA Std. 0.60 9.75 0.04 0.97 0.39 9.93 8.22 2.52 2.31 11.99 10.28 ns –1 0.50 8.12 0.03 0.81 0.32 8.27 6.85 2.10 1.93 9.99 8.57 ns 8 mA Std. 0.60 6.96 0.04 0.97 0.39 7.09 5.85 2.84 2.87 9.15 7.91 ns –1 0.50 5.80 0.03 0.81 0.32 5.91 4.88 2.37 2.39 7.62 6.59 ns 12 mA Std. 0.60 5.35 0.04 0.97 0.39 5.45 4.58 3.06 3.23 7.51 6.64 ns –1 0.50 4.46 0.03 0.81 0.32 4.54 3.82 2.55 2.69 6.26 5.53 ns 16 mA Std. 0.60 5.01 0.04 0.97 0.39 5.10 4.30 3.11 3.32 7.16 6.36 ns –1 0.50 4.17 0.03 0.81 0.32 4.25 3.58 2.59 2.77 5.97 5.30 ns 24 mA Std. 0.60 4.67 0.04 0.97 0.39 4.75 4.28 3.16 3.66 6.81 6.34 ns –1 0.50 3.89 0.03 0.81 0.32 3.96 3.57 2.64 3.05 5.68 5.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Table 2-40 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCxxxxIOBx = 3.0 V Applicable to MSS I/O Banks Drive Speed Strength Grade t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ 8 mA Std. 0.22 2.31 0.09 0.94 1.30 0.22 2.35 1.86 2.20 2.45 ns –1 0.18 1.92 0.07 0.78 1.09 0.18 1.96 1.55 1.83 2.04 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Revision 8 2-31 SmartFusion DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. Table 2-41 • Minimum and Maximum DC Input and Output Levels Applicable to FPGA I/O Banks 2.5 V LVCMOS VIL VIH VOL VOH I I I I I I OL OH OSL OSH IL IH Min. Max. Min. Max. Max. Min. Max. Max. 1 1 2 2 Drive Strength V V V V V VmAmA mA mA µA µA 2 mA –0.3 0.7 1.7 2.7 0.7 1.7 2 2 18 16 15 15 4 mA –0.3 0.7 1.7 2.7 0.7 1.7 4 4 18 16 15 15 6 mA –0.3 0.7 1.7 2.7 0.7 1.7 6 6 37 32 15 15 8 mA –0.3 0.7 1.7 2.7 0.7 1.7 8 8 37 32 15 15 12 mA –0.3 0.7 1.7 2.7 0.7 1.7 12 12 74 65 15 15 16 mA –0.3 0.7 1.7 2.7 0.7 1.7 16 16 87 83 15 15 24 mA –0.3 0.7 1.7 2.7 0.7 1.7 24 24 124 169 15 15 Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-42 • Minimum and Maximum DC Input and Output Levels Applicable to MSS I/O Banks 2.5 V LVCMOS VIL V VOL VOH I I I I I I IH OL OH OSL OSH IL IH Min. Max. Min. Max. Max. Min. Max. Max., 1 1 2 2 Drive Strength V V V V V VmAmA mA mA µA µA 8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 15 15 Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. R to VCCxxxxIOBx for t / t / t LZ ZL ZLS R = 1 K Test Point R to GND for t / t / t HZ ZH ZHS Test Point 35 pF 35 pF for t / t / t / t Datapath ZH ZHS ZL ZLS Enable Path 35 pF for t / t HZ LZ Figure 2-7 • AC Loading Table 2-43 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) V (typ.) (V) C (pF) REF LOAD 0 2.5 1.2 – 35 * Measuring point = V See Table 2-22 on page 2-24 for a complete table of trip points. trip. 2-32 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Timing Characteristics Table 2-44 • 2.5 V LVCMOS High Slew = 85°C, Worst-Case VCC = 1.425 V, Worst Commercial-Case Conditions: T J Worst-Case VCCxxxxIOBx = 2.3 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Drive Speed t t t t t t t t t t Units Strength Grade t DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS 4 mA Std. 0.55 8.10 0.04 1.23 0.39 7.37 8.10 2.54 2.17 9.43 10.15 ns –1 0.46 6.75 0.03 1.03 0.32 6.14 6.75 2.12 1.81 7.85 8.46 ns 8 mA Std. 0.55 4.85 0.04 1.23 0.39 4.76 4.85 2.90 2.83 6.82 6.91 ns –1 0.46 4.04 0.03 1.03 0.32 3.97 4.04 2.42 2.36 5.68 5.76 ns 12 mA Std. 0.60 3.28 0.04 1.23 0.39 3.46 3.23 3.15 3.24 5.52 5.29 ns –1 0.50 2.73 0.03 1.03 0.32 2.88 2.69 2.62 2.70 4.60 4.41 ns 16 mA Std. 0.60 3.09 0.04 1.23 0.39 3.27 2.88 3.20 3.35 5.33 4.94 ns –1 0.50 2.57 0.03 1.03 0.32 2.72 2.40 2.67 2.79 4.44 4.12 ns 24 mA Std. 0.60 2.95 0.04 1.23 0.39 3.01 2.31 3.27 3.76 5.07 4.37 ns –1 0.50 2.46 0.03 1.03 0.32 2.51 1.93 2.73 3.13 4.22 3.64 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Table 2-45 • 2.5 V LVCMOS Low Slew Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCxxxxIOBx = 2.3 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Drive Speed Strength Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS 4 mA Std. 0.55 10.50 0.04 1.23 0.39 10.69 10.50 2.54 2.07 12.75 12.56 ns –1 0.46 8.75 0.03 1.03 0.32 8.91 8.75 2.12 1.73 10.62 10.47 ns 8 mA Std. 0.55 7.61 0.04 1.23 0.39 7.46 7.19 2.81 2.66 9.52 9.25 ns –1 0.46 6.34 0.03 1.03 0.32 6.22 5.99 2.34 2.22 7.93 7.71 ns 12 mA Std. 0.60 5.92 0.04 1.23 0.39 5.79 5.45 3.04 3.06 7.85 7.51 ns –1 0.50 4.93 0.03 1.03 0.32 4.83 4.54 2.53 2.55 6.54 6.26 ns 16 mA Std. 0.60 5.53 0.04 1.23 0.39 5.40 5.09 3.09 3.16 7.46 7.14 ns –1 0.50 4.61 0.03 1.03 0.32 4.50 4.24 2.58 2.64 6.22 5.95 ns 24 mA Std. 0.60 5.18 0.04 1.23 0.39 5.28 5.14 3.27 3.64 7.34 7.20 ns –1 0.50 4.32 0.03 1.03 0.32 4.40 4.29 2.72 3.03 6.11 6.00 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Table 2-46 • 2.5 V LVCMOS High Slew Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCxxxxIOBx = 3.0 V Applicable to MSS I/O Banks Drive Speed Strength Grade t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ 8 mA Std. 0.22 2.35 0.09 1.18 1.39 0.22 2.40 2.18 2.19 2.32 ns –1 0.18 1.96 0.07 0.99 1.16 0.18 2.00 1.82 1.82 1.93 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Revision 8 2-33 SmartFusion DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-47 • Minimum and Maximum DC Input and Output Levels Applicable to FPGA I/O Banks 1.8 V I I I I I LVCMOS VIL VIH VOL VOH I OL OH OSL OSH IL IH Drive Min. Max. Min. Max. Max. Min. Max. Max. 1 1 2 2 Strength V V V V V VmAmA mA mA µA µA 2 mA –0.3 0.35 * 0.65 * 1.9 0.45 VCCxxxxIOBx 2 2 11 9 15 15 VCCxxxxIOBx VCCxxxxIOBx – 0.45 4 mA –0.3 0.35 * 0.65 * 1.9 0.45 VCCxxxxIOBx 4 4 22 17 15 15 VCCxxxxIOBx VCCxxxxIOBx – 0.45 6 mA –0.3 0.35 * 0.65 * 1.9 0.45 VCCxxxxIOBx 6 6 44 35 15 15 VCCxxxxIOBx VCCxxxxIOBx – 0.45 8 mA –0.3 0.35 * 0.65 * 1.9 0.45 VCCxxxxIOBx 8 8 51 45 15 15 VCCxxxxIOBx VCCxxxxIOBx – 0.45 12 mA –0.3 0.35 * 0.65 * 1.9 0.45 VCCxxxxIOBx 12 12 74 91 15 15 VCCxxxxIOBx VCCxxxxIOBx – 0.45 16 mA –0.3 0.35 * 0.65 * 1.9 0.45 VCCxxxxIOBx 16 16 74 91 15 15 VCCxxxxIOBx VCCxxxxIOBx – 0.45 Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-48 • Minimum and Maximum DC Input and Output Levels Applicable to MSS I/O Banks 1.8 V LVCMOS VIL VIH VOL VOH I I I I I I OL OH OSL OSH IL IH Drive Min. Max. Min. Max. Max. Min. Max. Max. 1 1 2 2 Strength V V V V V VmAmA mA mA µA µA 4 mA –0.3 0.35 * 0.65 * 3.6 0.45 VCCxxxxIOBx 4 4 22 17 15 15 VCCxxxxIOBx VCCxxxxIOBx – 0.45 Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. R to VCCxxxxIOBx for t / t / t LZ ZL ZLS R = 1 K Test Point R to GND for t / t / t HZ ZH ZHS Test Point 35 pF 35 pF for t / t / t / t Datapath ZH ZHS ZL ZLS Enable Path 35 pF for t / t HZ LZ Figure 2-8 • AC Loading Table 2-49 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) V (typ.) (V) C (pF) REF LOAD 0 1.8 0.9 – 35 * Measuring point = V See Table 2-22 on page 2-24 for a complete table of trip points. trip. 2-34 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Timing Characteristics Table 2-50 • 1.8 V LVCMOS High Slew = 85°C, Worst-Case VCC = 1.425 V, Worst Commercial-Case Conditions: T J Worst-Case VCCxxxxIOBx = 1.7 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Drive Speed Strength Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS 2 mA Std. 0.60 11.06 0.04 1.14 0.39 8.61 11.06 2.61 1.59 10.67 13.12 ns –1 0.50 9.22 0.03 0.95 0.32 7.17 9.22 2.18 1.33 8.89 10.93 ns 4 mA Std. 0.60 6.46 0.04 1.14 0.39 5.53 6.46 3.04 2.66 7.59 8.51 ns –1 0.50 5.38 0.03 0.95 0.32 4.61 5.38 2.54 2.22 6.33 7.10 ns 6 mA Std. 0.60 4.16 0.04 1.14 0.39 3.99 4.16 3.34 3.18 6.05 6.22 ns –1 0.50 3.47 0.03 0.95 0.32 3.32 3.47 2.78 2.65 5.04 5.18 ns 8 mA Std. 0.60 3.69 0.04 1.14 0.39 3.76 3.67 3.40 3.31 5.81 5.73 ns –1 0.50 3.07 0.03 0.95 0.32 3.13 3.06 2.84 2.76 4.85 4.78 ns 12 mA Std. 0.60 3.38 0.04 1.14 0.39 3.44 2.86 3.50 3.82 5.50 4.91 ns –1 0.50 2.81 0.03 0.95 0.32 2.87 2.38 2.92 3.18 4.58 4.10 ns 16 mA Std. 0.60 3.38 0.04 1.14 0.39 3.44 2.86 3.50 3.82 5.50 4.91 ns –1 0.50 2.81 0.03 0.95 0.32 2.87 2.38 2.92 3.18 4.58 4.10 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Table 2-51 • 1.8 V LVCMOS Low Slew Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCxxxxIOBx = 1.7 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Drive Speed Strength Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS 2 mA Std. 0.60 14.24 0.04 1.14 0.39 13.47 14.24 2.62 1.54 15.53 16.30 ns –1 0.50 11.87 0.03 0.95 0.32 11.23 11.87 2.18 1.28 12.94 13.59 ns 4 mA Std. 0.60 9.74 0.04 1.14 0.39 9.92 9.62 3.05 2.57 11.98 11.68 ns –1 0.50 8.11 0.03 0.95 0.32 8.26 8.02 2.54 2.14 9.98 9.74 ns 6 mA Std. 0.60 7.67 0.04 1.14 0.39 7.81 7.24 3.34 3.08 9.87 9.30 ns –1 0.50 6.39 0.03 0.95 0.32 6.51 6.03 2.79 2.56 8.23 7.75 ns 8 mA Std. 0.60 7.15 0.04 1.14 0.39 7.29 6.75 3.41 3.21 9.34 8.80 ns –1 0.50 5.96 0.03 0.95 0.32 6.07 5.62 2.84 2.68 7.79 7.34 ns 12 mA Std. 0.60 6.76 0.04 1.14 0.39 6.89 6.75 3.50 3.70 8.95 8.81 ns –1 0.50 5.64 0.03 0.95 0.32 5.74 5.62 2.92 3.08 7.46 7.34 ns 16 mA Std. 0.60 6.76 0.04 1.14 0.39 6.89 6.75 3.50 3.70 8.95 8.81 ns –1 0.50 5.64 0.03 0.95 0.32 5.74 5.62 2.92 3.08 7.46 7.34 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Revision 8 2-35 SmartFusion DC and Switching Characteristics Table 2-52 • 1.8 V LVCMOS High Slew Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCxxxxIOBx = 1.7 V Applicable to MSS I/O Banks Drive Speed Strength Grade t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ 4 mA Std. 0.22 2.77 0.09 1.09 1.64 0.22 2.82 2.72 2.21 2.25 ns –1 0.18 2.31 0.07 0.91 1.37 0.18 2.35 2.27 1.84 1.87 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. 2-36 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-53 • Minimum and Maximum DC Input and Output Levels Applicable to FPGA I/O Banks 1.5 V LVCMOS VIL VIH VOL VOH I I I I I I OL OH OSL OSH IL IH Drive Min. Max. Min. Max. Max. Min. Max. Max. 1 1 2 2 Strength V V V V V VmAmA mA mA µA µA 2 mA –0.3 0.35 * 0.65 * 1.575 0.25* 0.75 * 2 2 16 13 15 15 VCCxxxxIOBx VCCxxxxIOBx VCCxxxxIOBx VCCxxxxIOBx 4 mA – 0.35* 0.65 * 1.575 0.25* 0.75 * 4 4 33 25 15 15 0.3 VCCxxxxIOBx VCCxxxxIOBx VCCxxxxIOBx VCCxxxxIOBx 6 mA – 0.35 * 0.65 * 1.575 0.25* 0.75 * 6 6 39 32 15 15 0.3 VCCxxxxIOBx VCCxxxxIOBx VCCxxxxIOBx VCCxxxxIOBx 8 mA – 0.35 * 0.65 * 1.575 0.25* VCC 0.75 * 8 8 55 66 15 15 0.3 VCCxxxxIOBx VCCxxxxIOBx VCCxxxxIOBx 12 mA – 0.35 * 0.65 * 1.575 0.25 * 0.75 * 12 12 55 66 15 15 0.3 VCCxxxxIOBx VCCxxxxIOBx VCCxxxxIOBx VCCxxxxIOBx Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-54 • Minimum and Maximum DC Input and Output Levels Applicable to MSS I/O Banks 1.5 V LVCMOS VIL VIH VOL VOH I I I I I I OL OH OSL OSH IL IH Drive Min. Max. Min. Max. Max. Min. Max. Max. µA 1 1 2 2 Strength V V V V V VmAmA mA mA µA 2 mA –0.3 0.35 * 0.65 * 1.575 0.25 * 0.75 * 2 2 16 13 15 15 VCCxxxxIOBx VCCxxxxIOBx VCCxxxxIOBx VCCxxxxIOBx Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. R to VCCxxxxIOBx for t / t / t LZ ZL ZLS R = 1 K Test Point R to GND for t / t / t HZ ZH ZHS Test Point 35 pF 35 pF for t / t / t / t Datapath ZH ZHS ZL ZLS Enable Path 35 pF for t / t HZ LZ Figure 2-9 • AC Loading Table 2-55 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) V (typ.) (V) C (pF) REF LOAD 0 1.5 0.75 – 35 * Measuring point = V See Table 2-22 on page 2-24 for a complete table of trip points. trip. Revision 8 2-37 SmartFusion DC and Switching Characteristics Timing Characteristics Table 2-56 • 1.5 V LVCMOS High Slew = 85°C, Worst-Case VCC = 1.425 V, Worst Commercial-Case Conditions: T J Worst-Case VCCxxxxIOBx = 1.425 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Drive Speed t t t t t t t t t t Units Strength Grade t DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS 2 m Std. 0.60 7.79 0.04 1.34 0.39 6.43 7.79 3.19 2.59 8.49 9.85 ns –1 0.50 6.49 0.03 1.12 0.32 5.36 6.49 2.66 2.16 7.08 8.21 ns 4 mA Std. 0.60 4.95 0.04 1.34 0.39 4.61 4.96 3.53 3.19 6.67 7.02 ns –1 0.50 4.13 0.03 1.12 0.32 3.85 4.13 2.94 2.66 5.56 5.85 ns 6 mA Std. 0.60 4.36 0.04 1.34 0.39 4.34 4.36 3.60 3.34 6.40 6.42 ns –1 0.50 3.64 0.03 1.12 0.32 3.62 3.64 3.00 2.78 5.33 5.35 ns 8 mA Std. 0.60 3.89 0.04 1.34 0.39 3.96 3.34 3.72 3.92 6.02 5.40 ns –1 0.50 3.24 0.03 1.12 0.32 3.30 2.79 3.10 3.27 5.02 4.50 ns 12 mA Std. 0.60 3.89 0.04 1.34 0.39 3.96 3.34 3.72 3.92 6.02 5.40 ns –1 0.50 3.24 0.03 1.12 0.32 3.30 2.79 3.10 3.27 5.02 4.50 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Table 2-57 • 1.5 V LVCMOS Low Slew Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCxxxxIOBx = 1.4 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Drive Speed Strength Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS 2 mA Std. 0.60 11.96 0.04 1.34 0.39 12.18 11.70 3.20 2.47 14.24 13.76 ns –1 0.50 9.96 0.03 1.12 0.32 10.15 9.75 2.67 2.06 11.86 11.46 ns 4 mA Std. 0.60 9.51 0.04 1.34 0.39 9.68 8.76 3.54 3.07 11.74 10.82 ns –1 0.50 7.92 0.03 1.12 0.32 8.07 7.30 2.95 2.56 9.79 9.02 ns 6 mA Std. 0.60 8.86 0.04 1.34 0.39 9.03 8.17 3.61 3.22 11.08 10.23 ns –1 0.50 7.39 0.03 1.12 0.32 7.52 6.81 3.01 2.68 9.24 8.52 ns 8 mA Std. 0.60 8.44 0.04 1.34 0.39 8.60 8.18 3.73 3.78 10.66 10.24 ns –1 0.50 7.04 0.03 1.12 0.32 7.17 6.82 3.11 3.15 8.88 8.53 ns 12 mA Std. 0.60 8.44 0.04 1.34 0.39 8.60 8.18 3.73 3.78 10.66 10.24 ns –1 0.50 7.04 0.03 1.12 0.32 7.17 6.82 3.11 3.15 8.88 8.53 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Table 2-58 • 1.5 V LVCMOS High Slew Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCxxxxIOBx = 3.0 V Applicable to MSS I/O Banks Drive Speed Strength Grade t t t t t t t t t t Units DOUT DP DIN PY PYS EOUT ZL ZH LZ HZ 2 mA Std. 0.22 3.24 0.09 1.28 1.86 0.22 3.30 3.20 2.24 2.21 ns –1 0.18 2.70 0.07 1.07 1.55 0.18 2.75 2.67 1.87 1.85 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. 2-38 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-59 • Minimum and Maximum DC Input and Output Levels 3.3 V PCI/PCI-X VIL VIH VOL VOH I I I I I I OL OH OSL OSH IL IH Min. Max. Min. Max. Max. Min. Max. Max. 1 1 2 2 Drive Strength V V V V V VmAmA mA mA µA µA Per PCI specification Per PCI curves 15 15 Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the datapath; SoC Products Group loadings for enable path characterization are described in Figure 2-10. R to VCCXXXXIOBX for t / t / t LZ ZL ZLS R to VCCXXXXIOBX for t (F) DP R = 25 R = 1 k R to GND for t / t / t HZ ZH ZHS R to GND for t (R) Test Point DP Test Point 10 pF for t / t / t / t Datapath Enable Path ZH ZHS ZL ZLS 10 pF for t / t HZ LZ Figure 2-10 • AC Loading AC loadings are defined per PCI/PCI-X specifications for the datapath; SoC Products Group loading for tristate is described in Table 2-60. Table 2-60 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) V (typ.) (V) C (pF) REF LOAD 0 3.3 0.285 * VCCxxxxIOBx for t –10 DP(R) 0.615 * VCCxxxxIOBx for t DP(F) * Measuring point = V See Table 2-22 on page 2-24 for a complete table of trip points. trip. Timing Characteristics Table 2-61 • 3.3 V PCI Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCxxxxIOBx = 3.0 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 0.60 2.54 0.04 0.82 0.39 2.58 1.88 3.06 3.39 4.64 3.94 ns –1 0.50 2.11 0.03 0.68 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Table 2-62 • 3.3 V PCI-X Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCxxxxIOBx = 3.0 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Speed Grade t t t t t t t t t t t Units DOUT DP DIN PY EOUT ZL ZH LZ HZ ZLS ZHS Std. 0.60 2.54 0.04 0.77 0.39 2.58 1.88 3.06 3.39 4.64 3.94 ns –1 0.50 2.11 0.03 0.64 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Revision 8 2-39 SmartFusion DC and Switching Characteristics Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by SoC Products Group Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards. LVDS Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit be carried through two signal lines, so two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-11. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different. Along with LVDS I/O, SmartFusion cSoCs also support bus LVDS structure and multipoint LVDS (M-LVDS) configuration (up to 40 nodes). Bourns Part Number: CAT16-LV4F12 FPGA FPGA OUTBUF_LVDS P P 165 Ω Z = 50 Ω 0 INBUF_LVDS + 140 Ω 100 Ω – Z = 50 Ω 165 Ω 0 N N Figure 2-11 • LVDS Circuit Diagram and Board-Level Implementation 2-40 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Table 2-63 • LVDS Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Typ. Max. Units VCCFPGAIOBx Supply voltage 2.375 2.5 2.625 V VOL Output low voltage 0.9 1.075 1.25 V VOH Output high voltage 1.25 1.425 1.6 V 1 I Output lower current 0.65 0.91 1.16 mA OL 1 I Output high current 0.65 0.91 1.16 mA OH VI Input voltage 0 2.925 V 2 I Input high leakage current 15 µA IH 2 I Input low leakage current 15 µA IL V Differential output voltage 250 350 450 mV ODIFF V Output common mode voltage 1.125 1.25 1.375 V OCM V Input common mode voltage 0.05 1.25 2.35 V ICM V Input differential voltage 100 350 mV IDIFF Notes: 1. I /I defined by V /(resistor network). OL OH ODIFF 2. Currents are measured at 85°C junction temperature. Table 2-64 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) V (typ.) (V) REF 1.075 1.325 Cross point – * Measuring point = V See Table 2-22 on page 2-24 for a complete table of trip points. trip. Timing Characteristics Table 2-65 • LVDS Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCFPGAIOBx = 2.3 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Speed Grade t t t t Units DOUT DP DIN PY Std. 0.60 1.83 0.04 1.87 ns –1 0.50 1.53 0.03 1.55 ns Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Revision 8 2-41 SmartFusion DC and Switching Characteristics B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. SoC Products Group LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using SoC Products Group LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-12. The input and output buffer delays are available in the LVDS section in Table 2-65. Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required differential voltage, in worst-case commercial operating conditions, at the farthest receiver: R =60 Ω S and R =70 Ω, given Z =50 Ω (2") and Z =50 Ω (~1.5"). T 0 stub Receiver Transceiver Driver Receiver Transceiver EN EN D EN EN EN BIBUF_LVDS R T R T + - + - + - + - + - R R R R R R R R R R S S S S S S S S S S Z Z Z Z Z Z Z Z ... stub stub stub stub stub stub stub stub Z Z Z Z Z Z 0 0 0 0 0 0 R R T Z Z Z Z Z Z T 0 0 0 0 0 0 Figure 2-12 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers 2-42 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-13. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation because the output standard specifications are different. Bourns Part Number: CAT16-PC4F12 FPGA FPGA P P OUTBUF_LVPECL 100 Ω Z = 50 Ω 0 INBUF_LVPECL + 187 W 100 Ω – Z = 50 Ω 100 Ω 0 N N Figure 2-13 • LVPECL Circuit Diagram and Board-Level Implementation Table 2-66 • Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Max. Min. Max. Min. Max. Units VCCFPGAIOBx Supply Voltage 3.0 3.3 3.6 V VOL Output Low Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V VOH Output High Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V V , V Input Low, Input High Voltages 0 3.3 0 3.6 0 3.9 V IL IH V Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V ODIFF V Output Common-Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V OCM V Input Common-Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V ICM V Input Differential Voltage 300 300 300 mV IDIFF Table 2-67 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) V (typ.) (V) REF 1.64 1.94 Cross point – * Measuring point = V See Table 2-22 on page 2-24 for a complete table of trip points. trip. Timing Characteristics Table 2-68 • LVPECL Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V, J Worst-Case VCCFPGAIOBx = 3.0 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Speed Grade t t t t Units DOUT DP DIN PY Std. 0.60 1.76 0.04 1.76 ns –1 0.50 1.46 0.03 1.46 ns Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Revision 8 2-43 TRIBUF INBUF INBUF INBUF CLKBUF Pad Out SmartFusion DC and Switching Characteristics I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset L D DOUT Data_out PRE Y F PRE E Core Data DQ DQ Array C DFN1E1P1 G DFN1E1P1 E E Enable EOUT B H I CLK A PRE J DQ DFN1E1P1 K Data Input I/O Register with: E Active High Enable Active High Preset Positive-Edge Triggered Data Output Register and Enable Output Register with: Active High Enable Active High Preset CLKBUF INBUF INBUF Postive-Edge Triggered Figure 2-14 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset 2-44 Revision 8 CLK Enable D_Enable SmartFusion Customizable System-on-Chip (cSoC) Table 2-69 • Parameter Definition and Measuring Nodes Measuring Nodes Parameter Name Parameter Definition (from, to)* t Clock-to-Q of the Output Data Register H, DOUT OCLKQ t Data Setup Time for the Output Data Register F, H OSUD t Data Hold Time for the Output Data Register F, H OHD t Enable Setup Time for the Output Data Register G, H OSUE t Enable Hold Time for the Output Data Register G, H OHE t Asynchronous Preset-to-Q of the Output Data Register L, DOUT OPRE2Q t Asynchronous Preset Removal Time for the Output Data Register L, H OREMPRE t Asynchronous Preset Recovery Time for the Output Data Register L, H ORECPRE t Clock-to-Q of the Output Enable Register H, EOUT OECLKQ t Data Setup Time for the Output Enable Register J, H OESUD t Data Hold Time for the Output Enable Register J, H OEHD t Enable Setup Time for the Output Enable Register K, H OESUE t Enable Hold Time for the Output Enable Register K, H OEHE t Asynchronous Preset-to-Q of the Output Enable Register I, EOUT OEPRE2Q t Asynchronous Preset Removal Time for the Output Enable Register I, H OEREMPRE t Asynchronous Preset Recovery Time for the Output Enable Register I, H OERECPRE t Clock-to-Q of the Input Data Register A, E ICLKQ t Data Setup Time for the Input Data Register C, A ISUD t Data Hold Time for the Input Data Register C, A IHD t Enable Setup Time for the Input Data Register B, A ISUE t Enable Hold Time for the Input Data Register B, A IHE t Asynchronous Preset-to-Q of the Input Data Register D, E IPRE2Q t Asynchronous Preset Removal Time for the Input Data Register D, A IREMPRE t Asynchronous Preset Recovery Time for the Input Data Register D, A IRECPRE * See Figure 2-14 on page 2-44 for more information. Revision 8 2-45 TRIBUF INBUF INBUF INBUF CLKBUF Pad Out SmartFusion DC and Switching Characteristics Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear DOUT FF Data_out Y Core DQ DQ Data Array CC EE DFN1E1C1 DFN1E1C1 GG EOUT E E Enable BB CLR CLR LL HH CLK AA JJ DQ CLR DD DFN1E1C1 KK E Data Input I/O Register with CLR Active High Enable Active High Clear Positive-Edge Triggered Data Output Register and Enable Output Register with Active High Enable Active High Clear INBUF INBUF CLKBUF Positive-Edge Triggered Figure 2-15 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear 2-46 Revision 8 Enable D_Enable CLK SmartFusion Customizable System-on-Chip (cSoC) Table 2-70 • Parameter Definition and Measuring Nodes Measuring Nodes Parameter Name Parameter Definition (from, to)* t Clock-to-Q of the Output Data Register HH, DOUT OCLKQ t Data Setup Time for the Output Data Register FF, HH OSUD t Data Hold Time for the Output Data Register FF, HH OHD t Enable Setup Time for the Output Data Register GG, HH OSUE t Enable Hold Time for the Output Data Register GG, HH OHE t Asynchronous Clear-to-Q of the Output Data Register LL, DOUT OCLR2Q t Asynchronous Clear Removal Time for the Output Data Register LL, HH OREMCLR t Asynchronous Clear Recovery Time for the Output Data Register LL, HH ORECCLR t Clock-to-Q of the Output Enable Register HH, EOUT OECLKQ t Data Setup Time for the Output Enable Register JJ, HH OESUD t Data Hold Time for the Output Enable Register JJ, HH OEHD t Enable Setup Time for the Output Enable Register KK, HH OESUE t Enable Hold Time for the Output Enable Register KK, HH OEHE t Asynchronous Clear-to-Q of the Output Enable Register II, EOUT OECLR2Q t Asynchronous Clear Removal Time for the Output Enable Register II, HH OEREMCLR t Asynchronous Clear Recovery Time for the Output Enable Register II, HH OERECCLR t Clock-to-Q of the Input Data Register AA, EE ICLKQ t Data Setup Time for the Input Data Register CC, AA ISUD t Data Hold Time for the Input Data Register CC, AA IHD t Enable Setup Time for the Input Data Register BB, AA ISUE t Enable Hold Time for the Input Data Register BB, AA IHE t Asynchronous Clear-to-Q of the Input Data Register DD, EE ICLR2Q t Asynchronous Clear Removal Time for the Input Data Register DD, AA IREMCLR t Asynchronous Clear Recovery Time for the Input Data Register DD, AA IRECCLR * See Figure 2-15 on page 2-46 for more information. Revision 8 2-47 SmartFusion DC and Switching Characteristics Input Register t t ICKMPWH ICKMPWL 50% 50% 50% 50% 50% 50% 50% CLK t IHD t ISUD 1 50% 0 50% Data t t t Enable 50% IRECPRE IREMPRE IWPRE t IHE 50% 50% 50% t ISUE Preset t t t IWCLR IRECCLR IREMCLR 50% 50% 50% Clear t IPRE2Q 50% 50% 50% Out_1 t ICLR2Q t ICLKQ Figure 2-16 • Input Register Timing Diagram Timing Characteristics Table 2-71 • Input Data Register Propagation Delays Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V J Parameter Description –1 Std. Units t Clock-to-Q of the Input Data Register 0.24 0.29 ns ICLKQ t Data Setup Time for the Input Data Register 0.27 0.32 ns ISUD t Data Hold Time for the Input Data Register 0.00 0.00 ns IHD t Enable Setup Time for the Input Data Register 0.38 0.45 ns ISUE t Enable Hold Time for the Input Data Register 0.00 0.00 ns IHE t Asynchronous Clear-to-Q of the Input Data Register 0.46 0.55 ns ICLR2Q t Asynchronous Preset-to-Q of the Input Data Register 0.46 0.55 ns IPRE2Q t Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 ns IREMCLR t Asynchronous Clear Recovery Time for the Input Data Register 0.23 0.27 ns IRECCLR t Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 ns IREMPRE t Asynchronous Preset Recovery Time for the Input Data Register 0.23 0.27 ns IRECPRE t Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.22 ns IWCLR t Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.22 ns IWPRE t Clock Minimum Pulse Width High for the Input Data Register 0.36 0.36 ns ICKMPWH t Clock Minimum Pulse Width Low for the Input Data Register 0.32 0.32 ns ICKMPWL Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. 2-48 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Output Register t t OCKMPWH OCKMPWL 50% 50% 50% 50% 50% 50% 50% CLK t t OSUD OHD 1 50% 0 50% Data_out t Enable 50% OREMPRE t t OWPRE ORECPRE t OHE 50% 50% 50% t Preset OSUE t t OREMCLR t ORECCLR OWCLR 50% 50% 50% Clear t OPRE2Q 50% 50% 50% DOUT t OCLR2Q t OCLKQ Figure 2-17 • Output Register Timing Diagram Timing Characteristics Table 2-72 • Output Data Register Propagation Delays Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V J Parameter Description –1 Std. Units t Clock-to-Q of the Output Data Register 0.60 0.72 ns OCLKQ t Data Setup Time for the Output Data Register 0.32 0.38 ns OSUD t Data Hold Time for the Output Data Register 0.00 0.00 ns OHD t Enable Setup Time for the Output Data Register 0.44 0.53 ns OSUE t Enable Hold Time for the Output Data Register 0.00 0.00 ns OHE t Asynchronous Clear-to-Q of the Output Data Register 0.82 0.98 ns OCLR2Q t Asynchronous Preset-to-Q of the Output Data Register 0.82 0.98 ns OPRE2Q t Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 ns OREMCLR t Asynchronous Clear Recovery Time for the Output Data Register 0.23 0.27 ns ORECCLR t Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 ns OREMPRE t Asynchronous Preset Recovery Time for the Output Data Register 0.23 0.27 ns ORECPRE t Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.22 0.22 ns OWCLR t Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.22 0.22 ns OWPRE t Clock Minimum Pulse Width High for the Output Data Register 0.36 0.36 ns OCKMPWH t Clock Minimum Pulse Width Low for the Output Data Register 0.32 0.32 ns OCKMPWL Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Revision 8 2-49 SmartFusion DC and Switching Characteristics Output Enable Register t t OECKMPWH OECKMPWL 50% 50% 50% 50% 50% 50% 50% CLK t t OESUD OEHD 1 50% 0 50% D_Enable 50% Enable t t OEWPRE OEREMPRE t OERECPRE 50% 50% 50% t t OESUEOEHE Preset t t t OEREMCLR OEWCLR OERECCLR 50% 50% 50% Clear t t OECLR2Q OEPRE2Q 50% 50% 50% EOUT t OECLKQ Figure 2-18 • Output Enable Register Timing Diagram Timing Characteristics Table 2-73 • Output Enable Register Propagation Delays Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V J Parameter Description –1 Std. Units t Clock-to-Q of the Output Enable Register 0.45 0.54 ns OECLKQ t Data Setup Time for the Output Enable Register 0.32 0.38 ns OESUD t Data Hold Time for the Output Enable Register 0.00 0.00 ns OEHD t Enable Setup Time for the Output Enable Register 0.44 0.53 ns OESUE t Enable Hold Time for the Output Enable Register 0.00 0.00 ns OEHE t Asynchronous Clear-to-Q of the Output Enable Register 0.68 0.81 ns OECLR2Q t Asynchronous Preset-to-Q of the Output Enable Register 0.68 0.81 ns OEPRE2Q t Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 ns OEREMCLR t Asynchronous Clear Recovery Time for the Output Enable Register 0.23 0.27 ns OERECCLR t Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 ns OEREMPRE t Asynchronous Preset Recovery Time for the Output Enable Register 0.23 0.27 ns OERECPRE t Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.22 0.22 ns OEWCLR t Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.22 ns OEWPRE t Clock Minimum Pulse Width High for the Output Enable Register 0.36 0.36 ns OECKMPWH t Clock Minimum Pulse Width Low for the Output Enable Register 0.32 0.32 ns OECKMPWL Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. 2-50 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) DDR Module Specifications Input DDR Module Input DDR INBUF A D Out_QF Data (to core) FF1 B E Out_QR CLK (to core) CLKBUF FF2 C CLR INBUF DDR_IN Figure 2-19 • Input DDR Timing Model Table 2-74 • Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) t Clock-to-Out Out_QR B, D DDRICLKQ1 Clock-to-Out Out_QF B, E t DDRICLKQ2 t Data Setup Time of DDR input A, B DDRISUD t Data Hold Time of DDR input A, B DDRIHD Clear-to-Out Out_QR C, D t DDRICLR2Q1 t Clear-to-Out Out_QF C, E DDRICLR2Q2 t Clear Removal C, B DDRIREMCLR Clear Recovery C, B t DDRIRECCLR Revision 8 2-51 SmartFusion DC and Switching Characteristics CLK t t DDRISUD DDRIHD Data 12 3 4 5 6 7 8 9 t DDRIRECCLR CLR t DDRIREMCLR t DDRICLKQ1 t DDRICLR2Q1 Out_QF 2 4 6 t DDRICLKQ2 t DDRICLR2Q2 Out_QR 7 3 5 Figure 2-20 • Input DDR Timing Diagram Timing Characteristics Table 2-75 • Input DDR Propagation Delays Worst Commercial-Case Conditions: T = 85°C, Worst Case VCC = 1.425 V J Parameter Description –1 Units t Clock-to-Out Out_QR for Input DDR 0.39 ns DDRICLKQ1 t Clock-to-Out Out_QF for Input DDR 0.28 ns DDRICLKQ2 t Data Setup for Input DDR 0.29 ns DDRISUD t Data Hold for Input DDR 0.00 ns DDRIHD t Asynchronous Clear-to-Out Out_QR for Input DDR 0.58 ns DDRICLR2Q1 t Asynchronous Clear-to-Out Out_QF for Input DDR 0.47 ns DDRICLR2Q2 t Asynchronous Clear Removal time for Input DDR 0.00 ns DDRIREMCLR t Asynchronous Clear Recovery time for Input DDR 0.23 ns DDRIRECCLR t Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 ns DDRIWCLR t Clock Minimum Pulse Width High for Input DDR 0.36 ns DDRICKMPWH t Clock Minimum Pulse Width Low for Input DDR 0.32 ns DDRICKMPWL F Maximum Frequency for Input DDR 350 MHz DDRIMAX Note: For derating values at specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9 for derating values. 2-52 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Output DDR Module Output DDR A Data_F X (from core) FF1 Out B 0 CLK X E CLKBUF C X X OUTBUF D 1 Data_R X (from core) FF2 B X CLR INBUF C X DDR_OUT Figure 2-21 • Output DDR Timing Model Table 2-76 • Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tClock-to-Out B, E DDROCLKQ t Asynchronous Clear-to-Out C, E DDROCLR2Q t Clear Removal C, B DDROREMCLR t Clear Recovery C, B DDRORECCLR t Data Setup Data_F A, B DDROSUD1 t Data Setup Data_R D, B DDROSUD2 t Data Hold Data_F A, B DDROHD1 t Data Hold Data_R D, B DDROHD2 Revision 8 2-53 SmartFusion DC and Switching Characteristics CLK t t DDROHD2 DDROSUD2 45 Data_F 1 2 3 t t DDROHD1 DDROREMCLR Data_R 6 7 8 910 11 t DDRORECCLR t CLR DDROREMCLR t t DDROCLKQ DDROCLR2Q Out 71 28 3 9 40 Figure 2-22 • Output DDR Timing Diagram Timing Characteristics Table 2-77 • Output DDR Propagation Delays Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V J Parameter Description –1 Units t Clock-to-Out of DDR for Output DDR 0.71 ns DDROCLKQ t Data_F Data Setup for Output DDR 0.38 ns DDROSUD1 t Data_R Data Setup for Output DDR 0.38 ns DDROSUD2 t Data_F Data Hold for Output DDR 0.00 ns DDROHD1 t Data_R Data Hold for Output DDR 0.00 ns DDROHD2 t Asynchronous Clear-to-Out for Output DDR 0.81 ns DDROCLR2Q t Asynchronous Clear Removal Time for Output DDR 0.00 ns DDROREMCLR t Asynchronous Clear Recovery Time for Output DDR 0.23 ns DDRORECCLR t Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 ns DDROWCLR1 t Clock Minimum Pulse Width High for the Output DDR 0.36 ns DDROCKMPWH t Clock Minimum Pulse Width Low for the Output DDR 0.32 ns DDROCKMPWL F Maximum Frequency for the Output DDR 350 MHz DDOMAX Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. 2-54 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The SmartFusion library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the IGLOO/e, Fusion, ProASIC3/E, and SmartFusion Macro Library Guide. AY INV A A Y NOR2 OR2 Y B B A A AND2 Y Y NAND2 B B A A Y B XOR3 XOR2 Y B C A A MAJ3 0 Y A MUX2 BY B B NAND3 1 C C S Figure 2-23 • Sample of Combinatorial Cells Revision 8 2-55 SmartFusion DC and Switching Characteristics t PD A NAND2 or Y Any Combinatorial Logic B t = MAX(t , t , PD PD(RR) PD(RF) t , t ) where edges are PD(FF) PD(FR) applicable for the particular combinatorial cell VCC 50% 50% A, B, C GND VCC 50% 50% OUT GND t t PD PD (FF) (RR) VCC t PD OUT (FR) 50% 50% t PD GND (RF) Figure 2-24 • Timing Model and Waveforms 2-56 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Timing Characteristics Table 2-78 • Combinatorial Cell Propagation Delays Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V J Combinatorial Cell Equation Parameter –1 Std. Units INV Y = !A t 0.41 0.49 ns PD AND2 Y = A · B t 0.48 0.57 ns PD NAND2 Y = !(A · B) t 0.48 0.57 ns PD OR2 Y = A + B t 0.49 0.59 ns PD NOR2 Y = !(A + B) t 0.49 0.59 ns PD XOR2 Y = A ⊕ Bt 0.75 0.90 ns PD MAJ3 Y = MAJ(A, B, C) t 0.71 0.85 ns PD XOR3 Y = A ⊕ B ⊕ Ct 0.89 1.07 ns PD MUX2 Y = A !S + B S t 0.51 0.62 ns PD AND3 Y = A · B · C t 0.57 0.68 ns PD Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. VersaTile Specifications as a Sequential Module The SmartFusion library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the IGLOO/e, Fusion, ProASIC3/E, and SmartFusion Macro Library Guide. Data Out Data Out DQ D Q En DFN1 DFN1E1 CLK CLK PRE Data Out Data Out Q D DQ En DFN1C1 DFI1E1P1 CLK CLK CLR Figure 2-25 • Sample of Sequential Cells Revision 8 2-57 SmartFusion DC and Switching Characteristics t t CKMPWH CKMPWL 50% 50% 50% 50% 50% 50% 50% CLK t HD t SUD 50% 50% Data 0 EN 50% t t WPRE RECPRE t REMPRE t HE 50% 50% 50% t PRE SUE t t t REMCLR RECCLR WCLR 50% 50% 50% CLR t PRE2Q t CLR2Q 50% 50% 50% Out t CLKQ Figure 2-26 • Timing Model and Waveforms Timing Characteristics Table 2-79 • Register Delays Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V J Parameter Description –1 Std. Units t Clock-to-Q of the Core Register 0.56 0.67 ns CLKQ t Data Setup Time for the Core Register 0.44 0.52 ns SUD t Data Hold Time for the Core Register 0.00 0.00 ns HD t Enable Setup Time for the Core Register 0.46 0.55 ns SUE t Enable Hold Time for the Core Register 0.00 0.00 ns HE t Asynchronous Clear-to-Q of the Core Register 0.41 0.49 ns CLR2Q t Asynchronous Preset-to-Q of the Core Register 0.41 0.49 ns PRE2Q t Asynchronous Clear Removal Time for the Core Register 0.00 0.00 ns REMCLR t Asynchronous Clear Recovery Time for the Core Register 0.23 0.27 ns RECCLR t Asynchronous Preset Removal Time for the Core Register 0.00 0.00 ns REMPRE t Asynchronous Preset Recovery Time for the Core Register 0.23 0.27 ns RECPRE t Asynchronous Clear Minimum Pulse Width for the Core Register 0.22 0.22 ns WCLR t Asynchronous Preset Minimum Pulse Width for the Core Register 0.22 0.22 ns WPRE t Clock Minimum Pulse Width High for the Core Register 0.32 0.32 ns CKMPWH t Clock Minimum Pulse Width Low for the Core Register 0.36 0.36 ns CKMPWL Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. 2-58 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Global Resource Characteristics A2F200 Clock Tree Topology Clock delays are device-specific. Figure 2-27 is an example of a global tree used for clock routing. The global tree presented in Figure 2-27 is driven by a CCC located on the west side of the A2F200 device. It is used to drive all D-flip-flops in the device. Central Global Rib CCC VersaTile Rows Global Spine Figure 2-27 • Example of Global Tree Use in an A2F200 Device for Clock Routing Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-63. Table 2-80 through Table 2-82 on page 2-61 present minimum and maximum global clock delays for the SmartFusion cSoCs. Minimum and maximum delays are measured with minimum and maximum loading. Revision 8 2-59 SmartFusion DC and Switching Characteristics Timing Characteristics Table 2-80 • A2F500 Global Resource Worst Commercial-Case Conditions: T = 85°C, VCC = 1.425 V J –1 Std. 1 2 1 2 Parameter Description Min. Max. Min. Max. Units t Input Low Delay for Global Clock 1.54 1.73 1.84 2.08 ns RCKL t Input High Delay for Global Clock 1.53 1.76 1.84 2.12 ns RCKH t Minimum Pulse Width High for Global Clock ns RCKMPWH t Minimum Pulse Width Low for Global Clock ns RCKMPWL t Maximum Skew for Global Clock 0.23 0.28 ns RCKSW F Maximum Frequency for Global Clock MHz RMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9 for derating values. Table 2-81 • A2F200 Global Resource Worst Commercial-Case Conditions: T = 85°C, VCC = 1.425 V J –1 Std. 1 2 1 2 Parameter Description Min. Max. Min. Max. Units t Input Low Delay for Global Clock 0.74 0.99 0.88 1.19 ns RCKL t Input High Delay for Global Clock 0.76 1.05 0.91 1.26 ns RCKH t Minimum Pulse Width High for Global Clock ns RCKMPWH t Minimum Pulse Width Low for Global Clock ns RCKMPWL t Maximum Skew for Global Clock 0.29 0.35 ns RCKSW F Maximum Frequency for Global Clock MHz RMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9 for derating values. 2-60 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Table 2-82 • A2F060 Global Resource Worst Commercial-Case Conditions: T = 85°C, VCC = 1.425 V J –1 Std. 1 2 1 2 Parameter Description Min. Max. Min. Max. Units t Input Low Delay for Global Clock 0.75 0.96 0.90 1.15 ns RCKL t Input High Delay for Global Clock 0.72 0.98 0.86 1.17 ns RCKH t Minimum Pulse Width High for Global Clock ns RCKMPWH t Minimum Pulse Width Low for Global Clock ns RCKMPWL t Maximum Skew for Global Clock 0.26 0.31 ns RCKSW F Maximum Frequency for Global Clock MHz RMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9 for derating values. RC Oscillator The table below describes the electrical characteristics of the RC oscillator. RC Oscillator Characteristics Table 2-83 • Electrical Characteristics of the RC Oscillator Parameter Description Condition Min. Typ. Max. Units FRC Operating 100 MHz frequency Accuracy Temperature: 0°C to 85°C 1 % Voltage: 3.3 V ± 5% Output jitter Period jitter (at 5 K cycles) 100 ps Cycle-to-cycle jitter (at 5 K cycles) 100 ps Period jitter (at 5 K cycles) with 1 KHz / 300 150 ps mV peak-to-peak noise on power supply Cycle-to-cycle jitter (at 5 K cycles) with 1 KHz 150 ps / 300 mV peak-to-peak noise on power supply Output duty cycle 50 % IDYNRC Operating current 3.3 V domain 1 mA 1.5 V domain 2 mA Revision 8 2-61 SmartFusion DC and Switching Characteristics Main and Lower Power Crystal Oscillator The tables below describes the electrical characteristics of the main and low power crystal oscillator. Table 2-84 • Electrical Characteristics of the Main Crystal Oscillator Parameter Description Condition Min. Typ. Max. Units Operating frequency Using external crystal 0.032 20 MHz Using ceramic resonator 0.5 8 MHz Using RC Network 0.032 4 MHz Output duty cycle 50 % Output jitter With 10 MHz crystal 50 ps RMS IDYNXTAL Operating current RC 0.6 mA 0.032–0.2 0.6 mA 0.2–2.0 0.6 mA 2.0–20.0 0.6 mA ISTBXTAL Standby current of crystal oscillator 10 µA PSRRXTAL Power supply noise tolerance 0.5 Vp-p VIHXTAL Input logic level High 90% V of VCC VILXTAL Input logic level Low 10% V of VCC Startup time RC µs 0.032–0.2 µs 0.2–2.0 µs 2.0–20.0 µs Table 2-85 • Electrical Characteristics of the Low Power Oscillator Parameter Description Condition Min. Typ. Max. Units Operating frequency 32 KHz Output duty cycle 50 % Output jitter 50 ps RMS IDYNXTAL Operating current 32 KHz 10 µA ISTBXTAL Standby current of crystal oscillator µA Power supply noise tolerance 0.5 Vp-p PSRRXTAL VIHXTAL Input logic level High 90% of VCC V VILXTAL Input logic level Low 10% of VCC V Startup time Test load used: 20 pF 2.5 s 2-62 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-86 • SmartFusion CCC/PLL Specification Parameter Minimum Typical Maximum Units Clock Conditioning Circuitry Input Frequency f 1.5 350 MHz IN_CCC 1 Clock Conditioning Circuitry Output Frequency f 0.75 350 MHz OUT_CCC 2, 3 Delay Increments in Programmable Delay Blocks 160 ps Number of Programmable Values in Each 32 Programmable Delay Block Input Period Jitter 1.5 ns Acquisition Time LockControl = 0 300 µs LockControl = 1 6.0 ms 4 Tracking Jitter LockControl = 0 1.6 ns LockControl = 1 0.8 ns Output Duty Cycle 48.5 5.15 % 2,3 Delay Range in Block: Programmable Delay 1 0.6 5.56 ns 2,3 Delay Range in Block: Programmable Delay 2 0.025 5.56 ns 2,3 Delay Range in Block: Fixed Delay 2.2 ns 5,6 CCC Output Peak-to-Peak Period Jitter F Maximum Peak-to-Peak Period Jitter CCC_OUT SSO ≤ 2 SSO ≤ 4 SSO ≤ 8 SSO ≤ 16 FG/CS PQ FG/CS PQ FG/CS PQ FG/CS PQ 0.75 MHz to 50 MHz 0.5% 1.6% 0.9% 1.6% 0.9% 1.6% 0.9% 1.8% 50 MHz to 250 MHz 1.75% 3.5% 9.3% 9.3% 9.3% 17.9% 10.0% 17.9% 250 MHz to 350 MHz 2.5% 5.2% 13.0% 13.0% 13.0% 25.0% 14.0% 25.0% Notes: 1. One of the CCC outputs (GLA0) is used as an MSS clock and is limited to 100 MHz (maximum) by software. Details regarding CCC/PLL are in the "PLLs, Clock Conditioning Circuitry, and On-Chip Crystal Oscillators" chapter of the SmartFusion Microcontroller Subsystem User's Guide. 2. This delay is a function of voltage and temperature. See Table 2-7 on page 2-9 for deratings. 3. T = 25°C, VCC = 1.5 V J 4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. 5. Measurement done with LVTTL 3.3V 12mA I/O drive strength and High slew rate. VCC/VCCPLL = 1.425V, VCCI = 3.3V, 20 pF output load. All I/Os are placed outside of the PLL bank. 6. SSOs are outputs that are synchronous to a single clock domain and have their clock-to-out within ± 200 ps of each other. 7. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps. Revision 8 2-63 SmartFusion DC and Switching Characteristics Output Signal T T period_max period_min Note: Peak-to-peak jitter measurements are defined by T = T – T . peak-to-peak period_max period_min Figure 2-28 • Peak-to-Peak Jitter Definition 2-64 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) FPGA Fabric SRAM and FIFO Characteristics FPGA Fabric SRAM RAM4K9 RAM512X18 RADDR8 RD17 ADDRA11 DOUTA8 RADDR7 RD16 ADDRA10 DOUTA7 ADDRA0 DOUTA0 RADDR0 RD0 DINA8 DINA7 RW1 DINA0 RW0 WIDTHA1 WIDTHA0 PIPE PIPEA WMODEA BLKA REN WENA RCLK CLKA ADDRB11 DOUTB8 WADDR8 ADDRB10 DOUTB7 WADDR7 ADDRB0 DOUTB0 WADDR0 WD17 WD16 DINB8 DINB7 WD0 DINB0 WW1 WIDTHB1 WW0 WIDTHB0 PIPEB WMODEB BLKB WEN WENB CLKB WCLK RESET RESET Figure 2-29 • RAM Models Revision 8 2-65 SmartFusion DC and Switching Characteristics Timing Waveforms t CYC t t CKH CKL CLK t t AS AH A A A [R|W]ADDR 0 1 2 t BKS t BKH BLK t t ENS ENH WEN t CKQ1 D D D D DOUT|RD n 0 1 2 t DOH1 Figure 2-30 • RAM Read for Pass-Through Output. Applicable to both RAM4K9 and RAM512x18. t CYC t t CKH CKL CLK t t AH AS A A A [R|W]ADDR 0 1 2 t BKS t BKH BLK t t ENS ENH WEN t CKQ2 D DOUT|RD D D n 0 1 t DOH2 Figure 2-31 • RAM Read for Pipelined Output Applicable to both RAM4K9 and RAM512x18. 2-66 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) t CYC t t CKH CKL CLK t t AS AH A A A [R|W]ADDR 0 1 2 t BKS t BKH BLK t t ENS ENH WEN t t DS DH DI DI DIN|WD 0 1 D D DOUT|RD n 2 Figure 2-32 • RAM Write, Output Retained. Applicable to both RAM4K9 and RAM512x18. t CYC t t CKH CKL CLK t t AS AH A A A ADDR 0 1 2 t BKS t BKH BLK t ENS WEN t t DS DH DI DI DI DIN 0 1 2 DOUT D DI DI n 0 1 (pass-through) DOUT D DI DI n 0 1 (pipelined) Figure 2-33 • RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 only. Revision 8 2-67 SmartFusion DC and Switching Characteristics t CYC t t CKH CKL CLK RESET t RSTBQ D DOUT|RD D m n Figure 2-34 • RAM Reset. Applicable to both RAM4K9 and RAM512x18. 2-68 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Timing Characteristics Table 2-87 • RAM4K9 Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V J Parameter Description –1 Std. Units t Address setup time 0.25 0.30 ns AS t Address hold time 0.00 0.00 ns AH t REN, WEN setup time 0.15 0.17 ns ENS t REN, WEN hold time 0.10 0.12 ns ENH t BLK setup time 0.24 0.28 ns BKS t BLK hold time 0.02 0.02 ns BKH t Input data (DIN) setup time 0.19 0.22 ns DS t Input data (DIN) hold time 0.00 0.00 ns DH t Clock High to new data valid on DOUT (output retained, WMODE = 0) 1.81 2.18 ns CKQ1 Clock High to new data valid on DOUT (flow-through, WMODE = 1) 2.39 2.87 ns t Clock High to new data valid on DOUT (pipelined) 0.91 1.09 ns CKQ2 1 t Address collision clk-to-clk delay for reliable write after write on same 0.30 0.35 ns C2CWWH address—applicable to rising edge 1 t Address collision clk-to-clk delay for reliable read access after write on same 0.45 0.52 ns C2CRWH address—applicable to opening edge 1 t Address collision clk-to-clk delay for reliable write access after read on same 0.49 0.57 ns C2CWRH address— applicable to opening edge t RESET Low to data out Low on DOUT (flow-through) 0.941.12ns RSTBQ RESET Low to Data Out Low on DOUT (pipelined) 0.941.12ns t RESET removal 0.29 0.35 ns REMRSTB t RESET recovery 1.52 1.83 ns RECRSTB t RESET minimum pulse width 0.22 0.22 ns MPWRSTB t Clock cycle time 3.28 3.28 ns CYC F Maximum clock frequency 305 305 MHz MAX Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Revision 8 2-69 SmartFusion DC and Switching Characteristics Table 2-88 • RAM512X18 Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V J Parameter Description –1 Std. Units t Address setup time 0.25 0.30 ns AS t Address hold time 0.00 0.00 ns AH t REN, WEN setup time 0.09 0.11 ns ENS t REN, WEN hold time 0.06 0.07 ns ENH t Input data (WD) setup time 0.19 0.22 ns DS t Input data (WD) hold time 0.00 0.00 ns DH t Clock High to new data valid on RD (output retained, WMODE = 0) 2.19 2.63 ns CKQ1 t Clock High to new data valid on RD (pipelined) 0.91 1.09 ns CKQ2 1 t Address collision clk-to-clk delay for reliable read access after write on same 0.50 0.58 ns C2CRWH address—applicable to opening edge 1 t Address collision clk-to-clk delay for reliable write access after read on same 0.59 0.67 ns C2CWRH address—applicable to opening edge t RESET Low to data out Low on RD (flow-through) 0.941.12ns RSTBQ RESET Low to data out Low on RD (pipelined) 0.941.12ns t RESET removal 0.29 0.35 ns REMRSTB t RESET recovery 1.52 1.83 ns RECRSTB t RESET minimum pulse width 0.22 0.22 ns MPWRSTB t Clock cycle time 3.28 3.28 ns CYC F Maximum clock frequency 305 305 MHz MAX Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. 2-70 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) FIFO FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 RD0 WW0 ESTOP FULL FSTOP AFULL EMPTY AEVAL11 AEMPTY AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE RESET Figure 2-35 • FIFO Model Revision 8 2-71 SmartFusion DC and Switching Characteristics Timing Waveforms RCLK/ WCLK t t MPWRSTB RSTCK RESET t RSTFG EMPTY t RSTAF AEMPTY t RSTFG FULL t RSTAF AFULL WA/RA (Address Counter) MATCH (A ) 0 Figure 2-36 • FIFO Reset t CYC RCLK t RCKEF EMPTY t CKAF AEMPTY WA/RA NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY) (Address Counter) Figure 2-37 • FIFO EMPTY Flag and AEMPTY Flag Assertion 2-72 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) t CYC WCLK t WCKFF FULL t CKAF AFULL WA/RA NO MATCH NO MATCH Dist = AFF_TH MATCH (FULL) (Address Counter) Figure 2-38 • FIFO FULL Flag and AFULL Flag Assertion WCLK MATCH WA/RA NO MATCH NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1 (Address Counter) (EMPTY) 1st Rising 2nd Rising Edge Edge After 1st After 1st Write Write RCLK t RCKEF EMPTY t CKAF AEMPTY Figure 2-39 • FIFO EMPTY Flag and AEMPTY Flag Deassertion RCLK WA/RA MATCH (FULL) NO MATCH NO MATCH Dist = AFF_TH – 1 NO MATCH NO MATCH (Address Counter) 1st Rising 1st Rising Edge Edge After 1st After 2nd WCLK Read Read t WCKF FULL t CKAF AFULL Figure 2-40 • FIFO FULL Flag and AFULL Flag Deassertion Revision 8 2-73 SmartFusion DC and Switching Characteristics Timing Characteristics Table 2-89 • FIFO Worst Commercial-Case Conditions: T = 85°C, VCC = 1.425 V J Parameter Description –1 Std. Units t REN, WEN Setup Time 1.40 1.68 ns ENS t REN, WEN Hold Time 0.02 0.02 ns ENH t BLK Setup Time 0.19 0.19 ns BKS t BLK Hold Time 0.00 0.00 ns BKH t Input Data (WD) Setup Time 0.19 0.22 ns DS t Input Data (WD) Hold Time 0.00 0.00 ns DH t Clock High to New Data Valid on RD (flow-through) 2.39 2.87 ns CKQ1 t Clock High to New Data Valid on RD (pipelined) 0.91 1.09 ns CKQ2 t RCLK High to Empty Flag Valid 1.74 2.09 ns RCKEF t WCLK High to Full Flag Valid 1.66 1.99 ns WCKFF t Clock HIGH to Almost Empty/Full Flag Valid 6.29 7.54 ns CKAF t RESET Low to Empty/Full Flag Valid 1.72 2.06 ns RSTFG t RESET Low to Almost Empty/Full Flag Valid 6.22 7.47 ns RSTAF t RESET Low to Data Out Low on RD (flow-through) 0.94 1.12 ns RSTBQ RESET Low to Data Out Low on RD (pipelined) 0.94 1.12 ns t RESET Removal 0.29 0.35 ns REMRSTB t RESET Recovery 1.52 1.83 ns RECRSTB t RESET Minimum Pulse Width 0.22 0.22 ns MPWRSTB t Clock Cycle Time 3.28 3.28 ns CYC F Maximum Frequency for FIFO 305 305 MHz MAX Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Embedded Nonvolatile Memory Block (eNVM) Electrical Characteristics Table 2-90 describes the eNVM maximum performance. Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: T = 85°C, VCC = 1.425 V J A2F060 A2F200 A2F500 Parameter Description –1 Std. –1 Std. –1 Std. Units t Maximum frequency for clock for the control logic – 5 80 80 80 80 50 50 MHz FMAXCLKeNVM cycles (5:1:1:1*) t Maximum frequency for clock for the control logic – 6 100 80 100 80 100 80 MHz FMAXCLKeNVM cycles (6:1:1:1*) Note: *6:1:1:1 indicates 6 cycles for the first access and 1 each for the next three accesses. 5:1:1:1 indicates 5 cycles for the first access and 1 each for the next three accesses. 2-74 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Embedded FlashROM (eFROM) Electrical Characteristics Table 2-91 describes the eFROM maximum performance Table 2-91 • FlashROM Access Time, Worse Commercial Case Conditions: T = 85°C, VCC = 1.425 V J Parameter Description –1 Std. Units t Clock to out per configuration* 28.68 32.98 ns CK2Q F Maximum Clock frequency 15.00 15.00 MHz max JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-19 for more details. Timing Characteristics Table 2-92 • JTAG 1532 Worst Commercial-Case Conditions: T = 85°C, Worst-Case VCC = 1.425 V J Parameter Description –1 Std. Units t Test Data Input Setup Time 0.67 0.77 ns DISU t Test Data Input Hold Time 1.33 1.53 ns DIHD t Test Mode Select Setup Time 0.67 0.77 ns TMSSU t Test Mode Select Hold Time 1.33 1.53 ns TMDHD t Clock to Q (data out) 8.00 9.20 ns TCK2Q t Reset to Q (data out) 26.67 30.67 ns RSTB2Q F TCK Maximum Frequency 19.00 21.85 MHz TCKMAX t ResetB Removal Time 0.00 0.00 ns TRSTREM t ResetB Recovery Time 0.27 0.31 ns TRSTREC t ResetB Minimum Pulse TBD TBD ns TRSTMPW Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Revision 8 2-75 SmartFusion DC and Switching Characteristics Programmable Analog Specifications Current Monitor Unless otherwise noted, current monitor performance is specified at 25°C with nominal power supply voltages, with the output measured using the internal voltage reference with the internal ADC in 12-bit mode and 91 Ksps, after digital compensation. All results are based on averaging over 16 samples. Table 2-93 • Current Monitor Performance Specification Specification Test Conditions Min. Typical Max. Units Input voltage range (for driving ADC 0 – 48 0 – 50 1 – 51 mV over full range) Analog gain From the differential voltage across the 50 V/V input pads to the ADC input Input referred offset voltage Input referred offset voltage 0 0.1 0.5 mV –40ºC to +100ºC 0 0.1 0.5 mV Gain error Slope of BFSL vs. 50 V/V ±0.1 ±0.5 % nom. –40ºC to +100ºC ±0.5 % nom. Overall Accuracy Peak error from ideal transfer function, ±(0.1 + ±(0.4 + mV plus 25°C 0.25%) 1.5%) % reading Input referred noise 0 VDC input (no output averaging) 0.3 0.4 0.5 mVrms Common-mode rejection ratio 0 V to 12 VDC common-mode voltage –86 –87 dB Analog settling time To 0.1% of final value (with ADC load) From CM_STB (High) 5 µs From ADC_START (High) 5 200 µs Input capacitance 8pF Input biased current CM[n] or TM[n] pad, –40°C to +100°C over maximum input voltage range (plus is into pad) Strobe = 0; IBIAS on CM[n] 0 µA Strobe = 1; IBIAS on CM[n] 1 µA Strobe = 0; IBIAS on TM[n] 2 µA Strobe = 1; IBIAS on TM[n] 1 µA Power supply rejection ratio DC (0 – 10 KHz) 41 42 dB Incremental operational current VCC33A 150 µA monitor power supply current VCC33AP 140 µA requirements (per current monitor VCC15A 50 µA instance, not including ADC or VAREFx) Note: Under no condition should the TM pad ever be greater than 10 mV above the CM pad. This restriction is applicable only if current monitor is used. 2-76 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Temperature Monitor Unless otherwise noted, temperature monitor performance is specified with a 2N3904 diode-connected bipolar transistor from National Semiconductor or Infineon Technologies, nominal power supply voltages, with the output measured using the internal voltage reference with the internal ADC in 12-bit mode and 62.5 Ksps. After digital compensation. Unless otherwise noted, the specifications pertain to conditions where the SmartFusion cSoC and the sensing diode are at the same temperature. Table 2-94 • Temperature Monitor Performance Specifications Specification Test Conditions Min. Typical Max. Units Input diode temperature range –55 150 °C 233.2 378.15 K Temperature sensitivity 2.5 mV/K Intercept Extrapolated to 0K 0 V Input referred temperature offset At 25°C (298.15K) ±1 1.5 °C error Gain error Slope of BFSL vs. 2.5 mV/K ±1 2.5 % nom. Overall accuracy Peak error from ideal transfer function ±2 ±3 °C Input referred noise At 25°C (298.15K) – no output averaging 4 °C rms Output current Idle mode 100 µA Final measurement phases 10 µA Analog settling time Measured to 0.1% of final value, (with ADC load) From TM_STB (High) 5 µs From ADC_START (High) 5 105 µs AT parasitic capacitance 500 pF Power supply rejection ratio DC (0–10 KHz) 1.2 0.7 °C/V Input referred temperature Variation due to device temperature 0.005 0.008 °C/°C sensitivity error (–40°C to +100°C). External temperature sensor held constant. Temperature monitor (TM) VCC33A 200 µA operational power supply current VCC33AP 150 µA requirements (per temperature monitor instance, not including ADC VCC15A 50 µA or VAREFx) Note: All results are based on averaging over 64 samples. Revision 8 2-77 SmartFusion DC and Switching Characteristics 1 0 -1 -2 -3 -4 -5 -6 -7 1.00E -06 1.00E -05 1.00E -04 1.00E -03 1.00E -02 1.00E -01 1.00E+00 Capacitance (μF) Figure 2-41 • Temperature Error Versus External Capacitance 2-78 Revision 8 Temperature Error (°C) SmartFusion Customizable System-on-Chip (cSoC) Analog-to-Digital Converter (ADC) Unless otherwise noted, ADC direct input performance is specified at 25°C with nominal power supply voltages, with the output measured using the external voltage reference with the internal ADC in 12-bit mode and 500 KHz sampling frequency, after trimming and digital compensation. Table 2-95 • ADC Specifications Specification Test Conditions Min. Typ. Max. Units Input voltage range (for driving ADC 2.56 V over its full range) Gain error ±0.4 ±0.7 % –40ºC to +100ºC ±0.4 ±0.7 % Input referred offset voltage ±1 ±2 mV –40ºC to +100ºC ±1 ±2 Integral non-linearity (INL) RMS deviation from BFSL 12-bit mode 1.71 LSB 10-bit mode 0.60 1.00 LSB 8-bit mode 0.2 0.33 LSB Differential non-linearity (DNL) 12-bit mode 2.4 LSB 10-bit mode 0.80 0.94 LSB 8-bit mode 0.2 0.23 LSB Signal to noise ratio 62 64 dB Effective number of bits (ENOB) –1 dBFS input 12-bit mode 10 KHz 9.9 10 Bits SINAD – 1.76 dB --------------------------------------------- ENOB = 6.02 dB/bit 12-bit mode 100 KHz 9.9 10 Bits EQ 10 10-bit mode 10 KHz 9.5 9.6 Bits 10-bit mode 100 KHz 9.5 9.6 Bits 8-bit mode 10 KHz 7.8 7.9 Bits 8-bit mode 100 KHz 7.8 7.9 Bits Full power bandwidth At –3 dB; –1 dBFS input 300 KHz Analog settling time To 0.1% of final value (with 1 Kohm source 2µs impedance and with ADC load) Input capacitance Switched capacitance (ADC sample 12 15 pF capacitor) Cs: Static capacitance (Figure 2-42 on page 2-80) CM[n] input 5 7 pF TM[n] input 5 7 pF ADC[n] input 5 7 pF Input resistance Rin: Series resistance (Figure 2-42)2 KΩ Rsh: Shunt resistance, exclusive of 10 MΩ switched capacitance effects (Figure 2-42) Note: All 3.3 V supplies are tied together and varied from 3.0 V to 3.6 V. 1.5 V supplies are held constant. Revision 8 2-79 SmartFusion DC and Switching Characteristics Table 2-95 • ADC Specifications (continued) Specification Test Conditions Min. Typ. Max. Units Input leakage current –40°C to +100°C 1 µA Power supply rejection ratio DC 44 53 dB ADC power supply operational current VCC33ADCx 2.5 mA requirements VCC15A 2 mA Note: All 3.3 V supplies are tied together and varied from 3.0 V to 3.6 V. 1.5 V supplies are held constant. Rin Cst Csw Rsh Figure 2-42 • ADC Input Model Table 2-96 • VAREF Stabilization Time Required Settling Time for 8-Bit and Required Settling Time for 12-Bit VAREF Capacitor Value (µF) 10-Bit Mode (ms) Mode (ms) 0.01 1 1 0.1 3 4 0.2 6 8 0.3 10 11 0.5 17 20 0.7 18 21 132 37 2.2 62 73 3.3 99 117 10 275 325 22 635 751 47 1318 1557 2-80 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Analog Bipolar Prescaler (ABPS) With the ABPS set to its high range setting (GDEC = 00), a hypothetical input voltage in the range –15.36 V to +15.36 V is scaled and offset by the ABPS input amplifier to match the ADC full range of 0 V to 2.56 V using a nominal gain of –0.08333 V/V. However, due to reliability considerations, the voltage applied to the ABPS input should never be outside the range of –11.5 V to +14.4 V, restricting the usable ADC input voltage to 2.238 V to 0.080 V and the corresponding 12-bit output codes to the range of 3581 to 128 (decimal), respectively. Unless otherwise noted, ABPS performance is specified at 25°C with nominal power supply voltages, with the output measured using the internal voltage reference with the internal ADC in 12-bit mode and 100 KHz sampling frequency, after trimming and digital compensation; and applies to all ranges. Table 2-97 • ABPS Performance Specifications Specification Test Conditions Min. Typ. Max. Units Input voltage range (for driving ADC GDEC[1:0] = 11 ±2.56 V over its full range) GDEC[1:0] = 10 ±5.12 V GDEC[1:0] = 01 ±10.24 V GDEC[1:0] = 00 (limited by See note 1 V maximum rating) Analog gain (from input pad to ADC GDEC[1:0] = 11 –0.5 V/V input) GDEC[1:0] = 10 –0.25 V/V GDEC[1:0] = 01 –0.125 V/V GDEC[1:0] = 00 –0.0833 V/V Gain error –2.8 –0.4 0.7 % –40ºC to +100ºC –2.8 –0.4 0.7 % Input referred offset voltage GDEC[1:0] = 11 –0.31 –0.07 0.31 % FS* –40ºC to +100ºC –1.00 1.47 % FS* GDEC[1:0] = 10 –0.34 –0.07 0.34 % FS* –40ºC to +100ºC –0.90 1.37 % FS* GDEC[1:0] = 01 –0.61 –0.07 0.35 % FS* –40ºC to +100ºC –1.05 1.35 % FS* GDEC[1:0] = 00 –0.39 –0.07 0.35 % FS* –40ºC to +100ºC –1.06 1.38 % FS* SINAD 53 56 dB Non-linearity RMS deviation from BFSL 0.5 % FS* Note: *FS is full-scale error, defined as the difference between the actual value that triggers the transition to full-scale and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error. Refer to the Analog-to-Digital Converter chapter of the SmartFusion Programmable Analog User’s Guide for more information. Revision 8 2-81 SmartFusion DC and Switching Characteristics Table 2-97 • ABPS Performance Specifications (continued) Specification Test Conditions Min. Typ. Max. Units Effective number of bits (ENOB) GDEC[1:0] = 11 (±2.56 range), –1 dBFS input SINAD – 1.76 dB --------------------------------------------- ENOB = 12-bit mode 10 KHz 8.6 9.1 Bits 6.02 dB/bit 12-bit mode 100 KHz 8.6 9.1 Bits EQ 11 10-bit mode 10 KHz 8.5 8.9 Bits 10-bit mode 100 KHz 8.5 8.9 Bits 8-bit mode 10 KHz 7.7 7.8 Bits 8-bit mode 100 KHz 7.7 7.8 Bits Large-signal bandwidth –1 dBFS input 1 MHz Analog settling time To 0.1% of final value (with ADC 10 µs load) Input resistance 1MΩ Power supply rejection ratio DC (0–1 KHz) 38 40 dB ABPS power supply current ABPS_EN = 1 (operational mode) requirements (not including ADC or VCC33A 123 134 µA VAREFx) VCC33AP 89 94 µA VCC15A 1 µA Note: *FS is full-scale error, defined as the difference between the actual value that triggers the transition to full-scale and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error. Refer to the Analog-to-Digital Converter chapter of the SmartFusion Programmable Analog User’s Guide for more information. 2-82 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Comparator Unless otherwise specified, performance is specified at 25°C with nominal power supply voltages. Table 2-98 • Comparator Performance Specifications Specification Test Conditions Min. Typ. Max. Units Input voltage range Minimum 0 V Maximum 2.56 V Input offset voltage HYS[1:0] = 00 ±1 ±3 mV (no hysteresis) Input bias current Comparator 1, 3, 5, 7, 9 (measured at 2.56 V) 40 60 nA Comparator 0, 2, 4, 6, 8 (measured at 2.56 V) 150 300 nA Input resistance 10 MΩ Power supply rejection ratio DC (0 – 10 KHz) 50 60 dB Propagation delay 100 mV overdrive HYS[1:0] = 00 (no hysteresis) 15 18 ns 100 mV overdrive HYS[1:0] = 10 (with hysteresis) 25 30 ns Hysteresis HYS[1:0] = 00 Typical (25°C) 0 0 ±5 mV (± refers to rising and falling Across all corners (–40ºC to +100ºC) 0 ±5 mV threshold shifts, respectively) HYS[1:0] = 01 Typical (25°C) ±3 ± 16 ±30 mV Across all corners (–40ºC to +100ºC) 0 ±36 mV HYS[1:0] = 10 Typical (25°C) ±19 ± 31 ±48 mV Across all corners (–40ºC to +100ºC) ±12 ±54 mV HYS[1:0] = 11 Typical (25°C) ±80 ± 105 ±190 mV Across all corners (–40ºC to +100ºC) ±80 ±194 mV Comparator current VCC33A = 3.3 V (operational mode); COMP_EN = 1 requirements VCC33A 150 165 µA (per comparator) VCC33AP 140 165 µA VCC15A 1 3 µA Revision 8 2-83 SmartFusion DC and Switching Characteristics Analog Sigma-Delta Digital to Analog Converter (DAC) Unless otherwise noted, sigma-delta DAC performance is specified at 25°C with nominal power supply voltages, using the internal sigma-delta modulators with 16-bit inputs, HCLK = 100 MHz, modulator inputs updated at a 100 KHz rate, in voltage output mode with an external 160 pF capacitor to ground, after trimming and digital [pre-]compensation. Table 2-99 • Analog Sigma-Delta DAC Specification Test Conditions Min. Typ. Max. Units Resolution 8 24 Bits Output range 0 to 2.56 V Current output mode 0 to 256 µA Output Impedance 6 10 12 KΩ Current output mode 10 MΩ Output voltage compliance Current output mode 0–3.0 V –40ºC to +100ºC 0–2.7 0–3.4 V Gain error Voltage output mode 0.3 ±2 % A2F060: –40ºC to +100ºC 0.3 ±2 % A2F200: –40ºC to +100ºC 1.2 ±5.3 % A2F500: –40ºC to +100ºC 0.3 ±2 % Current output mode 0.3 ±2 % A2F060: –40ºC to +100ºC 0.3 ±2 % A2F200: –40ºC to +100ºC 1.2 ±5.3 % A2F500: –40ºC to +100ºC 0.3 ±2 % Output referred offset DACBYTE0 = h’00 (8-bit) 0.25 ±1 mV –40ºC to +100ºC 1 ±2.5 mV Current output mode 0.3 ±1 µA –40ºC to +100ºC 1 ±2.5 µA Integral non-linearity RMS deviation from BFSL 0.1 0.3 % FS* Differential non-linearity 0.05 0.4 % FS* Analog settling time Refer to µs Figure 2-43 on page 2-85 Power supply rejection ratio DC, full scale output 33 34 dB Note: *FS is full-scale error, defined as the difference between the actual value that triggers the transition to full-scale and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error. Refer to the Analog-to-Digital Converter chapter of the SmartFusion Programmable Analog User’s Guide for more information. 2-84 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Table 2-99 • Analog Sigma-Delta DAC (continued) Specification Test Conditions Min. Typ. Max. Units Sigma-delta DAC power supply current Input = 0, EN = 1 requirements (not including VAREFx) (operational mode) VCC33SDDx 30 35 µA VCC15A 3 5 µA Input = Half scale, EN = 1 (operational mode) VCC33SDDx 160 165 µA VCC15A 33 35 µA Input = Full scale, EN = 1 (operational mode) VCC33SDDx 280 285 µA VCC15A 70 75 µA Note: *FS is full-scale error, defined as the difference between the actual value that triggers the transition to full-scale and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error. Refer to the Analog-to-Digital Converter chapter of the SmartFusion Programmable Analog User’s Guide for more information. Sigma Delta DAC Settling Time 220 200 180 160 140 120 100 80 60 40 20 0 0123 4 5 6 7 8 9 10 32 48 64128 255 Input Code Figure 2-43 • Sigma-Delta DAC Setting Time Revision 8 2-85 Settling Time (us) SmartFusion DC and Switching Characteristics Voltage Regulator Table 2-100 • Voltage Regulator Symbol Parameter Test Conditions Min. Typ. Max. Unit V Output voltage T = 25°C 1.425 1.5 1.575 V OUT J V Output offset voltage T = 25°C 11 mV OS J ICC33A Operation current T = 25°C I = 1 mA 3.4 mA J LOAD I = 100 mA 11 mA LOAD I = 0.5 A 21 mA LOAD ΔV Load regulation T = 25°C I = 1 mA to 0.5 A 5.8 mV OUT J LOAD ΔV Line regulation T = 25°C VCC33A = 2.97 V to 3.63 V 5.3 mV/V OUT J I = 1 mA LOAD VCC33A = 2.97 V to 3.63 V 5.3 mV/V I = 100 mA LOAD VCC33A = 2.97 V to 3.63 V 5.3 mV/V I = 500mA LOAD 1 Dropout voltage T = 25°C I = 1 mA 0.63 V J LOAD I = 100 mA 0.84 V LOAD I = 0.5 A 1.35 V LOAD I PTBase current T = 25°C I = 1 mA 48 µA PTBASE J LOAD I = 100 mA 736 µA LOAD I = 0.5 A 12 mA LOAD 2 Startup time T = 25°C 200 ms J Notes: 1. Dropout voltage is defined as the minimum VCC33A voltage. The parameter is specified with respect to the output voltage. The specification represents the minimum input-to-output differential voltage required to maintain regulation. 2. Assumes 10 µF. 2-86 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Typical Output Voltage 0.015 Load = 10 mA 0.01 Load = 100 mA 0.005 Load = 500 mA 0 -0.005 -0.01 -0.015 -0.02 -0.025 -40 -20 0 20406080 100 Temperature (°C) Figure 2-44 • Typical Output Voltage Load Regulation 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 2-45 • Load Regulation Revision 8 2-87 Offset Voltage (V) Change in Output Voltage with Load (mV) SmartFusion DC and Switching Characteristics Serial Peripheral Interface (SPI) Characteristics This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output characteristics given for a 35 pF load on the pins and all sequential timing characteristics are related to SPI_x_CLK. For timing parameter definitions, refer to Figure 2-46 on page 2-89. Table 2-101 • SPI Characteristics Commercial Case Conditions: T = 85ºC, VDD = 1.425 V, –1 Speed Grade J Symbol Description and Condition A2F060 A2F200 A2F500 Unit sp1 SPI_x_CLK minimum period SPI_x_CLK = PCLK/2 20 NA 20 ns SPI_x_CLK = PCLK/4 40 40 40 ns SPI_x_CLK = PCLK/8 80 80 80 ns SPI_x_CLK = PCLK/16 0.16 0.16 0.16 µs SPI_x_CLK = PCLK/32 0.32 0.32 0.32 µs SPI_x_CLK = PCLK/64 0.64 0.64 0.64 µs SPI_x_CLK = PCLK/128 1.28 1.28 1.28 µs SPI_x_CLK = PCLK/256 2.56 2.56 2.56 µs sp2 SPI_x_CLK minimum pulse width high SPI_x_CLK = PCLK/2 10 NA 10 ns SPI_x_CLK = PCLK/4 20 20 20 ns SPI_x_CLK = PCLK/8 40 40 40 ns SPI_x_CLK = PCLK/16 0.08 0.08 0.08 µs SPI_x_CLK = PCLK/32 0.16 0.16 0.16 µs SPI_x_CLK = PCLK/64 0.32 0.32 0.32 µs SPI_x_CLK = PCLK/128 0.64 0.64 0.64 µs SPI_x_CLK = PCLK/256 1.28 1.28 1.28 us sp3 SPI_x_CLK minimum pulse width low SPI_x_CLK = PCLK/2 10 NA 10 ns SPI_x_CLK = PCLK/4 20 20 20 ns SPI_x_CLK = PCLK/8 40 40 40 ns SPI_x_CLK = PCLK/16 0.08 0.08 0.08 µs SPI_x_CLK = PCLK/32 0.16 0.16 0.16 µs SPI_x_CLK = PCLK/64 0.32 0.32 0.32 µs SPI_x_CLK = PCLK/128 0.64 0.64 0.64 µs SPI_x_CLK = PCLK/256 1.28 1.28 1.28 µs 1 sp4 SPI_x_CLK, SPI_x_DO, SPI_x_SS rise time (10%-90%) 4.7 4.7 4.7 ns 1 sp5 SPI_x_CLK, SPI_x_DO, SPI_x_SS fall time (10%-90%) 3.4 3.4 3.4 ns Notes: 1. These values are provided for a load of 35 pF. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website: http://www.microsemi.com/soc/download/ibis/default.aspx. 2. For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the SmartFusion Microcontroller Subsystem User’s Guide. 2-88 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Table 2-101 • SPI Characteristics Commercial Case Conditions: T = 85ºC, VDD = 1.425 V, –1 Speed Grade (continued) J Symbol Description and Condition A2F060 A2F200 A2F500 Unit 2 sp6 Data from master (SPI_x_DO) setup time 1 1 1 pclk cycles 2 sp7 Data from master (SPI_x_DO) hold time 1 1 1 pclk cycles 2 sp8 SPI_x_DI setup time 1 1 1 pclk cycles 2 sp9 SPI_x_DI hold time 1 1 1 pclk cycles Notes: 1. These values are provided for a load of 35 pF. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website: http://www.microsemi.com/soc/download/ibis/default.aspx. 2. For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the SmartFusion Microcontroller Subsystem User’s Guide. SP1 SP4 SP5 SP3 SP2 90% SPI_x_CLK 50% 50% 50% SPO = 0 10% 10% SPI_x_CLK SPO = 1 90% 90% SPI_x_SS 10% 10% SP5 SP4 SP6 SP7 90% 90% MSB 50% 50% SPI_x_DO 10% 10% SP8 SP9 SP5 SP4 SPI_x_DI 50% 50% MSB Figure 2-46 • SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1) Revision 8 2-89 SmartFusion DC and Switching Characteristics 2 Inter-Integrated Circuit (I C) Characteristics 2 This section describes the DC and switching of the I C interface. Unless otherwise noted, all output characteristics given are for a 100 pF load on the pins. For timing parameter definitions, refer to Figure 2- 47 on page 2-91. 2 Table 2-102 • I C Characteristics Commercial Case Conditions: T = 85ºC, V = 1.425 V, –1 Speed Grade J DD Parameter Definition Condition Value Unit V Minimum input low voltage – SeeTable2-36 on – IL page 2-30 Maximum input low voltage – See Table 2-36 – V Minimum input high voltage – See Table 2-36 – IH Maximum input high voltage – See Table 2-36 – V Maximum output voltage low I =8mA See Table 2-36 – OL OL I Input current high – See Table 2-36 – IL I Input current low – See Table 2-36 – IH V Hysteresis of Schmitt trigger – See Table 2-33 on V hyst inputs page 2-29 2 T Fall time VIHmin to VILMax, C = 400 pF 15.0 ns FALL load VIHmin to VILMax, C = 100 pF 4.0 ns load 2 T Rise time VILMax to VIHmin, C = 400pF 19.5 ns RISE load VILMax to VIHmin, C = 100pF 5.2 ns load Cin Pin capacitance VIN = 0, f = 1.0 MHz 8.0 pF R Output buffer maximum pull- –50 Ω pull-up 1 down Resistance R Output buffer maximum pull-up – 150 Ω pull-down 1 Resistance D Maximum data rate Fast mode 400 Kbps max 3 t Low period of I2C_x_SCL – 1 pclk cycles LOW 3 t High period of I2C_x_SCL – 1 pclk cycles HIGH 3 t START hold time – 1 pclk cycles HD;STA 3 t START setup time – 1 pclk cycles SU;STA 3 t DATA hold time – 1 pclk cycles HD;DAT 3 t DATA setup time – 1 pclk cycles SU;DAT Notes: 1. These maximum values are provided for information only. Minimum output buffer resistance values depend on VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the SoC Products Group website at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. These values are provided for a load of 100 pF and 400 pF. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the SoC Products Group website at http://www.microsemi.com/soc/download/ibis/default.aspx. 2 3. For allowable Pclk configurations, refer to the Inter-Integrated Circuit (I C) Peripherals section in the SmartFusion Microcontroller Subsystem User’s Guide. 2-90 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) 2 C Characteristics Table 2-102 • I Commercial Case Conditions: T = 85ºC, V = 1.425 V, –1 Speed Grade (continued) J DD Parameter Definition Condition Value Unit 3 t STOP setup time – 1 pclk cycles SU;STO t Maximum spike width filtered – 50 ns FILT Notes: 1. These maximum values are provided for information only. Minimum output buffer resistance values depend on VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the SoC Products Group website at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. These values are provided for a load of 100 pF and 400 pF. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the SoC Products Group website at http://www.microsemi.com/soc/download/ibis/default.aspx. 2 3. For allowable Pclk configurations, refer to the Inter-Integrated Circuit (I C) Peripherals section in the SmartFusion Microcontroller Subsystem User’s Guide. SDA T T RISE FALL SCL t LOW t HIGH t SU;STO t t t t SU;STA HD;STA HD;DAT SU;DAT S P Figure 2-47 • I2C Timing Parameter Definition Revision 8 2-91 3 – SmartFusion Development Tools Designing with SmartFusion cSoCs involves three different types of design: FPGA design, embedded design and analog design. These roles can be filled by three different designers, two designers or even a single designer, depending on company structure and project complexity. Types of Design Tools Microsemi has developed design tools and flows to meet the needs of these three types of designers so they can work together smoothly on a single project (Figure 3-1). FPGA Design Embedded Design Software IDE (SoftConsole, Keil, IAR) MSS Configurator MSS Configuration – Analog Configuration Design Entry and IP Libraries Drivers and Sample Projects Simulation and Synthesis Application Development Compile and Layout Build Project Timing and Power Analysis Simulation Hardware Debug Software Debug Hardware Interfaces FlashPro4, ULINK, J-LINK Figure 3-1 • Three Design Roles FPGA Design Libero Integrated Design Environment (IDE) is Microsemi’s comprehensive software toolset for designing with all Microsemi FPGAs and cSoCs. Libero IDE includes industry-leading synthesis, simulation and ® ® debug tools from Synopsys and Mentor Graphics , as well as innovative timing and power optimization and analysis. Revision 8 3-1 SmartFusion Development Tools Embedded Design Microsemi offers FREE SoftConsole Eclipse based IDE, which includes the GNU C/C++ compiler and GDB debugger. Microsemi also offers evaluation versions of software from Keil and IAR, with full versions available from respective suppliers. Analog Design The MSS configurator provides graphical configuration for current, voltage and temperature monitors, sample sequencing setup and post-processing configuration, as well as DAC output. The MSS configurator creates a bridge between the FPGA fabric and embedded designers so device configuration can be easily shared between multiple developers. The MSS configurator includes the following: • A simple configurator for the embedded designer to control the MSS peripherals and I/Os • A method to import and view a hardware configuration from the FPGA flow into the embedded flow containing the memory map • Automatic generation of drivers for any peripherals or soft IP used in the system configuration • Comprehensive analog configuration for the programmable analog components • Creation of a standard MSS block to be used in SmartDesign for connection of FPGA fabric designs and IP Figure 3-2 • MSS Configurator 3-2 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) SmartFusion Ecosystem The Microsemi SoC Products Group has a long history of supplying comprehensive FPGA development tools and recognizes the benefit of partnering with industry leaders to deliver the optimum usability and productivity to customers. Taking the same approach with processor development, Microsemi has partnered with key industry leaders in the microcontroller space to provide the robust SmartFusion ecosystem. Microsemi is partnering with Keil and IAR to provide Software IDE support to SmartFusion system designers. The result is a robust solution that can be easily adopted by developers who are already doing embedded design. The learning path is straightforward for FPGA designers. Support for the SoC Products Group device and ecosystem resources is represented in Figure 3-3. Application Code Customer Secret Sauce Middleware TCP/IP, HTTP, SMTP, DHCP, LCD µC/OS-III, RTX, Unison, FreeRTOS OS/RTOS Drivers Hardware Abstraction Microsemi CMSIS-based HAL Layer Figure 3-3 • SmartFusion Ecosystem Figure 3-3 shows the SmartFusion stack with examples of drivers, RTOS, and middleware from Microsemi and partners. By leveraging the SmartFusion stack, designers can decide at which level to add their own customization to their design, thus speeding time to market and reducing overhead in the design. ARM Because an ARM processor was chosen for SmartFusion cSoCs, Microsemi's customers can benefit from the extensive ARM ecosystem. By building on Microsemi supplied hardware abstraction layer (HAL) and drivers, third party vendors can easily port RTOS and middleware for the SmartFusion cSoC. • ARM Cortex-M Series Processors • ARM Cortex-M3 Processor Resource • ARM Cortex-M3 Technical Reference Manual • ARM Cortex-M3 Processor Software Development for ARM7TDMI Processor Programmers White Paper Revision 8 3-3 2 1 C SPI UART Ethernet Timer eNVM SmartFusion Development Tools Compile and Debug Microsemi's SoftConsole is a free Eclipse-based IDE that enables the rapid production of C and C++ executables for Microsemi FPGA and cSoCs using Cortex-M3, Cortex-M1 and Core8051s. For SmartFusion support, SoftConsole includes the GNU C/C++ compiler and GDB debugger. Additional examples can be found on the SoftConsole page: • Using UART with SmartFusion: SoftConsole Standalone Flow Tutorial – Design Files • Displaying POT Level with LEDs: Libero IDE and SoftConsole Flow Tutorial for SmartFusion – Design Files ® IAR Embedded Workbench for ARM/Cortex is an integrated development environment for building and debugging embedded ARM applications using assembler, C and C++. It includes a project manager, editor, build and debugger tools with support for RTOS-aware debugging on hardware or in a simulator. • Designing SmartFusion cSoC with IAR Systems • IAR Embedded Workbench IDE User Guide for ARM • Download Evaluation or Kickstart version of IAR Embedded Workbench for ARM Keil's Microcontroller Development Kit comes in two editions: MDK-ARM and MDK Basic. Both editions ® feature µVision , the ARM Compiler, MicroLib, and RTX, but the MDK Basic edition is limited to 256K so that small applications are more affordable. • Designing SmartFusion cSoC with Keil • Using Keil µVision and Microsemi SmartFusion cSoC – Programming file for use with this tutorial • Keil Microcontroller Development Kit for ARM Product Manuals • Download Evaluation version of Keil MDK-ARM Software IDE SoftConsole Vision IDE Embedded Workbench Website www.microsemi.com/soc www.keil.com www.iar.com Free versions from SoC Free with Libero IDE 32 K code limited 32 K code limited Products Group Available from Vendor N/A Full version Full version Compiler GNU GCC RealView C/C++ IAR ARM Compiler Debugger GDB debug Vision Debugger C-SPY Debugger Instruction Set Simulator No Vision Simulator Yes Debug Hardware FlashPro4 ULINK2 or ULINK-ME J-LINK or J-LINK Lite Operating Systems FreeRTOS™ is a portable, open source, royalty free, mini real-time kernel (a free-to-download and free- to-deploy RTOS that can be used in commercial applications without any requirement to expose your proprietary source code). FreeRTOS is scalable and designed specifically for small embedded systems. This FreeRTOS version ported by Microsemi is 6.0.1. For more information, visit the FreeRTOS website: www.freertos.org • SmartFusion Webserver Demo Using uIP and FreeRTOS • SmartFusion cSoC: Running Webserver, TFTP on IwIP TCP/IP Stack Application Note 3-4 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Emcraft Systems provides porting of the open-source U-boot firmware and uClinux™ kernel to the ® SmartFusion cSoC, a Linux -based cross-development framework, and other complementary components. Combined with the release of its A2F-Linux Evaluation Kit, this provides a low-cost platform for evaluation and development of Linux (uClinux) on the Cortex-M3 CPU core of the Microsemi SmartFusion cSoC. • Emcraft Linux on Microsemi's SmartFusion cSoC Keil offers the RTX Real-Time Kernel as a royalty-free, deterministic RTOS designed for ARM and Cortex-M devices. It allows you to create programs that simultaneously perform multiple functions and helps to create applications which are better structured and more easily maintained. • The RTX Real-Time Kernel is included with MDK-ARM. Download the Evaluation version of Keil MDK-ARM. • RTX source code is available as part of Keil/ARM Real-Time Library (RL-ARM), a group of tightly- coupled libraries designed to solve the real-time and communication challenges of embedded systems based on ARM-powered microcontroller devices. The RL-ARM library now supports SmartFusion cSoCs and designers with additional key features listed in the "Middleware" section on page 3-5. Micrium supports SmartFusion cSoCs with the company's flagship µC/OS family, recognized for a variety of features and benefits, including unparalleled reliability, performance, dependability, impeccable source code and vast documentation. Micrium supports the following products for SmartFusion cSoCs and continues to work with Microsemi on additional projects. • SmartFusion Quickstart Guide for Micrium µC/OS-III Examples – Design Files µC/OS-III™, Micrium's newest RTOS, is designed to save time on your next embedded project and puts greater control of the software in your hands. RoweBots provides an ultra tiny Linux-compatible RTOS called Unison for SmartFusion. Unison consists of a set of modular software components, which, like Linux, are either free or commercially licensed. ® Unison offers POSIX and Linux compatibility with hard real-time performance, complete I/O modules and an easily understood environment for device driver programming. Seamless integration with FPGA and analog features are fast and easy. • Unison V4-based products include a free Unison V4 Linux and POSIX-compatible kernel with serial I/O, file system, six demonstration programs, upgraded documentation and source code for Unison V4, and free (for non-commercial use) Unison V4 TCP/IP server. Commercial license upgrade is available for Unison V4 TCP/IP server with three demonstration programs, DHCP client and source code. • Unison V5-based products include commercial Unison V5 Linux- and POSIX-compatible kernel with serial I/O, file system, extensive feature set, full documentation, source code and more than 20 demonstration programs, Unison V5 TCP/IPv4 with extended feature set, sockets interface, multiple network interfaces, PPP support, DHCP client, documentation, source code and six demonstration programs, and multiple other features. Middleware Microsemi has ported both uIP and IwIP for Ethernet support as well as including TFTP file service. • SmartFusion Webserver Demo Using uIP and FreeRTOS • SmartFusion: Running Webserver, TFTP on IwIP TCP/IP Stack Application Note 1 The Keil/ARM Real-Time Library (RL-ARM) , in addition to RTX source, includes the following: • RL-TCPnet (TCP/IP) – The Keil RL-TCPnet library, supporting full TCP/IP and UDP protocols, is a full networking suite specifically written for small ARM and Cortex-M processor-based microcontrollers. TCPnet is now ported to and supports SmartFusion Cortex-M3. It is highly optimized, has a small code footprint, and gives excellent performance, providing a wide range of application level protocols and examples such as FTP, SNMP, SOAP and AJAX. An HTTP server example of TCPnet working in a SmartFusion design is available. 1. The CAN and USB functions within RL-ARM are not supported for SmartFusion cSoC. Revision 8 3-5 SmartFusion Development Tools • Flash File System (RL-Flash) allows your embedded applications to create, save, read, and modify files in standard storage devices such as ROM, RAM, or FlashROM, using a standard serial peripheral interface (SPI). Many ARM-based microcontrollers have a practical requirement for a standard file system. With RL-FlashFS you can implement new features in embedded applications such as data logging, storing program state during standby modes, or storing firmware upgrades. ® , offers the following support for SmartFusion cSoC: Micrium, in addition to µC/OS-III • µC/TCP-IP™ is a compact, reliable, and high-performance stack built from the ground up by Micrium and has the quality, scalability, and reliability that translates into a rapid configuration of network options, remarkable ease-of-use, and rapid time-to-market. • µC/Probe™ is one of the most useful tools in embedded systems design and puts you in the driver's seat, allowing you to take charge of virtually any variable, memory location, and I/O port in your embedded product, while your system is running. 3-6 Revision 8 4 – SmartFusion Programming SmartFusion cSoCs have three separate flash areas that can be programmed: 1. The FPGA fabric 2. The embedded nonvolatile memories (eNVMs) 3. The embedded flash ROM (eFROM) There are essentially three methodologies for programming these areas: 1. In-system programming (ISP) 2. In-application programming (IAP) a. A2F060 and A2F500: The FPGA fabric, eNVM, and eFROM b. A2F200: Only the FPGA fabric and the eNVM 3. Pre-programming (non-ISP) Programming, whether ISP or IAP methodologies are employed, can be done in two ways: 1. Securely using the on chip AES decryption logic 2. In plain text In-System Programming In-System Programming is performed with the aid of external JTAG programming hardware. Table 4-1 describes the JTAG programming hardware that will program a SmartFusion cSoC and Table 4-2 defines the JTAG pins that provide the interface for the programming hardware. Table 4-1 • Supported JTAG Programming Hardware Program Program Program 1 2 Dongle Source JTAG SWD SWV FPGA eFROM eNVM FlashPro3/4 SoC Yes No No Yes Yes Yes Products Group 3 3 ULINK Pro Keil Yes Yes Yes Yes Yes Yes 3 3 ULINK2 Keil Yes Yes Yes Yes Yes Yes 3 3 IAR J-Link IAR Yes Yes Yes Yes Yes Yes Notes: 1. SWD = ARM Serial Wire Debug 2. SWV = ARM Serial Wire Viewer 3. Planned support Table 4-2 • JTAG Pin Descriptions Pin Name Description JTAGSEL ARM Cortex-M3 or FPGA test access port (TAP) controller selection TRSTB Test reset bar TCK Test clock TMS Test mode select TDI Test data input TDO Test data output Revision 8 4-7 SmartFusion Programming The JTAGSEL pin selects the FPGA TAP controller or the Cortex-M3 debug logic. When JTAGSEL is asserted, the FPGA TAP controller is selected and the TRSTB input into the Cortex-M3 is held in a reset state (logic 0), as depicted in Figure 4-1. Users should tie the JTAGSEL pin high externally. Microsemi’s free Eclipse-based IDE, SoftConsole, has the ability to control the JTAGSEL pin directly with the FlashPro4 programmer. Manual jumpers are provided on the evaluation and development kits to allow manual selection of this function for the J-Link and ULINK debuggers. Note: Standard ARM JTAG connectors do not have access to the JTAGSEL pin. SoftConsole automatically selects the appropriate TAP controller using the CTXSELECT JTAG command. When using SoftConsole, the state of JTAGSEL is a "don't care." VJTAG (1.5 V to 3.3. V nominal) JTAG_SEL TAP Controller Cortex-M3 TRSTB TRSTB FPGA FPGA TAP Programming Control Controller Figure 4-1 • TRSTB Logic In-Application Programming In-application programming refers to the ability to reprogram the various flash areas under direct supervision of the Cortex-M3. Reprogramming the FPGA Fabric Using the Cortex-M3 In this mode, the Cortex-M3 is executing the programming algorithm on-chip. The IAP driver can be incorporated into the design project and executed from eNVM or eSRAM. The SoC Products Group provides working example projects for SoftConsole, IAR, and Keil development environments. These can be downloaded via the SoC Products Group Firmware Catalog. The new bitstream to be programmed into the FPGA can reside on the user’s printed circuit board (PCB) in a separate SPI flash memory. Alternately, the user can modify the existing projects supplied by the SoC Products Group and, via custom handshaking software, throttle the download of the new image and program the FPGA a piece at a time in real time. A cost-effective and reliable approach would be to store the bitstream in an external SPI flash. Another option is storing a redundant bitstream image in an external SPI flash and loading the newest version into the FPGA only when receiving an IAP command. Since the FPGA I/Os are tristated or held at predefined or last known state during FPGA programming, the user must use MSS I/Os to interface to external memories. Since there are two SPI controllers in the MSS, the user can dedicate one to an SPI flash and the other to the particulars of an application. The amount of flash memory required to program the FPGA always exceeds the size of the eNVM block that is on-chip. The external memory controller (EMC) cannot be used as an interface to a memory device for storage of a bitstream because its I/O pads are FPGA I/Os; hence they are tristated when the FPGA is in a programming state. 4-8 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Re-Programming the eNVM Blocks Using the Cortex-M3 In this mode the Cortex-M3 is executing the eNVM programming algorithm from eSRAM. Since individual pages (132 bytes) of the eNVM can be write-protected, the programming algorithm software can be protected from inadvertent erasure. When reprogramming the eNVM, both MSS I/Os and FPGA I/Os are available as interfaces for sourcing the new eNVM image. The SoC Products Group provides working example projects for SoftConsole, IAR, and Keil development environments. These can be downloaded via the SoC Products Group Firmware Catalog. Alternately, the eNVM can be reprogrammed by the Cortex-M3 via the IAP driver. This is necessary when using an encrypted image. Secure Programming For background, refer to the "Security in Low Power Flash Devices" chapter of the Fusion FPGA Fabric User’s Guide on the SoC Products Group website. SmartFusion ISP behaves identically to Fusion ISP. IAP of SmartFusion cSoCs is accomplished by using the IAP driver. Only the FPGA fabric and the eNVM can be reprogrammed with the protection of security measures by using the IAP driver. Typical Programming and Erase Times Table 4-3 documents the typical programming and erase times for two components of SmartFusion cSoCs, FPGA fabric and eNVM, using the SoC Products Group’s FlashPro hardware and software. These times will be different for other ISP and IAP methods. The Program action in FlashPro software includes erase, program, and verify to complete. The typical programming (including erase) time per page of the eNVM is 8 ms. Table 4-3 • Typical Programming and Erase Times FPGA Fabric (seconds) eNVM (seconds) A2F200 A2F500 A2F200 A2F500 Erase 21 21 N/A N/A Program 8 15 18 26 Verify 9 16 26 42 References User’s Guides DirectC User’s Guide http://www.microsemi.com/soc/documents/DirectC_UG.pdf Fusion FPGA Fabric User’s Guide http://www.microsei.com/soc/documents/Fusion_UG.pdf Chapters: "In-System Programming (ISP) of Actel’s Low-Power Flash Devices Using FlashPro4/3/3X" "Security in Low Power Flash Devices" "Programming Flash Devices" "Microprocessor Programming of Actel’s Low-Power Flash Devices" Revision 8 4-9 5 – Pin Descriptions Supply Pins Name Type Description GND Ground Digital ground to the FPGA fabric, microcontroller subsystem and GPIOs GND15ADC0 Ground Quiet analog ground to the 1.5 V circuitry of the first analog-to-digital converter (ADC) GND15ADC1 Ground Quiet analog ground to the 1.5 V circuitry of the second ADC GND15ADC2 Ground Quite analog ground to the 1.5 V circuitry of the third ADC GND33ADC0 Ground Quiet analog ground to the 3.3 V circuitry of the first ADC GND33ADC1 Ground Quiet analog ground to the 3.3 V circuitry of the second ADC GND33ADC2 Ground Quiet analog ground to the 3.3 V circuitry of the third ADC GNDA Ground Quiet analog ground to the analog front-end GNDAQ Ground Quiet analog ground to the analog I/O of SmartFusion cSoCs GNDENVM Ground Digital ground to the embedded nonvolatile memory (eNVM) GNDLPXTAL Ground Analog ground to the low power 32 KHz crystal oscillator circuitry GNDMAINXTAL Ground Analog ground to the main crystal oscillator circuitry GNDQ Ground Quiet digital ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise originated from the output buffer ground domain. This minimizes the noise transfer within the package and improves input signal integrity. GNDQ needs to always be connected on the board to GND. GNDRCOSC Ground Analog ground to the integrated RC oscillator circuit GNDSDD0 Ground Analog ground to the first sigma-delta DAC GNDSDD1 Ground Common analog ground to the second and third sigma-delta DACs GNDTM0 Ground Analog temperature monitor common ground for signal conditioning blocks SCB 0 and SCB 1 (see information for pins "TM0" and "TM1" in the "Analog Front-End (AFE)" section on page 5-13). GNDTM1 Ground Analog temperature monitor common ground for signal conditioning block SCB 2 and SBCB 3 (see information for pins "TM2" and "TM3" in the "Analog Front-End (AFE)" section on page 5-13). GNDTM2 Ground Analog temperature monitor common ground for signal conditioning block SCB4 GNDVAREF Ground Analog ground reference used by the ADC. This pad should be connected to a quiet analog ground. VCC Supply Digital supply to the FPGA fabric and MSS, nominally 1.5 V. VCC is also required for powering the JTAG state machine, in addition to VJTAG. Even when a SmartFusion cSoC is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass through the SmartFusion cSoC. VCC15A Supply Clean analog 1.5 V supply to the analog circuitry. Always power this pin. Notes: 1. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A, VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL. 2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC, VCC15A, and VCC15ADCx. Revision 8 5-1 Pin Descriptions Name Type Description VCC15ADC0 Supply Analog 1.5 V supply to the first ADC. Always power this pin. VCC15ADC1 Supply Analog 1.5 V supply to the second ADC. Always power this pin. VCC15ADC2 Supply Analog 1.5 V supply to the third ADC. Always power this pin. VCC33A Supply Clean 3.3 V analog supply to the analog circuitry. VCC33A is also used to feed the 1.5 V voltage regulator for designs that do not provide an external supply to VCC. Refer to the Voltage Regulator (VR), Power Supply Monitor (PSM), and Power Modes section in the SmartFusion Microcontroller Subsystem User’s Guide for more information. VCC33ADC0 Supply Analog 3.3 V supply to the first ADC. Never ground this pin. Can be left floating if 1 unused. VCC33ADC1 Supply Analog 3.3 V supply to the second ADC. Never ground this pin. Can be left floating if 1 unused. VCC33ADC2 Supply Analog 3.3 V supply to the third ADC. Never ground this pin. Can be left floating if 1 unused. VCC33AP Supply Analog clean 3.3 V supply to the charge pump. To avoid high current draw, VCC33AP should be powered up simultaneously with or after VCC33A. Can be pulled down if 1 unused. VCC33N Supply –3.3 V output from the voltage converter. A 2.2 µF capacitor must be connected from this pin to GND. Analog charge pump capacitors are not needed if none of the analog SCB features are used and none of the SDDs are used. In that case it should be left unconnected. VCC33SDD0 Supply Analog 3.3 V supply to the first sigma-delta DAC VCC33SDD1 Supply Common analog 3.3 V supply to the second and third sigma-delta DACs VCCENVM Supply Digital 1.5 V power supply to the embedded nonvolatile memory blocks. To avoid high current draw, VCC should be powered up before or simultaneously with VCCENVM. VCCESRAM Supply Digital 1.5 V power supply to the embedded SRAM blocks. Available only on the 208PQFP package. It should be connected to VCC (in other packages, it is internally connected to VCC). VCCFPGAIOB0 Supply Digital supply to the FPGA fabric I/O bank 0 (north FPGA I/O bank) for the output buffers and I/O logic. Each bank can have a separate VCCFPGAIO connection. All I/Os in a bank will run off the same VCCFPGAIO supply. VCCFPGAIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCFPGAIO pins tied to GND. VCCFPGAIOB1 Supply Digital supply to the FPGA fabric I/O bank 1 (east FPGA I/O bank) for the output buffers and I/O logic. Each bank can have a separate VCCFPGAIO connection. All I/Os in a bank will run off the same VCCFPGAIO supply. VCCFPGAIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCFPGAIO pins tied to GND. VCCFPGAIOB5 Supply Digital supply to the FPGA fabric I/O bank 5 (west FPGA I/O bank) for the output buffers and I/O logic. Each bank can have a separate VCCFPGAIO connection. All I/Os in a bank will run off the same VCCFPGAIO supply. VCCFPGAIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCFPGAIO pins tied to GND. Notes: 1. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A, VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL. 2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC, VCC15A, and VCC15ADCx. 5-2 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Name Type Description 1 VCCLPXTAL Supply Analog supply to the low power 32 KHz crystal oscillator. Always power this pin. 1 VCCMAINXTAL Supply Analog supply to the main crystal oscillator circuit. Always power this pin. VCCMSSIOB2 Supply Supply voltage to the microcontroller subsystem I/O bank 2 (east MSS I/O bank) for the output buffers and I/O logic. Each bank can have a separate VCCMSSIO connection. All I/Os in a bank will run off the same VCCMSSIO supply. VCCMSSIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCMSSIO pins tied to GND. VCCMSSIOB4 Supply Supply voltage to the microcontroller subsystem I/O bank 4 (west MSS I/O bank) for the output buffers and I/O logic. Each bank can have a separate VCCMSSIO connection. All I/Os in a bank will run off the same VCCMSSIO supply. VCCMSSIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCMSSIO pins tied to GND. VCCPLLx Supply Analog 1.5 V supply to the PLL. Always power this pin. 1 VCCRCOSC Supply Analog supply to the integrated RC oscillator circuit. Always power this pin. VCOMPLAx Supply Analog ground for the PLL VDDBAT Supply External battery connection to the low power 32 KHz crystal oscillator (along with VCCLPXTAL), RTC, and battery switchover circuit. Can be pulled down if unused. VJTAG Supply Digital supply to the JTAG controller SmartFusion cSoCs have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned to be used, the V pin together with the TRSTB pin could be tied to GND. Note that VCC JTAG is required to be powered for JTAG operation; VJTAG alone is insufficient. If a SmartFusion cSoC is in a JTAG chain of interconnected boards and it is desired to power down the board containing the device, this can be done provided both VJTAG and VCC to the device remain powered; otherwise, JTAG signals will not be able to transition the device, even in bypass mode. See "JTAG Pins" section on page 5-9. VPP Supply Digital programming circuitry supply SmartFusion cSoCs support single-voltage in-system programming (ISP) of the configuration flash, embedded FlashROM (eFROM), and embedded nonvolatile memory (eNVM). For programming, VPP should be in the 3.3 V ± 5% range. During normal device operation, VPP can be left floating or can be tied to any voltage between 0 V and 3.6 V. When the VPP pin is tied to ground, it shuts off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in parallel across VPP and GND, and positioned as close to the FPGA pins as possible. Notes: 1. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A, VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL. 2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC, VCC15A, and VCC15ADCx. Revision 8 5-3 Pin Descriptions User-Defined Supply Pins Polarity/ Name Type Bus Size Description VAREF0 Input 1 Analog reference voltage for first ADC The SmartFusion cSoC can be configured to generate a 2.56 V internal reference that can be used by the ADC. While using the internal reference, the reference voltage is output on the VAREFOUT pin for use as a system reference. If a different reference voltage is required, it can be supplied by an external source and applied to this pin. The valid range of values that can be supplied to the ADC is 1.0 V to 3.3 V. When VAREF0 is internally generated, a bypass capacitor must be connected from this pin to ground. The value of the bypass capacitor should be between 3.3 µF and 22 µF, which is based on the needs of the individual designs. The choice of the capacitor value has an impact on the settling time it takes the VAREF0 signal to reach the required specification of 2.56 V to initiate valid conversions by the ADC. If the lower capacitor value is chosen, the settling time required for VAREF0 to achieve 2.56 V will be shorter than when selecting the larger capacitor value. The above range of capacitor values supports the accuracy specification of the ADC, which is detailed in the datasheet. Designers choosing the smaller capacitor value will not obtain as much margin in the accuracy as that achieved with a larger capacitor value. See the Analog-to-Digital Converter (ADC) section in the SmartFusion Programmable Analog User’s Guide for more information. The SoC Products Group recommends customers use 10 µF as the value of the bypass capacitor. Designers choosing to use an external VAREF0 need to ensure that a stable and clean VAREF0 source is supplied to the VAREF0 pin before initiating conversions by the ADC. To use the internal voltage reference, you must connect the VAREFOUT pin to the appropriate ADC VAREFx input— either the VAREF0 or VAREF1 pin—on the PCB. VAREF1 Input 1 Analog reference voltage for second ADC See "VAREF0" above for more information. VAREF2 Input 1 Analog reference voltage for third ADC See "VAREF0" above for more. VAREFOUT Out 1 Internal 2.56 V voltage reference output. Can be used to provide the two ADCs with a unique voltage reference externally by connecting VAREFOUT to both VAREF0 and VAREF1. To use the internal voltage reference, you must connect the VAREFOUT pin to the appropriate ADC VAREFx input—either the VAREF0 or VAREF1 pin—on the PCB. 5-4 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Global I/O Naming Conventions Gmn (Gxxx) refers to Global I/Os. These Global I/Os are used to connect the input to global networks. Global networks have high fanout and low skew. The naming convention for Global I/Os is as follows: G = Global m = Global pin location associated with each CCC on the device: – A (northwest corner) – B (northeast corner) – C (east middle) – D (southeast corner) – E (southwest corner) – F (west middle) n = Global input MUX and pin number of the associated Global location m—A0, A1, A2, B0, B1, B2, C0, C1, or C2. Global (GL) I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global I/O connectivity in the clocking resources chapter of the SmartFusion FPGA Fabric User’s Guide and the clock conditioning circuitry chapter of the SmartFusion Microcontroller Subsystem User’s Guide. All inputs labeled GC/GF are direct inputs into the quadrant clocks. The inputs to the global network are multiplexed, and only one input can be used as a global input. For example, if GAA0 is used as a quadrant global input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. User Pins Polarity/B Name Type us Size Description GPIO_x In/out 32 Microcontroller Subsystem (MSS) General Purpose I/O (GPIO). The MSS GPIO pin functions as an input, output, tristate, or bidirectional buffer with configurable interrupt generation and Schmitt trigger support. Input and output signal levels are compatible with the I/O standard selected. Unused GPIO pins are tristated and do not include pull-up or pull-down resistors. During power-up, the used GPIO pins are tristated with no pull-up or pull-down resistors until Sys boot configures them. Some of these pins are also multiplexed with integrated peripherals in the MSS (SPI, 2 I C, and UART). GPIOs can be routed to dedicated I/O buffers (MSSIOBUF) or in some cases to the FPGA fabric interface through an IOMUX. This allows GPIO pins to be multiplexed as ® either I/Os for the FPGA fabric, the ARM Cortex-M3 or for given integrated MSS peripherals. The MSS peripherals are not multiplexed with each other; they are multiplexed only with the GPIO block. For more information, see the General Purpose I/O Block (GPIO) section in the SmartFusion Microcontroller Subsystem User’s Guide. IO In/out FPGA user I/O Revision 8 5-5 Pin Descriptions User I/O Naming Conventions The naming convention used for each FPGA user I/O is Gmn/IOuxwByVz, where: Gmn is only used for I/Os that also have CCC access—i.e., global pins. Refer to the "Global I/O Naming Conventions" section on page 5-5. u = I/O pair number in bank, starting at 00 from the northwest I/O bank and proceeding in a clockwise direction. x = P (positive) or N (negative) or S (single-ended) or R (regular, single-ended). w = D (Differential Pair), P (Pair), or S (Single-Ended). D (Differential Pair) if both members of the pair are bonded out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out. For Differential Pairs (D), adjacency for ball grid packages means only vertical or horizontal. Diagonal adjacency does not meet the requirements for a true differential pair. B = Bank y = Bank number starting at 0 from northwest I/O bank and incrementing clockwise. V = Reference voltage z = VREF mini bank number. The FPGA user I/O pin functions as an input, output, tristate or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected. Unused I/O pins are disabled by Libero IDE software and include a weak pull-up resistor. During power-up, the used I/O pins are tristated with no pull-up or pull-down resistors until I/O enable (there is a delay after voltage stabilizes, and different I/O banks power up sequentially to avoid a surge of ICCI). Unused I/Os are configured as follows: • Output buffer is disabled (with tristate value of high impedance) • Input buffer is disabled (with tristate value of high impedance) • Weak pull-up is programmed Some of these pins are also multiplexed with integrated peripherals in the MSS (Ethernet MAC and external memory controller). Unused MSS I/Os are neither weakly pulled-up nor weakly pulled-down. The Schmitt trigger is disabled. Essentially, I/Os have the reset values as defined in Table 19-25 IOMUX_n_CR, in the SmartFusion Microcontroller Subsystem User's Guide. During programming, I/Os become tristated and weakly pulled up to VCCI. With the VCCI and VCC supplies continuously powered up, when the device transitions from programming to operating mode, the I/Os are instantly configured to the desired user configuration. For more information, see the SmartFusion FPGA User I/Os section in the SmartFusion FPGA Fabric User’s Guide. 5-6 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Special Function Pins Name Type Polarity/Bus Size Description NC No connect This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. DC Do not connect. This pin should not be connected to any signals on the PCB. These pins should be left unconnected. LPXIN In 1 Low power 32 KHz crystal oscillator. Input from the 32 KHz oscillator. Pin for connecting a low power 32 KHz watch crystal. If not used, the LPXIN pin can be left floating. For more information, see the PLLs, Clock Conditioning Circuitry, and On- Chip Crystal Oscillators section in the SmartFusion Microcontroller Subsystem User’s Guide. LPXOUT In 1 Low power 32 KHz crystal oscillator. Output to the 32 KHz oscillator. Pin for connecting a low power 32 KHz watch crystal. If not used, the LPXOUT pin can be left floating. For more information, see the PLLs, Clock Conditioning Circuitry, and On- Chip Crystal Oscillators section in the SmartFusion Microcontroller Subsystem User’s Guide. MAINXIN In 1 Main crystal oscillator circuit. Input to the crystal oscillator circuit. Pin for connecting an external crystal, ceramic resonator, or RC network. When using an external crystal or ceramic oscillator, external capacitors are also recommended. Refer to documentation from the crystal oscillator manufacturer for proper capacitor value. If using an external RC network or clock input, MAINXIN should be grounded for better noise immunity. For more information, see the PLLs, Clock Conditioning Circuitry, and On-Chip Crystal Oscillators section in the SmartFusion Microcontroller Subsystem User’s Guide. MAINXOUT Out 1 Main crystal oscillator circuit. Output from the crystal oscillator circuit. Pin for connecting external crystal or ceramic resonator. When using an external crystal or ceramic oscillator, external capacitors are also recommended. Refer to documentation from the crystal oscillator manufacturer for proper capacitor value. If using external RC network or clock input, MAINXIN should be grounded and MAINXOUT left unconnected. For more information, see the PLLs, Clock Conditioning Circuitry, and On-Chip Crystal Oscillators section in the SmartFusion Microcontroller Subsystem User’s Guide. NCAP 1 Negative capacitor connection. This is the negative terminal of the charge pump. A capacitor, with a 2.2 µF recommended value, is required to connect between PCAP and NCAP. Analog charge pump capacitors are not needed if none of the analog SCB features are used and none of the SDDs are used. In that case it should be left unconnected. Revision 8 5-7 Pin Descriptions Name Type Polarity/Bus Size Description PCAP 1 Positive Capacitor connection. This is the positive terminal of the charge pump. A capacitor, with a 2.2 µF recommended value, is required to connect between PCAP and NCAP. If this pin is not used, it must be left unconnected/floating. In this case, no capacitor is needed. Analog charge pump capacitors are not needed if none of the analog SCB features are used, and none of the SDDs are used. PTBASE 1 Pass transistor base connection This is the control signal of the voltage regulator. This pin should be connected to the base of an external pass transistor used with the 1.5 V internal voltage regulator and can be floating if not used. PTEM 1 Pass transistor emitter connection. This is the feedback input of the voltage regulator. This pin should be connected to the emitter of an external pass transistor used with the 1.5 V internal voltage regulator and can be floating if not used. MSS_RESET_N Low Low Reset signal which can be used as an external reset and can also be used as a system level reset under control of the Cortex-M3 processor. MSS_RESET_N is an output asserted low after power-on reset. The direction of MSS_RESET_N changes during the execution of the Microsemi System Boot when chip-level reset is enabled. The Microsemi System Boot reconfigures MSS_RESET_N to become a reset input signal when chip-level reset is enabled. It has an internal pull-up so it can be left floating. In the current software, the MSS_RESET_N is modeled as an external input signal only. PU_N In Low Push-button is the connection for the external momentary switch used to turn on the 1.5 V voltage regulator and can be floating if not used. 5-8 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) JTAG Pins SmartFusion cSoCs have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the SmartFusion cSoC part must be supplied to allow JTAG signals to transition the SmartFusion cSoC. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility with supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned to be used, the VJTAG pin together with the TRSTB pin could be tied to GND. Polarity/ Name Type Bus Size Description JTAGSEL In 1 JTAG controller selection Depending on the state of the JTAGSEL pin, an external JTAG controller will either see the FPGA fabric TAP/auxiliary TAP (High) or the Cortex-M3 JTAG debug interface (Low). The JTAGSEL pin should be connected to an external pull-up resistor such that the default configuration selects the FPGA fabric TAP. TCK In 1 Test clock Serial input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-up/-down resistor. If JTAG is not used, it is recommended to tie off TCK to GND or V through a resistor placed close to the FPGA pin. This prevents JTAG JTAG operation in case TMS enters an undesired state. Note that to operate at all V voltages, 500 Ω to 1 kΩ will satisfy the requirements. JTAG Refer to Table 5-1 on page 5-10 for more information. Can be left floating when unused. TDI In 1 Test data Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin. TDO Out 1 Test data Serial output for JTAG boundary scan, ISP, and UJTAG usage. TMS In HIGH Test mode select The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin. Can be left floating when unused. TRSTB In HIGH Boundary scan reset pin The TRST pin functions as an active low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-down resistor could be included to ensure the TAP is held in reset mode. The resistor values must be chosen from Table 5-1 on page 5-10 and must satisfy the parallel resistance value requirement. The values in Table 5-1 on page 5-10 correspond to the resistor recommended when a single device is used. The values correspond to the equivalent parallel resistor when multiple devices are connected via a JTAG chain. In critical applications, an upset in the JTAG circuit could allow entering an undesired JTAG state. In such cases, it is recommended that you tie off TRST to GND through a resistor placed close to the FPGA pin. The TRSTB pin also resets the serial wire JTAG – debug port (SWJ-DP) circuitry within the Cortex-M3. Can be left floating when unused. Revision 8 5-9 Pin Descriptions Table 5-1 • Recommended Tie-Off Values for the TCK and TRST Pins 1, 2 VJTAG Tie-Off Resistance VJTAG at 3.3 V 200 Ω to 1 kΩ VJTAG at 2.5 V 200 Ω to 1 kΩ VJTAG at 1.8 V 500 Ω to 1 kΩ VJTAG at 1.5 V 500 Ω to 1 kΩ Notes: 1. The TCK pin can be pulled up/down. 2. The TRST pin can only be pulled down. 1. Equivalent parallel resistance if more than one device is on JTAG chain. 5-10 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Microcontroller Subsystem (MSS) Polarity/ Name Type Bus Size Description External Memory Controller EMC_ABx Out 26 External memory controller address bus Can also be used as an FPGA user I/O (see "IO" on page 5-5). EMC_BYTENx Out LOW/2 External memory controller byte enable Can also be used as an FPGA user I/O (see "IO" on page 5-5). EMC_CLK Out Rise External memory controller clock Can also be used as an FPGA user I/O (see "IO" on page 5-5). EMC_CSx_N Out LOW/2 External memory controller chip selects Can also be used as an FPGA User IO (see "IO" on page 5-5). EMC_DBx In/out 16 External memory controller data bus Can also be used as an FPGA user I/O (see "IO" on page 5-5). EMC_OENx_N Out LOW/2 External memory controller output enables Can also be used as an FPGA User IO (see "IO" on page 5-5). EMC_RW_N Out Level External memory controller read/write. Read = High, write = Low. Can also be used as an FPGA user I/O (see "IO" on page 5-5). 2 Inter-Integrated Circuit (I C) Peripherals 2 2 I2C_0_SCL In/out 1 I C bus serial clock output. First I C. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). 2 2 I2C_0_SDA In/out 1 I C bus serial data input/output. First I C. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). 2 2 I2C_1_SCL In/out 1 I C bus serial clock output. Second I C. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). 2 2 I2C_1_SDA In/out 1 I C bus serial data input/output. Second I C. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). Serial Peripheral Interface (SPI) Controllers SPI_0_CLK Out 1 Clock. First SPI. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). SPI_0_DI In 1 Data input. First SPI. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). SPI_0_DO Out 1 Data output. First SPI. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). SPI_0_SS Out 1 Slave select (chip select). First SPI. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). SPI_1_CLK Out 1 Clock. Second SPI. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). SPI_1_DI In 1 Data input. Second SPI. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). Revision 8 5-11 Pin Descriptions Polarity/ Name Type Bus Size Description SPI_1_DO Out 1 Data output. Second SPI. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). SPI_1_SS Out 1 Slave select (chip select). Second SPI. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). Universal Asynchronous Receiver/Transmitter (UART) Peripherals UART_0_RXD In 1 Receive data. First UART. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). UART_0_TXD Out 1 Transmit data. First UART. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). UART_1_RXD In 1 Receive data. Second UART. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). UART_1_TXD Out 1 Transmit data. Second UART. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5). Ethernet MAC MAC_CLK In Rise Receive clock. 50 MHz ± 50 ppm clock source received from RMII PHY. Can be left floating when unused. MAC_CRSDV In High Carrier sense/receive data valid for RMII PHY Can also be used as an FPGA User IO (see "IO" on page 5-5). MAC_MDC Out Rise RMII management clock Can also be used as an FPGA User IO (see "IO" on page 5-5). MAC_MDIO In/Out 1 RMII management data input/output Can also be used as an FPGA User IO (see "IO" on page 5-5). MAC_RXDx In 2 Ethernet MAC receive data. Data recovered and decoded by PHY. The RXD[0] signal is the least significant bit. Can also be used as an FPGA User I/O (see "IO" on page 5-5). MAC_RXER In HIGH Ethernet MAC receive error. If MACRX_ER is asserted during reception, the frame is received and status of the frame is updated with MACRX_ER. Can also be used as an FPGA user I/O (see "IO" on page 5-5). MAC_TXDx Out 2 Ethernet MAC transmit data. The TXD[0] signal is the least significant bit. Can also be used as an FPGA user I/O (see "IO" on page 5-5). MAC_TXEN Out HIGH Ethernet MAC transmit enable. When asserted, indicates valid data for the PHY on the TXD port. Can also be used as an FPGA User I/O (see "IO" on page 5-5). 5-12 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Analog Front-End (AFE) Associated With Name Type Description ADC/SDD SCB ABPS0 In SCB 0 / active bipolar prescaler input 1. ADC0 SCB0 See the Active Bipolar Prescaler (ABPS) section in the SmartFusion Programmable Analog User’s Guide. ABPS1 In SCB 0 / active bipolar prescaler Input 2 ADC0 SCB0 ABPS2 In SCB 1 / active bipolar prescaler Input 1 ADC0 SCB1 ABPS3 In SCB 1 / active bipolar prescaler Input 2 ADC0 SCB1 ABPS4 In SCB 2 / active bipolar prescaler Input 1 ADC1 SCB2 ABPS5 In SCB 2 / active bipolar prescaler Input 2 ADC1 SCB2 ABPS6 In SCB 3 / active bipolar prescaler Input 1 ADC1 SCB3 ABPS7 In SCB 3 / active bipolar prescaler input 2 ADC1 SCB3 ABPS8 In SCB 4 / active bipolar prescaler input 1 ADC2 SCB4 ABPS9 In SCB 4 / active bipolar prescaler input 2 ADC2 SCB4 ADC0 In ADC 0 direct input 0 / FPGA Input. ADC0 SCB0 See the "Sigma-Delta Digital-to-Analog Converter (DAC)" section in the SmartFusion Programmable Analog User’s Guide. ADC1 In ADC 0 direct input 1 / FPGA input ADC0 SCB0 ADC2 In ADC 0 direct input 2 / FPGA input ADC0 SCB1 ADC3 In ADC 0 direct input 3 / FPGA input ADC0 SCB1 ADC4 In ADC 1 direct input 0 / FPGA input ADC1 SCB2 ADC5 In ADC 1 direct input 1 / FPGA input ADC1 SCB2 ADC6 In ADC 1 direct input 2 / FPGA input ADC1 SCB3 ADC7 In ADC 1 direct input 3 / FPGA input ADC1 SCB3 ADC8 In ADC 2 direct input 0 / FPGA input ADC2 SCB4 ADC9 In ADC 2 direct input 1 / FPGA input ADC2 SCB4 ADC10 In ADC 2 direct input 2 / FPGA input ADC2 N/A ADC11 In ADC 2 direct input 3 / FPGA input ADC2 N/A CM0 In SCB 0 / high side of current monitor / comparator ADC0 SCB0 Positive input. See the Current Monitor section in the SmartFusion Programmable Analog User’s Guide. CM1 In SCB 1 / high side of current monitor / comparator. Positive input. ADC0 SCB1 CM2 In SCB 2 / high side of current monitor / comparator. Positive input. ADC1 SCB2 CM3 In SCB 3 / high side of current monitor / comparator. Positive input. ADC1 SCB3 CM4 In SCB 4 / high side of current monitor / comparator. Positive input. ADC2 SCB4 Note: Unused analog inputs should be grounded. This aids in shielding and prevents an undesired coupling path. Revision 8 5-13 Pin Descriptions Associated With Name Type Description ADC/SDD SCB TM0 In SCB 0 / low side of current monitor / comparator ADC0 SCB0 Negative input / high side of temperature monitor. See the Temperature Monitor section. TM1 In SCB 1 / low side of current monitor / comparator. Negative input / ADC0 SCB1 high side of temperature monitor. TM2 In SCB 2 / low side of current monitor / comparator. Negative input / ADC1 SCB2 high side of temperature monitor. TM3 In SCB 3 low side of current monitor / comparator. Negative input / high ADC1 SCB3 side of temperature monitor. TM4 In SCB 4 low side of current monitor / comparator. Negative input / high ADC2 SCB4 side of temperature monitor. SDD0 Out Output of SDD0 SDD0 N/A See the Sigma-Delta Digital-to-Analog Converter (DAC) section in the SmartFusion Programmable Analog User’s Guide. SDD1 Out Output of SDD1 SDD1 N/A SDD2 Out Output of SDD2 SDD2 N/A Note: Unused analog inputs should be grounded. This aids in shielding and prevents an undesired coupling path. 5-14 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Analog Front-End Pin-Level Function Multiplexing Table 5-2 describes the relationships between the various internal signals found in the analog front-end (AFE) and how they are multiplexed onto the external package pins. Note that, in general, only one function is available for those pads that have numerous functions listed. The exclusion to this rule is when a comparator is used; the ADC can still convert either input side of the comparator. Table 5-2 • Relationships Between Signals in the Analog Front-End ADC Dir.-In Current Temp. Pin Channel Option Prescaler Mon. Mon. Compar. LVTTL SDD MUX SDD ABPS0 ADC0_CH1 ABPS0_IN ABPS1 ADC0_CH2 ABPS1_IN ABPS2 ADC0_CH5 ABPS2_IN ABPS3 ADC0_CH6 ABPS3_IN ABPS4 ADC1_CH1 ABPS4_IN ABPS5 ADC1_CH2 ABPS5_IN ABPS6 ADC1_CH5 ABPS6_IN ABPS7 ADC1_CH6 ABPS7_IN ABPS8 ADC2_CH1 ABPS8_IN ABPS9 ADC2_CH2 ABPS9_IN ADC0 ADC0_CH9 Yes CMP1_P LVTTL0_IN ADC1 ADC0_CH10 Yes CMP1_N LVTTL1_IN SDDM0_OUT ADC2 ADC0_CH11 Yes CMP3_P LVTTL2_IN ADC3 ADC0_CH12 Yes CMP3_N LVTTL3_IN SDDM1_OUT ADC4 ADC1_CH9 Yes CMP5_P LVTTL4_IN ADC5 ADC1_CH10 Yes CMP5_N LVTTL5_IN SDDM2_OUT ADC6 ADC1_CH11 Yes CMP7_P LVTTL6_IN ADC7 ADC1_CH12 Yes CMP7_N LVTTL7_IN SDDM3_OUT ADC8 ADC2_CH9 Yes CMP9_P LVTTL8_IN ADC9 ADC2_CH10 Yes CMP9_N LVTTL9_IN SDDM4_OUT ADC10 ADC2_CH11 Yes LVTTL10_IN ADC11 ADC2_CH12 Yes LVTTL11_IN CM0 ADC0_CH3 Yes CM0_H CMP0_P CM1 ADC0_CH7 Yes CM1_H CMP2_P CM2 ADC1_CH3 Yes CM2_H CMP4_P CM3 ADC1_CH7 Yes CM3_H CMP6_P CM4 ADC2_CH3 Yes CM4_H CMP8_P SDD0 ADC0_CH15 SDD0_OUT SDD1 ADC1_CH15 SDD1_OUT Notes: 1. ABPSx_IN: Input to active bipolar prescaler channel x. 2. CMx_H/L: Current monitor channel x, high/low side. 3. TMx_IO: Temperature monitor channel x. 4. CMPx_P/N: Comparator channel x, positive/negative input. 5. LVTTLx_IN: LVTTL I/O channel x. 6. SDDMx_OUT: Output from sigma-delta DAC MUX channel x. 7. SDDx_OUT: Direct output from sigma-delta DAC channel x. Revision 8 5-15 Pin Descriptions Table 5-2 • Relationships Between Signals in the Analog Front-End ADC Dir.-In Current Temp. Pin Channel Option Prescaler Mon. Mon. Compar. LVTTL SDD MUX SDD SDD2 ADC2_CH15 SDD2_OUT TM0 ADC0_CH4 Yes CM0_L TM0_IO CMP0_N TM1 ADC0_CH8 Yes CM1_L TM1_IO CMP2_N TM2 ADC1_CH4 Yes CM2_L TM2_IO CMP4_N TM3 ADC1_CH8 Yes CM3_L TM3_IO CMP6_N TM4 ADC2_CH4 Yes CM4_L TM4_IO CMP8_N Notes: 1. ABPSx_IN: Input to active bipolar prescaler channel x. 2. CMx_H/L: Current monitor channel x, high/low side. 3. TMx_IO: Temperature monitor channel x. 4. CMPx_P/N: Comparator channel x, positive/negative input. 5. LVTTLx_IN: LVTTL I/O channel x. 6. SDDMx_OUT: Output from sigma-delta DAC MUX channel x. 7. SDDx_OUT: Direct output from sigma-delta DAC channel x. 5-16 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Pin Assignment Tables TQ144 144 1 144-Pin TQFP Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solu- tions/package/docs.aspx. Revision 8 5-17 Pin Descriptions TQ144 TQ144 Pin Number A2F060 Function Pin Number A2F060 Function 1 VCCPLL0 37 VCC33AP 2VCOMPLA0 38 VCC33N 3 GNDQ 39 SDD0 4 GFA2/IO42PDB5V0 40 GNDA 5 GFB2/IO42NDB5V0 41 GNDAQ 6 GFC2/IO41PDB5V0 42 GNDAQ 7 IO41NDB5V0 43 ADC0 8VCC 44 ADC1 9GND 45 ADC2 10 VCCFPGAIOB5 46 ADC3 11 IO38PDB5V0 47 ADC4 12 IO38NDB5V0 48 ADC5 13 IO36PDB5V0 49 ADC6 14 IO36NDB5V0 50 ADC7 15 GND 51 ADC8 16 GNDRCOSC 52 ADC9 17 VCCRCOSC 53 ADC10 18 MSS_RESET_N 54 NC 19 GPIO_0/IO33RSB4V0 55 NC 20 GPIO_1/IO32RSB4V0 56 NC 21 GPIO_2/IO31RSB4V0 57 GND15ADC0 22 GPIO_3/IO30RSB4V0 58 VCC15ADC0 23 GPIO_4/IO29RSB4V0 59 GND33ADC0 24 GND 60 VCC33ADC0 25 VCCMSSIOB4 61 GND33ADC0 26 VCC 62 VAREF0 27 GPIO_5/IO28RSB4V0 63 ABPS0 28 GPIO_6/IO27RSB4V0 64 ABPS1 29 GPIO_7/IO26RSB4V0 65 CM0 30 GPIO_8/IO25RSB4V0 66 TM0 31 VCCESRAM 67 GNDTM0 32 GNDSDD0 68 GNDAQ 33 VCC33SDD0 69 GNDA 34 VCC15A 70 GNDVAREF 35 PCAP 71 VAREFOUT 36 NCAP 72 PU_N 5-18 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) TQ144 TQ144 Pin Number A2F060 Function Pin Number A2F060 Function 73 VCC33A 109 VPP 74 PTEM 110 GNDQ 75 PTBASE 111 GCA1/IO20PDB0V0 76 SPI_0_DO/GPIO_16 112 GCA0/IO20NDB0V0 77 SPI_0_DI/GPIO_17 113 GCB1/IO19PDB0V0 78 SPI_0_CLK/GPIO_18 114 GCB0/IO19NDB0V0 79 SPI_0_SS/GPIO_19 115 GCC1/IO18PDB0V0 80 UART_0_RXD/GPIO_21 116 GCC0/IO18NDB0V0 81 UART_0_TXD/GPIO_20 117 VCCFPGAIOB0 82 UART_1_RXD/GPIO_29 118 GND 83 UART_1_TXD/GPIO_28 119 VCC 84 VCC 120 IO14PDB0V0 85 VCCMSSIOB2 121 IO14NDB0V0 86 GND 122 IO13NSB0V0 87 I2C_1_SDA/GPIO_30 123 IO11PDB0V0 88 I2C_1_SCL/GPIO_31 124 IO11NDB0V0 89 I2C_0_SDA/GPIO_22 125 IO09PDB0V0 90 I2C_0_SCL/GPIO_23 126 IO09NDB0V0 91 GNDENVM 127 VCCFPGAIOB0 92 VCCENVM 128 GND 93 JTAGSEL 129 IO07PDB0V0 94 TCK 130 IO07NDB0V0 95 TDI 131 IO06PDB0V0 96 TMS 132 IO06NDB0V0 97 TDO 133 IO05PDB0V0 98 TRSTB 134 IO05NDB0V0 99 VJTAG 135 IO03PDB0V0 100 VDDBAT 136 IO03NDB0V0 101 VCCLPXTAL 137 VCCFPGAIOB0 102 LPXOUT 138 GND 103 LPXIN 139 VCC 104 GNDLPXTAL 140 IO01PDB0V0 105 GNDMAINXTAL 141 IO01NDB0V0 106 MAINXOUT 142 IO00PDB0V0 107 MAINXIN 143 IO00NDB0V0 108 VCCMAINXTAL 144 GNDQ Revision 8 5-19 Pin Descriptions CS288 A1 Ball Pad Corner 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA Note: Bottom view Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 5-20 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) CS288 Pin No. A2F060 Function A2F200 Function A2F500 Function A1 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 A2 GNDQ GNDQ GNDQ A3 EMC_CLK/IO00NDB0V0 EMC_CLK/GAA0/IO00NDB0V0 EMC_CLK/GAA0/IO02NDB0V0 A4 EMC_RW_N/IO00PDB0V0 EMC_RW_N/GAA1/IO00PDB0V0 EMC_RW_N/GAA1/IO02PDB0V0 A5 GND GND GND A6 EMC_CS1_N/IO01PDB0V0 EMC_CS1_N/GAB1/IO01PDB0V0 EMC_CS1_N/GAB1/IO05PDB0V0 A7 EMC_CS0_N/IO01NDB0V0 EMC_CS0_N/GAB0/IO01NDB0V0 EMC_CS0_N/GAB0/IO05NDB0V0 A8 EMC_AB[0]/IO04NPB0V0 EMC_AB[0]/IO04NPB0V0 EMC_AB[0]/IO06NPB0V0 A9 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 A10 EMC_AB[4]/IO06NDB0V0 EMC_AB[4]/IO06NDB0V0 EMC_AB[4]/IO10NDB0V0 A11 EMC_AB[8]/IO08NPB0V0 EMC_AB[8]/IO08NPB0V0 EMC_AB[8]/IO13NPB0V0 A12 EMC_AB[14]/IO11NPB0V0 EMC_AB[14]/IO11NPB0V0 EMC_AB[14]/IO15NPB0V0 A13 GND GND GND A14 EMC_AB[18]/IO13NDB0V0 EMC_AB[18]/IO13NDB0V0 EMC_AB[18]/IO18NDB0V0 A15 EMC_AB[24]/IO16NDB0V0 EMC_AB[24]/IO16NDB0V0 EMC_AB[24]/IO20NDB0V0 A16 EMC_AB[25]/IO16PDB0V0 EMC_AB[25]/IO16PDB0V0 EMC_AB[25]/IO20PDB0V0 A17 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 A18 EMC_AB[20]/IO14NDB0V0 EMC_AB[20]/IO14NDB0V0 EMC_AB[20]/IO21NDB0V0 A19 EMC_AB[21]/IO14PDB0V0 EMC_AB[21]/IO14PDB0V0 EMC_AB[21]/IO21PDB0V0 A20 GNDQ GNDQ GNDQ A21 GND GND GND AA1 ADC1 ABPS1 ABPS1 AA2 GNDAQ GNDAQ GNDAQ AA3 GNDA GNDA GNDA AA4 VCC33N VCC33N VCC33N AA5 SDD0 SDD0 SDD0 AA6 ADC0 ABPS0 ABPS0 AA7 NC GNDTM0 GNDTM0 AA8 NC ABPS2 ABPS2 AA9 NC VAREF0 VAREF0 AA10 NC GND15ADC0 GND15ADC0 AA11 ADC9 ADC6 ADC6 AA12 ABPS1 ABPS7 ABPS7 AA13 ADC6 TM2 TM2 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-21 Pin Descriptions CS288 Pin No. A2F060 Function A2F200 Function A2F500 Function AA14 NC ABPS4 ABPS4 AA15 NC SDD1 SDD1 AA16 GNDVAREF GNDVAREF GNDVAREF AA17 VAREFOUT VAREFOUT VAREFOUT AA18 PU_N PU_N PU_N AA19 VCC33A VCC33A VCC33A AA20 PTEM PTEM PTEM AA21 GND GND GND B1 GND GND GND B21 IO17PDB0V0 GBB2/IO20NDB1V0 GBB2/IO27NDB1V0 C1 EMC_DB[15]/IO45PDB5V0 EMC_DB[15]/GAA2/IO71PDB5V0 EMC_DB[15]/GAA2/IO88PDB5V0 C3 VCOMPLA0 VCOMPLA VCOMPLA0 C4 VCCPLL0 VCCPLL VCCPLL0 C5 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 C6 EMC_AB[1]/IO04PPB0V0 EMC_AB[1]/IO04PPB0V0 EMC_AB[1]/IO06PPB0V0 C7 GND GND GND C8 EMC_OEN0_N/IO03NDB0V0 EMC_OEN0_N/IO03NDB0V0 EMC_OEN0_N/IO08NDB0V0 C9 EMC_AB[2]/IO05NDB0V0 EMC_AB[2]/IO05NDB0V0 EMC_AB[2]/IO09NDB0V0 C10 EMC_AB[5]/IO06PDB0V0 EMC_AB[5]/IO06PDB0V0 EMC_AB[5]/IO10PDB0V0 C11 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 C12 EMC_AB[9]/IO08PPB0V0 EMC_AB[9]/IO08PPB0V0 EMC_AB[9]/IO13PPB0V0 C13 EMC_AB[15]/IO11PPB0V0 EMC_AB[15]/IO11PPB0V0 EMC_AB[15]/IO15PPB0V0 C14 EMC_AB[19]/IO13PDB0V0 EMC_AB[19]/IO13PDB0V0 EMC_AB[19]/IO18PDB0V0 C15 GND GND GND C16 EMC_AB[22]/IO15NDB0V0 EMC_AB[22]/IO15NDB0V0 EMC_AB[22]/IO19NDB0V0 C17 EMC_AB[23]/IO15PDB0V0 EMC_AB[23]/IO15PDB0V0 EMC_AB[23]/IO19PDB0V0 C18 NC NC VCCPLL1 C19 NC NC VCOMPLA1 C21 IO17NDB0V0 GBA2/IO20PDB1V0 GBA2/IO27PDB1V0 D1 EMC_DB[14]/IO45NDB5V0 EMC_DB[14]/GAB2/IO71NDB5V0 EMC_DB[14]/GAB2/IO88NDB5V0 D3 VCCFPGAIOB5 VCCFPGAIOB5 VCCFPGAIOB5 D19 GND GND GND D21 VCCFPGAIOB1 VCCFPGAIOB1 VCCFPGAIOB1 E1 EMC_DB[13]/IO44PDB5V0 EMC_DB[13]/GAC2/IO70PDB5V0 EMC_DB[13]/GAC2/IO87PDB5V0 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 5-22 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) CS288 Pin No. A2F060 Function A2F200 Function A2F500 Function E3 EMC_DB[12]/IO44NDB5V0 EMC_DB[12]/IO70NDB5V0 EMC_DB[12]/IO87NDB5V0 E5 GNDQ GNDQ GNDQ E6 EMC_BYTEN[0]/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO07NDB0V0 E7 EMC_BYTEN[1]/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO07PDB0V0 E8 EMC_OEN1_N/IO03PDB0V0 EMC_OEN1_N/IO03PDB0V0 EMC_OEN1_N/IO08PDB0V0 E9 EMC_AB[3]/IO05PDB0V0 EMC_AB[3]/IO05PDB0V0 EMC_AB[3]/IO09PDB0V0 E10 EMC_AB[10]/IO09NDB0V0 EMC_AB[10]/IO09NDB0V0 EMC_AB[10]/IO11NDB0V0 E11 EMC_AB[7]/IO07PDB0V0 EMC_AB[7]/IO07PDB0V0 EMC_AB[7]/IO12PDB0V0 E12 EMC_AB[13]/IO10PDB0V0 EMC_AB[13]/IO10PDB0V0 EMC_AB[13]/IO14PDB0V0 E13 EMC_AB[16]/IO12NDB0V0 EMC_AB[16]/IO12NDB0V0 EMC_AB[16]/IO17NDB0V0 E14 EMC_AB[17]/IO12PDB0V0 EMC_AB[17]/IO12PDB0V0 EMC_AB[17]/IO17PDB0V0 E15 GCC0/IO18NPB0V0 GCB0/IO27NDB1V0 GCB0/IO34NDB1V0 E16 GCA1/IO20PPB0V0 GCB1/IO27PDB1V0 GCB1/IO34PDB1V0 E17 GCC1/IO18PPB0V0 GCB2/IO24PDB1V0 GCB2/IO33PDB1V0 E19 GCB2/IO22PPB1V0 GCA0/IO28NDB1V0 GCA0/IO36NDB1V0 E21 IO21NDB1V0 GCA1/IO28PDB1V0 GCA1/IO36PDB1V0 F1 VCCFPGAIOB5 VCCFPGAIOB5 VCCFPGAIOB5 F3 GFB2/IO42NDB5V0 GFB2/IO68NDB5V0 GFB2/IO85NDB5V0 F5 GFA2/IO42PDB5V0 GFA2/IO68PDB5V0 GFA2/IO85PDB5V0 F6 EMC_DB[11]/IO43PDB5V0 EMC_DB[11]/IO69PDB5V0 EMC_DB[11]/IO86PDB5V0 F7 GND GND GND F8 NC GFC1/IO66PPB5V0 GFC1/IO83PPB5V0 F9 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 F10 EMC_AB[11]/IO09PDB0V0 EMC_AB[11]/IO09PDB0V0 EMC_AB[11]/IO11PDB0V0 F11 EMC_AB[6]/IO07NDB0V0 EMC_AB[6]/IO07NDB0V0 EMC_AB[6]/IO12NDB0V0 F12 EMC_AB[12]/IO10NDB0V0 EMC_AB[12]/IO10NDB0V0 EMC_AB[12]/IO14NDB0V0 F13 GND GND GND F14 GCB1/IO19PPB0V0 GCC1/IO26PPB1V0 GCC1/IO35PPB1V0 F15 GNDQ GNDQ GNDQ F16 VCCFPGAIOB1 VCCFPGAIOB1 VCCFPGAIOB1 F17 GCB0/IO19NPB0V0 IO24NDB1V0 IO33NDB1V0 F19 IO23NDB1V0 GDB1/IO30PDB1V0 GDB1/IO39PDB1V0 F21 GCA2/IO21PDB1V0 GDB0/IO30NDB1V0 GDB0/IO39NDB1V0 G1 IO41NDB5V0 IO67NDB5V0 IO84NDB5V0 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-23 Pin Descriptions CS288 Pin No. A2F060 Function A2F200 Function A2F500 Function G3 GFC2/IO41PDB5V0 GFC2/IO67PDB5V0 GFC2/IO84PDB5V0 G5 NC GFB1/IO65PDB5V0 GFB1/IO82PDB5V0 G6 EMC_DB[10]/IO43NDB5V0 EMC_DB[10]/IO69NDB5V0 EMC_DB[10]/IO86NDB5V0 G9 NC GFC0/IO66NPB5V0 GFC0/IO83NPB5V0 G13 GCA0/IO20NPB0V0 GCC0/IO26NPB1V0 GCC0/IO35NPB1V0 G16 NC GDA0/IO31NDB1V0 GDA0/IO40NDB1V0 G17 IO22NPB1V0 GDC1/IO29PDB1V0 GDC1/IO38PDB1V0 G19 GCC2/IO23PDB1V0 GDC0/IO29NDB1V0 GDC0/IO38NDB1V0 G21 GND GND GND H1 EMC_DB[9]/IO40PPB5V0 EMC_DB[9]/GEC1/IO63PPB5V0 EMC_DB[9]/GEC1/IO80PPB5V0 H3 GND GND GND H5 NC GFB0/IO65NDB5V0 GFB0/IO82NDB5V0 H6 EMC_DB[7]/IO39PDB5V0 EMC_DB[7]/GEB1/IO62PDB5V0 EMC_DB[7]/GEB1/IO79PDB5V0 H8 GND GND GND H9 VCC VCC VCC H10 GND GND GND H11 VCC VCC VCC H12 GND GND GND H13 VCC VCC VCC H14 GND GND GND H16 NC GDA1/IO31PDB1V0 GDA1/IO40PDB1V0 H17 NC GDC2/IO32PPB1V0 GDC2/IO41PPB1V0 H19 VCCFPGAIOB1 VCCFPGAIOB1 VCCFPGAIOB1 H21 NC GDB2/IO33PDB1V0 GDB2/IO42PDB1V0 J1 EMC_DB[4]/IO38NPB5V0 EMC_DB[4]/GEA0/IO61NPB5V0 EMC_DB[4]/GEA0/IO78NPB5V0 J3 EMC_DB[8]/IO40NPB5V0 EMC_DB[8]/GEC0/IO63NPB5V0 EMC_DB[8]/GEC0/IO80NPB5V0 J5 EMC_DB[1]/IO36PDB5V0 EMC_DB[1]/GEB2/IO59PDB5V0 EMC_DB[1]/GEB2/IO76PDB5V0 J6 EMC_DB[6]/IO39NDB5V0 EMC_DB[6]/GEB0/IO62NDB5V0 EMC_DB[6]/GEB0/IO79NDB5V0 J7 VCCFPGAIOB5 VCCFPGAIOB5 VCCFPGAIOB5 J8 VCC VCC VCC J9 GND GND GND J10 VCC VCC VCC J11 GND GND GND J12 VCC VCC VCC Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 5-24 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) CS288 Pin No. A2F060 Function A2F200 Function A2F500 Function J13 GND GND GND J14 VCC VCC VCC J15 VPP VPP VPP J16 NC IO32NPB1V0 IO41NPB1V0 J17 NC GNDQ GNDQ J19 VCCMAINXTAL VCCMAINXTAL VCCMAINXTAL J21 NC GDA2/IO33NDB1V0 GDA2/IO42NDB1V0 K1 GND GND GND K3 EMC_DB[5]/IO38PPB5V0 EMC_DB[5]/GEA1/IO61PPB5V0 EMC_DB[5]/GEA1/IO78PPB5V0 K5 EMC_DB[0]/IO36NDB5V0 EMC_DB[0]/GEA2/IO59NDB5V0 EMC_DB[0]/GEA2/IO76NDB5V0 K6 EMC_DB[3]/IO37PPB5V0 EMC_DB[3]/GEC2/IO60PPB5V0 EMC_DB[3]/GEC2/IO77PPB5V0 K8 GND GND GND K9 VCC VCC VCC K10 GND GND GND K11 VCC VCC VCC K12 GND GND GND K13 VCC VCC VCC K14 GND GND GND K16 LPXOUT LPXOUT LPXOUT K17 GNDLPXTAL GNDLPXTAL GNDLPXTAL K19 GNDMAINXTAL GNDMAINXTAL GNDMAINXTAL K21 MAINXIN MAINXIN MAINXIN L1 GNDRCOSC GNDRCOSC GNDRCOSC L3 VCCFPGAIOB5 VCCFPGAIOB5 VCCFPGAIOB5 L5 EMC_DB[2]/IO37NPB5V0 EMC_DB[2]/IO60NPB5V0 EMC_DB[2]/IO77NPB5V0 L6 NC GNDQ GNDQ L8 VCC VCC VCC L9 GND GND GND L10 VCC VCC VCC L12 VCC VCC VCC L13 GND GND GND L14 VCC VCC VCC L16 VCCLPXTAL VCCLPXTAL VCCLPXTAL L17 VDDBAT VDDBAT VDDBAT Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-25 Pin Descriptions CS288 Pin No. A2F060 Function A2F200 Function A2F500 Function L19 LPXIN LPXIN LPXIN L21 MAINXOUT MAINXOUT MAINXOUT M1 VCCRCOSC VCCRCOSC VCCRCOSC M3 MSS_RESET_N MSS_RESET_N MSS_RESET_N M5 GPIO_5/IO28RSB4V0 GPIO_5/IO42RSB4V0 GPIO_5/IO51RSB4V0 M6 GND GND GND M8 GND GND GND M9 VCC VCC VCC M10 GND GND GND M11 VCC VCC VCC M12 GND GND GND M13 VCC VCC VCC M14 GND GND GND M16 TMS TMS TMS M17 VJTAG VJTAG VJTAG M19 TDO TDO TDO M21 TRSTB TRSTB TRSTB N1 VCCMSSIOB4 VCCMSSIOB4 VCCMSSIOB4 N3 GND GND GND N5 GPIO_4/IO29RSB4V0 GPIO_4/IO43RSB4V0 GPIO_4/IO52RSB4V0 N6 GPIO_8/IO25RSB4V0 GPIO_8/IO39RSB4V0 GPIO_8/IO48RSB4V0 N7 GPIO_9/IO24RSB4V0 GPIO_9/IO38RSB4V0 GPIO_9/IO47RSB4V0 N8 VCC VCC VCC N9 GND GND GND N10 VCC VCC VCC N11 GND GND GND N12 VCC VCC VCC N13 GND GND GND N14 VCC VCC VCC N15 GND GND GND N16 TCK TCK TCK N17 TDI TDI TDI N19 GNDENVM GNDENVM GNDENVM N21 VCCENVM VCCENVM VCCENVM Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 5-26 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) CS288 Pin No. A2F060 Function A2F200 Function A2F500 Function P1 GPIO_0/IO33RSB4V0 MAC_MDC/IO48RSB4V0 MAC_MDC/IO57RSB4V0 P3 GPIO_7/IO26RSB4V0 GPIO_7/IO40RSB4V0 GPIO_7/IO49RSB4V0 P5 GPIO_6/IO27RSB4V0 GPIO_6/IO41RSB4V0 GPIO_6/IO50RSB4V0 P6 VCCMSSIOB4 VCCMSSIOB4 VCCMSSIOB4 P8 GND GND GND P9 VCC VCC VCC P10 GND GND GND P11 VCC VCC VCC P12 GND GND GND P13 VCC VCC VCC P14 GND GND GND P16 JTAGSEL JTAGSEL JTAGSEL P17 I2C_0_SCL/GPIO_23 I2C_0_SCL/GPIO_23 I2C_0_SCL/GPIO_23 P19 VCCMSSIOB2 VCCMSSIOB2 VCCMSSIOB2 P21 GND GND GND R1 GPIO_2/IO31RSB4V0 MAC_MDIO/IO49RSB4V0 MAC_MDIO/IO58RSB4V0 R3 GPIO_1/IO32RSB4V0 MAC_TXEN/IO52RSB4V0 MAC_TXEN/IO61RSB4V0 R5 GPIO_3/IO30RSB4V0 MAC_TXD[0]/IO56RSB4V0 MAC_TXD[0]/IO65RSB4V0 R6 GPIO_10/IO35RSB4V0 MAC_CRSDV/IO51RSB4V0 MAC_CRSDV/IO60RSB4V0 R9 GNDA GNDA GNDA R13 GNDA GNDA GNDA R16 UART_1_RXD/GPIO_29 UART_1_RXD/GPIO_29 UART_1_RXD/GPIO_29 R17 UART_1_TXD/GPIO_28 UART_1_TXD/GPIO_28 UART_1_TXD/GPIO_28 R19 I2C_0_SDA/GPIO_22 I2C_0_SDA/GPIO_22 I2C_0_SDA/GPIO_22 R21 I2C_1_SDA/GPIO_30 I2C_1_SDA/GPIO_30 I2C_1_SDA/GPIO_30 T1 GND GND GND T3 NC MAC_TXD[1]/IO55RSB4V0 MAC_TXD[1]/IO64RSB4V0 T5 NC MAC_RXD[1]/IO53RSB4V0 MAC_RXD[1]/IO62RSB4V0 T6 GPIO_11/IO34RSB4V0 MAC_RXER/IO50RSB4V0 MAC_RXER/IO59RSB4V0 T7 NC CM1 CM1 T8 NC ADC1 ADC1 T9 NC GND33ADC0 GND33ADC0 T10 NC VCC15ADC0 VCC15ADC0 T11 GND33ADC0 GND33ADC1 GND33ADC1 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-27 Pin Descriptions CS288 Pin No. A2F060 Function A2F200 Function A2F500 Function T12 VAREF0 VAREF1 VAREF1 T13 ADC7 ADC4 ADC4 T14 TM0 TM3 TM3 T15 SPI_1_SS/GPIO_27 SPI_1_SS/GPIO_27 SPI_1_SS/GPIO_27 T16 VCCMSSIOB2 VCCMSSIOB2 VCCMSSIOB2 T17 UART_0_RXD/GPIO_21 UART_0_RXD/GPIO_21 UART_0_RXD/GPIO_21 T19 UART_0_TXD/GPIO_20 UART_0_TXD/GPIO_20 UART_0_TXD/GPIO_20 T21 I2C_1_SCL/GPIO_31 I2C_1_SCL/GPIO_31 I2C_1_SCL/GPIO_31 U1 NC MAC_RXD[0]/IO54RSB4V0 MAC_RXD[0]/IO63RSB4V0 U3 VCCMSSIOB4 VCCMSSIOB4 VCCMSSIOB4 U5 VCC33SDD0 VCC33SDD0 VCC33SDD0 U6 VCC15A VCC15A VCC15A U7 NC ABPS3 ABPS3 U8 NC ADC2 ADC2 U9 NC VCC33ADC0 VCC33ADC0 U10 GND15ADC0 GND15ADC1 GND15ADC1 U11 VCC33ADC0 VCC33ADC1 VCC33ADC1 U12 ADC10 ADC7 ADC7 U13 ABPS0 ABPS6 ABPS6 U14 GNDTM0 GNDTM1 GNDTM1 U15 SPI_1_CLK/GPIO_26 SPI_1_CLK/GPIO_26 SPI_1_CLK/GPIO_26 U16 SPI_0_CLK/GPIO_18 SPI_0_CLK/GPIO_18 SPI_0_CLK/GPIO_18 U17 SPI_0_SS/GPIO_19 SPI_0_SS/GPIO_19 SPI_0_SS/GPIO_19 U19 GND GND GND U21 SPI_1_DO/GPIO_24 SPI_1_DO/GPIO_24 SPI_1_DO/GPIO_24 V1 NC MAC_CLK MAC_CLK V3 GNDSDD0 GNDSDD0 GNDSDD0 V19 SPI_1_DI/GPIO_25 SPI_1_DI/GPIO_25 SPI_1_DI/GPIO_25 V21 VCCMSSIOB2 VCCMSSIOB2 VCCMSSIOB2 W1 PCAP PCAP PCAP W3 NCAP NCAP NCAP W4 ADC2 CM0 CM0 W5 ADC3 TM0 TM0 W6 ADC4 TM1 TM1 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 5-28 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) CS288 Pin No. A2F060 Function A2F200 Function A2F500 Function W7 NC ADC0 ADC0 W8 NC ADC3 ADC3 W9 NC GND33ADC0 GND33ADC0 W10 VCC15ADC0 VCC15ADC1 VCC15ADC1 W11 GND33ADC0 GND33ADC1 GND33ADC1 W12 ADC8 ADC5 ADC5 W13 CM0 CM3 CM3 W14 ADC5 CM2 CM2 W15 NC ABPS5 ABPS5 W16 GNDAQ GNDAQ GNDAQ W17 NC VCC33SDD1 VCC33SDD1 W18 NC GNDSDD1 GNDSDD1 W19 PTBASE PTBASE PTBASE W21 SPI_0_DI/GPIO_17 SPI_0_DI/GPIO_17 SPI_0_DI/GPIO_17 Y1 VCC33AP VCC33AP VCC33AP Y21 SPI_0_DO/GPIO_16 SPI_0_DO/GPIO_16 SPI_0_DO/GPIO_16 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-29 Pin Descriptions PQ208 208 1 208-Pin PQFP Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 5-30 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) PQ208 Pin Number A2F200 A2F500 1 VCCPLL VCCPLL0 2 VCOMPLA VCOMPLA0 3 GNDQ GNDQ 4 EMC_DB[15]/GAA2/IO71PDB5V0 GAA2/IO88PDB5V0 5 EMC_DB[14]/GAB2/IO71NDB5V0 GAB2/IO88NDB5V0 6 EMC_DB[13]/GAC2/IO70PDB5V0 GAC2/IO87PDB5V0 7 EMC_DB[12]/IO70NDB5V0 IO87NDB5V0 8VCC VCC 9GND GND 10 VCCFPGAIOB5 VCCFPGAIOB5 11 EMC_DB[11]/IO69PDB5V0 IO86PDB5V0 12 EMC_DB[10]/IO69NDB5V0 IO86NDB5V0 13 GFA2/IO68PSB5V0 GFA2/IO85PSB5V0 14 GFA1/IO64PDB5V0 GFA1/IO81PDB5V0 15 GFA0/IO64NDB5V0 GFA0/IO81NDB5V0 16 EMC_DB[9]/GEC1/IO63PDB5V0 GEC1/IO80PDB5V0 17 EMC_DB[8]/GEC0/IO63NDB5V0 GEC0/IO80NDB5V0 18 EMC_DB[7]/GEB1/IO62PDB5V0 GEB1/IO79PDB5V0 19 EMC_DB[6]/GEB0/IO62NDB5V0 GEB0/IO79NDB5V0 20 EMC_DB[5]/GEA1/IO61PDB5V0 GEA1/IO78PDB5V0 21 EMC_DB[4]/GEA0/IO61NDB5V0 GEA0/IO78NDB5V0 22 VCC VCC 23 GND GND 24 VCCFPGAIOB5 VCCFPGAIOB5 25 EMC_DB[3]/GEC2/IO60PDB5V0 GEC2/IO77PDB5V0 26 EMC_DB[2]/IO60NDB5V0 IO77NDB5V0 27 EMC_DB[1]/GEB2/IO59PDB5V0 GEB2/IO76PDB5V0 28 EMC_DB[0]/GEA2/IO59NDB5V0 GEA2/IO76NDB5V0 29 VCC VCC 30 GND GND 31 GNDRCOSC GNDRCOSC 32 VCCRCOSC VCCRCOSC 33 MSS_RESET_N MSS_RESET_N 34 VCCESRAM VCCESRAM 35 MAC_MDC/IO48RSB4V0 MAC_MDC/IO57RSB4V0 36 MAC_MDIO/IO49RSB4V0 MAC_MDIO/IO58RSB4V0 Revision 8 5-31 Pin Descriptions PQ208 Pin Number A2F200 A2F500 37 MAC_TXEN/IO52RSB4V0 MAC_TXEN/IO61RSB4V0 38 MAC_CRSDV/IO51RSB4V0 MAC_CRSDV/IO60RSB4V0 39 MAC_RXER/IO50RSB4V0 MAC_RXER/IO59RSB4V0 40 GND GND 41 VCCMSSIOB4 VCCMSSIOB4 42 VCC VCC 43 MAC_TXD[0]/IO56RSB4V0 MAC_TXD[0]/IO65RSB4V0 44 MAC_TXD[1]/IO55RSB4V0 MAC_TXD[1]/IO64RSB4V0 45 MAC_RXD[0]/IO54RSB4V0 MAC_RXD[0]/IO63RSB4V0 46 MAC_RXD[1]/IO53RSB4V0 MAC_RXD[1]/IO62RSB4V0 47 MAC_CLK MAC_CLK 48 GNDSDD0 GNDSDD0 49 VCC33SDD0 VCC33SDD0 50 VCC15A VCC15A 51 PCAP PCAP 52 NCAP NCAP 53 VCC33AP VCC33AP 54 VCC33N VCC33N 55 SDD0 SDD0 56 GNDA GNDA 57 GNDAQ GNDAQ 58 ABPS0 ABPS0 59 ABPS1 ABPS1 60 CM0 CM0 61 TM0 TM0 62 GNDTM0 GNDTM0 63 TM1 TM1 64 CM1 CM1 65 ABPS3 ABPS3 66 ABPS2 ABPS2 67 ADC0 ADC0 68 ADC1 ADC1 69 ADC2 ADC2 70 ADC3 ADC3 71 VAREF0 VAREF0 72 GND33ADC0 GND33ADC0 5-32 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) PQ208 Pin Number A2F200 A2F500 73 VCC33ADC0 VCC33ADC0 74 GND33ADC0 GND33ADC0 75 VCC15ADC0 VCC15ADC0 76 GND15ADC0 GND15ADC0 77 GND15ADC1 GND15ADC1 78 VCC15ADC1 VCC15ADC1 79 GND33ADC1 GND33ADC1 80 VCC33ADC1 VCC33ADC1 81 GND33ADC1 GND33ADC1 82 VAREF1 VAREF1 83 ADC7 ADC7 84 ADC6 ADC6 85 ADC5 ADC5 86 ADC4 ADC4 87 ABPS6 ABPS6 88 ABPS7 ABPS7 89 CM3 CM3 90 TM3 TM3 91 GNDTM1 GNDTM1 92 TM2 TM2 93 CM2 CM2 94 ABPS5 ABPS5 95 ABPS4 ABPS4 96 GNDAQ GNDAQ 97 GNDA GNDA 98 NC NC 99 GNDVAREF GNDVAREF 100 VAREFOUT VAREFOUT 101 PU_N PU_N 102 VCC33A VCC33A 103 PTEM PTEM 104 PTBASE PTBASE 105 SPI_0_DO/GPIO_16 SPI_0_DO/GPIO_16 106 SPI_0_DI/GPIO_17 SPI_0_DI/GPIO_17 107 SPI_0_CLK/GPIO_18 SPI_0_CLK/GPIO_18 108 SPI_0_SS/GPIO_19 SPI_0_SS/GPIO_19 Revision 8 5-33 Pin Descriptions PQ208 Pin Number A2F200 A2F500 109 UART_0_RXD/GPIO_21 UART_0_RXD/GPIO_21 110 UART_0_TXD/GPIO_20 UART_0_TXD/GPIO_20 111 UART_1_RXD/GPIO_29 UART_1_RXD/GPIO_29 112 UART_1_TXD/GPIO_28 UART_1_TXD/GPIO_28 113 VCC VCC 114 VCCMSSIOB2 VCCMSSIOB2 115 GND GND 116 I2C_1_SDA/GPIO_30 I2C_1_SDA/GPIO_30 117 I2C_1_SCL/GPIO_31 I2C_1_SCL/GPIO_31 118 I2C_0_SDA/GPIO_22 I2C_0_SDA/GPIO_22 119 I2C_0_SCL/GPIO_23 I2C_0_SCL/GPIO_23 120 GNDENVM GNDENVM 121 VCCENVM VCCENVM 122 JTAGSEL JTAGSEL 123 TCK TCK 124 TDI TDI 125 TMS TMS 126 TDO TDO 127 TRSTB TRSTB 128 VJTAG VJTAG 129 VDDBAT VDDBAT 130 VCCLPXTAL VCCLPXTAL 131 LPXOUT LPXOUT 132 LPXIN LPXIN 133 GNDLPXTAL GNDLPXTAL 134 GNDMAINXTAL GNDMAINXTAL 135 MAINXOUT MAINXOUT 136 MAINXIN MAINXIN 137 VCCMAINXTAL VCCMAINXTAL 138 GND GND 139 VCC VCC 140 VPP VPP 141 VCCFPGAIOB1 VCCFPGAIOB1 142 GDA0/IO31NDB1V0 GDA0/IO40NDB1V0 143 GDA1/IO31PDB1V0 GDA1/IO40PDB1V0 144 GDC0/IO29NSB1V0 GDC0/IO38NSB1V0 5-34 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) PQ208 Pin Number A2F200 A2F500 145 GCA0/IO28NDB1V0 GCA0/IO36NDB1V0 146 GCA1/IO28PDB1V0 GCA1/IO36PDB1V0 147 VCCFPGAIOB1 VCCFPGAIOB1 148 GND GND 149 VCC VCC 150 IO25NDB1V0 IO30NDB1V0 151 GCC2/IO25PDB1V0 GBC2/IO30PDB1V0 152 IO23NDB1V0 IO28NDB1V0 153 GCA2/IO23PDB1V0 GCA2/IO28PDB1V0 154 GBC2/IO21PSB1V0 GBB2/IO27NDB1V0 155 GBA2/IO20PSB1V0 GBA2/IO27PDB1V0 156 GNDQ GNDQ 157 GNDQ GNDQ 158 VCCFPGAIOB0 VCCFPGAIOB0 159 GBA1/IO19PDB0V0 GBA1/IO23PDB0V0 160 GBA0/IO19NDB0V0 GBA0/IO23NDB0V0 161 VCCFPGAIOB0 VCCFPGAIOB0 162 GND GND 163 VCC VCC 164 EMC_AB[25]/IO16PDB0V0 IO21PDB0V0 165 EMC_AB[24]/IO16NDB0V0 IO21NDB0V0 166 EMC_AB[23]/IO15PDB0V0 IO20PDB0V0 167 EMC_AB[22]/IO15NDB0V0 IO20NDB0V0 168 EMC_AB[21]/IO14PDB0V0 IO19PDB0V0 169 EMC_AB[20]/IO14NDB0V0 IO19NDB0V0 170 EMC_AB[19]/IO13PDB0V0 IO18PDB0V0 171 EMC_AB[18]/IO13NDB0V0 IO18NDB0V0 172 EMC_AB[17]/IO12PDB0V0 IO17PDB0V0 173 EMC_AB[16]/IO12NDB0V0 IO17NDB0V0 174 VCCFPGAIOB0 VCCFPGAIOB0 175 GND GND 176 VCC VCC 177 EMC_AB[15]/IO11PDB0V0 IO14PDB0V0 178 EMC_AB[14]/IO11NDB0V0 IO14NDB0V0 179 EMC_AB[13]/IO10PDB0V0 IO13PDB0V0 180 EMC_AB[12]/IO10NDB0V0 IO13NDB0V0 Revision 8 5-35 Pin Descriptions PQ208 Pin Number A2F200 A2F500 181 EMC_AB[11]/IO09PDB0V0 IO12PDB0V0 182 EMC_AB[10]/IO09NDB0V0 IO12NDB0V0 183 EMC_AB[9]/IO08PDB0V0 IO11PDB0V0 184 EMC_AB[8]/IO08NDB0V0 IO11NDB0V0 185 EMC_AB[7]/IO07PDB0V0 IO10PDB0V0 186 EMC_AB[6]/IO07NDB0V0 IO10NDB0V0 187 VCCFPGAIOB0 VCCFPGAIOB0 188 GND GND 189 VCC VCC 190 EMC_AB[5]/IO06PDB0V0 IO08PDB0V0 191 EMC_AB[4]/IO06NDB0V0 IO08NDB0V0 192 EMC_AB[3]/IO05PDB0V0 GAC1/IO07PDB0V0 193 EMC_AB[2]/IO05NDB0V0 GAC0/IO07NDB0V0 194 EMC_AB[1]/IO04PDB0V0 IO04PDB0V0 195 EMC_AB[0]/IO04NDB0V0 IO04NDB0V0 196 EMC_OEN1_N/IO03PDB0V0 IO03PDB0V0 197 EMC_OEN0_N/IO03NDB0V0 IO03NDB0V0 198 EMC_BYTEN[1]/GAC1/IO02PDB0V0 GAA1/IO02PDB0V0 199 EMC_BYTEN[0]/GAC0/IO02NDB0V0 GAA0/IO02NDB0V0 200 VCCFPGAIOB0 VCCFPGAIOB0 201 GND GND 202 VCC VCC 203 EMC_CS1_N/GAB1/IO01PDB0V0 IO01PDB0V0 204 EMC_CS0_N/GAB0/IO01NDB0V0 IO01NDB0V0 205 EMC_RW_N/GAA1/IO00PDB0V0 IO00PDB0V0 206 EMC_CLK/GAA0/IO00NDB0V0 IO00NDB0V0 207 VCCFPGAIOB0 VCCFPGAIOB0 208 GNDQ GNDQ 5-36 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) FG256 A1 Ball Pad Corner 14 13 12 11 10 9 7 6 4 3 2 1 16 15 8 5 A B C D E F G H J K L M N P R T Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Revision 8 5-37 Pin Descriptions FG256 Pin No. A2F060 Function A2F200 Function A2F500 Function A1 GND GND GND A2 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 A3 EMC_AB[0]/IO04NDB0V0 EMC_AB[0]/IO04NDB0V0 EMC_AB[0]/IO06NDB0V0 A4 EMC_AB[1]/IO04PDB0V0 EMC_AB[1]/IO04PDB0V0 EMC_AB[1]/IO06PDB0V0 A5 GND GND GND A6 EMC_AB[3]/IO05PDB0V0 EMC_AB[3]/IO05PDB0V0 EMC_AB[3]/IO09PDB0V0 A7 EMC_AB[5]/IO06PDB0V0 EMC_AB[5]/IO06PDB0V0 EMC_AB[5]/IO10PDB0V0 A8 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 A9 GND GND GND A10 EMC_AB[14]/IO11NDB0V0 EMC_AB[14]/IO11NDB0V0 EMC_AB[14]/IO15NDB0V0 A11 EMC_AB[15]/IO11PDB0V0 EMC_AB[15]/IO11PDB0V0 EMC_AB[15]/IO15PDB0V0 A12 GND GND GND A13 EMC_AB[20]/IO14NDB0V0 EMC_AB[20]/IO14NDB0V0 EMC_AB[20]/IO21NDB0V0 A14 EMC_AB[24]/IO16NDB0V0 EMC_AB[24]/IO16NDB0V0 EMC_AB[24]/IO20NDB0V0 A15 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 A16 GND GND GND B1 EMC_DB[15]/IO45PDB5V0 EMC_DB[15]/GAA2/IO71PDB5V0 EMC_DB[15]/GAA2/IO88PDB5V0 B2 GND GND GND B3 EMC_BYTEN[1]/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO07PDB0V0 B4 EMC_OEN0_N/IO03NDB0V0 EMC_OEN0_N/IO03NDB0V0 EMC_OEN0_N/IO08NDB0V0 B5 EMC_OEN1_N/IO03PDB0V0 EMC_OEN1_N/IO03PDB0V0 EMC_OEN1_N/IO08PDB0V0 B6 EMC_AB[2]/IO05NDB0V0 EMC_AB[2]/IO05NDB0V0 EMC_AB[2]/IO09NDB0V0 B7 EMC_AB[4]/IO06NDB0V0 EMC_AB[4]/IO06NDB0V0 EMC_AB[4]/IO10NDB0V0 B8 EMC_AB[9]/IO08PDB0V0 EMC_AB[9]/IO08PDB0V0 EMC_AB[9]/IO13PDB0V0 B9 EMC_AB[12]/IO10NDB0V0 EMC_AB[12]/IO10NDB0V0 EMC_AB[12]/IO14NDB0V0 B10 EMC_AB[13]/IO10PDB0V0 EMC_AB[13]/IO10PDB0V0 EMC_AB[13]/IO14PDB0V0 B11 EMC_AB[16]/IO12NDB0V0 EMC_AB[16]/IO12NDB0V0 EMC_AB[16]/IO17NDB0V0 B12 EMC_AB[18]/IO13NDB0V0 EMC_AB[18]/IO13NDB0V0 EMC_AB[18]/IO18NDB0V0 B13 EMC_AB[21]/IO14PDB0V0 EMC_AB[21]/IO14PDB0V0 EMC_AB[21]/IO21PDB0V0 B14 EMC_AB[25]/IO16PDB0V0 EMC_AB[25]/IO16PDB0V0 EMC_AB[25]/IO20PDB0V0 B15 GND GND GND B16 GNDQ GNDQ GNDQ C1 EMC_DB[14]/IO45NDB5V0 EMC_DB[14]/GAB2/IO71NDB5V0 EMC_DB[14]/GAB2/IO88NDB5V0 C2 VCCPLL0 VCCPLL VCCPLL0 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 5-38 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) FG256 Pin No. A2F060 Function A2F200 Function A2F500 Function C3 EMC_BYTEN[0]/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO07NDB0V0 C4 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 C5 EMC_CS0_N/IO01NDB0V0 EMC_CS0_N/GAB0/IO01NDB0V0 EMC_CS0_N/GAB0/IO05NDB0V0 C6 EMC_CS1_N/IO01PDB0V0 EMC_CS1_N/GAB1/IO01PDB0V0 EMC_CS1_N/GAB1/IO05PDB0V0 C7 GND GND GND C8 EMC_AB[8]/IO08NDB0V0 EMC_AB[8]/IO08NDB0V0 EMC_AB[8]/IO13NDB0V0 C9 EMC_AB[11]/IO09PDB0V0 EMC_AB[11]/IO09PDB0V0 EMC_AB[11]/IO11PDB0V0 C10 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 C11 EMC_AB[17]/IO12PDB0V0 EMC_AB[17]/IO12PDB0V0 EMC_AB[17]/IO17PDB0V0 C12 EMC_AB[19]/IO13PDB0V0 EMC_AB[19]/IO13PDB0V0 EMC_AB[19]/IO18PDB0V0 C13 GND GND GND C14 GCC0/IO18NPB0V0 GBA2/IO20PPB1V0 GBA2/IO27PPB1V0 C15 GCB0/IO19NDB0V0 GCA2/IO23PDB1V0 GCA2/IO28PDB1V0 C16 GCB1/IO19PDB0V0 IO23NDB1V0 IO28NDB1V0 D1 VCCFPGAIOB5 VCCFPGAIOB5 VCCFPGAIOB5 D2 VCOMPLA0 VCOMPLA VCOMPLA0 D3 GND GND GND D4 GNDQ GNDQ GNDQ D5 EMC_CLK/IO00NDB0V0 EMC_CLK/GAA0/IO00NDB0V0 EMC_CLK/GAA0/IO02NDB0V0 D6 EMC_RW_N/IO00PDB0V0 EMC_RW_N/GAA1/IO00PDB0V0 EMC_RW_N/GAA1/IO02PDB0V0 D7 EMC_AB[6]/IO07NDB0V0 EMC_AB[6]/IO07NDB0V0 EMC_AB[6]/IO12NDB0V0 D8 EMC_AB[7]/IO07PDB0V0 EMC_AB[7]/IO07PDB0V0 EMC_AB[7]/IO12PDB0V0 D9 EMC_AB[10]/IO09NDB0V0 EMC_AB[10]/IO09NDB0V0 EMC_AB[10]/IO11NDB0V0 D10 EMC_AB[22]/IO15NDB0V0 EMC_AB[22]/IO15NDB0V0 EMC_AB[22]/IO19NDB0V0 D11 EMC_AB[23]/IO15PDB0V0 EMC_AB[23]/IO15PDB0V0 EMC_AB[23]/IO19PDB0V0 D12 GNDQ GNDQ GNDQ D13 GCC1/IO18PPB0V0 GBB2/IO20NPB1V0 GBB2/IO27NPB1V0 D14 GCA0/IO20NDB0V0 GCB2/IO24PDB1V0 GCB2/IO33PDB1V0 D15 GCA1/IO20PDB0V0 IO24NDB1V0 IO33NDB1V0 D16 VCCFPGAIOB1 VCCFPGAIOB1 VCCFPGAIOB1 E1 EMC_DB[13]/IO44PDB5V0 EMC_DB[13]/GAC2/IO70PDB5V0 EMC_DB[13]/GAC2/IO87PDB5V0 E2 EMC_DB[12]/IO44NDB5V0 EMC_DB[12]/IO70NDB5V0 EMC_DB[12]/IO87NDB5V0 E3 GFA2/IO42PDB5V0 GFA2/IO68PDB5V0 GFA2/IO85PDB5V0 E4 EMC_DB[10]/IO43NPB5V0 EMC_DB[10]/IO69NPB5V0 EMC_DB[10]/IO86NPB5V0 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-39 Pin Descriptions FG256 Pin No. A2F060 Function A2F200 Function A2F500 Function E5 GNDQ GNDQ GNDQ E6 GND GND GND E7 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 E8 GND GND GND E9 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 E10 GND GND GND E11 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 E12 GCB2/IO22PDB1V0 GCA1/IO28PDB1V0 GCA1/IO36PDB1V0 E13 VCCFPGAIOB1 VCCFPGAIOB1 VCCFPGAIOB1 E14 GCA2/IO21PDB1V0 GCB1/IO27PDB1V0 GCB1/IO34PDB1V0 E15 GCC2/IO23PDB1V0 GDC1/IO29PDB1V0 GDC1/IO38PDB1V0 E16 IO23NDB1V0 GDC0/IO29NDB1V0 GDC0/IO38NDB1V0 F1 EMC_DB[9]/IO40PDB5V0 EMC_DB[9]/GEC1/IO63PDB5V0 EMC_DB[9]/GEC1/IO80PDB5V0 F2 GND GND GND F3 GFB2/IO42NDB5V0 GFB2/IO68NDB5V0 GFB2/IO85NDB5V0 F4 VCCFPGAIOB5 VCCFPGAIOB5 VCCFPGAIOB5 F5 EMC_DB[11]/IO43PPB5V0 EMC_DB[11]/IO69PPB5V0 EMC_DB[11]/IO86PPB5V0 F6 VCCFPGAIOB5 VCCFPGAIOB5 VCCFPGAIOB5 F7 GND GND GND F8 VCC VCC VCC F9 GND GND GND F10 VCC VCC VCC F11 GND GND GND F12 IO22NDB1V0 GCA0/IO28NDB1V0 GCA0/IO36NDB1V0 F13 NC GNDQ GNDQ F14 IO21NDB1V0 GCB0/IO27NDB1V0 GCB0/IO34NDB1V0 F15 GND GND GND F16 VCCENVM VCCENVM VCCENVM G1 EMC_DB[8]/IO40NDB5V0 EMC_DB[8]/GEC0/IO63NDB5V0 EMC_DB[8]/GEC0/IO80NDB5V0 G2 EMC_DB[7]/IO39PDB5V0 EMC_DB[7]/GEB1/IO62PDB5V0 EMC_DB[7]/GEB1/IO79PDB5V0 G3 EMC_DB[6]/IO39NDB5V0 EMC_DB[6]/GEB0/IO62NDB5V0 EMC_DB[6]/GEB0/IO79NDB5V0 G4 GFC2/IO41PDB5V0 GFC2/IO67PDB5V0 GFC2/IO84PDB5V0 G5 IO41NDB5V0 IO67NDB5V0 IO84NDB5V0 G6 GND GND GND Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 5-40 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) FG256 Pin No. A2F060 Function A2F200 Function A2F500 Function G7 VCC VCC VCC G8 GND GND GND G9 VCC VCC VCC G10 GND GND GND G11 VCCFPGAIOB1 VCCFPGAIOB1 VCCFPGAIOB1 G12 VPP VPP VPP G13 TRSTB TRSTB TRSTB G14 TMS TMS TMS G15 TCK TCK TCK G16 GNDENVM GNDENVM GNDENVM H1 GND GND GND H2 EMC_DB[5]/IO38PPB5V0 EMC_DB[5]/GEA1/IO61PPB5V0 EMC_DB[5]/GEA1/IO78PPB5V0 H3 VCCFPGAIOB5 VCCFPGAIOB5 VCCFPGAIOB5 H4 EMC_DB[1]/IO36PDB5V0 EMC_DB[1]/GEB2/IO59PDB5V0 EMC_DB[1]/GEB2/IO76PDB5V0 H5 EMC_DB[0]/IO36NDB5V0 EMC_DB[0]/GEA2/IO59NDB5V0 EMC_DB[0]/GEA2/IO76NDB5V0 H6 VCCFPGAIOB5 VCCFPGAIOB5 VCCFPGAIOB5 H7 GND GND GND H8 VCC VCC VCC H9 GND GND GND H10 VCC VCC VCC H11 GND GND GND H12 VJTAG VJTAG VJTAG H13 TDO TDO TDO H14 TDI TDI TDI H15 JTAGSEL JTAGSEL JTAGSEL H16 GND GND GND J1 EMC_DB[4]/IO38NPB5V0 EMC_DB[4]/GEA0/IO61NPB5V0 EMC_DB[4]/GEA0/IO78NPB5V0 J2 EMC_DB[3]/IO37PDB5V0 EMC_DB[3]/GEC2/IO60PDB5V0 EMC_DB[3]/GEC2/IO77PDB5V0 J3 EMC_DB[2]/IO37NDB5V0 EMC_DB[2]/IO60NDB5V0 EMC_DB[2]/IO77NDB5V0 J4 GNDRCOSC GNDRCOSC GNDRCOSC J5 NC GNDQ GNDQ J6 GND GND GND J7 VCC VCC VCC J8 GND GND GND Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-41 Pin Descriptions FG256 Pin No. A2F060 Function A2F200 Function A2F500 Function J9 VCC VCC VCC J10 GND GND GND J11 VCCMSSIOB2 VCCMSSIOB2 VCCMSSIOB2 J12 I2C_0_SCL/GPIO_23 I2C_0_SCL/GPIO_23 I2C_0_SCL/GPIO_23 J13 I2C_0_SDA/GPIO_22 I2C_0_SDA/GPIO_22 I2C_0_SDA/GPIO_22 J14 I2C_1_SCL/GPIO_31 I2C_1_SCL/GPIO_31 I2C_1_SCL/GPIO_31 J15 VCCMSSIOB2 VCCMSSIOB2 VCCMSSIOB2 J16 I2C_1_SDA/GPIO_30 I2C_1_SDA/GPIO_30 I2C_1_SDA/GPIO_30 K1 GPIO_1/IO32RSB4V0 MAC_MDIO/IO49RSB4V0 MAC_MDIO/IO58RSB4V0 K2 GPIO_0/IO33RSB4V0 MAC_MDC/IO48RSB4V0 MAC_MDC/IO57RSB4V0 K3 VCCMSSIOB4 VCCMSSIOB4 VCCMSSIOB4 K4 MSS_RESET_N MSS_RESET_N MSS_RESET_N K5 VCCRCOSC VCCRCOSC VCCRCOSC K6 VCCMSSIOB4 VCCMSSIOB4 VCCMSSIOB4 K7 GND GND GND K8 VCC VCC VCC K9 GND GND GND K10 VCC VCC VCC K11 GND GND GND K12 UART_0_RXD/GPIO_21 UART_0_RXD/GPIO_21 UART_0_RXD/GPIO_21 K13 GND GND GND K14 UART_1_TXD/GPIO_28 UART_1_TXD/GPIO_28 UART_1_TXD/GPIO_28 K15 UART_1_RXD/GPIO_29 UART_1_RXD/GPIO_29 UART_1_RXD/GPIO_29 K16 UART_0_TXD/GPIO_20 UART_0_TXD/GPIO_20 UART_0_TXD/GPIO_20 L1 GND GND GND L2 GPIO_2/IO31RSB4V0 MAC_TXEN/IO52RSB4V0 MAC_TXEN/IO61RSB4V0 L3 GPIO_3/IO30RSB4V0 MAC_CRSDV/IO51RSB4V0 MAC_CRSDV/IO60RSB4V0 L4 GPIO_4/IO29RSB4V0 MAC_RXER/IO50RSB4V0 MAC_RXER/IO59RSB4V0 L5 GPIO_9/IO24RSB4V0 MAC_CLK MAC_CLK L6 GND GND GND L7 VCC VCC VCC L8 GND GND GND L9 VCC VCC VCC L10 GND GND GND Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 5-42 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) FG256 Pin No. A2F060 Function A2F200 Function A2F500 Function L11 VCCMSSIOB2 VCCMSSIOB2 VCCMSSIOB2 L12 SPI_1_DO/GPIO_24 SPI_1_DO/GPIO_24 SPI_1_DO/GPIO_24 L13 SPI_1_SS/GPIO_27 SPI_1_SS/GPIO_27 SPI_1_SS/GPIO_27 L14 SPI_1_CLK/GPIO_26 SPI_1_CLK/GPIO_26 SPI_1_CLK/GPIO_26 L15 SPI_1_DI/GPIO_25 SPI_1_DI/GPIO_25 SPI_1_DI/GPIO_25 L16 GND GND GND M1 GPIO_5/IO28RSB4V0 MAC_TXD[0]/IO56RSB4V0 MAC_TXD[0]/IO65RSB4V0 M2 GPIO_6/IO27RSB4V0 MAC_TXD[1]/IO55RSB4V0 MAC_TXD[1]/IO64RSB4V0 M3 GPIO_7/IO26RSB4V0 MAC_RXD[0]/IO54RSB4V0 MAC_RXD[0]/IO63RSB4V0 M4 GND GND GND M5 NC ADC3 ADC3 M6 NC GND15ADC0 GND15ADC0 M7 GND33ADC0 GND33ADC1 GND33ADC1 M8 GND33ADC0 GND33ADC1 GND33ADC1 M9 ADC7 ADC4 ADC4 M10 GNDTM0 GNDTM1 GNDTM1 M11 ADC6 TM2 TM2 M12 ADC5 CM2 CM2 M13 SPI_0_SS/GPIO_19 SPI_0_SS/GPIO_19 SPI_0_SS/GPIO_19 M14 VCCMSSIOB2 VCCMSSIOB2 VCCMSSIOB2 M15 SPI_0_CLK/GPIO_18 SPI_0_CLK/GPIO_18 SPI_0_CLK/GPIO_18 M16 SPI_0_DI/GPIO_17 SPI_0_DI/GPIO_17 SPI_0_DI/GPIO_17 N1 GPIO_8/IO25RSB4V0 MAC_RXD[1]/IO53RSB4V0 MAC_RXD[1]/IO62RSB4V0 N2 VCCMSSIOB4 VCCMSSIOB4 VCCMSSIOB4 N3 VCC15A VCC15A VCC15A N4 VCC33AP VCC33AP VCC33AP N5 NC ABPS3 ABPS3 N6 ADC4 TM1 TM1 N7 NC GND33ADC0 GND33ADC0 N8 VCC33ADC0 VCC33ADC1 VCC33ADC1 N9 ADC8 ADC5 ADC5 N10 CM0 CM3 CM3 N11 GNDAQ GNDAQ GNDAQ N12 VAREFOUT VAREFOUT VAREFOUT Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-43 Pin Descriptions FG256 Pin No. A2F060 Function A2F200 Function A2F500 Function N13 NC GNDSDD1 GNDSDD1 N14 NC VCC33SDD1 VCC33SDD1 N15 GND GND GND N16 SPI_0_DO/GPIO_16 SPI_0_DO/GPIO_16 SPI_0_DO/GPIO_16 P1 GNDSDD0 GNDSDD0 GNDSDD0 P2 VCC33SDD0 VCC33SDD0 VCC33SDD0 P3 VCC33N VCC33N VCC33N P4 GNDA GNDA GNDA P5 GNDAQ GNDAQ GNDAQ P6 NC CM1 CM1 P7 NC ADC2 ADC2 P8 NC VCC15ADC0 VCC15ADC0 P9 ADC9 ADC6 ADC6 P10 TM0 TM3 TM3 P11 GNDA GNDA GNDA P12 VCCMAINXTAL VCCMAINXTAL VCCMAINXTAL P13 GNDLPXTAL GNDLPXTAL GNDLPXTAL P14 VDDBAT VDDBAT VDDBAT P15 PTEM PTEM PTEM P16 PTBASE PTBASE PTBASE R1 PCAP PCAP PCAP R2 SDD0 SDD0 SDD0 R3 ADC0 ABPS0 ABPS0 R4 ADC3 TM0 TM0 R5 NC ABPS2 ABPS2 R6 NC ADC1 ADC1 R7 NC VCC33ADC0 VCC33ADC0 R8 VCC15ADC0 VCC15ADC1 VCC15ADC1 R9 ADC10 ADC7 ADC7 R10 ABPS1 ABPS7 ABPS7 R11 NC ABPS4 ABPS4 R12 MAINXIN MAINXIN MAINXIN R13 MAINXOUT MAINXOUT MAINXOUT R14 LPXIN LPXIN LPXIN Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 5-44 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) FG256 Pin No. A2F060 Function A2F200 Function A2F500 Function R15 LPXOUT LPXOUT LPXOUT R16 VCC33A VCC33A VCC33A T1 NCAP NCAP NCAP T2 ADC1 ABPS1 ABPS1 T3 ADC2 CM0 CM0 T4 NC GNDTM0 GNDTM0 T5 NC ADC0 ADC0 T6 NC VAREF0 VAREF0 T7 NC GND33ADC0 GND33ADC0 T8 GND15ADC0 GND15ADC1 GND15ADC1 T9 VAREF0 VAREF1 VAREF1 T10 ABPS0 ABPS6 ABPS6 T11 NC ABPS5 ABPS5 T12 NC SDD1 SDD1 T13 GNDVAREF GNDVAREF GNDVAREF T14 GNDMAINXTAL GNDMAINXTAL GNDMAINXTAL T15 VCCLPXTAL VCCLPXTAL VCCLPXTAL T16 PU_N PU_N PU_N Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-45 Pin Descriptions FG484 A1 Ball Pad Corner 22212019181716151413121110 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 5-46 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) FG484 Pin Number A2F200 Function A2F500 Function A1 GND GND A2 NC NC A3 NC NC A4 GND GND A5 EMC_CS0_N/GAB0/IO01NDB0V0 EMC_CS0_N/GAB0/IO05NDB0V0 A6 EMC_CS1_N/GAB1/IO01PDB0V0 EMC_CS1_N/GAB1/IO05PDB0V0 A7 GND GND A8 EMC_AB[0]/IO04NDB0V0 EMC_AB[0]/IO06NDB0V0 A9 EMC_AB[1]/IO04PDB0V0 EMC_AB[1]/IO06PDB0V0 A10 GND GND A11 NC NC A12 EMC_AB[7]/IO07PDB0V0 EMC_AB[7]/IO12PDB0V0 A13 GND GND A14 EMC_AB[12]/IO10NDB0V0 EMC_AB[12]/IO14NDB0V0 A15 EMC_AB[13]/IO10PDB0V0 EMC_AB[13]/IO14PDB0V0 A16 GND GND A17 NC IO16NDB0V0 A18 NC IO16PDB0V0 A19 GND GND A20 NC NC A21 NC NC A22 GND GND AA1 GPIO_4/IO43RSB4V0 GPIO_4/IO52RSB4V0 AA2 GPIO_12/IO37RSB4V0 GPIO_12/IO46RSB4V0 AA3 MAC_MDC/IO48RSB4V0 MAC_MDC/IO57RSB4V0 AA4 MAC_RXER/IO50RSB4V0 MAC_RXER/IO59RSB4V0 AA5 MAC_TXD[0]/IO56RSB4V0 MAC_TXD[0]/IO65RSB4V0 AA6 ABPS0 ABPS0 AA7 TM1 TM1 AA8 ADC1 ADC1 AA9 GND15ADC1 GND15ADC1 AA10 GND33ADC1 GND33ADC1 AA11 CM3 CM3 AA12 GNDTM1 GNDTM1 AA13 NC ADC10 AA14 NC ADC9 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-47 Pin Descriptions FG484 Pin Number A2F200 Function A2F500 Function AA15 NC GND15ADC2 AA16 MAINXIN MAINXIN AA17 MAINXOUT MAINXOUT AA18 LPXIN LPXIN AA19 LPXOUT LPXOUT AA20 NC NC AA21 NC NC AA22 SPI_1_CLK/GPIO_26 SPI_1_CLK/GPIO_26 AB1 GND GND AB2 GPIO_13/IO36RSB4V0 GPIO_13/IO45RSB4V0 AB3 GPIO_14/IO35RSB4V0 GPIO_14/IO44RSB4V0 AB4 GND GND AB5 PCAP PCAP AB6 NCAP NCAP AB7 ABPS3 ABPS3 AB8 ADC3 ADC3 AB9 GND15ADC0 GND15ADC0 AB10 VCC33ADC1 VCC33ADC1 AB11 VAREF1 VAREF1 AB12 TM2 TM2 AB13 CM2 CM2 AB14 ABPS4 ABPS4 AB15 GNDAQ GNDAQ AB16 GNDMAINXTAL GNDMAINXTAL AB17 GNDLPXTAL GNDLPXTAL AB18 VCCLPXTAL VCCLPXTAL AB19 VDDBAT VDDBAT AB20 PTBASE PTBASE AB21 NC NC AB22 GND GND B1 EMC_DB[15]/GAA2/IO71PDB5V0 EMC_DB[15]/GAA2/IO88PDB5V0 B2 GND GND B3 NC NC B4 NC NC B5 VCCFPGAIOB0 VCCFPGAIOB0 B6 EMC_RW_N/GAA1/IO00PDB0V0 EMC_RW_N/GAA1/IO02PDB0V0 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 5-48 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) FG484 Pin Number A2F200 Function A2F500 Function B7 NC IO04PPB0V0 B8 VCCFPGAIOB0 VCCFPGAIOB0 B9 EMC_BYTEN[0]/GAC0/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO07NDB0V0 B10 EMC_AB[2]/IO05NDB0V0 EMC_AB[2]/IO09NDB0V0 B11 EMC_AB[3]/IO05PDB0V0 EMC_AB[3]/IO09PDB0V0 B12 EMC_AB[6]/IO07NDB0V0 EMC_AB[6]/IO12NDB0V0 B13 EMC_AB[14]/IO11NDB0V0 EMC_AB[14]/IO15NDB0V0 B14 EMC_AB[15]/IO11PDB0V0 EMC_AB[15]/IO15PDB0V0 B15 VCCFPGAIOB0 VCCFPGAIOB0 B16 EMC_AB[18]/IO13NDB0V0 EMC_AB[18]/IO18NDB0V0 B17 EMC_AB[19]/IO13PDB0V0 EMC_AB[19]/IO18PDB0V0 B18 VCCFPGAIOB0 VCCFPGAIOB0 B19 GBB0/IO18NDB0V0 GBB0/IO24NDB0V0 B20 GBB1/IO18PDB0V0 GBB1/IO24PDB0V0 B21 GND GND B22 GBA2/IO20PDB1V0 GBA2/IO27PDB1V0 C1 EMC_DB[14]/GAB2/IO71NDB5V0 EMC_DB[14]/GAB2/IO88NDB5V0 C2 NC NC C3 NC NC C4 NC IO01NDB0V0 C5 NC IO01PDB0V0 C6 EMC_CLK/GAA0/IO00NDB0V0 EMC_CLK/GAA0/IO02NDB0V0 C7 NC IO03PPB0V0 C8 NC IO04NPB0V0 C9 EMC_BYTEN[1]/GAC1/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO07PDB0V0 C10 EMC_OEN1_N/IO03PDB0V0 EMC_OEN1_N/IO08PDB0V0 C11 GND GND C12 VCCFPGAIOB0 VCCFPGAIOB0 C13 EMC_AB[8]/IO08NDB0V0 EMC_AB[8]/IO13NDB0V0 C14 EMC_AB[16]/IO12NDB0V0 EMC_AB[16]/IO17NDB0V0 C15 EMC_AB[17]/IO12PDB0V0 EMC_AB[17]/IO17PDB0V0 C16 EMC_AB[24]/IO16NDB0V0 EMC_AB[24]/IO20NDB0V0 C17 EMC_AB[22]/IO15NDB0V0 EMC_AB[22]/IO19NDB0V0 C18 EMC_AB[23]/IO15PDB0V0 EMC_AB[23]/IO19PDB0V0 C19 GBA0/IO19NPB0V0 GBA0/IO23NPB0V0 C20 NC NC Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-49 Pin Descriptions FG484 Pin Number A2F200 Function A2F500 Function C21 GBC2/IO21PDB1V0 GBC2/IO30PDB1V0 C22 GBB2/IO20NDB1V0 GBB2/IO27NDB1V0 D1 GND GND D2 EMC_DB[12]/IO70NDB5V0 EMC_DB[12]/IO87NDB5V0 D3 EMC_DB[13]/GAC2/IO70PDB5V0 EMC_DB[13]/GAC2/IO87PDB5V0 D4 NC NC D5 NC NC D6 GND GND D7 NC IO00NPB0V0 D8 NC IO03NPB0V0 D9 GND GND D10 EMC_OEN0_N/IO03NDB0V0 EMC_OEN0_N/IO08NDB0V0 D11 EMC_AB[10]/IO09NDB0V0 EMC_AB[10]/IO11NDB0V0 D12 EMC_AB[11]/IO09PDB0V0 EMC_AB[11]/IO11PDB0V0 D13 EMC_AB[9]/IO08PDB0V0 EMC_AB[9]/IO13PDB0V0 D14 GND GND D15 GBC1/IO17PPB0V0 GBC1/IO22PPB0V0 D16 EMC_AB[25]/IO16PDB0V0 EMC_AB[25]/IO20PDB0V0 D17 GND GND D18 GBA1/IO19PPB0V0 GBA1/IO23PPB0V0 D19 NC NC D20 NC NC D21 IO21NDB1V0 IO30NDB1V0 D22 GND GND E1 GFC2/IO67PPB5V0 GFC2/IO84PPB5V0 E2 VCCFPGAIOB5 VCCFPGAIOB5 E3 GFA2/IO68PDB5V0 GFA2/IO85PDB5V0 E4 GND GND E5 NC NC E6 GNDQ GNDQ E7 VCCFPGAIOB0 VCCFPGAIOB0 E8 NC IO00PPB0V0 E9 NC NC E10 VCCFPGAIOB0 VCCFPGAIOB0 E11 EMC_AB[4]/IO06NDB0V0 EMC_AB[4]/IO10NDB0V0 E12 EMC_AB[5]/IO06PDB0V0 EMC_AB[5]/IO10PDB0V0 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 5-50 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) FG484 Pin Number A2F200 Function A2F500 Function E13 VCCFPGAIOB0 VCCFPGAIOB0 E14 GBC0/IO17NPB0V0 GBC0/IO22NPB0V0 E15 NC NC E16 VCCFPGAIOB0 VCCFPGAIOB0 E17 NC VCOMPLA1 E18 NC IO25NPB1V0 E19 GND GND E20 NC NC E21 VCCFPGAIOB1 VCCFPGAIOB1 E22 IO22NDB1V0 IO32NDB1V0 F1 GFB1/IO65PPB5V0 GFB1/IO82PPB5V0 F2 IO67NPB5V0 IO84NPB5V0 F3 GFB2/IO68NDB5V0 GFB2/IO85NDB5V0 F4 EMC_DB[10]/IO69NPB5V0 EMC_DB[10]/IO86NPB5V0 F5 VCCFPGAIOB5 VCCFPGAIOB5 F6 VCCPLL VCCPLL0 F7 VCOMPLA VCOMPLA0 F8 NC NC F9 NC NC F10 NC NC F11 NC NC F12 NC NC F13 EMC_AB[20]/IO14NDB0V0 EMC_AB[20]/IO21NDB0V0 F14 EMC_AB[21]/IO14PDB0V0 EMC_AB[21]/IO21PDB0V0 F15 GNDQ GNDQ F16 NC VCCPLL1 F17 NC IO25PPB1V0 F18 VCCFPGAIOB1 VCCFPGAIOB1 F19 IO23NDB1V0 IO28NDB1V0 F20 NC IO31PDB1V0 F21 NC IO31NDB1V0 F22 IO22PDB1V0 IO32PDB1V0 G1 GND GND G2 GFB0/IO65NPB5V0 GFB0/IO82NPB5V0 G3 EMC_DB[9]/GEC1/IO63PDB5V0 EMC_DB[9]/GEC1/IO80PDB5V0 G4 GFC1/IO66PPB5V0 GFC1/IO83PPB5V0 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-51 Pin Descriptions FG484 Pin Number A2F200 Function A2F500 Function G5 EMC_DB[11]/IO69PPB5V0 EMC_DB[11]/IO86PPB5V0 G6 GNDQ GNDQ G7 NC NC G8 GND GND G9 VCCFPGAIOB0 VCCFPGAIOB0 G10 GND GND G11 VCCFPGAIOB0 VCCFPGAIOB0 G12 GND GND G13 VCCFPGAIOB0 VCCFPGAIOB0 G14 GND GND G15 VCCFPGAIOB0 VCCFPGAIOB0 G16 GNDQ GNDQ G17 NC IO26PDB1V0 G18 NC IO26NDB1V0 G19 GCA2/IO23PDB1V0 GCA2/IO28PDB1V0 G20 IO24NDB1V0 IO33NDB1V0 G21 GCB2/IO24PDB1V0 GCB2/IO33PDB1V0 G22 GND GND H1 EMC_DB[7]/GEB1/IO62PDB5V0 EMC_DB[7]/GEB1/IO79PDB5V0 H2 VCCFPGAIOB5 VCCFPGAIOB5 H3 EMC_DB[8]/GEC0/IO63NDB5V0 EMC_DB[8]/GEC0/IO80NDB5V0 H4 GND GND H5 GFC0/IO66NPB5V0 GFC0/IO83NPB5V0 H6 GFA1/IO64PDB5V0 GFA1/IO81PDB5V0 H7 GND GND H8 VCC VCC H9 GND GND H10 VCC VCC H11 GND GND H12 VCC VCC H13 GND GND H14 VCC VCC H15 GND GND H16 VCCFPGAIOB1 VCCFPGAIOB1 H17 IO25NDB1V0 IO29NDB1V0 H18 GCC2/IO25PDB1V0 GCC2/IO29PDB1V0 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 5-52 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) FG484 Pin Number A2F200 Function A2F500 Function H19 GND GND H20 GCC0/IO26NPB1V0 GCC0/IO35NPB1V0 H21 VCCFPGAIOB1 VCCFPGAIOB1 H22 GCB0/IO27NDB1V0 GCB0/IO34NDB1V0 J1 EMC_DB[6]/GEB0/IO62NDB5V0 EMC_DB[6]/GEB0/IO79NDB5V0 J2 EMC_DB[5]/GEA1/IO61PDB5V0 EMC_DB[5]/GEA1/IO78PDB5V0 J3 EMC_DB[4]/GEA0/IO61NDB5V0 EMC_DB[4]/GEA0/IO78NDB5V0 J4 EMC_DB[3]/GEC2/IO60PPB5V0 EMC_DB[3]/GEC2/IO77PPB5V0 J5 VCCFPGAIOB5 VCCFPGAIOB5 J6 GFA0/IO64NDB5V0 GFA0/IO81NDB5V0 J7 VCCFPGAIOB5 VCCFPGAIOB5 J8 GND GND J9 VCC VCC J10 GND GND J11 VCC VCC J12 GND GND J13 VCC VCC J14 GND GND J15 VCC VCC J16 GND GND J17 NC IO37PDB1V0 J18 VCCFPGAIOB1 VCCFPGAIOB1 J19 GCA0/IO28NDB1V0 GCA0/IO36NDB1V0 J20 GCA1/IO28PDB1V0 GCA1/IO36PDB1V0 J21 GCC1/IO26PPB1V0 GCC1/IO35PPB1V0 J22 GCB1/IO27PDB1V0 GCB1/IO34PDB1V0 K1 GND GND K2 EMC_DB[0]/GEA2/IO59NDB5V0 EMC_DB[0]/GEA2/IO76NDB5V0 K3 EMC_DB[1]/GEB2/IO59PDB5V0 EMC_DB[1]/GEB2/IO76PDB5V0 K4 NC IO74PPB5V0 K5 EMC_DB[2]/IO60NPB5V0 EMC_DB[2]/IO77NPB5V0 K6 NC IO75PDB5V0 K7 GND GND K8 VCC VCC K9 GND GND K10 VCC VCC Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-53 Pin Descriptions FG484 Pin Number A2F200 Function A2F500 Function K11 GND GND K12 VCC VCC K13 GND GND K14 VCC VCC K15 GND GND K16 VCCFPGAIOB1 VCCFPGAIOB1 K17 NC IO37NDB1V0 K18 GDA1/IO31PDB1V0 GDA1/IO40PDB1V0 K19 GDA0/IO31NDB1V0 GDA0/IO40NDB1V0 K20 GDC1/IO29PDB1V0 GDC1/IO38PDB1V0 K21 GDC0/IO29NDB1V0 GDC0/IO38NDB1V0 K22 GND GND L1 NC IO73PDB5V0 L2 NC IO73NDB5V0 L3 NC IO72PPB5V0 L4 GND GND L5 NC IO74NPB5V0 L6 NC IO75NDB5V0 L7 VCCFPGAIOB5 VCCFPGAIOB5 L8 GND GND L9 VCC VCC L10 GND GND L11 VCC VCC L12 GND GND L13 VCC VCC L14 GND GND L15 VCC VCC L16 GND GND L17 GNDQ GNDQ L18 GDA2/IO33NDB1V0 GDA2/IO42NDB1V0 L19 VCCFPGAIOB1 VCCFPGAIOB1 L20 GDB1/IO30PDB1V0 GDB1/IO39PDB1V0 L21 GDB0/IO30NDB1V0 GDB0/IO39NDB1V0 L22 GDC2/IO32PDB1V0 GDC2/IO41PDB1V0 M1 NC IO71PDB5V0 M2 NC IO71NDB5V0 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 5-54 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) FG484 Pin Number A2F200 Function A2F500 Function M3 VCCFPGAIOB5 VCCFPGAIOB5 M4 NC IO72NPB5V0 M5 GNDQ GNDQ M6 NC IO68PDB5V0 M7 GND GND M8 VCC VCC M9 GND GND M10 VCC VCC M11 GND GND M12 VCC VCC M13 GND GND M14 VCC VCC M15 GND GND M16 VCCFPGAIOB1 VCCFPGAIOB1 M17 NC NC M18 GDB2/IO33PDB1V0 GDB2/IO42PDB1V0 M19 VJTAG VJTAG M20 GND GND M21 VPP VPP M22 IO32NDB1V0 IO41NDB1V0 N1 GND GND N2 NC IO70PDB5V0 N3 NC IO70NDB5V0 N4 VCCRCOSC VCCRCOSC N5 VCCFPGAIOB5 VCCFPGAIOB5 N6 NC IO68NDB5V0 N7 VCCFPGAIOB5 VCCFPGAIOB5 N8 GND GND N9 VCC VCC N10 GND GND N11 VCC VCC N12 GND GND N13 VCC VCC N14 GND GND N15 VCC VCC N16 NC GND Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-55 Pin Descriptions FG484 Pin Number A2F200 Function A2F500 Function N17 NC NC N18 VCCFPGAIOB1 VCCFPGAIOB1 N19 VCCENVM VCCENVM N20 GNDENVM GNDENVM N21 NC NC N22 GND GND P1 NC IO69NDB5V0 P2 NC IO69PDB5V0 P3 GNDRCOSC GNDRCOSC P4 GND GND P5 NC NC P6 NC NC P7 GND GND P8 VCC VCC P9 GND GND P10 VCC VCC P11 GND GND P12 VCC VCC P13 GND GND P14 VCC VCC P15 GND GND P16 VCCFPGAIOB1 VCCFPGAIOB1 P17 TDI TDI P18 TCK TCK P19 GND GND P20 TMS TMS P21 TDO TDO P22 TRSTB TRSTB R1 MSS_RESET_N MSS_RESET_N R2 VCCFPGAIOB5 VCCFPGAIOB5 R3 GPIO_1/IO46RSB4V0 GPIO_1/IO55RSB4V0 R4 NC NC R5 NC NC R6 NC NC R7 NC NC R8 GND GND Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 5-56 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) FG484 Pin Number A2F200 Function A2F500 Function R9 VCC VCC R10 GND GND R11 VCC VCC R12 GND GND R13 VCC VCC R14 GND GND R15 VCC VCC R16 JTAGSEL JTAGSEL R17 NC NC R18 NC NC R19 NC NC R20 NC NC R21 VCCFPGAIOB1 VCCFPGAIOB1 R22 NC NC T1 GND GND T2 VCCMSSIOB4 VCCMSSIOB4 T3 GPIO_8/IO39RSB4V0 GPIO_8/IO48RSB4V0 T4 GPIO_11/IO57RSB4V0 GPIO_11/IO66RSB4V0 T5 GND GND T6 MAC_CLK MAC_CLK T7 VCCMSSIOB4 VCCMSSIOB4 T8 VCC33SDD0 VCC33SDD0 T9 VCC15A VCC15A T10 GNDAQ GNDAQ T11 GND33ADC0 GND33ADC0 T12 ADC7 ADC7 T13 NC TM4 T14 NC VAREF2 T15 VAREFOUT VAREFOUT T16 VCCMSSIOB2 VCCMSSIOB2 T17 SPI_1_DO/GPIO_24 SPI_1_DO/GPIO_24 T18 GND GND T19 NC NC T20 NC NC T21 VCCMSSIOB2 VCCMSSIOB2 T22 GND GND Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-57 Pin Descriptions FG484 Pin Number A2F200 Function A2F500 Function U1 GND GND U2 GPIO_5/IO42RSB4V0 GPIO_5/IO51RSB4V0 U3 GPIO_10/IO58RSB4V0 GPIO_10/IO67RSB4V0 U4 VCCMSSIOB4 VCCMSSIOB4 U5 MAC_RXD[1]/IO53RSB4V0 MAC_RXD[1]/IO62RSB4V0 U6 NC NC U7 VCC33AP VCC33AP U8 VCC33N VCC33N U9 CM1 CM1 U10 VAREF0 VAREF0 U11 GND33ADC1 GND33ADC1 U12 ADC4 ADC4 U13 NC GNDTM2 U14 NC ADC11 U15 GNDVAREF GNDVAREF U16 VCC33SDD1 VCC33SDD1 U17 SPI_0_DO/GPIO_16 SPI_0_DO/GPIO_16 U18 UART_0_RXD/GPIO_21 UART_0_RXD/GPIO_21 U19 VCCMSSIOB2 VCCMSSIOB2 U20 I2C_1_SCL/GPIO_31 I2C_1_SCL/GPIO_31 U21 I2C_0_SCL/GPIO_23 I2C_0_SCL/GPIO_23 U22 GND GND V1 GPIO_0/IO47RSB4V0 GPIO_0/IO56RSB4V0 V2 GPIO_6/IO41RSB4V0 GPIO_6/IO50RSB4V0 V3 GPIO_9/IO38RSB4V0 GPIO_9/IO47RSB4V0 V4 MAC_MDIO/IO49RSB4V0 MAC_MDIO/IO58RSB4V0 V5 MAC_RXD[0]/IO54RSB4V0 MAC_RXD[0]/IO63RSB4V0 V6 GND GND V7 SDD0 SDD0 V8 ABPS1 ABPS1 V9 ADC2 ADC2 V10 VCC33ADC0 VCC33ADC0 V11 ADC6 ADC6 V12 ADC5 ADC5 V13 ABPS5 ABPS5 V14 NC ADC8 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 5-58 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) FG484 Pin Number A2F200 Function A2F500 Function V15 NC GND33ADC2 V16 NC NC V17 GND GND V18 SPI_0_DI/GPIO_17 SPI_0_DI/GPIO_17 V19 SPI_1_DI/GPIO_25 SPI_1_DI/GPIO_25 V20 UART_1_TXD/GPIO_28 UART_1_TXD/GPIO_28 V21 I2C_0_SDA/GPIO_22 I2C_0_SDA/GPIO_22 V22 I2C_1_SDA/GPIO_30 I2C_1_SDA/GPIO_30 W1 GPIO_2/IO45RSB4V0 GPIO_2/IO54RSB4V0 W2 GPIO_7/IO40RSB4V0 GPIO_7/IO49RSB4V0 W3 GND GND W4 MAC_CRSDV/IO51RSB4V0 MAC_CRSDV/IO60RSB4V0 W5 MAC_TXD[1]/IO55RSB4V0 MAC_TXD[1]/IO64RSB4V0 W6 NC SDD2 W7 GNDA GNDA W8 TM0 TM0 W9 ABPS2 ABPS2 W10 GND33ADC0 GND33ADC0 W11 VCC15ADC1 VCC15ADC1 W12 ABPS6 ABPS6 W13 NC CM4 W14 NC ABPS9 W15 NC VCC33ADC2 W16 GNDA GNDA W17 PU_N PU_N W18 GNDSDD1 GNDSDD1 W19 SPI_0_CLK/GPIO_18 SPI_0_CLK/GPIO_18 W20 GND GND W21 SPI_1_SS/GPIO_27 SPI_1_SS/GPIO_27 W22 UART_1_RXD/GPIO_29 UART_1_RXD/GPIO_29 Y1 GPIO_3/IO44RSB4V0 GPIO_3/IO53RSB4V0 Y2 VCCMSSIOB4 VCCMSSIOB4 Y3 GPIO_15/IO34RSB4V0 GPIO_15/IO43RSB4V0 Y4 MAC_TXEN/IO52RSB4V0 MAC_TXEN/IO61RSB4V0 Y5 VCCMSSIOB4 VCCMSSIOB4 Y6 GNDSDD0 GNDSDD0 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. Revision 8 5-59 Pin Descriptions FG484 Pin Number A2F200 Function A2F500 Function Y7 CM0 CM0 Y8 GNDTM0 GNDTM0 Y9 ADC0 ADC0 Y10 VCC15ADC0 VCC15ADC0 Y11 ABPS7 ABPS7 Y12 TM3 TM3 Y13 NC ABPS8 Y14 NC GND33ADC2 Y15 NC VCC15ADC2 Y16 VCCMAINXTAL VCCMAINXTAL Y17 SDD1 SDD1 Y18 PTEM PTEM Y19 VCC33A VCC33A Y20 SPI_0_SS/GPIO_19 SPI_0_SS/GPIO_19 Y21 VCCMSSIOB2 VCCMSSIOB2 Y22 UART_0_TXD/GPIO_20 UART_0_TXD/GPIO_20 Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 5-60 Revision 8 6 – Datasheet Information List of Changes The following table lists critical changes that were made in each revision of the SmartFusion datasheet. Revision Changes Page Revision 8 In the "Analog Front-End (AFE)" section, the resolultion for the first-order sigma delta I, II (March 2012) DAC was corrected from 12-bit to "8-bit, 16-bit, or 24-bit." The same correction was made in the "SmartFusion cSoC Family Product Table" (SAR 36541). The "SmartFusion cSoC Family Product Table" was revised to break out the features II by package as well as device. The table now indicates that only one SPI is available for the PQ208 package in A2F200 and A2F500, and in the TQ144 package for A2F060 (SAR 33477). The EMC address bus size has been corrected to 26 bits (SAR 35664). The "SmartFusion cSoC Device Status" table was revised to change the CS288 III package for A2F200 and A2F500 from preliminary to production status (SAR 37811). TQ144 package information for A2F060 was added to the "Package I/Os: MSS + III, VI FPGA I/Os" table, "SmartFusion cSoC Device Status" table, "Product Ordering Codes", and "Temperature Grade Offerings" table (SAR 36246). Table 1 • SmartFusion cSoC Package Sizes Dimensions is new (SAR 31178). III The Halogen-Free Packaging code (H) was removed from the "Product Ordering VI Codes" table (SAR 34017). The "Specifying I/O States During Programming" section is new (SAR 34836). 1-3 The reference to guidelines for global spines and VersaTile rows, given in the "Global 2-15 Clock Dynamic Contribution—PCLOCK" section, was corrected to the "Device Architecture" chapter in the SmartFusion FPGA Fabric User's Guide (SAR 34742). The AC Loading figures in the "Single-Ended I/O Characteristics" section were 2-30, updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O 2-24 Software Settings" section (SAR 34891). The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 34799): 2-32 "It uses a 5 V–tolerant input buffer and push-pull output buffer." In the SRAM "Timing Characteristics" tables, reference was made to a new application 2-69 note, Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based cSoCs and FPGAs, which covers these cases in detail (SAR 34874). The note for Table 2-93 • Current Monitor Performance Specification was modified to 2-76 include the statement that the restriction on the the TM pad being no greater than 10 mV above the CM pad.is applicable only if current monitor is used (SAR 26373). The unit "FR" in Table 2-97 • ABPS Performance Specifications and Table 2-99 • 2-81, Analog Sigma-Delta DAC, used to designate full-scale error, was changed to "FS" and 2-84 clarified with a table note (SAR 35342). The description of "In-application programming (IAP)" methodology was changed to 4-7 state the difference for A2F060 and A2F500 compared to A2F200 (SAR 37808). The "Global I/O Naming Conventions" section is new (SARs 28996, 31147). The 5-5, 5-5 description for IO "User Pins" was revised accordingly and moved out of the table and into a new section: "User I/O Naming Conventions". Revision 8 6-1 Datasheet Information Revision Changes Page Revision 8 The descriptions for "MAINXIN" and "MAINXOUT" were revised to state how they 5-7 (continued) should be handled if using an external RC network or clock input (SAR 32594). The description and type was revised for the "MSS_RESET_N" pin (SAR 34133). 5-8 The "TQ144" section and pin table for A2F060 are new (SAR 36246). 5-17 Revision 7 The title of the datasheet was changed from SmartFusion Intelligent Mixed Signal N/A (August 2011) FPGAs to SmartFusion Customizable System-on-Chip (cSoC). Terminology throughout was changed accordingly. The term cSoC defines a category of devices that include at least FPGA fabric and a processor subsystem of some sort. It can also include any of the following: analog, SerDes, ASIC blocks, customer specific IP, or application-specific IP. SmartFusion is Microsemi’s first cSoC (SAR 33071). The "SmartFusion cSoC Family Product Table" was revised to remove the note stating II that the A2F060 device is under definition and subject to change (SAR 33070). A note was added for EMC, stating that it is not available on A2F500 for the PQ208 package (SAR 33041). The "SmartFusion cSoC Device Status" table was revised. The status for A2F060 III CS288 and FG256 moved from Advance to Preliminary. A2F200 PQ208 and A2F500 PQ208 moved from Advance to Production (SAR 33069). The "Package I/Os: MSS + FPGA I/Os" table was revised. The number of direct analog III inputs for A2F060 packages increased from 6 to 11. The number of MSS I/Os for the A2F060 FG256 package increased from 25 to 26 (SAR 33070). A note was added stating that EMC is not available for the A2F500 PQ208 package (SAR 33041). The note associated with the "SmartFusion cSoC System Architecture" diagram was V corrected from "Architecture for A2F500" to "Architecture for A2F200" (SAR 32578). The Licensed DPA Logo was added to the "Product Ordering Codes" section. The VI trademarked Licensed DPA Logo identifies that a product is covered by a DPA counter-measures license from Cryptography Research (SAR 32151). The "Security" section and "Secure Programming" section were updated to clarify that 1-2, 4-9 although no existing security measures can give an absolute guarantee, SmartFusion cSoCs implement the best security available in the industry (SAR 32865). Storage temperature, T , and junction temperature, T , were added to Table 2-1 • 2-1 STG J Absolute Maximum Ratings (SAR 30863). AC/DC characteristics for A2F060 were added to the "SmartFusion DC and Switching Characteristics" chapter (SAR 33132). The following tables were updated: 2-12 Table 2-14 • Different Components Contributing to Dynamic Power Consumption in SmartFusion cSoCs 2-13 Table 2-15 • Different Components Contributing to the Static Power Consumption in SmartFusion cSoCs 2-74 Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C, VCC = 1.425 V 2-84 Table 2-99 • Analog Sigma-Delta DAC 2-88 Table 2-101 • SPI Characteristics The following sentence was removed from the "I/O Power-Up and Supply Voltage 2-4 Thresholds for Power-On Reset (Commercial and Industrial)" section because it is incorrect (SAR 31047): "The many different supplies can power up in any sequence with minimized current spikes or surges." 6-2 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Revision Changes Page Revision 7 Table 2-8 • Quiescent Supply Current Characteristics was divided into two tables: one 2-10 (continued) for power supplies configurations and one for quiescent supply current. SoC mode was added to both tables (SAR 26378) and VCOMPLAx was removed from Table 2-8 • Power Supplies Configuration (SAR 29591). Quiescent supply current values were updated in Table 2-9 • Quiescent Supply Current Characteristics (SAR 33067). The "Total Static Power Consumption—PSTAT" section was revised: "N * 2-14 eNVM-BLOCKS P " was removed from the equation for P (SAR 33067). DC4 STAT Table 2-14 • Different Components Contributing to Dynamic Power Consumption in 2-12, SmartFusion cSoCs and Table 2-15 • Different Components Contributing to the Static 2-13 Power Consumption in SmartFusion cSoCs were revised to reflect updates in the SmartFusion power calculator (SARs 26405, 33067). Table 2-82 • A2F060 Global Resource is new (SAR 33132). 2-61 Output duty cycle was corrected to 50% in Table 2-83 • Electrical Characteristics of the 2-61 RC Oscillator. It was incorrectly noted as 1% previously. Operating current for 3.3 domain was added (SAR 32940). Table 2-86 • SmartFusion CCC/PLL Specification was revised to add information and 2-63 measurements regarding CCC output peak-to-peak period jitter (SAR 32996). The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics" 2-66 to tables, Figure 2-36 • FIFO Reset, and the FIFO "Timing Waveforms" tables were 2-74 revised to ensure consistency with the software names (SAR 29991). Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C, VCC 2-74 = 1.425 V was revised to correct the maximum frequencies (SAR 32410). Table2-96 • VAREF Stabilization Time was moved to the "SmartFusion DC and 2-80 Switching Characteristics" section from the SmartFusion Programmable Analog User’s Guide because the information is extracted from characterization (SAR 24298). The hysteresis section in Table 2-98 • Comparator Performance Specifications was 2-83 revised (SAR 33158). The "SmartFusion Development Tools" was extensively updated (SAR 33216). 3-1 The text following Table 4-2 • JTAG Pin Descriptions was updated to add information 4-7 on control of the JTAGSEL pin. Manual jumpers on the evaluation and development kits allow manual selection of this function for J-Link and ULINK debuggers (SAR 25592). Usage instructions, such as how to handle the pin when unused, were added for the 5-1 following supply pins (SAR 29769): through "VCC15A" 5-3 "VCC15ADC0" through "VCC15ADC2" "VCC33ADC0" through "VCC33ADC2" "VCC33AP" "VCC33ADC2" "VCCLPXTAL" "VCCMAINXTAL" "VCCMSSIOB2" "VCCPLLx" "VCCRCOSC" "VDDBAT" Revision 8 6-3 Datasheet Information Revision Changes Page Revision 7 The "IO" description was revised to clarify the definitions of u, I/O pair, and w, 5-5 (continued) differential pair (SAR 31147). Information on configuration of unused I/Os (including unused MSS I/Os, SAR 26891) was added (SAR 32643). Usage instructions were added for the following pins (SAR 29769): 5-8 through "MSS_RESET_N" 5-12 "TCK" "TMS" "TRSTB" "MAC_CLK" Package names used in the "Pin Assignment Tables" section were revised to match 5-17 standards given in Package Mechanical Drawings (SAR 27395). The pin assignments for A2F060 for "TQ144" and "FG256" have been revised due to 5-17, the device status change from advance to preliminary (SAR 33068). 5-37 The "TQ144" and "FG256" pin assignment sections previously compared functions between A2F060/A2F200 devices in one table and A2F200/A2F500 in a separate table. Functions for all three devices have now been combined into one table for each package (SAR 33072). The "PQ208" pin table was revised for A2F500 to remove EMC functions, which are 5-30 not available for this device/package combination (SAR 33041). Revision 6 The "PQ208" package was added to product tables and "Product Ordering Codes" for III (March 2011) A2F200 and A2F500 (SAR 31005). The "Package I/Os: MSS + FPGA I/Os" table was revised to add the CS288 package III for A2F060 and the PQ208 package for A2F200 and A2F500. A row was added for shared analog inputs (SAR 31034). The "SmartFusion cSoC Device Status" table was updated (SAR 31084). III VCCESRAM was added to Table2-1 • Absolute Maximum Ratings, Table2-3 • 2-1, 2-3, Recommended Operating Conditions, Table 2-8 • Power Supplies Configuration, and 2-10, 5-1 the "Supply Pins" table (SAR 31035). The following note was removed from Table 2-8 • Power Supplies Configuration (SAR 2-10 30984): "Current monitors and temperature monitors should not be used when Power-Down and/or Sleep mode are required by the application." Dynamic power values were updated in the following tables. The table subtitles changed where FPGA I/O banks were involved to note "I/O assigned to EMC I/O pins" (SAR 30987). 2-10 Table 2-10 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings 2-11 Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings. The "Timing Model" was updated (SAR 30986). 2-19 6-4 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Revision Changes Page Revision 6 Values in the timing tables for the following sections were updated. Table subtitles (continued) were updated for FPGA I/O banks to note "I/O assigned to EMC I/O pins" (SAR 30986). 2-23 "Overview of I/O Performance" section: Table 2-24, Table 2-25 2-26 "Detailed I/O DC Characteristics" section: Table 2-38, Table 2-39, Table 2-40, Table 2-44, Table 2-45, Table 2-46, Table 2-50, Table 2-51, Table 2-52, Table 2-56, Table 2-57, Table 2-58, Table 2-61, Table 2-62 "LVDS" section: Table 2-65 2-40 "LVPECL" section: Table 2-68 2-43 2-59 "Global Tree Timing Characteristics" section: Table 2-80, Table 2-81 The "PQ208" section and pin tables are new (SAR 31005). 5-30 Global clocks were removed from the A2F060 pin table for the "CS288" and "FG256" 5-38 packages, resulting in changed function names for affected pins (SAR 31033). Revision 5 Table 2-2 • Analog Maximum Ratings was revised. The recommended CM[n] pad 2-2 (December 2010) voltage (relative to ground) was changed from –11 to –0.3 (SAR 28219). Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays was revised 2-9 to change the values for 100ºC. Power-down and Sleep modes, and all associated notes, were removed from 2-10 Table 2-8 • Power Supplies Configuration (SAR 29479). IDC3 and IDC4 were renamed to IDC1 and IDC2 (SAR 29478). These modes are no longer supported. A note was added to the table stating that current monitors and temperature monitors should not be used when Power-down and/or Sleep mode are required by the application. The "Power-Down and Sleep Mode Implementation" section was deleted (SAR N/A 29479). Values for PAC9 and PAC10 for LVDS and LVPECL were revised in Table 2-10 • 2-10, Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings and 2-11 Table 2-12 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings*. Values for PAC1 through PAC4, PDC1, and PDC2 were added for A2F500 in 2-12, Table 2-14 • Different Components Contributing to Dynamic Power Consumption in 2-13 SmartFusion cSoCs and Table 2-15 • Different Components Contributing to the Static Power Consumption in SmartFusion cSoCs The equation for "Total Dynamic Power Consumption—PDYN" in "SoC Mode" was 2-14, revised to add P . The "Microcontroller Subsystem Dynamic Contribution—PMSS" 2-18 MSS section is new (SAR 29462). Information in Table 2-24 • Summary of I/O Timing Characteristics—Software Default 2-25 Settings (applicable to FPGA I/O banks) and Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings (applicable to MSS I/O banks) was updated. Available values for the Std. speed were added to the timing tables from Table 2-38 • 2-31 to 3.3 V LVTTL / 3.3 V LVCMOS High Slew to Table 2-92 • JTAG 1532 (SAR 29331). 2-75 One or more values changed for the –1 speed in tables covering 3.3 V LVCMOS, 2.5 V LVCMOS, 1.8 V LVCMOS, 1.5 V LVCMOS, Combinatorial Cell Propagation Delays, and A2F200 Global Resources. Table 2-80 • A2F500 Global Resource is new. 2-60 Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C, VCC 2-74 = 1.425 V was revised (SAR 27585). Revision 8 6-5 Datasheet Information Revision Changes Page Revision 5 The programmable analog specifications tables were revised with updated information. 2-76 to (continued) 2-86 Table 4-1 • Supported JTAG Programming Hardware was revised by adding a note to 4-7 indicate "planned support" for several of the items in the table. The note on JTAGSEL in the "In-System Programming" section was revised to state 4-7 that SoftConsole selects the appropriate TAP controller using the CTXSELECT JTAG command. When using SoftConsole, the state of JTAGSEL is a "don't care" (SAR 29261). The "CS288" and "FG256" pin tables for A2F060 are new, comparing the A2F060 5-21 function with the A2F200 function (SAR 29353). The "Handling When Unused" column was removed from the "FG256" pin table for 5-37 A2F200 and A2F500 (SAR 29691). Revision 4 Table 2-8 • Power Supplies Configuration was revised. VCCRCOSC was moved to a 2-10 (September column of its own with new values. VCCENVM was added to the table. Standby mode 2010) for VJTAG and VPP was changed from 0 V to N/A. "Disable" was changed to "Off" in the eNVM column. The column for RCOSC was deleted. The "Power-Down and Sleep Mode Implementation" section was revised to include 2-11 VCCROSC. Revision 3 The "I/Os and Operating Voltage" section was revised to list "single 3.3 V power supply I (September with on-chip 1.5 V regulator" and "external 1.5 V is allowed" (SAR 27663). 2010) The CS288 package was added to the "Package I/Os: MSS + FPGA I/Os" table (SAR III, VI, VI 27101), "Product Ordering Codes" table, and "Temperature Grade Offerings" table (SAR 27044). The number of direct analog inputs for the FG256 package in A2F060 was changed from 8 to 6. Two notes were added to the "SmartFusion cSoC Family Product Table" indicating II limitations for features of the A2F500 device: Two PLLs are available in CS288 and FG484 (one PLL in FG256). [ADCs, DACs, SCBs, comparators, current monitors, and bipolar high voltage monitors are] Available on FG484 only. FG256 and CS288 packages offer the same programmable analog capabilities as A2F200. Table cells were merged in rows containing the same values for easier reading (SAR 24748). The security feature option was added to the "Product Ordering Codes" table. VI 6-6 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Revision Changes Page Revision 3 In Table2-3 • Recommended Operating Conditions, the VDDBAT recommended 2-3 (continued) operating range was changed from "2.97 to 3.63" to "2.7 to 3.63" (SAR 25246). Recommended operating range was changed to "3.15 to 3.45" for the following voltages: VCC33A VCC33ADCx VCC33AP VCC33SDDx VCCMAINXTAL VCCLPXTAL Two notes were added to the table (SAR 27109): 1. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A, VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL. 2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC, VCC15A, and VCC15ADCx. In Table 2-3 • Recommended Operating Conditions, the description for VCCLPXTAL 2-3 was corrected to change "32 Hz" to "32 KHz" (SAR 27110). The "Power Supply Sequencing Requirement" section is new (SAR 27178). 2-4 Table 2-8 • Power Supplies Configuration was revised to change most on/off entries to 2-10 voltages. Note 5 was added, stating that "on" means proper voltage is applied. The values of 6 µA and 16 µA were removed for IDC1 and IDC2 for 3.3 V. A note was added for IDC1 and IDC2: "Power mode and Sleep mode are consuming higher current than expected in the current version of silicon. These specifications will be updated when new version of the silicon is available" (SAR 27926). The "Power-Down and Sleep Mode Implementation" section is new (SAR 27178). 2-11 A note was added to Table 2-86 • SmartFusion CCC/PLL Specification, pertaining to 2-63 f , stating that "one of the CCC outputs (GLA0) is used as an MSS clock and is out_CCC limited to 100 MHz (maximum) by software" (SAR 26388). Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C, VCC 2-74 = 1.425 V was revised. Values were included for A2F200 and A2F500, for –1 and Std. speed grades. A note was added to define 6:1:1:1 and 5:1:1:1 (SAR 26166). The units were corrected (mV instead of V) for input referred offset voltage, GDEC[1:0] 2-81 = 00 in Table 2-97 • ABPS Performance Specifications (SAR 25381). The test condition values for operating current (ICC33A, typical) were changed in 2-86 Table 2-100 • Voltage Regulator (SAR 26465). Figure 2-44 • Typical Output Voltage was revised to add legends for the three curves, 2-87 stating the load represented by each (SAR 25247). The "SmartFusion Programming" chapter was moved to this document from the 4-7 SmartFusion Subsystem Microcontroller User’s Guide (SAR 26542). The "Typical Programming and Erase Times" section was added to this chapter. Figure 4-1 • TRSTB Logic was revised to change 1.5 V to "VJTAG (1.5 V to 3.3 V 4-8 nominal)" (SAR 24694). Revision 8 6-7 Datasheet Information Revision Changes Page Revision 3 Two notes were added to the "Supply Pins" table (SAR 27109): 5-1 (continued) 1. The following supplies should be connected together while following proper noise filtering practices: VCC33A, VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL. 2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC, VCC15A, and VCC15ADCx. The descriptions for the "VCC33N", "NCAP", and "PCAP" pins were revised to include 5-2, 5-7, information on what to do if analog SCB features and SDDs are not used (SAR 5-8 26744). Information was added to the "User Pins" table regarding tristating of used and unused 5-5 GPIO pins. The IO portion of the table was revised to state that unused I/O pins are disabled by Libero IDE software and include a weak pull-up resistor (SAR 26890). Information was added regarding behavior of used I/O pins during power-up. The type for "EMC_RW_N" was changed from In/out to Out (SAR 25113). 5-11 A note was added to the "Analog Front-End (AFE)" table stating that unused analog 5-13 inputs should be grounded (SAR 26744). The "TQ144" section is new, with pin tables for A2F200 and A2F500 (SAR 27044). 5-17 The "FG256" pin table was replaced and now includes "Handling When Unused" 5-37 information (SAR 27709). Revision 2 Embedded nonvolatile flash memory (eNVM) was changed from "64 to 512 Kbytes" to I, II (May 2010) "128 to 512 Kbytes" in the "Microcontroller Subsystem (MSS)" section and "SmartFusion cSoC Family Product Table" (SAR 26005). The main oscillator range of values was changed to "32 KHz to 20 MHz" in the I, II "Microcontroller Subsystem (MSS)" section and the "SmartFusion cSoC Family Product Table" (SAR 24906). The value for t was changed from 50ns to 15ns for the high-speed voltage I PD comparators listed in the "Analog Front-End (AFE)" section (SAR 26005). The number of PLLs for A2F200 was changed from 2 to 1 in the "SmartFusion cSoC II Family Product Table" (SAR 25093). Values for direct analog input, total analog input, and total I/Os were updated for the III FG256 package, A2F060, in the "Package I/Os: MSS + FPGA I/Os" table. The Max. column was removed from the table (SAR 26005). The Speed Grade section of the "Product Ordering Codes" table was revised VI (SAR 25257). Revision 1 The "Product Ordering Codes" table was revised to add "blank" as an option for lead- VI (March 2010) free packaging and application (junction temperature range). Table2-3 • Recommended Operating Conditions was revised. Ta (ambient 2-3 temperature) was replaced with T (junction temperature). J PDC5 was deleted from Table 2-15 • Different Components Contributing to the Static 2-13 Power Consumption in SmartFusion cSoCs. The formulas in the footnotes for Table2-29 • I/O Weak Pull-Up/Pull-Down 2-27 Resistances were revised. The values for input biased current were revised in Table 2-93 • Current Monitor 2-76 Performance Specification. 6-8 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Revision Changes Page Revision 0 The "Analog Front-End (AFE)" section was updated to change the throughput for 10- I (March 2010) bit mode from 600 Ksps to 550 Ksps. The A2F060 device was added to product information tables. N/A The "Product Ordering Codes" table was updated to removed Std. speed and add VI speed grade 1. Pre-production was removed from the application ordering code category. The "SmartFusion cSoC Block Diagram" was revised. IV The "Datasheet Categories" section was updated, referencing the "SmartFusion cSoC 1-4, IV Block Diagram" table, which is new. The "VCCI" parameter was renamed to "VCCxxxxIOBx." N/A "Advanced I/Os" were renamed to "FPGA I/Os." Generic pin names that represent multiple pins were standardized with a lower case x as a placeholder. For example, VAREFx designates VAREF0, VAREF1, and VAREF2. Modes were renamed as follows: Operating mode was renamed to SoC mode. 32KHz Active mode was renamed to Standby mode. Battery mode was renamed to Time Keeping mode. Table entries have been filled with values as data has become available. Table 2-1 • Absolute Maximum Ratings, Table 2-2 • Analog Maximum Ratings, and 2-1 Table 2-3 • Recommended Operating Conditions were revised extensively. through 2-3 Device names were updated in Table 2-6 • Package Thermal Resistance. 2-7 Table 2-8 • Power Supplies Configuration was revised extensively. 2-10 Table 2-11 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software 2-11 Settings was revised extensively. Removed "Example of Power Calculation." N/A Table 2-14 • Different Components Contributing to Dynamic Power Consumption in 2-12 SmartFusion cSoCs was revised extensively. Table 2-15 • Different Components Contributing to the Static Power Consumption in 2-13 SmartFusion cSoCs was revised extensively. The "Power Calculation Methodology" section was revised. 2-14 Table 2-83 • Electrical Characteristics of the RC Oscillator was revised extensively. 2-61 Table2-85 • Electrical Characteristics of the Low Power Oscillator was revised 2-62 extensively. The parameter t was changed to T in Table 2-87 • RAM4K9. 2-69 RSTBQ C2CWRH The 12-bit mode row for integral non-linearity was removed from Table 2-95 • ADC 2-79 Specifications. The typical value for 10-bit mode was revised. The table note was punctuated correctly to make it clear. Figure 37-34 • Write Access after Write onto Same Address, Figure 37-34 • Read N/A Access after Write onto Same Address, and Figure 37-34 • Write Access after Read onto Same Address were deleted. Table 2-100 • Voltage Regulator was revised extensively. 2-86 The "Serial Peripheral Interface (SPI) Characteristics" section and "Inter-Integrated 2-88, Circuit (I2C) Characteristics" section are new. 2-90 Revision 8 6-9 Datasheet Information Revision Changes Page Revision 0 "SmartFusion Development Tools" section was replaced with new content. 3-1 (continued) The pin description tables were revised by adding additional pins to reflect the pinout 5-1 for A2F500. through 5-15 The descriptions for "GNDSDD1" and "VCC33SDD1" were revised. 5-1, 5-2 The description for "VCC33A" was revised. 5-2 The pin tables for the "FG256" and "FG484" were replaced with tables that compare 5-37 pin functions across densities for each package. Draft B The "Digital I/Os" section was renamed to the "I/Os and Operating Voltage" section I (December 2009) and information was added regarding digital and analog VCC. The "SmartFusion cSoC Family Product Table" and "Package I/Os: MSS + FPGA I/Os" II section were revised. The terminology for the analog blocks was changed to "programmable analog," IV consisting of two blocks: the analog front-end and analog compute engine. This is reflected throughout the text and in the "SmartFusion cSoC Block Diagram". The "Product Ordering Codes" table was revised to add G as an ordering code for VI eNVM size. Timing tables were populated with information that has become available for speed N/A grade –1. All occurrences of the VMV parameter were removed. N/A The SDD[n] voltage parameter was removed from Table2-2 • Analog Maximum 2-2 Ratings. Table 36-4 • Flash Programming Limits – Retention, Storage and Operating 2-4 Temperature was replaced with Table 2-4 • FPGA and Embedded Flash Programming, Storage and Operating Limits. The "Thermal Characteristics" section was revised extensively. 2-7 Table 2-8 • Power Supplies Configuration was revised significantly. 2-10 Table 2-14 • Different Components Contributing to Dynamic Power Consumption in 2-12 SmartFusion cSoCs and Table 2-15 • Different Components Contributing to the Static Power Consumption in SmartFusion cSoCs were updated. Figure 2-2 • Timing Model was updated. 2-19 The temperature associated with the reliability for LVTTL/LVCMOS in Table 2-34 • I/O 2-29 Input Rise Time, Fall Time, and Related I/O Reliability was changed from 110º to 100º. The values in Table 2-78 • Combinatorial Cell Propagation Delays were updated. 2-57 Table 2-85 • Electrical Characteristics of the Low Power Oscillator is new. Table 2-84 • 2-62 Electrical Characteristics of the Main Crystal Oscillator was revised. Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C, VCC 2-74 = 1.425V and Table2-91 • FlashROM Access Time, Worse Commercial Case Conditions: TJ = 85°C, VCC = 1.425 V are new. The performance tables in the "Programmable Analog Specifications" section were 2-76 revised, including new data available. Table 2-99 • Analog Sigma-Delta DAC is new. The "256-Pin FBGA" table for A2F200 is new. 4-15 6-10 Revision 8 SmartFusion Customizable System-on-Chip (cSoC) Datasheet Categories Categories In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "SmartFusion cSoC Device Status" table on page III, is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Production This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Microsemi SoC Products Group Safety Critical, Life Support, and High-Reliability Applications Policy The SoC Products Group products described in this advance status document may not have completed the SoC Products Group’s qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the SoC Products Group’s Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of the SoC Products Group’s products is available on the SoC Products Group website at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi SoC Products Group also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local SoC Products Group sales office for additional reliability information. Revision 8 6-11 Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA © 2012 Microsemi Corporation. All rights reserved. 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