Industry Pack Modules Industry Pack Modules NEW! IP-1K110 * Reconfigurable FPGA Modules This series of plug-in mezzanine modules provides a user-customizable FPGA on an Industry Pack (IP) module. The module allows users to develop and store their own instruction set in the FPGA for adaptive These modules support adaptive computing applications with an FPGA running custom programs to control system communication. computing applications. Typical uses include specialized communication systems over RS422/485 networks, test Engineering Design Kit Specifications Engineering Design Kit: Provides user with basic information fixture simulation of signals over TTL-switched lines, FPGA required to develop a custom FPGA program for download and analysis of acquired data using specialized FPGA: Altera EP1K100. to the Altera FPGA. This kit must be ordered with the first mathematical formulas such as those developed with purchase of a IP-1K110. FPGA configuration: Downloadable via IP bus. ® MathWorks’s MatLab software. Kit on CD-ROM includes: Clock: Programmable PLL-based clock synthesizer. Schematics (.pdf) The FPGA on Acromag’s IP-1K110 modules can control Input/output signals: Parts List and Part Location drawing (.pdf) up to 48 TTL or 24 RS485 I/O signals or a mix of both IP-1K110-0024: 24 differential RS485 lines Example VHDL Source File (.vhd) IP-1K110-2412: 24 TTL lines and 12 RS485 types. User application programs are downloaded Example Pin Definition File (.acf) IP-1K110-4800: 48 TTL lines Example VHDL Object code (.hex) through the IP bus directly into the FPGA. A pre- Readme file (.txt) IP bus clock frequency: Supports 8 and 32MHz clocks. programmed internal CPLD facilitates initialization by Only one Design Kit purchase is required. User should be ID space: 8-bit data. acting as the bus controller during power-up and fluent in the use of Altera MAX+PLUS or Quartus design I/O space: 8 or 16-bit data. while the program is downloading. This bus controller is tools. Additionally, user should also purchase either the limited to functions necessary for power-up and down- Memory space: Wired to FPGA but not supported with IPSW-API-VXW (VxWorks source code library) or the example FPGA design firmware. loading. After the program downloads, the FPGA takes IPSW-ATX-PCI (ActiveX driver package). These programs Interrupt support: Two IP request levels. include important driver support programs to assist in control of the IP bus and the CPLD is disabled. transferring developed code between user's processor and DMA support: Wired to FPGA but not supported with example Altera 1K100. FPGA design firmware. Features ® IP logic interface: EPLD maintains ID space and two locations ■Altera EP1K100 FPGA Ordering Information in IO space for FPGA configuration. Remaining IO space and INT space are defined by the configured FPGA.■Three models available: Industry Pack Modules IP-1K110-0024: 24 differential RS485 lines Example FPGA program: VHDL provided implements IP bus IP-1K110-0024: 24 differential RS485 lines interface to IO, ID, and INT space. Requires user proficiency IP-1K110-2412: 24 TTL lines and 12 RS485 ® ® IP-1K110-0024E: Same as above with extended with VHDL and Altera MAX+PLUS II or Quartus software IP-1K110-4800: 48 TTL lines temperature range tools. See Engineering Design Kit. IP-1K110-2412: 24 TTL lines and 12 RS485■FPGA programmable via the IP bus IP Compliance (ANSI/VITA 4) IP-1K110-2412E: Same as above with extended Meets IP specifications per ANSI/VITA 4-1995.■Local static RAM (64K x 16) under FPGA control temperature range IP data transfer cycle types supported: Input/output (IOSel*), IP-1K110-4800: 48 TTL lines■Programmable PLL-based clock synthesizer ID read (IDSel*), Interrupt select (INTSel*). IP-1K110-4800E: Same as above with extended ■Supports 8MHz and 32MHz IP bus Access times (8MHz or 32MHz clock): temperature range ID space read: 0 wait states (250ns cycle). IP-1K110-EDK: Engineering Design Kit (one kit required)■User-programmable interval timer Registers read/write: 1 wait states (500ns cycle). For Industry Pack Carrier Cards, see Page 5. Interrupt read/write: 0 wait states (250ns cycle). ■Example FPGA design code provided as VHDL - 8MHz IP bus interface Environmental Software (see Page 81) ® Operating temperature: 0 to 70°C (IP-1K110) - Digital I/O control register IPSW-API-VXW: VxWorks software support package or -40 to 85°C (IP-1K110 E models). ® - others IPSW-API-QNX: QNX software support package Storage temperature: -55 to 125°C. ® IPSW-ATX-PCI: ActiveX /OLE Controls 2.0 software ■Hardware support for DMA and memory space Relative humidity: 5 to 95% non-condensing. ™ IPSW-LINUX: Linux support (website download only) * Replaces IP-1K100 model for new designs. Current MTBF: 5,554,167 hrs. at 25°C, MIL-HDBK-217F, notice 2 For accessories information, see Page 87. IP-1K100 customers consult factory for availability. Acromag, Inc.  PO Box 437, Wixom, MI 48393  Phone: 248-624-1541  Fax: 248-624-9234  solutions@acromag.com  www.acromag.com 13