Industry Pack Modules IP-1K100 User-Programmable FPGA Modules This series of plug-in mezzanine modules provides a user-customizable FPGA on an Industry Pack (IP) module. The module allows users to develop and store their own instruction set in the FPGA for These modules support adaptive computing applications with an FPGA running custom programs to control system communication. adaptive computing applications. Typical uses include specialized communication systems over Engineering Design Kit Specifications Engineering Design Kit: Provides user with basic infor- EIA-422/485 networks, test fixture simulation of FPGA mation required to develop a custom FPGA program signals over TTL-switched lines, and analysis of FPGA: Altera EP1K100. for download to the Altera FPGA. This kit must be acquired data using specialized mathematical for- ordered with the first purchase of a IP-1K100. FPGA configuration: Downloadable via IP bus. mulas such as those developed with MathWorks’s Kit on CD-ROM includes: Clock: Programmable PLL-based clock synthesizer. ® MatLab software. Schematics (.pdf) Input/output signals: Parts List (.pdf) The FPGA on Acromag’s IP-1K100 modules can IP-1K100-0024: 24 differential EIA-485 lines Part Location drawing (.pdf) IP-1K100-2412: 24 TTL lines and 12 EIA-485 control up to 48 TTL or 24 EIA-485 I/O signals or Example VHDL Source File (.vhd) IP-1K100-4800: 48 TTL lines Example Pin Definition File (.acf) a mix of both types. User application programs are IP bus clock frequency: Supports 8 and 32MHz clocks. Example VHDL Object code (.hex) downloaded through the IP bus directly into the Readme file (.txt) ID space: 8-bit data. FPGA. A pre-programmed internal CPLD facilitates Only one Design Kit purchase is required. User should initialization by acting as the bus controller during I/O space: 8 or 16-bit data. be fluent in the use of Altera MAX+PLUS or Quartus power-up and while the program is downloading. Memory space: Wired to FPGA but not supported with design tools. Additionally, user should also purchase example FPGA design firmware. This bus controller is limited to functions neces- either the IPSW-API-VXW (VxWorks source code sary for power-up and downloading. After the Interrupt support: Two IP request levels. library) or the IPSW-ATX-PCI (ActiveX driver pack- age). These programs include important driver support program downloads, the FPGA takes control of the DMA support: Wired to FPGA but not supported with programs to assist in transferring developed code example FPGA design firmware. IP bus and the CPLD is disabled. between user's processor and Altera 1K100. IP logic interface: EPLD maintains ID space and two locations in IO space for FPGA configuration. Features Ordering Information Remaining IO space and INT space are defined by the ® ■Altera EP1K100 FPGA configured FPGA. Industry Pack Modules Example FPGA program: VHDL provided implements IP■Three models available: IP-1K100-0024 bus interface to IO, ID, and INT space. Requires user IP-1K100-0024: 24 differential EIA-485 lines 24 differential EIA-485 lines ® proficiency with VHDL and Altera MAX+PLUS II or IP-1K100-2412: 24 TTL lines and 12 EIA-485 ® IP-1K100-2412 Quartus software tools. See Engineering Design Kit. 24 TTL lines and 12 EIA-485 IP-1K100-4800: 48 TTL lines IP Compliance (ANSI/VITA 4) IP-1K100-4800 ■FPGA programmable via the IP bus Meets IP specifications per ANSI/VITA 4-1995. 48 TTL lines IP data transfer cycle types supported: Input/output IP-1K100-EDK■Local static RAM (64K x 16) under FPGA control (IOSel*), ID read (IDSel*), Interrupt select (INTSel*). Engineering Design Kit (one kit required) ■Programmable PLL-based clock synthesizer Access times (8MHz or 32MHz clock): For Industry Pack Carrier Cards, see Page 5. ID space read: 0 wait states (250ns cycle). ■Supports 8MHz and 32MHz IP bus Registers read/write: 1 wait states (500ns cycle). Software* ® Interrupt read/write: 0 wait states (250ns cycle).■User-programmable interval timer IPSW-API-VXW: VxWorks software support package ® IPSW-API-QNX: QNX software support package Environmental■Example FPGA design code provided as VHDL ® IPSW-ATX-PCI: ActiveX /OLE Controls 2.0 software Operating temperature: 0 to 70°C. - 8MHz IP bus interface package Storage temperature: -55 to 125°C. - Digital I/O control register IPSW-LINUX: Linux support (website download only) Relative humidity: 5 to 95% noncondensing. - others * For software information, see Page 65. MTBF: 5,554,167 hrs. at 25°C, MIL-HDBK-217F, notice 2 ■Hardware support for DMA and memory space For accessories information, see Page 71. Tel: 248-624-1541 Fax: 248-624-9234 e-mail: sales@acromag.com www.acromag.com 13 IP Modules